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IB/mlx5: Expose multi-packet RQ capabilities
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
c2e53b2c 37#include <linux/mlx5/fs.h>
e126ba97 38#include "mlx5_ib.h"
e126ba97
EC		 39
40/* not supported currently */
41static int wq_signature;
42
43enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45};
46
47enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52};
53
54enum {
55 MLX5_IB_SQ_STRIDE = 6,
e126ba97
EC		 56};
57
58static const u32 mlx5_ib_opcode[] = {
59 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 60 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
73};
74
f0313965
ES		 75struct mlx5_wqe_eth_pad {
76 u8 rsvd0[16];
77};
e126ba97 78
eb49ab0c
AV		 79enum raw_qp_set_mask_map {
80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 81 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 82};
83
0680efa2
AV		 84struct mlx5_modify_raw_qp_param {
85 u16 operation;
eb49ab0c
AV		 86
87 u32 set_mask; /* raw_qp_set_mask_map */
7d29f349 88 u32 rate_limit;
eb49ab0c 89 u8 rq_q_ctr_id;
0680efa2
AV		 90};
91
89ea94a7
MG		 92static void get_cqs(enum ib_qp_type qp_type,
93 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
94 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
95
e126ba97
EC		 96static int is_qp0(enum ib_qp_type qp_type)
97{
98 return qp_type == IB_QPT_SMI;
99}
100
e126ba97
EC		 101static int is_sqp(enum ib_qp_type qp_type)
102{
103 return is_qp0(qp_type) || is_qp1(qp_type);
104}
105
106static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
107{
108 return mlx5_buf_offset(&qp->buf, offset);
109}
110
111static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
112{
113 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
114}
115
116void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
117{
118 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
119}
120
c1395a2a
HE		 121/**
122 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
123 *
124 * @qp: QP to copy from.
125 * @send: copy from the send queue when non-zero, use the receive queue
126 * otherwise.
127 * @wqe_index: index to start copying from. For send work queues, the
128 * wqe_index is in units of MLX5_SEND_WQE_BB.
129 * For receive work queue, it is the number of work queue
130 * element in the queue.
131 * @buffer: destination buffer.
132 * @length: maximum number of bytes to copy.
133 *
134 * Copies at least a single WQE, but may copy more data.
135 *
136 * Return: the number of bytes copied, or an error code.
137 */
138int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 139 void *buffer, u32 length,
140 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 141{
142 struct ib_device *ibdev = qp->ibqp.device;
143 struct mlx5_ib_dev *dev = to_mdev(ibdev);
144 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
145 size_t offset;
146 size_t wq_end;
19098df2 147 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 148 u32 first_copy_length;
149 int wqe_length;
150 int ret;
151
152 if (wq->wqe_cnt == 0) {
153 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
154 qp->ibqp.qp_type);
155 return -EINVAL;
156 }
157
158 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
159 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
160
161 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
162 return -EINVAL;
163
164 if (offset > umem->length ||
165 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
166 return -EINVAL;
167
168 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
169 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
170 if (ret)
171 return ret;
172
173 if (send) {
174 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
175 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
176
177 wqe_length = ds * MLX5_WQE_DS_UNITS;
178 } else {
179 wqe_length = 1 << wq->wqe_shift;
180 }
181
182 if (wqe_length <= first_copy_length)
183 return first_copy_length;
184
185 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
186 wqe_length - first_copy_length);
187 if (ret)
188 return ret;
189
190 return wqe_length;
191}
192
e126ba97
EC		 193static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
194{
195 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
196 struct ib_event event;
197
19098df2 198 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
199 /* This event is only valid for trans_qps */
200 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
201 }
e126ba97
EC		 202
203 if (ibqp->event_handler) {
204 event.device = ibqp->device;
205 event.element.qp = ibqp;
206 switch (type) {
207 case MLX5_EVENT_TYPE_PATH_MIG:
208 event.event = IB_EVENT_PATH_MIG;
209 break;
210 case MLX5_EVENT_TYPE_COMM_EST:
211 event.event = IB_EVENT_COMM_EST;
212 break;
213 case MLX5_EVENT_TYPE_SQ_DRAINED:
214 event.event = IB_EVENT_SQ_DRAINED;
215 break;
216 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
217 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
218 break;
219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
220 event.event = IB_EVENT_QP_FATAL;
221 break;
222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
223 event.event = IB_EVENT_PATH_MIG_ERR;
224 break;
225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
226 event.event = IB_EVENT_QP_REQ_ERR;
227 break;
228 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
229 event.event = IB_EVENT_QP_ACCESS_ERR;
230 break;
231 default:
232 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
233 return;
234 }
235
236 ibqp->event_handler(&event, ibqp->qp_context);
237 }
238}
239
240static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
241 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
242{
243 int wqe_size;
244 int wq_size;
245
246 /* Sanity check RQ size before proceeding */
938fe83c 247 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 248 return -EINVAL;
249
250 if (!has_rq) {
251 qp->rq.max_gs = 0;
252 qp->rq.wqe_cnt = 0;
253 qp->rq.wqe_shift = 0;
0540d814
NO		 254 cap->max_recv_wr = 0;
255 cap->max_recv_sge = 0;
e126ba97
EC		 256 } else {
257 if (ucmd) {
258 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
259 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
260 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
261 qp->rq.max_post = qp->rq.wqe_cnt;
262 } else {
263 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
264 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
265 wqe_size = roundup_pow_of_two(wqe_size);
266 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
267 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
268 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 269 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 270 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
271 wqe_size,
938fe83c
SM		 272 MLX5_CAP_GEN(dev->mdev,
273 max_wqe_sz_rq));
e126ba97
EC		 274 return -EINVAL;
275 }
276 qp->rq.wqe_shift = ilog2(wqe_size);
277 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
278 qp->rq.max_post = qp->rq.wqe_cnt;
279 }
280 }
281
282 return 0;
283}
284
f0313965 285static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 286{
618af384 287 int size = 0;
e126ba97 288
f0313965 289 switch (attr->qp_type) {
e126ba97 290 case IB_QPT_XRC_INI:
b125a54b 291 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 292 /* fall through */
293 case IB_QPT_RC:
294 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 295 max(sizeof(struct mlx5_wqe_atomic_seg) +
296 sizeof(struct mlx5_wqe_raddr_seg),
297 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
298 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 299 break;
300
b125a54b
EC		 301 case IB_QPT_XRC_TGT:
302 return 0;
303
e126ba97 304 case IB_QPT_UC:
b125a54b 305 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 306 max(sizeof(struct mlx5_wqe_raddr_seg),
307 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
308 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 309 break;
310
311 case IB_QPT_UD:
f0313965
ES		 312 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
313 size += sizeof(struct mlx5_wqe_eth_pad) +
314 sizeof(struct mlx5_wqe_eth_seg);
315 /* fall through */
e126ba97 316 case IB_QPT_SMI:
d16e91da 317 case MLX5_IB_QPT_HW_GSI:
b125a54b 318 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 319 sizeof(struct mlx5_wqe_datagram_seg);
320 break;
321
322 case MLX5_IB_QPT_REG_UMR:
b125a54b 323 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 324 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
325 sizeof(struct mlx5_mkey_seg);
326 break;
327
328 default:
329 return -EINVAL;
330 }
331
332 return size;
333}
334
335static int calc_send_wqe(struct ib_qp_init_attr *attr)
336{
337 int inl_size = 0;
338 int size;
339
f0313965 340 size = sq_overhead(attr);
e126ba97
EC		 341 if (size < 0)
342 return size;
343
344 if (attr->cap.max_inline_data) {
345 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
346 attr->cap.max_inline_data;
347 }
348
349 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 350 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
351 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
352 return MLX5_SIG_WQE_SIZE;
353 else
354 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 355}
356
288c01b7
EC		 357static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
358{
359 int max_sge;
360
361 if (attr->qp_type == IB_QPT_RC)
362 max_sge = (min_t(int, wqe_size, 512) -
363 sizeof(struct mlx5_wqe_ctrl_seg) -
364 sizeof(struct mlx5_wqe_raddr_seg)) /
365 sizeof(struct mlx5_wqe_data_seg);
366 else if (attr->qp_type == IB_QPT_XRC_INI)
367 max_sge = (min_t(int, wqe_size, 512) -
368 sizeof(struct mlx5_wqe_ctrl_seg) -
369 sizeof(struct mlx5_wqe_xrc_seg) -
370 sizeof(struct mlx5_wqe_raddr_seg)) /
371 sizeof(struct mlx5_wqe_data_seg);
372 else
373 max_sge = (wqe_size - sq_overhead(attr)) /
374 sizeof(struct mlx5_wqe_data_seg);
375
376 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
377 sizeof(struct mlx5_wqe_data_seg));
378}
379
e126ba97
EC		 380static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
381 struct mlx5_ib_qp *qp)
382{
383 int wqe_size;
384 int wq_size;
385
386 if (!attr->cap.max_send_wr)
387 return 0;
388
389 wqe_size = calc_send_wqe(attr);
390 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
391 if (wqe_size < 0)
392 return wqe_size;
393
938fe83c 394 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 395 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 396 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 397 return -EINVAL;
398 }
399
f0313965
ES		 400 qp->max_inline_data = wqe_size - sq_overhead(attr) -
401 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 402 attr->cap.max_inline_data = qp->max_inline_data;
403
e1e66cc2
SG		 404 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
405 qp->signature_en = true;
406
e126ba97
EC		 407 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
408 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 409 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 410 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
411 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 412 qp->sq.wqe_cnt,
413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 414 return -ENOMEM;
415 }
e126ba97 416 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 417 qp->sq.max_gs = get_send_sge(attr, wqe_size);
418 if (qp->sq.max_gs < attr->cap.max_send_sge)
419 return -ENOMEM;
420
421 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 422 qp->sq.max_post = wq_size / wqe_size;
423 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 424
425 return wq_size;
426}
427
428static int set_user_buf_size(struct mlx5_ib_dev *dev,
429 struct mlx5_ib_qp *qp,
19098df2 430 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 431 struct mlx5_ib_qp_base *base,
432 struct ib_qp_init_attr *attr)
e126ba97
EC		 433{
434 int desc_sz = 1 << qp->sq.wqe_shift;
435
938fe83c 436 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 437 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 438 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 439 return -EINVAL;
440 }
441
442 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
443 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
444 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
445 return -EINVAL;
446 }
447
448 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
449
938fe83c 450 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 451 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 452 qp->sq.wqe_cnt,
453 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 454 return -EINVAL;
455 }
456
c2e53b2c
YH		 457 if (attr->qp_type == IB_QPT_RAW_PACKET ||
458 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 459 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
460 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
461 } else {
462 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
463 (qp->sq.wqe_cnt << 6);
464 }
e126ba97
EC		 465
466 return 0;
467}
468
469static int qp_has_rq(struct ib_qp_init_attr *attr)
470{
471 if (attr->qp_type == IB_QPT_XRC_INI ||
472 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
473 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
474 !attr->cap.max_recv_wr)
475 return 0;
476
477 return 1;
478}
479
2f5ff264 480static int first_med_bfreg(void)
c1be5232
EC		 481{
482 return 1;
483}
484
0b80c14f
EC		 485enum {
486 /* this is the first blue flame register in the array of bfregs assigned
487 * to a processes. Since we do not use it for blue flame but rather
488 * regular 64 bit doorbells, we do not need a lock for maintaiing
489 * "odd/even" order
490 */
491 NUM_NON_BLUE_FLAME_BFREGS = 1,
492};
493
b037c29a
EC		 494static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
495{
496 return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
497}
498
499static int num_med_bfreg(struct mlx5_ib_dev *dev,
500 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 501{
502 int n;
503
b037c29a
EC		 504 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
505 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 506
507 return n >= 0 ? n : 0;
508}
509
b037c29a
EC		 510static int first_hi_bfreg(struct mlx5_ib_dev *dev,
511 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 512{
513 int med;
c1be5232 514
b037c29a
EC		 515 med = num_med_bfreg(dev, bfregi);
516 return ++med;
c1be5232
EC		 517}
518
b037c29a
EC		 519static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
520 struct mlx5_bfreg_info *bfregi)
e126ba97 521{
e126ba97
EC		 522 int i;
523
b037c29a
EC		 524 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
525 if (!bfregi->count[i]) {
2f5ff264 526 bfregi->count[i]++;
e126ba97
EC		 527 return i;
528 }
529 }
530
531 return -ENOMEM;
532}
533
b037c29a
EC		 534static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
535 struct mlx5_bfreg_info *bfregi)
e126ba97 536{
2f5ff264 537 int minidx = first_med_bfreg();
e126ba97
EC		 538 int i;
539
b037c29a 540 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 541 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 542 minidx = i;
0b80c14f
EC		 543 if (!bfregi->count[minidx])
544 break;
e126ba97
EC		 545 }
546
2f5ff264 547 bfregi->count[minidx]++;
e126ba97
EC		 548 return minidx;
549}
550
b037c29a
EC		 551static int alloc_bfreg(struct mlx5_ib_dev *dev,
552 struct mlx5_bfreg_info *bfregi,
2f5ff264 553 enum mlx5_ib_latency_class lat)
e126ba97 554{
2f5ff264 555 int bfregn = -EINVAL;
e126ba97 556
2f5ff264 557 mutex_lock(&bfregi->lock);
e126ba97
EC		 558 switch (lat) {
559 case MLX5_IB_LATENCY_CLASS_LOW:
0b80c14f 560 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 561 bfregn = 0;
562 bfregi->count[bfregn]++;
e126ba97
EC		 563 break;
564
565 case MLX5_IB_LATENCY_CLASS_MEDIUM:
2f5ff264
EC		 566 if (bfregi->ver < 2)
567 bfregn = -ENOMEM;
78c0f98c 568 else
b037c29a 569 bfregn = alloc_med_class_bfreg(dev, bfregi);
e126ba97
EC		 570 break;
571
572 case MLX5_IB_LATENCY_CLASS_HIGH:
2f5ff264
EC		 573 if (bfregi->ver < 2)
574 bfregn = -ENOMEM;
78c0f98c 575 else
b037c29a 576 bfregn = alloc_high_class_bfreg(dev, bfregi);
e126ba97
EC		 577 break;
578 }
2f5ff264 579 mutex_unlock(&bfregi->lock);
e126ba97 580
2f5ff264 581 return bfregn;
e126ba97
EC		 582}
583
b037c29a 584static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 585{
2f5ff264 586 mutex_lock(&bfregi->lock);
b037c29a 587 bfregi->count[bfregn]--;
2f5ff264 588 mutex_unlock(&bfregi->lock);
e126ba97
EC		 589}
590
591static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
592{
593 switch (state) {
594 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
595 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
596 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
597 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
598 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
599 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
600 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
601 default: return -1;
602 }
603}
604
605static int to_mlx5_st(enum ib_qp_type type)
606{
607 switch (type) {
608 case IB_QPT_RC: return MLX5_QP_ST_RC;
609 case IB_QPT_UC: return MLX5_QP_ST_UC;
610 case IB_QPT_UD: return MLX5_QP_ST_UD;
611 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
612 case IB_QPT_XRC_INI:
613 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
614 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 615 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
e126ba97 616 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 617 case IB_QPT_RAW_PACKET:
0fb2ed66 618 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 619 case IB_QPT_MAX:
620 default: return -EINVAL;
621 }
622}
623
89ea94a7
MG		 624static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
625 struct mlx5_ib_cq *recv_cq);
626static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
627 struct mlx5_ib_cq *recv_cq);
628
b037c29a
EC		 629static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
630 struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 631{
b037c29a
EC		 632 int bfregs_per_sys_page;
633 int index_of_sys_page;
634 int offset;
635
636 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
637 MLX5_NON_FP_BFREGS_PER_UAR;
638 index_of_sys_page = bfregn / bfregs_per_sys_page;
639
640 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
641
642 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 643}
644
19098df2 645static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
646 struct ib_pd *pd,
647 unsigned long addr, size_t size,
648 struct ib_umem **umem,
649 int *npages, int *page_shift, int *ncont,
650 u32 *offset)
651{
652 int err;
653
654 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
655 if (IS_ERR(*umem)) {
656 mlx5_ib_dbg(dev, "umem_get failed\n");
657 return PTR_ERR(*umem);
658 }
659
762f899a 660 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 661
662 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
663 if (err) {
664 mlx5_ib_warn(dev, "bad offset\n");
665 goto err_umem;
666 }
667
668 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
669 addr, size, *npages, *page_shift, *ncont, *offset);
670
671 return 0;
672
673err_umem:
674 ib_umem_release(*umem);
675 *umem = NULL;
676
677 return err;
678}
679
fe248c3a
MG		 680static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
681 struct mlx5_ib_rwq *rwq)
79b20a6c
YH		 682{
683 struct mlx5_ib_ucontext *context;
684
fe248c3a
MG		 685 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
686 atomic_dec(&dev->delay_drop.rqs_cnt);
687
79b20a6c
YH		 688 context = to_mucontext(pd->uobject->context);
689 mlx5_ib_db_unmap_user(context, &rwq->db);
690 if (rwq->umem)
691 ib_umem_release(rwq->umem);
692}
693
694static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
695 struct mlx5_ib_rwq *rwq,
696 struct mlx5_ib_create_wq *ucmd)
697{
698 struct mlx5_ib_ucontext *context;
699 int page_shift = 0;
700 int npages;
701 u32 offset = 0;
702 int ncont = 0;
703 int err;
704
705 if (!ucmd->buf_addr)
706 return -EINVAL;
707
708 context = to_mucontext(pd->uobject->context);
709 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
710 rwq->buf_size, 0, 0);
711 if (IS_ERR(rwq->umem)) {
712 mlx5_ib_dbg(dev, "umem_get failed\n");
713 err = PTR_ERR(rwq->umem);
714 return err;
715 }
716
762f899a 717 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 718 &ncont, NULL);
719 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
720 &rwq->rq_page_offset);
721 if (err) {
722 mlx5_ib_warn(dev, "bad offset\n");
723 goto err_umem;
724 }
725
726 rwq->rq_num_pas = ncont;
727 rwq->page_shift = page_shift;
728 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
729 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
730
731 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
732 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
733 npages, page_shift, ncont, offset);
734
735 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
736 if (err) {
737 mlx5_ib_dbg(dev, "map failed\n");
738 goto err_umem;
739 }
740
741 rwq->create_type = MLX5_WQ_USER;
742 return 0;
743
744err_umem:
745 ib_umem_release(rwq->umem);
746 return err;
747}
748
b037c29a
EC		 749static int adjust_bfregn(struct mlx5_ib_dev *dev,
750 struct mlx5_bfreg_info *bfregi, int bfregn)
751{
752 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
753 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
754}
755
e126ba97
EC		 756static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
757 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 758 struct ib_qp_init_attr *attr,
09a7d9ec 759 u32 **in,
19098df2 760 struct mlx5_ib_create_qp_resp *resp, int *inlen,
761 struct mlx5_ib_qp_base *base)
e126ba97
EC		 762{
763 struct mlx5_ib_ucontext *context;
764 struct mlx5_ib_create_qp ucmd;
19098df2 765 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 766 int page_shift = 0;
e126ba97
EC		 767 int uar_index;
768 int npages;
9e9c47d0 769 u32 offset = 0;
2f5ff264 770 int bfregn;
9e9c47d0 771 int ncont = 0;
09a7d9ec
SM		 772 __be64 *pas;
773 void *qpc;
e126ba97
EC		 774 int err;
775
776 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
777 if (err) {
778 mlx5_ib_dbg(dev, "copy failed\n");
779 return err;
780 }
781
782 context = to_mucontext(pd->uobject->context);
783 /*
784 * TBD: should come from the verbs when we have the API
785 */
051f2630
LR		 786 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
787 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 788 bfregn = MLX5_CROSS_CHANNEL_BFREG;
051f2630 789 else {
b037c29a 790 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
2f5ff264
EC		 791 if (bfregn < 0) {
792 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
051f2630 793 mlx5_ib_dbg(dev, "reverting to medium latency\n");
b037c29a 794 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
2f5ff264
EC		 795 if (bfregn < 0) {
796 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
051f2630 797 mlx5_ib_dbg(dev, "reverting to high latency\n");
b037c29a 798 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
2f5ff264
EC		 799 if (bfregn < 0) {
800 mlx5_ib_warn(dev, "bfreg allocation failed\n");
801 return bfregn;
051f2630 802 }
c1be5232 803 }
e126ba97
EC		 804 }
805 }
806
b037c29a 807 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn);
2f5ff264 808 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
e126ba97 809
48fea837
HE		 810 qp->rq.offset = 0;
811 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
812 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
813
0fb2ed66 814 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 815 if (err)
2f5ff264 816 goto err_bfreg;
e126ba97 817
19098df2 818 if (ucmd.buf_addr && ubuffer->buf_size) {
819 ubuffer->buf_addr = ucmd.buf_addr;
820 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
821 ubuffer->buf_size,
822 &ubuffer->umem, &npages, &page_shift,
823 &ncont, &offset);
824 if (err)
2f5ff264 825 goto err_bfreg;
9e9c47d0 826 } else {
19098df2 827 ubuffer->umem = NULL;
e126ba97 828 }
e126ba97 829
09a7d9ec
SM		 830 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
831 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 832 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 833 if (!*in) {
834 err = -ENOMEM;
835 goto err_umem;
836 }
09a7d9ec
SM		 837
838 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 839 if (ubuffer->umem)
09a7d9ec
SM		 840 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
841
842 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
843
844 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
845 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 846
09a7d9ec 847 MLX5_SET(qpc, qpc, uar_page, uar_index);
b037c29a 848 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
2f5ff264 849 qp->bfregn = bfregn;
e126ba97
EC		 850
851 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
852 if (err) {
853 mlx5_ib_dbg(dev, "map failed\n");
854 goto err_free;
855 }
856
857 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
858 if (err) {
859 mlx5_ib_dbg(dev, "copy failed\n");
860 goto err_unmap;
861 }
862 qp->create_type = MLX5_QP_USER;
863
864 return 0;
865
866err_unmap:
867 mlx5_ib_db_unmap_user(context, &qp->db);
868
869err_free:
479163f4 870 kvfree(*in);
e126ba97
EC		 871
872err_umem:
19098df2 873 if (ubuffer->umem)
874 ib_umem_release(ubuffer->umem);
e126ba97 875
2f5ff264 876err_bfreg:
b037c29a 877 free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 878 return err;
879}
880
b037c29a
EC		 881static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
882 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 883{
884 struct mlx5_ib_ucontext *context;
885
886 context = to_mucontext(pd->uobject->context);
887 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 888 if (base->ubuffer.umem)
889 ib_umem_release(base->ubuffer.umem);
b037c29a 890 free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 891}
892
893static int create_kernel_qp(struct mlx5_ib_dev *dev,
894 struct ib_qp_init_attr *init_attr,
895 struct mlx5_ib_qp *qp,
09a7d9ec 896 u32 **in, int *inlen,
19098df2 897 struct mlx5_ib_qp_base *base)
e126ba97 898{
e126ba97 899 int uar_index;
09a7d9ec 900 void *qpc;
e126ba97
EC		 901 int err;
902
f0313965
ES		 903 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
904 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c 905 IB_QP_CREATE_IPOIB_UD_LSO |
93d576af 906 IB_QP_CREATE_NETIF_QP |
b11a4f9c 907 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 908 return -EINVAL;
e126ba97
EC		 909
910 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 911 qp->bf.bfreg = &dev->fp_bfreg;
912 else
913 qp->bf.bfreg = &dev->bfreg;
e126ba97 914
d8030b0d
EC		 915 /* We need to divide by two since each register is comprised of
916 * two buffers of identical size, namely odd and even
917 */
918 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 919 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 920
921 err = calc_sq_size(dev, init_attr, qp);
922 if (err < 0) {
923 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 924 return err;
e126ba97
EC		 925 }
926
927 qp->rq.offset = 0;
928 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 929 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 930
19098df2 931 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 932 if (err) {
933 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 934 return err;
e126ba97
EC		 935 }
936
937 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 938 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
939 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 940 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 941 if (!*in) {
942 err = -ENOMEM;
943 goto err_buf;
944 }
09a7d9ec
SM		 945
946 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
947 MLX5_SET(qpc, qpc, uar_page, uar_index);
948 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
949
e126ba97 950 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 951 MLX5_SET(qpc, qpc, fre, 1);
952 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 953
b11a4f9c 954 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 955 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 956 qp->flags |= MLX5_IB_QP_SQPN_QP1;
957 }
958
09a7d9ec
SM		 959 mlx5_fill_page_array(&qp->buf,
960 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 961
9603b61d 962 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 963 if (err) {
964 mlx5_ib_dbg(dev, "err %d\n", err);
965 goto err_free;
966 }
967
b5883008
LD		 968 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
969 sizeof(*qp->sq.wrid), GFP_KERNEL);
970 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
971 sizeof(*qp->sq.wr_data), GFP_KERNEL);
972 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
973 sizeof(*qp->rq.wrid), GFP_KERNEL);
974 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
975 sizeof(*qp->sq.w_list), GFP_KERNEL);
976 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
977 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
e126ba97
EC		 978
979 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
980 !qp->sq.w_list || !qp->sq.wqe_head) {
981 err = -ENOMEM;
982 goto err_wrid;
983 }
984 qp->create_type = MLX5_QP_KERNEL;
985
986 return 0;
987
988err_wrid:
b5883008
LD		 989 kvfree(qp->sq.wqe_head);
990 kvfree(qp->sq.w_list);
991 kvfree(qp->sq.wrid);
992 kvfree(qp->sq.wr_data);
993 kvfree(qp->rq.wrid);
f4044dac 994 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 995
996err_free:
479163f4 997 kvfree(*in);
e126ba97
EC		 998
999err_buf:
9603b61d 1000 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1001 return err;
1002}
1003
1004static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1005{
b5883008
LD		 1006 kvfree(qp->sq.wqe_head);
1007 kvfree(qp->sq.w_list);
1008 kvfree(qp->sq.wrid);
1009 kvfree(qp->sq.wr_data);
1010 kvfree(qp->rq.wrid);
f4044dac 1011 mlx5_db_free(dev->mdev, &qp->db);
9603b61d 1012 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1013}
1014
09a7d9ec 1015static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1016{
1017 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1018 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1019 return MLX5_SRQ_RQ;
e126ba97 1020 else if (!qp->has_rq)
09a7d9ec 1021 return MLX5_ZERO_LEN_RQ;
e126ba97 1022 else
09a7d9ec 1023 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1024}
1025
1026static int is_connected(enum ib_qp_type qp_type)
1027{
1028 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1029 return 1;
1030
1031 return 0;
1032}
1033
0fb2ed66 1034static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
c2e53b2c 1035 struct mlx5_ib_qp *qp,
0fb2ed66 1036 struct mlx5_ib_sq *sq, u32 tdn)
1037{
c4f287c4 1038 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1039 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1040
0fb2ed66 1041 MLX5_SET(tisc, tisc, transport_domain, tdn);
c2e53b2c
YH		 1042 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1043 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1044
0fb2ed66 1045 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1046}
1047
1048static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1049 struct mlx5_ib_sq *sq)
1050{
1051 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1052}
1053
1054static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1055 struct mlx5_ib_sq *sq, void *qpin,
1056 struct ib_pd *pd)
1057{
1058 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1059 __be64 *pas;
1060 void *in;
1061 void *sqc;
1062 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1063 void *wq;
1064 int inlen;
1065 int err;
1066 int page_shift = 0;
1067 int npages;
1068 int ncont = 0;
1069 u32 offset = 0;
1070
1071 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1072 &sq->ubuffer.umem, &npages, &page_shift,
1073 &ncont, &offset);
1074 if (err)
1075 return err;
1076
1077 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1b9a07ee 1078 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1079 if (!in) {
1080 err = -ENOMEM;
1081 goto err_umem;
1082 }
1083
1084 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1085 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
795b609c
BW		 1086 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1087 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
0fb2ed66 1088 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1089 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1090 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1091 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1092 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
96dc3fc5
NO		 1093 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1094 MLX5_CAP_ETH(dev->mdev, swp))
1095 MLX5_SET(sqc, sqc, allow_swp, 1);
0fb2ed66 1096
1097 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1098 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1099 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1100 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1101 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1102 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1103 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1104 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1105 MLX5_SET(wq, wq, page_offset, offset);
1106
1107 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1108 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1109
1110 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1111
1112 kvfree(in);
1113
1114 if (err)
1115 goto err_umem;
1116
1117 return 0;
1118
1119err_umem:
1120 ib_umem_release(sq->ubuffer.umem);
1121 sq->ubuffer.umem = NULL;
1122
1123 return err;
1124}
1125
1126static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1127 struct mlx5_ib_sq *sq)
1128{
1129 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1130 ib_umem_release(sq->ubuffer.umem);
1131}
1132
1133static int get_rq_pas_size(void *qpc)
1134{
1135 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1136 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1137 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1138 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1139 u32 po_quanta = 1 << (log_page_size - 6);
1140 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1141 u32 page_size = 1 << log_page_size;
1142 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1143 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1144
1145 return rq_num_pas * sizeof(u64);
1146}
1147
1148static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1149 struct mlx5_ib_rq *rq, void *qpin)
1150{
358e42ea 1151 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1152 __be64 *pas;
1153 __be64 *qp_pas;
1154 void *in;
1155 void *rqc;
1156 void *wq;
1157 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1158 int inlen;
1159 int err;
1160 u32 rq_pas_size = get_rq_pas_size(qpc);
1161
1162 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1163 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1164 if (!in)
1165 return -ENOMEM;
1166
1167 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1168 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1169 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1170 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1171 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1172 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1173 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1174 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1175
358e42ea
MD		 1176 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1177 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1178
0fb2ed66 1179 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1180 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1181 MLX5_SET(wq, wq, end_padding_mode,
01581fb8 1182 MLX5_GET(qpc, qpc, end_padding_mode));
0fb2ed66 1183 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1184 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1185 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1186 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1187 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1188 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1189
1190 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1191 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1192 memcpy(pas, qp_pas, rq_pas_size);
1193
1194 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1195
1196 kvfree(in);
1197
1198 return err;
1199}
1200
1201static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1202 struct mlx5_ib_rq *rq)
1203{
1204 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1205}
1206
1207static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1208 struct mlx5_ib_rq *rq, u32 tdn)
1209{
1210 u32 *in;
1211 void *tirc;
1212 int inlen;
1213 int err;
1214
1215 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1216 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1217 if (!in)
1218 return -ENOMEM;
1219
1220 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1221 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1222 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1223 MLX5_SET(tirc, tirc, transport_domain, tdn);
1224
1225 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1226
1227 kvfree(in);
1228
1229 return err;
1230}
1231
1232static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1233 struct mlx5_ib_rq *rq)
1234{
1235 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1236}
1237
1238static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
09a7d9ec 1239 u32 *in,
0fb2ed66 1240 struct ib_pd *pd)
1241{
1242 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1243 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1244 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1245 struct ib_uobject *uobj = pd->uobject;
1246 struct ib_ucontext *ucontext = uobj->context;
1247 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1248 int err;
1249 u32 tdn = mucontext->tdn;
1250
1251 if (qp->sq.wqe_cnt) {
c2e53b2c 1252 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
0fb2ed66 1253 if (err)
1254 return err;
1255
1256 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1257 if (err)
1258 goto err_destroy_tis;
1259
1260 sq->base.container_mibqp = qp;
1d31e9c0 1261 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1262 }
1263
1264 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1265 rq->base.container_mibqp = qp;
1266
e4cc4fa7
NO		 1267 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1268 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
0fb2ed66 1269 err = create_raw_packet_qp_rq(dev, rq, in);
1270 if (err)
1271 goto err_destroy_sq;
1272
0fb2ed66 1273
1274 err = create_raw_packet_qp_tir(dev, rq, tdn);
1275 if (err)
1276 goto err_destroy_rq;
1277 }
1278
1279 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1280 rq->base.mqp.qpn;
1281
1282 return 0;
1283
1284err_destroy_rq:
1285 destroy_raw_packet_qp_rq(dev, rq);
1286err_destroy_sq:
1287 if (!qp->sq.wqe_cnt)
1288 return err;
1289 destroy_raw_packet_qp_sq(dev, sq);
1290err_destroy_tis:
1291 destroy_raw_packet_qp_tis(dev, sq);
1292
1293 return err;
1294}
1295
1296static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1297 struct mlx5_ib_qp *qp)
1298{
1299 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1300 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1301 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1302
1303 if (qp->rq.wqe_cnt) {
1304 destroy_raw_packet_qp_tir(dev, rq);
1305 destroy_raw_packet_qp_rq(dev, rq);
1306 }
1307
1308 if (qp->sq.wqe_cnt) {
1309 destroy_raw_packet_qp_sq(dev, sq);
1310 destroy_raw_packet_qp_tis(dev, sq);
1311 }
1312}
1313
1314static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1315 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1316{
1317 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1318 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1319
1320 sq->sq = &qp->sq;
1321 rq->rq = &qp->rq;
1322 sq->doorbell = &qp->db;
1323 rq->doorbell = &qp->db;
1324}
1325
28d61370
YH		 1326static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1327{
1328 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1329}
1330
1331static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1332 struct ib_pd *pd,
1333 struct ib_qp_init_attr *init_attr,
1334 struct ib_udata *udata)
1335{
1336 struct ib_uobject *uobj = pd->uobject;
1337 struct ib_ucontext *ucontext = uobj->context;
1338 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1339 struct mlx5_ib_create_qp_resp resp = {};
1340 int inlen;
1341 int err;
1342 u32 *in;
1343 void *tirc;
1344 void *hfso;
1345 u32 selected_fields = 0;
1346 size_t min_resp_len;
1347 u32 tdn = mucontext->tdn;
1348 struct mlx5_ib_create_qp_rss ucmd = {};
1349 size_t required_cmd_sz;
1350
1351 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1352 return -EOPNOTSUPP;
1353
1354 if (init_attr->create_flags || init_attr->send_cq)
1355 return -EINVAL;
1356
2f5ff264 1357 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1358 if (udata->outlen < min_resp_len)
1359 return -EINVAL;
1360
1361 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1362 if (udata->inlen < required_cmd_sz) {
1363 mlx5_ib_dbg(dev, "invalid inlen\n");
1364 return -EINVAL;
1365 }
1366
1367 if (udata->inlen > sizeof(ucmd) &&
1368 !ib_is_udata_cleared(udata, sizeof(ucmd),
1369 udata->inlen - sizeof(ucmd))) {
1370 mlx5_ib_dbg(dev, "inlen is not supported\n");
1371 return -EOPNOTSUPP;
1372 }
1373
1374 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1375 mlx5_ib_dbg(dev, "copy failed\n");
1376 return -EFAULT;
1377 }
1378
1379 if (ucmd.comp_mask) {
1380 mlx5_ib_dbg(dev, "invalid comp mask\n");
1381 return -EOPNOTSUPP;
1382 }
1383
1384 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1385 mlx5_ib_dbg(dev, "invalid reserved\n");
1386 return -EOPNOTSUPP;
1387 }
1388
1389 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1390 if (err) {
1391 mlx5_ib_dbg(dev, "copy failed\n");
1392 return -EINVAL;
1393 }
1394
1395 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1396 in = kvzalloc(inlen, GFP_KERNEL);
28d61370
YH		 1397 if (!in)
1398 return -ENOMEM;
1399
1400 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1401 MLX5_SET(tirc, tirc, disp_type,
1402 MLX5_TIRC_DISP_TYPE_INDIRECT);
1403 MLX5_SET(tirc, tirc, indirect_table,
1404 init_attr->rwq_ind_tbl->ind_tbl_num);
1405 MLX5_SET(tirc, tirc, transport_domain, tdn);
1406
1407 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1408 switch (ucmd.rx_hash_function) {
1409 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1410 {
1411 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1412 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1413
1414 if (len != ucmd.rx_key_len) {
1415 err = -EINVAL;
1416 goto err;
1417 }
1418
1419 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1420 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1421 memcpy(rss_key, ucmd.rx_hash_key, len);
1422 break;
1423 }
1424 default:
1425 err = -EOPNOTSUPP;
1426 goto err;
1427 }
1428
1429 if (!ucmd.rx_hash_fields_mask) {
1430 /* special case when this TIR serves as steering entry without hashing */
1431 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1432 goto create_tir;
1433 err = -EINVAL;
1434 goto err;
1435 }
1436
1437 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1438 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1439 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1440 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1441 err = -EINVAL;
1442 goto err;
1443 }
1444
1445 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1446 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1447 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1448 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1449 MLX5_L3_PROT_TYPE_IPV4);
1450 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1451 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1452 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1453 MLX5_L3_PROT_TYPE_IPV6);
1454
1455 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1456 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1457 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1458 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1459 err = -EINVAL;
1460 goto err;
1461 }
1462
1463 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1464 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1465 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1466 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1467 MLX5_L4_PROT_TYPE_TCP);
1468 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1469 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1470 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1471 MLX5_L4_PROT_TYPE_UDP);
1472
1473 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1474 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1475 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1476
1477 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1478 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1479 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1480
1481 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1482 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1483 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1484
1485 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1486 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1487 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1488
1489 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1490
1491create_tir:
1492 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1493
1494 if (err)
1495 goto err;
1496
1497 kvfree(in);
1498 /* qpn is reserved for that QP */
1499 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1500 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1501 return 0;
1502
1503err:
1504 kvfree(in);
1505 return err;
1506}
1507
e126ba97
EC		 1508static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1509 struct ib_qp_init_attr *init_attr,
1510 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1511{
1512 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1513 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1514 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1515 struct mlx5_ib_create_qp_resp resp;
89ea94a7
MG		 1516 struct mlx5_ib_cq *send_cq;
1517 struct mlx5_ib_cq *recv_cq;
1518 unsigned long flags;
cfb5e088 1519 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1520 struct mlx5_ib_create_qp ucmd;
1521 struct mlx5_ib_qp_base *base;
cfb5e088 1522 void *qpc;
09a7d9ec
SM		 1523 u32 *in;
1524 int err;
e126ba97
EC		 1525
1526 mutex_init(&qp->mutex);
1527 spin_lock_init(&qp->sq.lock);
1528 spin_lock_init(&qp->rq.lock);
1529
28d61370
YH		 1530 if (init_attr->rwq_ind_tbl) {
1531 if (!udata)
1532 return -ENOSYS;
1533
1534 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1535 return err;
1536 }
1537
f360d88a 1538 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1539 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1540 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1541 return -EINVAL;
1542 } else {
1543 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1544 }
1545 }
1546
051f2630
LR		 1547 if (init_attr->create_flags &
1548 (IB_QP_CREATE_CROSS_CHANNEL |
1549 IB_QP_CREATE_MANAGED_SEND |
1550 IB_QP_CREATE_MANAGED_RECV)) {
1551 if (!MLX5_CAP_GEN(mdev, cd)) {
1552 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1553 return -EINVAL;
1554 }
1555 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1556 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1557 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1558 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1559 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1560 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1561 }
f0313965
ES		 1562
1563 if (init_attr->qp_type == IB_QPT_UD &&
1564 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1565 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1566 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1567 return -EOPNOTSUPP;
1568 }
1569
358e42ea
MD		 1570 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1571 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1572 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1573 return -EOPNOTSUPP;
1574 }
1575 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1576 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1577 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1578 return -EOPNOTSUPP;
1579 }
1580 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1581 }
1582
e126ba97
EC		 1583 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1584 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1585
e4cc4fa7
NO		 1586 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1587 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1588 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1589 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1590 return -EOPNOTSUPP;
1591 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1592 }
1593
e126ba97
EC		 1594 if (pd && pd->uobject) {
1595 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1596 mlx5_ib_dbg(dev, "copy failed\n");
1597 return -EFAULT;
1598 }
1599
cfb5e088
HA		 1600 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1601 &ucmd, udata->inlen, &uidx);
1602 if (err)
1603 return err;
1604
e126ba97
EC		 1605 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1606 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
c2e53b2c
YH		 1607
1608 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1609 if (init_attr->qp_type != IB_QPT_UD ||
1610 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1611 MLX5_CAP_PORT_TYPE_IB) ||
1612 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1613 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1614 return -EOPNOTSUPP;
1615 }
1616
1617 qp->flags |= MLX5_IB_QP_UNDERLAY;
1618 qp->underlay_qpn = init_attr->source_qpn;
1619 }
e126ba97
EC		 1620 } else {
1621 qp->wq_sig = !!wq_signature;
1622 }
1623
c2e53b2c
YH		 1624 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1625 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1626 &qp->raw_packet_qp.rq.base :
1627 &qp->trans_qp.base;
1628
e126ba97
EC		 1629 qp->has_rq = qp_has_rq(init_attr);
1630 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1631 qp, (pd && pd->uobject) ? &ucmd : NULL);
1632 if (err) {
1633 mlx5_ib_dbg(dev, "err %d\n", err);
1634 return err;
1635 }
1636
1637 if (pd) {
1638 if (pd->uobject) {
938fe83c
SM		 1639 __u32 max_wqes =
1640 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1641 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1642 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1643 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1644 mlx5_ib_dbg(dev, "invalid rq params\n");
1645 return -EINVAL;
1646 }
938fe83c 1647 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1648 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1649 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1650 return -EINVAL;
1651 }
b11a4f9c
HE		 1652 if (init_attr->create_flags &
1653 mlx5_ib_create_qp_sqpn_qp1()) {
1654 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1655 return -EINVAL;
1656 }
0fb2ed66 1657 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1658 &resp, &inlen, base);
e126ba97
EC		 1659 if (err)
1660 mlx5_ib_dbg(dev, "err %d\n", err);
1661 } else {
19098df2 1662 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1663 base);
e126ba97
EC		 1664 if (err)
1665 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1666 }
1667
1668 if (err)
1669 return err;
1670 } else {
1b9a07ee 1671 in = kvzalloc(inlen, GFP_KERNEL);
e126ba97
EC		 1672 if (!in)
1673 return -ENOMEM;
1674
1675 qp->create_type = MLX5_QP_EMPTY;
1676 }
1677
1678 if (is_sqp(init_attr->qp_type))
1679 qp->port = init_attr->port_num;
1680
09a7d9ec
SM		 1681 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1682
1683 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1684 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1685
1686 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1687 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1688 else
09a7d9ec
SM		 1689 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1690
e126ba97
EC		 1691
1692 if (qp->wq_sig)
09a7d9ec 1693 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1694
f360d88a 1695 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1696 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1697
051f2630 1698 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1699 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1700 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1701 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1702 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1703 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1704
e126ba97
EC		 1705 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1706 int rcqe_sz;
1707 int scqe_sz;
1708
1709 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1710 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1711
1712 if (rcqe_sz == 128)
09a7d9ec 1713 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1714 else
09a7d9ec 1715 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1716
1717 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1718 if (scqe_sz == 128)
09a7d9ec 1719 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1720 else
09a7d9ec 1721 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1722 }
1723 }
1724
1725 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1726 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1727 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1728 }
1729
09a7d9ec 1730 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97 1731
3fd3307e 1732 if (qp->sq.wqe_cnt) {
09a7d9ec 1733 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
3fd3307e 1734 } else {
09a7d9ec 1735 MLX5_SET(qpc, qpc, no_sq, 1);
3fd3307e
AK		 1736 if (init_attr->srq &&
1737 init_attr->srq->srq_type == IB_SRQT_TM)
1738 MLX5_SET(qpc, qpc, offload_type,
1739 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1740 }
e126ba97
EC		 1741
1742 /* Set default resources */
1743 switch (init_attr->qp_type) {
1744 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1745 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1746 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1747 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1748 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1749 break;
1750 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1751 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1752 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1753 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1754 break;
1755 default:
1756 if (init_attr->srq) {
09a7d9ec
SM		 1757 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1758 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1759 } else {
09a7d9ec
SM		 1760 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1761 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1762 }
1763 }
1764
1765 if (init_attr->send_cq)
09a7d9ec 1766 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1767
1768 if (init_attr->recv_cq)
09a7d9ec 1769 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1770
09a7d9ec 1771 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1772
09a7d9ec
SM		 1773 /* 0xffffff means we ask to work with cqe version 0 */
1774 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1775 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1776
f0313965
ES		 1777 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1778 if (init_attr->qp_type == IB_QPT_UD &&
1779 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1780 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1781 qp->flags |= MLX5_IB_QP_LSO;
1782 }
cfb5e088 1783
c2e53b2c
YH		 1784 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1785 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 1786 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1787 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1788 err = create_raw_packet_qp(dev, qp, in, pd);
1789 } else {
1790 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1791 }
1792
e126ba97
EC		 1793 if (err) {
1794 mlx5_ib_dbg(dev, "create qp failed\n");
1795 goto err_create;
1796 }
1797
479163f4 1798 kvfree(in);
e126ba97 1799
19098df2 1800 base->container_mibqp = qp;
1801 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1802
89ea94a7
MG		 1803 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1804 &send_cq, &recv_cq);
1805 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1806 mlx5_ib_lock_cqs(send_cq, recv_cq);
1807 /* Maintain device to QPs access, needed for further handling via reset
1808 * flow
1809 */
1810 list_add_tail(&qp->qps_list, &dev->qp_list);
1811 /* Maintain CQ to QPs access, needed for further handling via reset flow
1812 */
1813 if (send_cq)
1814 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1815 if (recv_cq)
1816 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1817 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1818 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1819
e126ba97
EC		 1820 return 0;
1821
1822err_create:
1823 if (qp->create_type == MLX5_QP_USER)
b037c29a 1824 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 1825 else if (qp->create_type == MLX5_QP_KERNEL)
1826 destroy_qp_kernel(dev, qp);
1827
479163f4 1828 kvfree(in);
e126ba97
EC		 1829 return err;
1830}
1831
1832static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1833 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1834{
1835 if (send_cq) {
1836 if (recv_cq) {
1837 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1838 spin_lock(&send_cq->lock);
e126ba97
EC		 1839 spin_lock_nested(&recv_cq->lock,
1840 SINGLE_DEPTH_NESTING);
1841 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1842 spin_lock(&send_cq->lock);
e126ba97
EC		 1843 __acquire(&recv_cq->lock);
1844 } else {
89ea94a7 1845 spin_lock(&recv_cq->lock);
e126ba97
EC		 1846 spin_lock_nested(&send_cq->lock,
1847 SINGLE_DEPTH_NESTING);
1848 }
1849 } else {
89ea94a7 1850 spin_lock(&send_cq->lock);
6a4f139a 1851 __acquire(&recv_cq->lock);
e126ba97
EC		 1852 }
1853 } else if (recv_cq) {
89ea94a7 1854 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1855 __acquire(&send_cq->lock);
1856 } else {
1857 __acquire(&send_cq->lock);
1858 __acquire(&recv_cq->lock);
e126ba97
EC		 1859 }
1860}
1861
1862static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1863 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1864{
1865 if (send_cq) {
1866 if (recv_cq) {
1867 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1868 spin_unlock(&recv_cq->lock);
89ea94a7 1869 spin_unlock(&send_cq->lock);
e126ba97
EC		 1870 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1871 __release(&recv_cq->lock);
89ea94a7 1872 spin_unlock(&send_cq->lock);
e126ba97
EC		 1873 } else {
1874 spin_unlock(&send_cq->lock);
89ea94a7 1875 spin_unlock(&recv_cq->lock);
e126ba97
EC		 1876 }
1877 } else {
6a4f139a 1878 __release(&recv_cq->lock);
89ea94a7 1879 spin_unlock(&send_cq->lock);
e126ba97
EC		 1880 }
1881 } else if (recv_cq) {
6a4f139a 1882 __release(&send_cq->lock);
89ea94a7 1883 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 1884 } else {
1885 __release(&recv_cq->lock);
1886 __release(&send_cq->lock);
e126ba97
EC		 1887 }
1888}
1889
1890static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1891{
1892 return to_mpd(qp->ibqp.pd);
1893}
1894
89ea94a7
MG		 1895static void get_cqs(enum ib_qp_type qp_type,
1896 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 1897 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1898{
89ea94a7 1899 switch (qp_type) {
e126ba97
EC		 1900 case IB_QPT_XRC_TGT:
1901 *send_cq = NULL;
1902 *recv_cq = NULL;
1903 break;
1904 case MLX5_IB_QPT_REG_UMR:
1905 case IB_QPT_XRC_INI:
89ea94a7 1906 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 1907 *recv_cq = NULL;
1908 break;
1909
1910 case IB_QPT_SMI:
d16e91da 1911 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1912 case IB_QPT_RC:
1913 case IB_QPT_UC:
1914 case IB_QPT_UD:
1915 case IB_QPT_RAW_IPV6:
1916 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 1917 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 1918 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1919 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 1920 break;
1921
e126ba97
EC		 1922 case IB_QPT_MAX:
1923 default:
1924 *send_cq = NULL;
1925 *recv_cq = NULL;
1926 break;
1927 }
1928}
1929
ad5f8e96 1930static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 1931 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1932 u8 lag_tx_affinity);
ad5f8e96 1933
e126ba97
EC		 1934static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1935{
1936 struct mlx5_ib_cq *send_cq, *recv_cq;
c2e53b2c 1937 struct mlx5_ib_qp_base *base;
89ea94a7 1938 unsigned long flags;
e126ba97
EC		 1939 int err;
1940
28d61370
YH		 1941 if (qp->ibqp.rwq_ind_tbl) {
1942 destroy_rss_raw_qp_tir(dev, qp);
1943 return;
1944 }
1945
c2e53b2c
YH		 1946 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
1947 qp->flags & MLX5_IB_QP_UNDERLAY) ?
0fb2ed66 1948 &qp->raw_packet_qp.rq.base :
1949 &qp->trans_qp.base;
1950
6aec21f6 1951 if (qp->state != IB_QPS_RESET) {
c2e53b2c
YH		 1952 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
1953 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
ad5f8e96 1954 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 1955 MLX5_CMD_OP_2RST_QP, 0,
1956 NULL, &base->mqp);
ad5f8e96 1957 } else {
0680efa2
AV		 1958 struct mlx5_modify_raw_qp_param raw_qp_param = {
1959 .operation = MLX5_CMD_OP_2RST_QP
1960 };
1961
13eab21f 1962 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 1963 }
1964 if (err)
427c1e7b 1965 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 1966 base->mqp.qpn);
6aec21f6 1967 }
e126ba97 1968
89ea94a7
MG		 1969 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1970 &send_cq, &recv_cq);
1971
1972 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1973 mlx5_ib_lock_cqs(send_cq, recv_cq);
1974 /* del from lists under both locks above to protect reset flow paths */
1975 list_del(&qp->qps_list);
1976 if (send_cq)
1977 list_del(&qp->cq_send_list);
1978
1979 if (recv_cq)
1980 list_del(&qp->cq_recv_list);
e126ba97
EC		 1981
1982 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 1983 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 1984 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1985 if (send_cq != recv_cq)
19098df2 1986 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1987 NULL);
e126ba97 1988 }
89ea94a7
MG		 1989 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1990 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 1991
c2e53b2c
YH		 1992 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
1993 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 1994 destroy_raw_packet_qp(dev, qp);
1995 } else {
1996 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1997 if (err)
1998 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1999 base->mqp.qpn);
2000 }
e126ba97 2001
e126ba97
EC		 2002 if (qp->create_type == MLX5_QP_KERNEL)
2003 destroy_qp_kernel(dev, qp);
2004 else if (qp->create_type == MLX5_QP_USER)
b037c29a 2005 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 2006}
2007
2008static const char *ib_qp_type_str(enum ib_qp_type type)
2009{
2010 switch (type) {
2011 case IB_QPT_SMI:
2012 return "IB_QPT_SMI";
2013 case IB_QPT_GSI:
2014 return "IB_QPT_GSI";
2015 case IB_QPT_RC:
2016 return "IB_QPT_RC";
2017 case IB_QPT_UC:
2018 return "IB_QPT_UC";
2019 case IB_QPT_UD:
2020 return "IB_QPT_UD";
2021 case IB_QPT_RAW_IPV6:
2022 return "IB_QPT_RAW_IPV6";
2023 case IB_QPT_RAW_ETHERTYPE:
2024 return "IB_QPT_RAW_ETHERTYPE";
2025 case IB_QPT_XRC_INI:
2026 return "IB_QPT_XRC_INI";
2027 case IB_QPT_XRC_TGT:
2028 return "IB_QPT_XRC_TGT";
2029 case IB_QPT_RAW_PACKET:
2030 return "IB_QPT_RAW_PACKET";
2031 case MLX5_IB_QPT_REG_UMR:
2032 return "MLX5_IB_QPT_REG_UMR";
2033 case IB_QPT_MAX:
2034 default:
2035 return "Invalid QP type";
2036 }
2037}
2038
2039struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2040 struct ib_qp_init_attr *init_attr,
2041 struct ib_udata *udata)
2042{
2043 struct mlx5_ib_dev *dev;
2044 struct mlx5_ib_qp *qp;
2045 u16 xrcdn = 0;
2046 int err;
2047
2048 if (pd) {
2049 dev = to_mdev(pd->device);
0fb2ed66 2050
2051 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2052 if (!pd->uobject) {
2053 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2054 return ERR_PTR(-EINVAL);
2055 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2056 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2057 return ERR_PTR(-EINVAL);
2058 }
2059 }
09f16cf5
MD		 2060 } else {
2061 /* being cautious here */
2062 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2063 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2064 pr_warn("%s: no PD for transport %s\n", __func__,
2065 ib_qp_type_str(init_attr->qp_type));
2066 return ERR_PTR(-EINVAL);
2067 }
2068 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2069 }
2070
2071 switch (init_attr->qp_type) {
2072 case IB_QPT_XRC_TGT:
2073 case IB_QPT_XRC_INI:
938fe83c 2074 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2075 mlx5_ib_dbg(dev, "XRC not supported\n");
2076 return ERR_PTR(-ENOSYS);
2077 }
2078 init_attr->recv_cq = NULL;
2079 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2080 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2081 init_attr->send_cq = NULL;
2082 }
2083
2084 /* fall through */
0fb2ed66 2085 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2086 case IB_QPT_RC:
2087 case IB_QPT_UC:
2088 case IB_QPT_UD:
2089 case IB_QPT_SMI:
d16e91da 2090 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2091 case MLX5_IB_QPT_REG_UMR:
2092 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2093 if (!qp)
2094 return ERR_PTR(-ENOMEM);
2095
2096 err = create_qp_common(dev, pd, init_attr, udata, qp);
2097 if (err) {
2098 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2099 kfree(qp);
2100 return ERR_PTR(err);
2101 }
2102
2103 if (is_qp0(init_attr->qp_type))
2104 qp->ibqp.qp_num = 0;
2105 else if (is_qp1(init_attr->qp_type))
2106 qp->ibqp.qp_num = 1;
2107 else
19098df2 2108 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2109
2110 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2111 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2112 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2113 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2114
19098df2 2115 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2116
2117 break;
2118
d16e91da
HE		 2119 case IB_QPT_GSI:
2120 return mlx5_ib_gsi_create_qp(pd, init_attr);
2121
e126ba97
EC		 2122 case IB_QPT_RAW_IPV6:
2123 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2124 case IB_QPT_MAX:
2125 default:
2126 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2127 init_attr->qp_type);
2128 /* Don't support raw QPs */
2129 return ERR_PTR(-EINVAL);
2130 }
2131
2132 return &qp->ibqp;
2133}
2134
2135int mlx5_ib_destroy_qp(struct ib_qp *qp)
2136{
2137 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2138 struct mlx5_ib_qp *mqp = to_mqp(qp);
2139
d16e91da
HE		 2140 if (unlikely(qp->qp_type == IB_QPT_GSI))
2141 return mlx5_ib_gsi_destroy_qp(qp);
2142
e126ba97
EC		 2143 destroy_qp_common(dev, mqp);
2144
2145 kfree(mqp);
2146
2147 return 0;
2148}
2149
2150static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2151 int attr_mask)
2152{
2153 u32 hw_access_flags = 0;
2154 u8 dest_rd_atomic;
2155 u32 access_flags;
2156
2157 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2158 dest_rd_atomic = attr->max_dest_rd_atomic;
2159 else
19098df2 2160 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2161
2162 if (attr_mask & IB_QP_ACCESS_FLAGS)
2163 access_flags = attr->qp_access_flags;
2164 else
19098df2 2165 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2166
2167 if (!dest_rd_atomic)
2168 access_flags &= IB_ACCESS_REMOTE_WRITE;
2169
2170 if (access_flags & IB_ACCESS_REMOTE_READ)
2171 hw_access_flags |= MLX5_QP_BIT_RRE;
2172 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2173 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2174 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2175 hw_access_flags |= MLX5_QP_BIT_RWE;
2176
2177 return cpu_to_be32(hw_access_flags);
2178}
2179
2180enum {
2181 MLX5_PATH_FLAG_FL = 1 << 0,
2182 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2183 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2184};
2185
2186static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2187{
2188 if (rate == IB_RATE_PORT_CURRENT) {
2189 return 0;
2190 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2191 return -EINVAL;
2192 } else {
2193 while (rate != IB_RATE_2_5_GBPS &&
2194 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2195 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2196 --rate;
2197 }
2198
2199 return rate + MLX5_STAT_RATE_OFFSET;
2200}
2201
75850d0b 2202static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2203 struct mlx5_ib_sq *sq, u8 sl)
2204{
2205 void *in;
2206 void *tisc;
2207 int inlen;
2208 int err;
2209
2210 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2211 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 2212 if (!in)
2213 return -ENOMEM;
2214
2215 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2216
2217 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2218 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2219
2220 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2221
2222 kvfree(in);
2223
2224 return err;
2225}
2226
13eab21f
AH		 2227static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2228 struct mlx5_ib_sq *sq, u8 tx_affinity)
2229{
2230 void *in;
2231 void *tisc;
2232 int inlen;
2233 int err;
2234
2235 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2236 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 2237 if (!in)
2238 return -ENOMEM;
2239
2240 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2241
2242 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2243 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2244
2245 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2246
2247 kvfree(in);
2248
2249 return err;
2250}
2251
75850d0b 2252static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
90898850 2253 const struct rdma_ah_attr *ah,
e126ba97 2254 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2255 u32 path_flags, const struct ib_qp_attr *attr,
2256 bool alt)
e126ba97 2257{
d8966fcd 2258 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 2259 int err;
ed88451e 2260 enum ib_gid_type gid_type;
d8966fcd
DC		 2261 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2262 u8 sl = rdma_ah_get_sl(ah);
e126ba97 2263
e126ba97 2264 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2265 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2266 attr->pkey_index);
e126ba97 2267
d8966fcd
DC		 2268 if (ah_flags & IB_AH_GRH) {
2269 if (grh->sgid_index >=
938fe83c 2270 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2271 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 2272 grh->sgid_index,
938fe83c 2273 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2274 return -EINVAL;
2275 }
2811ba51 2276 }
44c58487
DC		 2277
2278 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 2279 if (!(ah_flags & IB_AH_GRH))
2811ba51 2280 return -EINVAL;
d8966fcd 2281 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
ed88451e
MD		 2282 &gid_type);
2283 if (err)
2284 return err;
44c58487 2285 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2811ba51 2286 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
d8966fcd
DC		 2287 grh->sgid_index);
2288 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
ed88451e 2289 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
d8966fcd 2290 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2811ba51 2291 } else {
d3ae2bde
NO		 2292 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2293 path->fl_free_ar |=
2294 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
d8966fcd
DC		 2295 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2296 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2297 if (ah_flags & IB_AH_GRH)
2811ba51 2298 path->grh_mlid |= 1 << 7;
d8966fcd 2299 path->dci_cfi_prio_sl = sl & 0xf;
2811ba51
AS		 2300 }
2301
d8966fcd
DC		 2302 if (ah_flags & IB_AH_GRH) {
2303 path->mgid_index = grh->sgid_index;
2304 path->hop_limit = grh->hop_limit;
e126ba97 2305 path->tclass_flowlabel =
d8966fcd
DC		 2306 cpu_to_be32((grh->traffic_class << 20) |
2307 (grh->flow_label));
2308 memcpy(path->rgid, grh->dgid.raw, 16);
e126ba97
EC		 2309 }
2310
d8966fcd 2311 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 2312 if (err < 0)
2313 return err;
2314 path->static_rate = err;
2315 path->port = port;
2316
e126ba97 2317 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2318 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2319
75850d0b 2320 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2321 return modify_raw_packet_eth_prio(dev->mdev,
2322 &qp->raw_packet_qp.sq,
d8966fcd 2323 sl & 0xf);
75850d0b 2324
e126ba97
EC		 2325 return 0;
2326}
2327
2328static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2329 [MLX5_QP_STATE_INIT] = {
2330 [MLX5_QP_STATE_INIT] = {
2331 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2332 MLX5_QP_OPTPAR_RAE |
2333 MLX5_QP_OPTPAR_RWE |
2334 MLX5_QP_OPTPAR_PKEY_INDEX |
2335 MLX5_QP_OPTPAR_PRI_PORT,
2336 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2337 MLX5_QP_OPTPAR_PKEY_INDEX |
2338 MLX5_QP_OPTPAR_PRI_PORT,
2339 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2340 MLX5_QP_OPTPAR_Q_KEY |
2341 MLX5_QP_OPTPAR_PRI_PORT,
2342 },
2343 [MLX5_QP_STATE_RTR] = {
2344 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2345 MLX5_QP_OPTPAR_RRE |
2346 MLX5_QP_OPTPAR_RAE |
2347 MLX5_QP_OPTPAR_RWE |
2348 MLX5_QP_OPTPAR_PKEY_INDEX,
2349 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2350 MLX5_QP_OPTPAR_RWE |
2351 MLX5_QP_OPTPAR_PKEY_INDEX,
2352 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2353 MLX5_QP_OPTPAR_Q_KEY,
2354 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2355 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2356 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2357 MLX5_QP_OPTPAR_RRE |
2358 MLX5_QP_OPTPAR_RAE |
2359 MLX5_QP_OPTPAR_RWE |
2360 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2361 },
2362 },
2363 [MLX5_QP_STATE_RTR] = {
2364 [MLX5_QP_STATE_RTS] = {
2365 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2366 MLX5_QP_OPTPAR_RRE |
2367 MLX5_QP_OPTPAR_RAE |
2368 MLX5_QP_OPTPAR_RWE |
2369 MLX5_QP_OPTPAR_PM_STATE |
2370 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2371 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2372 MLX5_QP_OPTPAR_RWE |
2373 MLX5_QP_OPTPAR_PM_STATE,
2374 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2375 },
2376 },
2377 [MLX5_QP_STATE_RTS] = {
2378 [MLX5_QP_STATE_RTS] = {
2379 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2380 MLX5_QP_OPTPAR_RAE |
2381 MLX5_QP_OPTPAR_RWE |
2382 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2383 MLX5_QP_OPTPAR_PM_STATE |
2384 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2385 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2386 MLX5_QP_OPTPAR_PM_STATE |
2387 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2388 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2389 MLX5_QP_OPTPAR_SRQN |
2390 MLX5_QP_OPTPAR_CQN_RCV,
2391 },
2392 },
2393 [MLX5_QP_STATE_SQER] = {
2394 [MLX5_QP_STATE_RTS] = {
2395 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2396 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2397 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2398 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2399 MLX5_QP_OPTPAR_RWE |
2400 MLX5_QP_OPTPAR_RAE |
2401 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2402 },
2403 },
2404};
2405
2406static int ib_nr_to_mlx5_nr(int ib_mask)
2407{
2408 switch (ib_mask) {
2409 case IB_QP_STATE:
2410 return 0;
2411 case IB_QP_CUR_STATE:
2412 return 0;
2413 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2414 return 0;
2415 case IB_QP_ACCESS_FLAGS:
2416 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2417 MLX5_QP_OPTPAR_RAE;
2418 case IB_QP_PKEY_INDEX:
2419 return MLX5_QP_OPTPAR_PKEY_INDEX;
2420 case IB_QP_PORT:
2421 return MLX5_QP_OPTPAR_PRI_PORT;
2422 case IB_QP_QKEY:
2423 return MLX5_QP_OPTPAR_Q_KEY;
2424 case IB_QP_AV:
2425 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2426 MLX5_QP_OPTPAR_PRI_PORT;
2427 case IB_QP_PATH_MTU:
2428 return 0;
2429 case IB_QP_TIMEOUT:
2430 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2431 case IB_QP_RETRY_CNT:
2432 return MLX5_QP_OPTPAR_RETRY_COUNT;
2433 case IB_QP_RNR_RETRY:
2434 return MLX5_QP_OPTPAR_RNR_RETRY;
2435 case IB_QP_RQ_PSN:
2436 return 0;
2437 case IB_QP_MAX_QP_RD_ATOMIC:
2438 return MLX5_QP_OPTPAR_SRA_MAX;
2439 case IB_QP_ALT_PATH:
2440 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2441 case IB_QP_MIN_RNR_TIMER:
2442 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2443 case IB_QP_SQ_PSN:
2444 return 0;
2445 case IB_QP_MAX_DEST_RD_ATOMIC:
2446 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2447 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2448 case IB_QP_PATH_MIG_STATE:
2449 return MLX5_QP_OPTPAR_PM_STATE;
2450 case IB_QP_CAP:
2451 return 0;
2452 case IB_QP_DEST_QPN:
2453 return 0;
2454 }
2455 return 0;
2456}
2457
2458static int ib_mask_to_mlx5_opt(int ib_mask)
2459{
2460 int result = 0;
2461 int i;
2462
2463 for (i = 0; i < 8 * sizeof(int); i++) {
2464 if ((1 << i) & ib_mask)
2465 result |= ib_nr_to_mlx5_nr(1 << i);
2466 }
2467
2468 return result;
2469}
2470
eb49ab0c
AV		 2471static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2472 struct mlx5_ib_rq *rq, int new_state,
2473 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2474{
2475 void *in;
2476 void *rqc;
2477 int inlen;
2478 int err;
2479
2480 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 2481 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2482 if (!in)
2483 return -ENOMEM;
2484
2485 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2486
2487 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2488 MLX5_SET(rqc, rqc, state, new_state);
2489
eb49ab0c
AV		 2490 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2491 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2492 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 2493 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 2494 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2495 } else
2496 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2497 dev->ib_dev.name);
2498 }
2499
2500 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 2501 if (err)
2502 goto out;
2503
2504 rq->state = new_state;
2505
2506out:
2507 kvfree(in);
2508 return err;
2509}
2510
2511static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
7d29f349
BW		 2512 struct mlx5_ib_sq *sq,
2513 int new_state,
2514 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2515{
7d29f349
BW		 2516 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2517 u32 old_rate = ibqp->rate_limit;
2518 u32 new_rate = old_rate;
2519 u16 rl_index = 0;
ad5f8e96 2520 void *in;
2521 void *sqc;
2522 int inlen;
2523 int err;
2524
2525 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 2526 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2527 if (!in)
2528 return -ENOMEM;
2529
2530 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2531
2532 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2533 MLX5_SET(sqc, sqc, state, new_state);
2534
7d29f349
BW		 2535 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2536 if (new_state != MLX5_SQC_STATE_RDY)
2537 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2538 __func__);
2539 else
2540 new_rate = raw_qp_param->rate_limit;
2541 }
2542
2543 if (old_rate != new_rate) {
2544 if (new_rate) {
2545 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2546 if (err) {
2547 pr_err("Failed configuring rate %u: %d\n",
2548 new_rate, err);
2549 goto out;
2550 }
2551 }
2552
2553 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2554 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2555 }
2556
ad5f8e96 2557 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 2558 if (err) {
2559 /* Remove new rate from table if failed */
2560 if (new_rate &&
2561 old_rate != new_rate)
2562 mlx5_rl_remove_rate(dev, new_rate);
ad5f8e96 2563 goto out;
7d29f349
BW		 2564 }
2565
2566 /* Only remove the old rate after new rate was set */
2567 if ((old_rate &&
2568 (old_rate != new_rate)) ||
2569 (new_state != MLX5_SQC_STATE_RDY))
2570 mlx5_rl_remove_rate(dev, old_rate);
ad5f8e96 2571
7d29f349 2572 ibqp->rate_limit = new_rate;
ad5f8e96 2573 sq->state = new_state;
2574
2575out:
2576 kvfree(in);
2577 return err;
2578}
2579
2580static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2581 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2582 u8 tx_affinity)
ad5f8e96 2583{
2584 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2585 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2586 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 2587 int modify_rq = !!qp->rq.wqe_cnt;
2588 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 2589 int rq_state;
2590 int sq_state;
2591 int err;
2592
0680efa2 2593 switch (raw_qp_param->operation) {
ad5f8e96 2594 case MLX5_CMD_OP_RST2INIT_QP:
2595 rq_state = MLX5_RQC_STATE_RDY;
2596 sq_state = MLX5_SQC_STATE_RDY;
2597 break;
2598 case MLX5_CMD_OP_2ERR_QP:
2599 rq_state = MLX5_RQC_STATE_ERR;
2600 sq_state = MLX5_SQC_STATE_ERR;
2601 break;
2602 case MLX5_CMD_OP_2RST_QP:
2603 rq_state = MLX5_RQC_STATE_RST;
2604 sq_state = MLX5_SQC_STATE_RST;
2605 break;
ad5f8e96 2606 case MLX5_CMD_OP_RTR2RTS_QP:
2607 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 2608 if (raw_qp_param->set_mask ==
2609 MLX5_RAW_QP_RATE_LIMIT) {
2610 modify_rq = 0;
2611 sq_state = sq->state;
2612 } else {
2613 return raw_qp_param->set_mask ? -EINVAL : 0;
2614 }
2615 break;
2616 case MLX5_CMD_OP_INIT2INIT_QP:
2617 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 2618 if (raw_qp_param->set_mask)
2619 return -EINVAL;
2620 else
2621 return 0;
ad5f8e96 2622 default:
2623 WARN_ON(1);
2624 return -EINVAL;
2625 }
2626
7d29f349
BW		 2627 if (modify_rq) {
2628 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
ad5f8e96 2629 if (err)
2630 return err;
2631 }
2632
7d29f349 2633 if (modify_sq) {
13eab21f
AH		 2634 if (tx_affinity) {
2635 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2636 tx_affinity);
2637 if (err)
2638 return err;
2639 }
2640
7d29f349 2641 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
13eab21f 2642 }
ad5f8e96 2643
2644 return 0;
2645}
2646
e126ba97
EC		 2647static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2648 const struct ib_qp_attr *attr, int attr_mask,
2649 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2650{
427c1e7b 2651 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2652 [MLX5_QP_STATE_RST] = {
2653 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2654 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2655 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2656 },
2657 [MLX5_QP_STATE_INIT] = {
2658 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2659 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2660 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2661 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2662 },
2663 [MLX5_QP_STATE_RTR] = {
2664 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2665 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2666 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2667 },
2668 [MLX5_QP_STATE_RTS] = {
2669 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2670 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2671 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2672 },
2673 [MLX5_QP_STATE_SQD] = {
2674 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2675 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2676 },
2677 [MLX5_QP_STATE_SQER] = {
2678 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2679 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2680 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2681 },
2682 [MLX5_QP_STATE_ERR] = {
2683 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2684 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2685 }
2686 };
2687
e126ba97
EC		 2688 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2689 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2690 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2691 struct mlx5_ib_cq *send_cq, *recv_cq;
2692 struct mlx5_qp_context *context;
e126ba97 2693 struct mlx5_ib_pd *pd;
eb49ab0c 2694 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 2695 enum mlx5_qp_state mlx5_cur, mlx5_new;
2696 enum mlx5_qp_optpar optpar;
e126ba97
EC		 2697 int mlx5_st;
2698 int err;
427c1e7b 2699 u16 op;
13eab21f 2700 u8 tx_affinity = 0;
e126ba97 2701
1a412fb1
SM		 2702 context = kzalloc(sizeof(*context), GFP_KERNEL);
2703 if (!context)
e126ba97
EC		 2704 return -ENOMEM;
2705
e126ba97 2706 err = to_mlx5_st(ibqp->qp_type);
158abf86
HE		 2707 if (err < 0) {
2708 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2709 goto out;
158abf86 2710 }
e126ba97
EC		 2711
2712 context->flags = cpu_to_be32(err << 16);
2713
2714 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2715 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2716 } else {
2717 switch (attr->path_mig_state) {
2718 case IB_MIG_MIGRATED:
2719 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2720 break;
2721 case IB_MIG_REARM:
2722 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2723 break;
2724 case IB_MIG_ARMED:
2725 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2726 break;
2727 }
2728 }
2729
13eab21f
AH		 2730 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2731 if ((ibqp->qp_type == IB_QPT_RC) ||
2732 (ibqp->qp_type == IB_QPT_UD &&
2733 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2734 (ibqp->qp_type == IB_QPT_UC) ||
2735 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2736 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2737 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2738 if (mlx5_lag_is_active(dev->mdev)) {
2739 tx_affinity = (unsigned int)atomic_add_return(1,
2740 &dev->roce.next_port) %
2741 MLX5_MAX_PORTS + 1;
2742 context->flags |= cpu_to_be32(tx_affinity << 24);
2743 }
2744 }
2745 }
2746
d16e91da 2747 if (is_sqp(ibqp->qp_type)) {
e126ba97 2748 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
c2e53b2c
YH		 2749 } else if ((ibqp->qp_type == IB_QPT_UD &&
2750 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
e126ba97
EC		 2751 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2752 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2753 } else if (attr_mask & IB_QP_PATH_MTU) {
2754 if (attr->path_mtu < IB_MTU_256 ||
2755 attr->path_mtu > IB_MTU_4096) {
2756 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2757 err = -EINVAL;
2758 goto out;
2759 }
938fe83c
SM		 2760 context->mtu_msgmax = (attr->path_mtu << 5) |
2761 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2762 }
2763
2764 if (attr_mask & IB_QP_DEST_QPN)
2765 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2766
2767 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 2768 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 2769
2770 /* todo implement counter_index functionality */
2771
2772 if (is_sqp(ibqp->qp_type))
2773 context->pri_path.port = qp->port;
2774
2775 if (attr_mask & IB_QP_PORT)
2776 context->pri_path.port = attr->port_num;
2777
2778 if (attr_mask & IB_QP_AV) {
75850d0b 2779 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 2780 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 2781 attr_mask, 0, attr, false);
e126ba97
EC		 2782 if (err)
2783 goto out;
2784 }
2785
2786 if (attr_mask & IB_QP_TIMEOUT)
2787 context->pri_path.ackto_lt |= attr->timeout << 3;
2788
2789 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2790 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2791 &context->alt_path,
f879ee8d
AS		 2792 attr->alt_port_num,
2793 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2794 0, attr, true);
e126ba97
EC		 2795 if (err)
2796 goto out;
2797 }
2798
2799 pd = get_pd(qp);
89ea94a7
MG		 2800 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2801 &send_cq, &recv_cq);
e126ba97
EC		 2802
2803 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2804 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2805 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2806 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2807
2808 if (attr_mask & IB_QP_RNR_RETRY)
2809 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2810
2811 if (attr_mask & IB_QP_RETRY_CNT)
2812 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2813
2814 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2815 if (attr->max_rd_atomic)
2816 context->params1 |=
2817 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2818 }
2819
2820 if (attr_mask & IB_QP_SQ_PSN)
2821 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2822
2823 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2824 if (attr->max_dest_rd_atomic)
2825 context->params2 |=
2826 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2827 }
2828
2829 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2830 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2831
2832 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2833 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2834
2835 if (attr_mask & IB_QP_RQ_PSN)
2836 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2837
2838 if (attr_mask & IB_QP_QKEY)
2839 context->qkey = cpu_to_be32(attr->qkey);
2840
2841 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2842 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2843
0837e86a
MB		 2844 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2845 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2846 qp->port) - 1;
c2e53b2c
YH		 2847
2848 /* Underlay port should be used - index 0 function per port */
2849 if (qp->flags & MLX5_IB_QP_UNDERLAY)
2850 port_num = 0;
2851
eb49ab0c 2852 mibport = &dev->port[port_num];
0837e86a 2853 context->qp_counter_set_usr_page |=
e1f24a79 2854 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
0837e86a
MB		 2855 }
2856
e126ba97
EC		 2857 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2858 context->sq_crq_size |= cpu_to_be16(1 << 4);
2859
b11a4f9c
HE		 2860 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2861 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 2862
2863 mlx5_cur = to_mlx5_state(cur_state);
2864 mlx5_new = to_mlx5_state(new_state);
2865 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 2866 if (mlx5_st < 0)
e126ba97
EC		 2867 goto out;
2868
427c1e7b 2869 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2870 !optab[mlx5_cur][mlx5_new])
2871 goto out;
2872
2873 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 2874 optpar = ib_mask_to_mlx5_opt(attr_mask);
2875 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 2876
c2e53b2c
YH		 2877 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2878 qp->flags & MLX5_IB_QP_UNDERLAY) {
0680efa2
AV		 2879 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2880
2881 raw_qp_param.operation = op;
eb49ab0c 2882 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
e1f24a79 2883 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
eb49ab0c
AV		 2884 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2885 }
7d29f349
BW		 2886
2887 if (attr_mask & IB_QP_RATE_LIMIT) {
2888 raw_qp_param.rate_limit = attr->rate_limit;
2889 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2890 }
2891
13eab21f 2892 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 2893 } else {
1a412fb1 2894 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 2895 &base->mqp);
0680efa2
AV		 2896 }
2897
e126ba97
EC		 2898 if (err)
2899 goto out;
2900
2901 qp->state = new_state;
2902
2903 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 2904 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 2905 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 2906 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 2907 if (attr_mask & IB_QP_PORT)
2908 qp->port = attr->port_num;
2909 if (attr_mask & IB_QP_ALT_PATH)
19098df2 2910 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 2911
2912 /*
2913 * If we moved a kernel QP to RESET, clean up all old CQ
2914 * entries and reinitialize the QP.
2915 */
2916 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 2917 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2918 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2919 if (send_cq != recv_cq)
19098df2 2920 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 2921
2922 qp->rq.head = 0;
2923 qp->rq.tail = 0;
2924 qp->sq.head = 0;
2925 qp->sq.tail = 0;
2926 qp->sq.cur_post = 0;
2927 qp->sq.last_poll = 0;
2928 qp->db.db[MLX5_RCV_DBR] = 0;
2929 qp->db.db[MLX5_SND_DBR] = 0;
2930 }
2931
2932out:
1a412fb1 2933 kfree(context);
e126ba97
EC		 2934 return err;
2935}
2936
2937int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2938 int attr_mask, struct ib_udata *udata)
2939{
2940 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2941 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 2942 enum ib_qp_type qp_type;
e126ba97
EC		 2943 enum ib_qp_state cur_state, new_state;
2944 int err = -EINVAL;
2945 int port;
2811ba51 2946 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 2947
28d61370
YH		 2948 if (ibqp->rwq_ind_tbl)
2949 return -ENOSYS;
2950
d16e91da
HE		 2951 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2952 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2953
2954 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2955 IB_QPT_GSI : ibqp->qp_type;
2956
e126ba97
EC		 2957 mutex_lock(&qp->mutex);
2958
2959 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2960 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2961
2811ba51
AS		 2962 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2963 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2964 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2965 }
2966
c2e53b2c
YH		 2967 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
2968 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
2969 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
2970 attr_mask);
2971 goto out;
2972 }
2973 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
d16e91da 2974 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 2975 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2976 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 2977 goto out;
158abf86 2978 }
e126ba97
EC		 2979
2980 if ((attr_mask & IB_QP_PORT) &&
938fe83c 2981 (attr->port_num == 0 ||
158abf86
HE		 2982 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2983 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2984 attr->port_num, dev->num_ports);
e126ba97 2985 goto out;
158abf86 2986 }
e126ba97
EC		 2987
2988 if (attr_mask & IB_QP_PKEY_INDEX) {
2989 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 2990 if (attr->pkey_index >=
158abf86
HE		 2991 dev->mdev->port_caps[port - 1].pkey_table_len) {
2992 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2993 attr->pkey_index);
e126ba97 2994 goto out;
158abf86 2995 }
e126ba97
EC		 2996 }
2997
2998 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 2999 attr->max_rd_atomic >
158abf86
HE		 3000 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3001 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3002 attr->max_rd_atomic);
e126ba97 3003 goto out;
158abf86 3004 }
e126ba97
EC		 3005
3006 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 3007 attr->max_dest_rd_atomic >
158abf86
HE		 3008 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3009 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3010 attr->max_dest_rd_atomic);
e126ba97 3011 goto out;
158abf86 3012 }
e126ba97
EC		 3013
3014 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3015 err = 0;
3016 goto out;
3017 }
3018
3019 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
3020
3021out:
3022 mutex_unlock(&qp->mutex);
3023 return err;
3024}
3025
3026static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3027{
3028 struct mlx5_ib_cq *cq;
3029 unsigned cur;
3030
3031 cur = wq->head - wq->tail;
3032 if (likely(cur + nreq < wq->max_post))
3033 return 0;
3034
3035 cq = to_mcq(ib_cq);
3036 spin_lock(&cq->lock);
3037 cur = wq->head - wq->tail;
3038 spin_unlock(&cq->lock);
3039
3040 return cur + nreq >= wq->max_post;
3041}
3042
3043static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3044 u64 remote_addr, u32 rkey)
3045{
3046 rseg->raddr = cpu_to_be64(remote_addr);
3047 rseg->rkey = cpu_to_be32(rkey);
3048 rseg->reserved = 0;
3049}
3050
f0313965
ES		 3051static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3052 struct ib_send_wr *wr, void *qend,
3053 struct mlx5_ib_qp *qp, int *size)
3054{
3055 void *seg = eseg;
3056
3057 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3058
3059 if (wr->send_flags & IB_SEND_IP_CSUM)
3060 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3061 MLX5_ETH_WQE_L4_CSUM;
3062
3063 seg += sizeof(struct mlx5_wqe_eth_seg);
3064 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3065
3066 if (wr->opcode == IB_WR_LSO) {
3067 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2b31f7ae 3068 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
f0313965
ES		 3069 u64 left, leftlen, copysz;
3070 void *pdata = ud_wr->header;
3071
3072 left = ud_wr->hlen;
3073 eseg->mss = cpu_to_be16(ud_wr->mss);
2b31f7ae 3074 eseg->inline_hdr.sz = cpu_to_be16(left);
f0313965
ES		 3075
3076 /*
3077 * check if there is space till the end of queue, if yes,
3078 * copy all in one shot, otherwise copy till the end of queue,
3079 * rollback and than the copy the left
3080 */
2b31f7ae 3081 leftlen = qend - (void *)eseg->inline_hdr.start;
f0313965
ES		 3082 copysz = min_t(u64, leftlen, left);
3083
3084 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3085
3086 if (likely(copysz > size_of_inl_hdr_start)) {
3087 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3088 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3089 }
3090
3091 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3092 seg = mlx5_get_send_wqe(qp, 0);
3093 left -= copysz;
3094 pdata += copysz;
3095 memcpy(seg, pdata, left);
3096 seg += ALIGN(left, 16);
3097 *size += ALIGN(left, 16) / 16;
3098 }
3099 }
3100
3101 return seg;
3102}
3103
e126ba97
EC		 3104static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3105 struct ib_send_wr *wr)
3106{
e622f2f4
CH		 3107 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3108 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3109 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3110}
3111
3112static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3113{
3114 dseg->byte_count = cpu_to_be32(sg->length);
3115 dseg->lkey = cpu_to_be32(sg->lkey);
3116 dseg->addr = cpu_to_be64(sg->addr);
3117}
3118
31616255 3119static u64 get_xlt_octo(u64 bytes)
e126ba97 3120{
31616255
AK		 3121 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3122 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3123}
3124
3125static __be64 frwr_mkey_mask(void)
3126{
3127 u64 result;
3128
3129 result = MLX5_MKEY_MASK_LEN |
3130 MLX5_MKEY_MASK_PAGE_SIZE |
3131 MLX5_MKEY_MASK_START_ADDR |
3132 MLX5_MKEY_MASK_EN_RINVAL |
3133 MLX5_MKEY_MASK_KEY |
3134 MLX5_MKEY_MASK_LR |
3135 MLX5_MKEY_MASK_LW |
3136 MLX5_MKEY_MASK_RR |
3137 MLX5_MKEY_MASK_RW |
3138 MLX5_MKEY_MASK_A |
3139 MLX5_MKEY_MASK_SMALL_FENCE |
3140 MLX5_MKEY_MASK_FREE;
3141
3142 return cpu_to_be64(result);
3143}
3144
e6631814
SG		 3145static __be64 sig_mkey_mask(void)
3146{
3147 u64 result;
3148
3149 result = MLX5_MKEY_MASK_LEN |
3150 MLX5_MKEY_MASK_PAGE_SIZE |
3151 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3152 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3153 MLX5_MKEY_MASK_EN_RINVAL |
3154 MLX5_MKEY_MASK_KEY |
3155 MLX5_MKEY_MASK_LR |
3156 MLX5_MKEY_MASK_LW |
3157 MLX5_MKEY_MASK_RR |
3158 MLX5_MKEY_MASK_RW |
3159 MLX5_MKEY_MASK_SMALL_FENCE |
3160 MLX5_MKEY_MASK_FREE |
3161 MLX5_MKEY_MASK_BSF_EN;
3162
3163 return cpu_to_be64(result);
3164}
3165
8a187ee5 3166static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3167 struct mlx5_ib_mr *mr)
8a187ee5 3168{
31616255 3169 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3170
3171 memset(umr, 0, sizeof(*umr));
b005d316 3172
8a187ee5 3173 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
31616255 3174 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3175 umr->mkey_mask = frwr_mkey_mask();
3176}
3177
dd01e66a 3178static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3179{
3180 memset(umr, 0, sizeof(*umr));
dd01e66a 3181 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3182 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3183}
3184
31616255 3185static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 3186{
3187 u64 result;
3188
31616255 3189 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 3190 MLX5_MKEY_MASK_FREE;
3191
968e78dd
HE		 3192 return cpu_to_be64(result);
3193}
3194
31616255 3195static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 3196{
3197 u64 result;
3198
3199 result = MLX5_MKEY_MASK_FREE;
3200
3201 return cpu_to_be64(result);
3202}
3203
56e11d62
NO		 3204static __be64 get_umr_update_translation_mask(void)
3205{
3206 u64 result;
3207
3208 result = MLX5_MKEY_MASK_LEN |
3209 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 3210 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 3211
3212 return cpu_to_be64(result);
3213}
3214
31616255 3215static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 3216{
3217 u64 result;
3218
31616255
AK		 3219 result = MLX5_MKEY_MASK_LR |
3220 MLX5_MKEY_MASK_LW |
56e11d62 3221 MLX5_MKEY_MASK_RR |
31616255
AK		 3222 MLX5_MKEY_MASK_RW;
3223
3224 if (atomic)
3225 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 3226
3227 return cpu_to_be64(result);
3228}
3229
3230static __be64 get_umr_update_pd_mask(void)
3231{
3232 u64 result;
3233
31616255 3234 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 3235
3236 return cpu_to_be64(result);
3237}
3238
e126ba97 3239static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
578e7264 3240 struct ib_send_wr *wr, int atomic)
e126ba97 3241{
e622f2f4 3242 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3243
3244 memset(umr, 0, sizeof(*umr));
3245
968e78dd
HE		 3246 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3247 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3248 else
3249 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3250
31616255
AK		 3251 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3252 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3253 u64 offset = get_xlt_octo(umrwr->offset);
3254
3255 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3256 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3257 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 3258 }
31616255
AK		 3259 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3260 umr->mkey_mask |= get_umr_update_translation_mask();
3261 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3262 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3263 umr->mkey_mask |= get_umr_update_pd_mask();
3264 }
3265 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3266 umr->mkey_mask |= get_umr_enable_mr_mask();
3267 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3268 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 3269
3270 if (!wr->num_sge)
968e78dd 3271 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3272}
3273
3274static u8 get_umr_flags(int acc)
3275{
3276 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3277 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3278 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3279 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3280 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3281}
3282
8a187ee5
SG		 3283static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3284 struct mlx5_ib_mr *mr,
3285 u32 key, int access)
3286{
3287 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3288
3289 memset(seg, 0, sizeof(*seg));
b005d316 3290
ec22eb53 3291 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3292 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3293 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3294 /* KLMs take twice the size of MTTs */
3295 ndescs *= 2;
3296
3297 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3298 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3299 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3300 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3301 seg->len = cpu_to_be64(mr->ibmr.length);
3302 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3303}
3304
dd01e66a 3305static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3306{
3307 memset(seg, 0, sizeof(*seg));
dd01e66a 3308 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3309}
3310
3311static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3312{
e622f2f4 3313 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3314
e126ba97 3315 memset(seg, 0, sizeof(*seg));
31616255 3316 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 3317 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 3318
968e78dd 3319 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 3320 if (umrwr->pd)
3321 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3322 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3323 !umrwr->length)
3324 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3325
3326 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 3327 seg->len = cpu_to_be64(umrwr->length);
3328 seg->log2_page_size = umrwr->page_shift;
746b5583 3329 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3330 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3331}
3332
8a187ee5
SG		 3333static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3334 struct mlx5_ib_mr *mr,
3335 struct mlx5_ib_pd *pd)
3336{
3337 int bcount = mr->desc_size * mr->ndescs;
3338
3339 dseg->addr = cpu_to_be64(mr->desc_map);
3340 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3341 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3342}
3343
e126ba97
EC		 3344static __be32 send_ieth(struct ib_send_wr *wr)
3345{
3346 switch (wr->opcode) {
3347 case IB_WR_SEND_WITH_IMM:
3348 case IB_WR_RDMA_WRITE_WITH_IMM:
3349 return wr->ex.imm_data;
3350
3351 case IB_WR_SEND_WITH_INV:
3352 return cpu_to_be32(wr->ex.invalidate_rkey);
3353
3354 default:
3355 return 0;
3356 }
3357}
3358
3359static u8 calc_sig(void *wqe, int size)
3360{
3361 u8 *p = wqe;
3362 u8 res = 0;
3363 int i;
3364
3365 for (i = 0; i < size; i++)
3366 res ^= p[i];
3367
3368 return ~res;
3369}
3370
3371static u8 wq_sig(void *wqe)
3372{
3373 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3374}
3375
3376static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3377 void *wqe, int *sz)
3378{
3379 struct mlx5_wqe_inline_seg *seg;
3380 void *qend = qp->sq.qend;
3381 void *addr;
3382 int inl = 0;
3383 int copy;
3384 int len;
3385 int i;
3386
3387 seg = wqe;
3388 wqe += sizeof(*seg);
3389 for (i = 0; i < wr->num_sge; i++) {
3390 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3391 len = wr->sg_list[i].length;
3392 inl += len;
3393
3394 if (unlikely(inl > qp->max_inline_data))
3395 return -ENOMEM;
3396
3397 if (unlikely(wqe + len > qend)) {
3398 copy = qend - wqe;
3399 memcpy(wqe, addr, copy);
3400 addr += copy;
3401 len -= copy;
3402 wqe = mlx5_get_send_wqe(qp, 0);
3403 }
3404 memcpy(wqe, addr, len);
3405 wqe += len;
3406 }
3407
3408 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3409
3410 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3411
3412 return 0;
3413}
3414
e6631814
SG		 3415static u16 prot_field_size(enum ib_signature_type type)
3416{
3417 switch (type) {
3418 case IB_SIG_TYPE_T10_DIF:
3419 return MLX5_DIF_SIZE;
3420 default:
3421 return 0;
3422 }
3423}
3424
3425static u8 bs_selector(int block_size)
3426{
3427 switch (block_size) {
3428 case 512: return 0x1;
3429 case 520: return 0x2;
3430 case 4096: return 0x3;
3431 case 4160: return 0x4;
3432 case 1073741824: return 0x5;
3433 default: return 0;
3434 }
3435}
3436
78eda2bb
SG		 3437static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3438 struct mlx5_bsf_inl *inl)
e6631814 3439{
142537f4
SG		 3440 /* Valid inline section and allow BSF refresh */
3441 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3442 MLX5_BSF_REFRESH_DIF);
3443 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3444 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3445 /* repeating block */
3446 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3447 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3448 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3449
78eda2bb
SG		 3450 if (domain->sig.dif.ref_remap)
3451 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3452
78eda2bb
SG		 3453 if (domain->sig.dif.app_escape) {
3454 if (domain->sig.dif.ref_escape)
3455 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3456 else
3457 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3458 }
3459
78eda2bb
SG		 3460 inl->dif_app_bitmask_check =
3461 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3462}
3463
3464static int mlx5_set_bsf(struct ib_mr *sig_mr,
3465 struct ib_sig_attrs *sig_attrs,
3466 struct mlx5_bsf *bsf, u32 data_size)
3467{
3468 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3469 struct mlx5_bsf_basic *basic = &bsf->basic;
3470 struct ib_sig_domain *mem = &sig_attrs->mem;
3471 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3472
c7f44fbd 3473 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3474
3475 /* Basic + Extended + Inline */
3476 basic->bsf_size_sbs = 1 << 7;
3477 /* Input domain check byte mask */
3478 basic->check_byte_mask = sig_attrs->check_mask;
3479 basic->raw_data_size = cpu_to_be32(data_size);
3480
3481 /* Memory domain */
e6631814 3482 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3483 case IB_SIG_TYPE_NONE:
3484 break;
e6631814 3485 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3486 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3487 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3488 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3489 break;
3490 default:
3491 return -EINVAL;
3492 }
e6631814 3493
78eda2bb
SG		 3494 /* Wire domain */
3495 switch (sig_attrs->wire.sig_type) {
3496 case IB_SIG_TYPE_NONE:
3497 break;
3498 case IB_SIG_TYPE_T10_DIF:
e6631814 3499 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3500 mem->sig_type == wire->sig_type) {
e6631814 3501 /* Same block structure */
142537f4 3502 basic->bsf_size_sbs |= 1 << 4;
e6631814 3503 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3504 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3505 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3506 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3507 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3508 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3509 } else
3510 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3511
142537f4 3512 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3513 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3514 break;
e6631814
SG		 3515 default:
3516 return -EINVAL;
3517 }
3518
3519 return 0;
3520}
3521
e622f2f4
CH		 3522static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3523 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3524{
e622f2f4
CH		 3525 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3526 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3527 struct mlx5_bsf *bsf;
e622f2f4
CH		 3528 u32 data_len = wr->wr.sg_list->length;
3529 u32 data_key = wr->wr.sg_list->lkey;
3530 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3531 int ret;
3532 int wqe_size;
3533
e622f2f4
CH		 3534 if (!wr->prot ||
3535 (data_key == wr->prot->lkey &&
3536 data_va == wr->prot->addr &&
3537 data_len == wr->prot->length)) {
e6631814
SG		 3538 /**
3539 * Source domain doesn't contain signature information
5c273b16 3540 * or data and protection are interleaved in memory.
e6631814
SG		 3541 * So need construct:
3542 * ------------------
3543 * | data_klm |
3544 * ------------------
3545 * | BSF |
3546 * ------------------
3547 **/
3548 struct mlx5_klm *data_klm = *seg;
3549
3550 data_klm->bcount = cpu_to_be32(data_len);
3551 data_klm->key = cpu_to_be32(data_key);
3552 data_klm->va = cpu_to_be64(data_va);
3553 wqe_size = ALIGN(sizeof(*data_klm), 64);
3554 } else {
3555 /**
3556 * Source domain contains signature information
3557 * So need construct a strided block format:
3558 * ---------------------------
3559 * | stride_block_ctrl |
3560 * ---------------------------
3561 * | data_klm |
3562 * ---------------------------
3563 * | prot_klm |
3564 * ---------------------------
3565 * | BSF |
3566 * ---------------------------
3567 **/
3568 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3569 struct mlx5_stride_block_entry *data_sentry;
3570 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3571 u32 prot_key = wr->prot->lkey;
3572 u64 prot_va = wr->prot->addr;
e6631814
SG		 3573 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3574 int prot_size;
3575
3576 sblock_ctrl = *seg;
3577 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3578 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3579
3580 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3581 if (!prot_size) {
3582 pr_err("Bad block size given: %u\n", block_size);
3583 return -EINVAL;
3584 }
3585 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3586 prot_size);
3587 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3588 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3589 sblock_ctrl->num_entries = cpu_to_be16(2);
3590
3591 data_sentry->bcount = cpu_to_be16(block_size);
3592 data_sentry->key = cpu_to_be32(data_key);
3593 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3594 data_sentry->stride = cpu_to_be16(block_size);
3595
e6631814
SG		 3596 prot_sentry->bcount = cpu_to_be16(prot_size);
3597 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3598 prot_sentry->va = cpu_to_be64(prot_va);
3599 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3600
e6631814
SG		 3601 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3602 sizeof(*prot_sentry), 64);
3603 }
3604
3605 *seg += wqe_size;
3606 *size += wqe_size / 16;
3607 if (unlikely((*seg == qp->sq.qend)))
3608 *seg = mlx5_get_send_wqe(qp, 0);
3609
3610 bsf = *seg;
3611 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3612 if (ret)
3613 return -EINVAL;
3614
3615 *seg += sizeof(*bsf);
3616 *size += sizeof(*bsf) / 16;
3617 if (unlikely((*seg == qp->sq.qend)))
3618 *seg = mlx5_get_send_wqe(qp, 0);
3619
3620 return 0;
3621}
3622
3623static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
31616255 3624 struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 3625 u32 length, u32 pdn)
3626{
e622f2f4 3627 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3628 u32 sig_key = sig_mr->rkey;
d5436ba0 3629 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3630
3631 memset(seg, 0, sizeof(*seg));
3632
e622f2f4 3633 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 3634 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 3635 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3636 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3637 MLX5_MKEY_BSF_EN | pdn);
3638 seg->len = cpu_to_be64(length);
31616255 3639 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 3640 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3641}
3642
3643static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3644 u32 size)
e6631814
SG		 3645{
3646 memset(umr, 0, sizeof(*umr));
3647
3648 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 3649 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 3650 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3651 umr->mkey_mask = sig_mkey_mask();
3652}
3653
3654
e622f2f4 3655static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3656 void **seg, int *size)
3657{
e622f2f4
CH		 3658 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3659 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 3660 u32 pdn = get_pd(qp)->pdn;
31616255 3661 u32 xlt_size;
e6631814
SG		 3662 int region_len, ret;
3663
e622f2f4
CH		 3664 if (unlikely(wr->wr.num_sge != 1) ||
3665 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3666 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3667 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3668 return -EINVAL;
3669
3670 /* length of the protected region, data + protection */
e622f2f4
CH		 3671 region_len = wr->wr.sg_list->length;
3672 if (wr->prot &&
3673 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3674 wr->prot->addr != wr->wr.sg_list->addr ||
3675 wr->prot->length != wr->wr.sg_list->length))
3676 region_len += wr->prot->length;
e6631814
SG		 3677
3678 /**
3679 * KLM octoword size - if protection was provided
3680 * then we use strided block format (3 octowords),
3681 * else we use single KLM (1 octoword)
3682 **/
31616255 3683 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 3684
31616255 3685 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 3686 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3687 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3688 if (unlikely((*seg == qp->sq.qend)))
3689 *seg = mlx5_get_send_wqe(qp, 0);
3690
31616255 3691 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 3692 *seg += sizeof(struct mlx5_mkey_seg);
3693 *size += sizeof(struct mlx5_mkey_seg) / 16;
3694 if (unlikely((*seg == qp->sq.qend)))
3695 *seg = mlx5_get_send_wqe(qp, 0);
3696
3697 ret = set_sig_data_segment(wr, qp, seg, size);
3698 if (ret)
3699 return ret;
3700
d5436ba0 3701 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3702 return 0;
3703}
3704
3705static int set_psv_wr(struct ib_sig_domain *domain,
3706 u32 psv_idx, void **seg, int *size)
3707{
3708 struct mlx5_seg_set_psv *psv_seg = *seg;
3709
3710 memset(psv_seg, 0, sizeof(*psv_seg));
3711 psv_seg->psv_num = cpu_to_be32(psv_idx);
3712 switch (domain->sig_type) {
78eda2bb
SG		 3713 case IB_SIG_TYPE_NONE:
3714 break;
e6631814
SG		 3715 case IB_SIG_TYPE_T10_DIF:
3716 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3717 domain->sig.dif.app_tag);
3718 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3719 break;
e6631814 3720 default:
12bbf1ea
LR		 3721 pr_err("Bad signature type (%d) is given.\n",
3722 domain->sig_type);
3723 return -EINVAL;
e6631814
SG		 3724 }
3725
78eda2bb
SG		 3726 *seg += sizeof(*psv_seg);
3727 *size += sizeof(*psv_seg) / 16;
3728
e6631814
SG		 3729 return 0;
3730}
3731
8a187ee5
SG		 3732static int set_reg_wr(struct mlx5_ib_qp *qp,
3733 struct ib_reg_wr *wr,
3734 void **seg, int *size)
3735{
3736 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3737 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3738
3739 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3740 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3741 "Invalid IB_SEND_INLINE send flag\n");
3742 return -EINVAL;
3743 }
3744
3745 set_reg_umr_seg(*seg, mr);
3746 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3747 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3748 if (unlikely((*seg == qp->sq.qend)))
3749 *seg = mlx5_get_send_wqe(qp, 0);
3750
3751 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3752 *seg += sizeof(struct mlx5_mkey_seg);
3753 *size += sizeof(struct mlx5_mkey_seg) / 16;
3754 if (unlikely((*seg == qp->sq.qend)))
3755 *seg = mlx5_get_send_wqe(qp, 0);
3756
3757 set_reg_data_seg(*seg, mr, pd);
3758 *seg += sizeof(struct mlx5_wqe_data_seg);
3759 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3760
3761 return 0;
3762}
3763
dd01e66a 3764static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 3765{
dd01e66a 3766 set_linv_umr_seg(*seg);
e126ba97
EC		 3767 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3768 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3769 if (unlikely((*seg == qp->sq.qend)))
3770 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 3771 set_linv_mkey_seg(*seg);
e126ba97
EC		 3772 *seg += sizeof(struct mlx5_mkey_seg);
3773 *size += sizeof(struct mlx5_mkey_seg) / 16;
3774 if (unlikely((*seg == qp->sq.qend)))
3775 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 3776}
3777
3778static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3779{
3780 __be32 *p = NULL;
3781 int tidx = idx;
3782 int i, j;
3783
3784 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3785 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3786 if ((i & 0xf) == 0) {
3787 void *buf = mlx5_get_send_wqe(qp, tidx);
3788 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3789 p = buf;
3790 j = 0;
3791 }
3792 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3793 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3794 be32_to_cpu(p[j + 3]));
3795 }
3796}
3797
6e5eadac
SG		 3798static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3799 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 3800 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 3801 int *size, int nreq)
3802{
b2a232d2
LR		 3803 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3804 return -ENOMEM;
6e5eadac
SG		 3805
3806 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3807 *seg = mlx5_get_send_wqe(qp, *idx);
3808 *ctrl = *seg;
3809 *(uint32_t *)(*seg + 8) = 0;
3810 (*ctrl)->imm = send_ieth(wr);
3811 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3812 (wr->send_flags & IB_SEND_SIGNALED ?
3813 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3814 (wr->send_flags & IB_SEND_SOLICITED ?
3815 MLX5_WQE_CTRL_SOLICITED : 0);
3816
3817 *seg += sizeof(**ctrl);
3818 *size = sizeof(**ctrl) / 16;
3819
b2a232d2 3820 return 0;
6e5eadac
SG		 3821}
3822
3823static void finish_wqe(struct mlx5_ib_qp *qp,
3824 struct mlx5_wqe_ctrl_seg *ctrl,
3825 u8 size, unsigned idx, u64 wr_id,
6e8484c5 3826 int nreq, u8 fence, u32 mlx5_opcode)
6e5eadac
SG		 3827{
3828 u8 opmod = 0;
3829
3830 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3831 mlx5_opcode | ((u32)opmod << 24));
19098df2 3832 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac 3833 ctrl->fm_ce_se |= fence;
6e5eadac
SG		 3834 if (unlikely(qp->wq_sig))
3835 ctrl->signature = wq_sig(ctrl);
3836
3837 qp->sq.wrid[idx] = wr_id;
3838 qp->sq.w_list[idx].opcode = mlx5_opcode;
3839 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3840 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3841 qp->sq.w_list[idx].next = qp->sq.cur_post;
3842}
3843
3844
e126ba97
EC		 3845int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3846 struct ib_send_wr **bad_wr)
3847{
3848 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3849 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 3850 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 3851 struct mlx5_ib_qp *qp;
e6631814 3852 struct mlx5_ib_mr *mr;
e126ba97
EC		 3853 struct mlx5_wqe_data_seg *dpseg;
3854 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 3855 struct mlx5_bf *bf;
e126ba97 3856 int uninitialized_var(size);
d16e91da 3857 void *qend;
e126ba97 3858 unsigned long flags;
e126ba97
EC		 3859 unsigned idx;
3860 int err = 0;
e126ba97
EC		 3861 int num_sge;
3862 void *seg;
3863 int nreq;
3864 int i;
3865 u8 next_fence = 0;
e126ba97
EC		 3866 u8 fence;
3867
d16e91da
HE		 3868 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3869 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3870
3871 qp = to_mqp(ibqp);
5fe9dec0 3872 bf = &qp->bf;
d16e91da
HE		 3873 qend = qp->sq.qend;
3874
e126ba97
EC		 3875 spin_lock_irqsave(&qp->sq.lock, flags);
3876
89ea94a7
MG		 3877 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3878 err = -EIO;
3879 *bad_wr = wr;
3880 nreq = 0;
3881 goto out;
3882 }
3883
e126ba97 3884 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 3885 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 3886 mlx5_ib_warn(dev, "\n");
3887 err = -EINVAL;
3888 *bad_wr = wr;
3889 goto out;
3890 }
3891
6e5eadac
SG		 3892 num_sge = wr->num_sge;
3893 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 3894 mlx5_ib_warn(dev, "\n");
24be409b 3895 err = -EINVAL;
e126ba97
EC		 3896 *bad_wr = wr;
3897 goto out;
3898 }
3899
6e5eadac
SG		 3900 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3901 if (err) {
e126ba97
EC		 3902 mlx5_ib_warn(dev, "\n");
3903 err = -ENOMEM;
3904 *bad_wr = wr;
3905 goto out;
3906 }
3907
6e8484c5
MG		 3908 if (wr->opcode == IB_WR_LOCAL_INV ||
3909 wr->opcode == IB_WR_REG_MR) {
3910 fence = dev->umr_fence;
3911 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3912 } else if (wr->send_flags & IB_SEND_FENCE) {
3913 if (qp->next_fence)
3914 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
3915 else
3916 fence = MLX5_FENCE_MODE_FENCE;
3917 } else {
3918 fence = qp->next_fence;
3919 }
3920
e126ba97
EC		 3921 switch (ibqp->qp_type) {
3922 case IB_QPT_XRC_INI:
3923 xrc = seg;
e126ba97
EC		 3924 seg += sizeof(*xrc);
3925 size += sizeof(*xrc) / 16;
3926 /* fall through */
3927 case IB_QPT_RC:
3928 switch (wr->opcode) {
3929 case IB_WR_RDMA_READ:
3930 case IB_WR_RDMA_WRITE:
3931 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3932 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3933 rdma_wr(wr)->rkey);
f241e749 3934 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 3935 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3936 break;
3937
3938 case IB_WR_ATOMIC_CMP_AND_SWP:
3939 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 3940 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 3941 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3942 err = -ENOSYS;
3943 *bad_wr = wr;
3944 goto out;
e126ba97
EC		 3945
3946 case IB_WR_LOCAL_INV:
e126ba97
EC		 3947 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3948 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 3949 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 3950 num_sge = 0;
3951 break;
3952
8a187ee5 3953 case IB_WR_REG_MR:
8a187ee5
SG		 3954 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3955 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3956 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3957 if (err) {
3958 *bad_wr = wr;
3959 goto out;
3960 }
3961 num_sge = 0;
3962 break;
3963
e6631814
SG		 3964 case IB_WR_REG_SIG_MR:
3965 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 3966 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 3967
3968 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3969 err = set_sig_umr_wr(wr, qp, &seg, &size);
3970 if (err) {
3971 mlx5_ib_warn(dev, "\n");
3972 *bad_wr = wr;
3973 goto out;
3974 }
3975
6e8484c5
MG		 3976 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3977 fence, MLX5_OPCODE_UMR);
e6631814
SG		 3978 /*
3979 * SET_PSV WQEs are not signaled and solicited
3980 * on error
3981 */
3982 wr->send_flags &= ~IB_SEND_SIGNALED;
3983 wr->send_flags |= IB_SEND_SOLICITED;
3984 err = begin_wqe(qp, &seg, &ctrl, wr,
3985 &idx, &size, nreq);
3986 if (err) {
3987 mlx5_ib_warn(dev, "\n");
3988 err = -ENOMEM;
3989 *bad_wr = wr;
3990 goto out;
3991 }
3992
e622f2f4 3993 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 3994 mr->sig->psv_memory.psv_idx, &seg,
3995 &size);
3996 if (err) {
3997 mlx5_ib_warn(dev, "\n");
3998 *bad_wr = wr;
3999 goto out;
4000 }
4001
6e8484c5
MG		 4002 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4003 fence, MLX5_OPCODE_SET_PSV);
e6631814
SG		 4004 err = begin_wqe(qp, &seg, &ctrl, wr,
4005 &idx, &size, nreq);
4006 if (err) {
4007 mlx5_ib_warn(dev, "\n");
4008 err = -ENOMEM;
4009 *bad_wr = wr;
4010 goto out;
4011 }
4012
e622f2f4 4013 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 4014 mr->sig->psv_wire.psv_idx, &seg,
4015 &size);
4016 if (err) {
4017 mlx5_ib_warn(dev, "\n");
4018 *bad_wr = wr;
4019 goto out;
4020 }
4021
6e8484c5
MG		 4022 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4023 fence, MLX5_OPCODE_SET_PSV);
4024 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e6631814
SG		 4025 num_sge = 0;
4026 goto skip_psv;
4027
e126ba97
EC		 4028 default:
4029 break;
4030 }
4031 break;
4032
4033 case IB_QPT_UC:
4034 switch (wr->opcode) {
4035 case IB_WR_RDMA_WRITE:
4036 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4037 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4038 rdma_wr(wr)->rkey);
e126ba97
EC		 4039 seg += sizeof(struct mlx5_wqe_raddr_seg);
4040 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4041 break;
4042
4043 default:
4044 break;
4045 }
4046 break;
4047
e126ba97 4048 case IB_QPT_SMI:
1e0e50b6
MG		 4049 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4050 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4051 err = -EPERM;
4052 *bad_wr = wr;
4053 goto out;
4054 }
f6b1ee34 4055 /* fall through */
d16e91da 4056 case MLX5_IB_QPT_HW_GSI:
e126ba97 4057 set_datagram_seg(seg, wr);
f241e749 4058 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 4059 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4060 if (unlikely((seg == qend)))
4061 seg = mlx5_get_send_wqe(qp, 0);
4062 break;
f0313965
ES		 4063 case IB_QPT_UD:
4064 set_datagram_seg(seg, wr);
4065 seg += sizeof(struct mlx5_wqe_datagram_seg);
4066 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4067
4068 if (unlikely((seg == qend)))
4069 seg = mlx5_get_send_wqe(qp, 0);
4070
4071 /* handle qp that supports ud offload */
4072 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4073 struct mlx5_wqe_eth_pad *pad;
e126ba97 4074
f0313965
ES		 4075 pad = seg;
4076 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4077 seg += sizeof(struct mlx5_wqe_eth_pad);
4078 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4079
4080 seg = set_eth_seg(seg, wr, qend, qp, &size);
4081
4082 if (unlikely((seg == qend)))
4083 seg = mlx5_get_send_wqe(qp, 0);
4084 }
4085 break;
e126ba97
EC		 4086 case MLX5_IB_QPT_REG_UMR:
4087 if (wr->opcode != MLX5_IB_WR_UMR) {
4088 err = -EINVAL;
4089 mlx5_ib_warn(dev, "bad opcode\n");
4090 goto out;
4091 }
4092 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4093 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
578e7264 4094 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
e126ba97
EC		 4095 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4096 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4097 if (unlikely((seg == qend)))
4098 seg = mlx5_get_send_wqe(qp, 0);
4099 set_reg_mkey_segment(seg, wr);
4100 seg += sizeof(struct mlx5_mkey_seg);
4101 size += sizeof(struct mlx5_mkey_seg) / 16;
4102 if (unlikely((seg == qend)))
4103 seg = mlx5_get_send_wqe(qp, 0);
4104 break;
4105
4106 default:
4107 break;
4108 }
4109
4110 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4111 int uninitialized_var(sz);
4112
4113 err = set_data_inl_seg(qp, wr, seg, &sz);
4114 if (unlikely(err)) {
4115 mlx5_ib_warn(dev, "\n");
4116 *bad_wr = wr;
4117 goto out;
4118 }
e126ba97
EC		 4119 size += sz;
4120 } else {
4121 dpseg = seg;
4122 for (i = 0; i < num_sge; i++) {
4123 if (unlikely(dpseg == qend)) {
4124 seg = mlx5_get_send_wqe(qp, 0);
4125 dpseg = seg;
4126 }
4127 if (likely(wr->sg_list[i].length)) {
4128 set_data_ptr_seg(dpseg, wr->sg_list + i);
4129 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4130 dpseg++;
4131 }
4132 }
4133 }
4134
6e8484c5
MG		 4135 qp->next_fence = next_fence;
4136 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
6e5eadac 4137 mlx5_ib_opcode[wr->opcode]);
e6631814 4138skip_psv:
e126ba97
EC		 4139 if (0)
4140 dump_wqe(qp, idx, size);
4141 }
4142
4143out:
4144 if (likely(nreq)) {
4145 qp->sq.head += nreq;
4146
4147 /* Make sure that descriptors are written before
4148 * updating doorbell record and ringing the doorbell
4149 */
4150 wmb();
4151
4152 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4153
ada388f7
EC		 4154 /* Make sure doorbell record is visible to the HCA before
4155 * we hit doorbell */
4156 wmb();
4157
5fe9dec0
EC		 4158 /* currently we support only regular doorbells */
4159 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4160 /* Make sure doorbells don't leak out of SQ spinlock
4161 * and reach the HCA out of order.
4162 */
4163 mmiowb();
e126ba97 4164 bf->offset ^= bf->buf_size;
e126ba97
EC		 4165 }
4166
4167 spin_unlock_irqrestore(&qp->sq.lock, flags);
4168
4169 return err;
4170}
4171
4172static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4173{
4174 sig->signature = calc_sig(sig, size);
4175}
4176
4177int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4178 struct ib_recv_wr **bad_wr)
4179{
4180 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4181 struct mlx5_wqe_data_seg *scat;
4182 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4183 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4184 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4185 unsigned long flags;
4186 int err = 0;
4187 int nreq;
4188 int ind;
4189 int i;
4190
d16e91da
HE		 4191 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4192 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4193
e126ba97
EC		 4194 spin_lock_irqsave(&qp->rq.lock, flags);
4195
89ea94a7
MG		 4196 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4197 err = -EIO;
4198 *bad_wr = wr;
4199 nreq = 0;
4200 goto out;
4201 }
4202
e126ba97
EC		 4203 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4204
4205 for (nreq = 0; wr; nreq++, wr = wr->next) {
4206 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4207 err = -ENOMEM;
4208 *bad_wr = wr;
4209 goto out;
4210 }
4211
4212 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4213 err = -EINVAL;
4214 *bad_wr = wr;
4215 goto out;
4216 }
4217
4218 scat = get_recv_wqe(qp, ind);
4219 if (qp->wq_sig)
4220 scat++;
4221
4222 for (i = 0; i < wr->num_sge; i++)
4223 set_data_ptr_seg(scat + i, wr->sg_list + i);
4224
4225 if (i < qp->rq.max_gs) {
4226 scat[i].byte_count = 0;
4227 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4228 scat[i].addr = 0;
4229 }
4230
4231 if (qp->wq_sig) {
4232 sig = (struct mlx5_rwqe_sig *)scat;
4233 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4234 }
4235
4236 qp->rq.wrid[ind] = wr->wr_id;
4237
4238 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4239 }
4240
4241out:
4242 if (likely(nreq)) {
4243 qp->rq.head += nreq;
4244
4245 /* Make sure that descriptors are written before
4246 * doorbell record.
4247 */
4248 wmb();
4249
4250 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4251 }
4252
4253 spin_unlock_irqrestore(&qp->rq.lock, flags);
4254
4255 return err;
4256}
4257
4258static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4259{
4260 switch (mlx5_state) {
4261 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4262 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4263 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4264 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4265 case MLX5_QP_STATE_SQ_DRAINING:
4266 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4267 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4268 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4269 default: return -1;
4270 }
4271}
4272
4273static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4274{
4275 switch (mlx5_mig_state) {
4276 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4277 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4278 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4279 default: return -1;
4280 }
4281}
4282
4283static int to_ib_qp_access_flags(int mlx5_flags)
4284{
4285 int ib_flags = 0;
4286
4287 if (mlx5_flags & MLX5_QP_BIT_RRE)
4288 ib_flags |= IB_ACCESS_REMOTE_READ;
4289 if (mlx5_flags & MLX5_QP_BIT_RWE)
4290 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4291 if (mlx5_flags & MLX5_QP_BIT_RAE)
4292 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4293
4294 return ib_flags;
4295}
4296
38349389 4297static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
d8966fcd 4298 struct rdma_ah_attr *ah_attr,
38349389 4299 struct mlx5_qp_path *path)
e126ba97 4300{
9603b61d 4301 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97 4302
d8966fcd 4303 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 4304
44c58487 4305 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
d8966fcd
DC		 4306 rdma_ah_set_port_num(ah_attr, path->port);
4307 if (rdma_ah_get_port_num(ah_attr) == 0 ||
4308 rdma_ah_get_port_num(ah_attr) > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 4309 return;
4310
d8966fcd
DC		 4311 rdma_ah_set_port_num(ah_attr, path->port);
4312 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4313
4314 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4315 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4316 rdma_ah_set_static_rate(ah_attr,
4317 path->static_rate ? path->static_rate - 5 : 0);
4318 if (path->grh_mlid & (1 << 7)) {
4319 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4320
4321 rdma_ah_set_grh(ah_attr, NULL,
4322 tc_fl & 0xfffff,
4323 path->mgid_index,
4324 path->hop_limit,
4325 (tc_fl >> 20) & 0xff);
4326 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
e126ba97
EC		 4327 }
4328}
4329
6d2f89df 4330static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4331 struct mlx5_ib_sq *sq,
4332 u8 *sq_state)
4333{
4334 void *out;
4335 void *sqc;
4336 int inlen;
4337 int err;
4338
4339 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
1b9a07ee 4340 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4341 if (!out)
4342 return -ENOMEM;
4343
4344 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4345 if (err)
4346 goto out;
4347
4348 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4349 *sq_state = MLX5_GET(sqc, sqc, state);
4350 sq->state = *sq_state;
4351
4352out:
4353 kvfree(out);
4354 return err;
4355}
4356
4357static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4358 struct mlx5_ib_rq *rq,
4359 u8 *rq_state)
4360{
4361 void *out;
4362 void *rqc;
4363 int inlen;
4364 int err;
4365
4366 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 4367 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4368 if (!out)
4369 return -ENOMEM;
4370
4371 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4372 if (err)
4373 goto out;
4374
4375 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4376 *rq_state = MLX5_GET(rqc, rqc, state);
4377 rq->state = *rq_state;
4378
4379out:
4380 kvfree(out);
4381 return err;
4382}
4383
4384static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4385 struct mlx5_ib_qp *qp, u8 *qp_state)
4386{
4387 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4388 [MLX5_RQC_STATE_RST] = {
4389 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4390 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4391 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4392 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4393 },
4394 [MLX5_RQC_STATE_RDY] = {
4395 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4396 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4397 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4398 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4399 },
4400 [MLX5_RQC_STATE_ERR] = {
4401 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4402 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4403 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4404 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4405 },
4406 [MLX5_RQ_STATE_NA] = {
4407 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4408 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4409 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4410 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4411 },
4412 };
4413
4414 *qp_state = sqrq_trans[rq_state][sq_state];
4415
4416 if (*qp_state == MLX5_QP_STATE_BAD) {
4417 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4418 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4419 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4420 return -EINVAL;
4421 }
4422
4423 if (*qp_state == MLX5_QP_STATE)
4424 *qp_state = qp->state;
4425
4426 return 0;
4427}
4428
4429static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4430 struct mlx5_ib_qp *qp,
4431 u8 *raw_packet_qp_state)
4432{
4433 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4434 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4435 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4436 int err;
4437 u8 sq_state = MLX5_SQ_STATE_NA;
4438 u8 rq_state = MLX5_RQ_STATE_NA;
4439
4440 if (qp->sq.wqe_cnt) {
4441 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4442 if (err)
4443 return err;
4444 }
4445
4446 if (qp->rq.wqe_cnt) {
4447 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4448 if (err)
4449 return err;
4450 }
4451
4452 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4453 raw_packet_qp_state);
4454}
4455
4456static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4457 struct ib_qp_attr *qp_attr)
e126ba97 4458{
09a7d9ec 4459 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 4460 struct mlx5_qp_context *context;
4461 int mlx5_state;
09a7d9ec 4462 u32 *outb;
e126ba97
EC		 4463 int err = 0;
4464
09a7d9ec 4465 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4466 if (!outb)
4467 return -ENOMEM;
4468
19098df2 4469 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 4470 outlen);
e126ba97 4471 if (err)
6d2f89df 4472 goto out;
e126ba97 4473
09a7d9ec
SM		 4474 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4475 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4476
e126ba97
EC		 4477 mlx5_state = be32_to_cpu(context->flags) >> 28;
4478
4479 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4480 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4481 qp_attr->path_mig_state =
4482 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4483 qp_attr->qkey = be32_to_cpu(context->qkey);
4484 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4485 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4486 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4487 qp_attr->qp_access_flags =
4488 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4489
4490 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
38349389
DC		 4491 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4492 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4493 qp_attr->alt_pkey_index =
4494 be16_to_cpu(context->alt_path.pkey_index);
d8966fcd
DC		 4495 qp_attr->alt_port_num =
4496 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
e126ba97
EC		 4497 }
4498
d3ae2bde 4499 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4500 qp_attr->port_num = context->pri_path.port;
4501
4502 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4503 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4504
4505 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4506
4507 qp_attr->max_dest_rd_atomic =
4508 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4509 qp_attr->min_rnr_timer =
4510 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4511 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4512 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4513 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4514 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4515
4516out:
4517 kfree(outb);
4518 return err;
4519}
4520
4521int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4522 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4523{
4524 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4525 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4526 int err = 0;
4527 u8 raw_packet_qp_state;
4528
28d61370
YH		 4529 if (ibqp->rwq_ind_tbl)
4530 return -ENOSYS;
4531
d16e91da
HE		 4532 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4533 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4534 qp_init_attr);
4535
c2e53b2c
YH		 4536 /* Not all of output fields are applicable, make sure to zero them */
4537 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4538 memset(qp_attr, 0, sizeof(*qp_attr));
4539
6d2f89df 4540 mutex_lock(&qp->mutex);
4541
c2e53b2c
YH		 4542 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4543 qp->flags & MLX5_IB_QP_UNDERLAY) {
6d2f89df 4544 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4545 if (err)
4546 goto out;
4547 qp->state = raw_packet_qp_state;
4548 qp_attr->port_num = 1;
4549 } else {
4550 err = query_qp_attr(dev, qp, qp_attr);
4551 if (err)
4552 goto out;
4553 }
4554
4555 qp_attr->qp_state = qp->state;
e126ba97
EC		 4556 qp_attr->cur_qp_state = qp_attr->qp_state;
4557 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4558 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4559
4560 if (!ibqp->uobject) {
0540d814 4561 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4562 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4563 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4564 } else {
4565 qp_attr->cap.max_send_wr = 0;
4566 qp_attr->cap.max_send_sge = 0;
4567 }
4568
0540d814
NO		 4569 qp_init_attr->qp_type = ibqp->qp_type;
4570 qp_init_attr->recv_cq = ibqp->recv_cq;
4571 qp_init_attr->send_cq = ibqp->send_cq;
4572 qp_init_attr->srq = ibqp->srq;
4573 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4574
4575 qp_init_attr->cap = qp_attr->cap;
4576
4577 qp_init_attr->create_flags = 0;
4578 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4579 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4580
051f2630
LR		 4581 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4582 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4583 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4584 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4585 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4586 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4587 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4588 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4589
e126ba97
EC		 4590 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4591 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4592
e126ba97
EC		 4593out:
4594 mutex_unlock(&qp->mutex);
4595 return err;
4596}
4597
4598struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4599 struct ib_ucontext *context,
4600 struct ib_udata *udata)
4601{
4602 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4603 struct mlx5_ib_xrcd *xrcd;
4604 int err;
4605
938fe83c 4606 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4607 return ERR_PTR(-ENOSYS);
4608
4609 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4610 if (!xrcd)
4611 return ERR_PTR(-ENOMEM);
4612
9603b61d 4613 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4614 if (err) {
4615 kfree(xrcd);
4616 return ERR_PTR(-ENOMEM);
4617 }
4618
4619 return &xrcd->ibxrcd;
4620}
4621
4622int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4623{
4624 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4625 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4626 int err;
4627
9603b61d 4628 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4629 if (err) {
4630 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4631 return err;
4632 }
4633
4634 kfree(xrcd);
4635
4636 return 0;
4637}
79b20a6c 4638
350d0e4c
YH		 4639static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4640{
4641 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4642 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4643 struct ib_event event;
4644
4645 if (rwq->ibwq.event_handler) {
4646 event.device = rwq->ibwq.device;
4647 event.element.wq = &rwq->ibwq;
4648 switch (type) {
4649 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4650 event.event = IB_EVENT_WQ_FATAL;
4651 break;
4652 default:
4653 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4654 return;
4655 }
4656
4657 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4658 }
4659}
4660
03404e8a
MG		 4661static int set_delay_drop(struct mlx5_ib_dev *dev)
4662{
4663 int err = 0;
4664
4665 mutex_lock(&dev->delay_drop.lock);
4666 if (dev->delay_drop.activate)
4667 goto out;
4668
4669 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
4670 if (err)
4671 goto out;
4672
4673 dev->delay_drop.activate = true;
4674out:
4675 mutex_unlock(&dev->delay_drop.lock);
fe248c3a
MG		 4676
4677 if (!err)
4678 atomic_inc(&dev->delay_drop.rqs_cnt);
03404e8a
MG		 4679 return err;
4680}
4681
79b20a6c
YH		 4682static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4683 struct ib_wq_init_attr *init_attr)
4684{
4685 struct mlx5_ib_dev *dev;
4be6da1e 4686 int has_net_offloads;
79b20a6c
YH		 4687 __be64 *rq_pas0;
4688 void *in;
4689 void *rqc;
4690 void *wq;
4691 int inlen;
4692 int err;
4693
4694 dev = to_mdev(pd->device);
4695
4696 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 4697 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 4698 if (!in)
4699 return -ENOMEM;
4700
4701 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4702 MLX5_SET(rqc, rqc, mem_rq_type,
4703 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4704 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4705 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4706 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4707 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4708 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4709 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4710 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4711 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4712 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4713 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4714 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4715 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4716 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4717 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 4718 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 4719 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 4720 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 4721 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4722 err = -EOPNOTSUPP;
4723 goto out;
4724 }
4725 } else {
4726 MLX5_SET(rqc, rqc, vsd, 1);
4727 }
4be6da1e
NO		 4728 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4729 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4730 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4731 err = -EOPNOTSUPP;
4732 goto out;
4733 }
4734 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4735 }
03404e8a
MG		 4736 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4737 if (!(dev->ib_dev.attrs.raw_packet_caps &
4738 IB_RAW_PACKET_CAP_DELAY_DROP)) {
4739 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4740 err = -EOPNOTSUPP;
4741 goto out;
4742 }
4743 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4744 }
79b20a6c
YH		 4745 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4746 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 4747 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
03404e8a
MG		 4748 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4749 err = set_delay_drop(dev);
4750 if (err) {
4751 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4752 err);
4753 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4754 } else {
4755 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4756 }
4757 }
b1f74a84 4758out:
79b20a6c
YH		 4759 kvfree(in);
4760 return err;
4761}
4762
4763static int set_user_rq_size(struct mlx5_ib_dev *dev,
4764 struct ib_wq_init_attr *wq_init_attr,
4765 struct mlx5_ib_create_wq *ucmd,
4766 struct mlx5_ib_rwq *rwq)
4767{
4768 /* Sanity check RQ size before proceeding */
4769 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4770 return -EINVAL;
4771
4772 if (!ucmd->rq_wqe_count)
4773 return -EINVAL;
4774
4775 rwq->wqe_count = ucmd->rq_wqe_count;
4776 rwq->wqe_shift = ucmd->rq_wqe_shift;
4777 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4778 rwq->log_rq_stride = rwq->wqe_shift;
4779 rwq->log_rq_size = ilog2(rwq->wqe_count);
4780 return 0;
4781}
4782
4783static int prepare_user_rq(struct ib_pd *pd,
4784 struct ib_wq_init_attr *init_attr,
4785 struct ib_udata *udata,
4786 struct mlx5_ib_rwq *rwq)
4787{
4788 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4789 struct mlx5_ib_create_wq ucmd = {};
4790 int err;
4791 size_t required_cmd_sz;
4792
4793 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4794 if (udata->inlen < required_cmd_sz) {
4795 mlx5_ib_dbg(dev, "invalid inlen\n");
4796 return -EINVAL;
4797 }
4798
4799 if (udata->inlen > sizeof(ucmd) &&
4800 !ib_is_udata_cleared(udata, sizeof(ucmd),
4801 udata->inlen - sizeof(ucmd))) {
4802 mlx5_ib_dbg(dev, "inlen is not supported\n");
4803 return -EOPNOTSUPP;
4804 }
4805
4806 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4807 mlx5_ib_dbg(dev, "copy failed\n");
4808 return -EFAULT;
4809 }
4810
4811 if (ucmd.comp_mask) {
4812 mlx5_ib_dbg(dev, "invalid comp mask\n");
4813 return -EOPNOTSUPP;
4814 }
4815
4816 if (ucmd.reserved) {
4817 mlx5_ib_dbg(dev, "invalid reserved\n");
4818 return -EOPNOTSUPP;
4819 }
4820
4821 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4822 if (err) {
4823 mlx5_ib_dbg(dev, "err %d\n", err);
4824 return err;
4825 }
4826
4827 err = create_user_rq(dev, pd, rwq, &ucmd);
4828 if (err) {
4829 mlx5_ib_dbg(dev, "err %d\n", err);
4830 if (err)
4831 return err;
4832 }
4833
4834 rwq->user_index = ucmd.user_index;
4835 return 0;
4836}
4837
4838struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4839 struct ib_wq_init_attr *init_attr,
4840 struct ib_udata *udata)
4841{
4842 struct mlx5_ib_dev *dev;
4843 struct mlx5_ib_rwq *rwq;
4844 struct mlx5_ib_create_wq_resp resp = {};
4845 size_t min_resp_len;
4846 int err;
4847
4848 if (!udata)
4849 return ERR_PTR(-ENOSYS);
4850
4851 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4852 if (udata->outlen && udata->outlen < min_resp_len)
4853 return ERR_PTR(-EINVAL);
4854
4855 dev = to_mdev(pd->device);
4856 switch (init_attr->wq_type) {
4857 case IB_WQT_RQ:
4858 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4859 if (!rwq)
4860 return ERR_PTR(-ENOMEM);
4861 err = prepare_user_rq(pd, init_attr, udata, rwq);
4862 if (err)
4863 goto err;
4864 err = create_rq(rwq, pd, init_attr);
4865 if (err)
4866 goto err_user_rq;
4867 break;
4868 default:
4869 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4870 init_attr->wq_type);
4871 return ERR_PTR(-EINVAL);
4872 }
4873
350d0e4c 4874 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 4875 rwq->ibwq.state = IB_WQS_RESET;
4876 if (udata->outlen) {
4877 resp.response_length = offsetof(typeof(resp), response_length) +
4878 sizeof(resp.response_length);
4879 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4880 if (err)
4881 goto err_copy;
4882 }
4883
350d0e4c
YH		 4884 rwq->core_qp.event = mlx5_ib_wq_event;
4885 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 4886 return &rwq->ibwq;
4887
4888err_copy:
350d0e4c 4889 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c 4890err_user_rq:
fe248c3a 4891 destroy_user_rq(dev, pd, rwq);
79b20a6c
YH		 4892err:
4893 kfree(rwq);
4894 return ERR_PTR(err);
4895}
4896
4897int mlx5_ib_destroy_wq(struct ib_wq *wq)
4898{
4899 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4900 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4901
350d0e4c 4902 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
fe248c3a 4903 destroy_user_rq(dev, wq->pd, rwq);
79b20a6c
YH		 4904 kfree(rwq);
4905
4906 return 0;
4907}
4908
c5f90929
YH		 4909struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4910 struct ib_rwq_ind_table_init_attr *init_attr,
4911 struct ib_udata *udata)
4912{
4913 struct mlx5_ib_dev *dev = to_mdev(device);
4914 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4915 int sz = 1 << init_attr->log_ind_tbl_size;
4916 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4917 size_t min_resp_len;
4918 int inlen;
4919 int err;
4920 int i;
4921 u32 *in;
4922 void *rqtc;
4923
4924 if (udata->inlen > 0 &&
4925 !ib_is_udata_cleared(udata, 0,
4926 udata->inlen))
4927 return ERR_PTR(-EOPNOTSUPP);
4928
efd7f400
MG		 4929 if (init_attr->log_ind_tbl_size >
4930 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4931 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4932 init_attr->log_ind_tbl_size,
4933 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4934 return ERR_PTR(-EINVAL);
4935 }
4936
c5f90929
YH		 4937 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4938 if (udata->outlen && udata->outlen < min_resp_len)
4939 return ERR_PTR(-EINVAL);
4940
4941 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4942 if (!rwq_ind_tbl)
4943 return ERR_PTR(-ENOMEM);
4944
4945 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 4946 in = kvzalloc(inlen, GFP_KERNEL);
c5f90929
YH		 4947 if (!in) {
4948 err = -ENOMEM;
4949 goto err;
4950 }
4951
4952 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4953
4954 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4955 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4956
4957 for (i = 0; i < sz; i++)
4958 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4959
4960 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4961 kvfree(in);
4962
4963 if (err)
4964 goto err;
4965
4966 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4967 if (udata->outlen) {
4968 resp.response_length = offsetof(typeof(resp), response_length) +
4969 sizeof(resp.response_length);
4970 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4971 if (err)
4972 goto err_copy;
4973 }
4974
4975 return &rwq_ind_tbl->ib_rwq_ind_tbl;
4976
4977err_copy:
4978 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4979err:
4980 kfree(rwq_ind_tbl);
4981 return ERR_PTR(err);
4982}
4983
4984int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4985{
4986 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4987 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4988
4989 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4990
4991 kfree(rwq_ind_tbl);
4992 return 0;
4993}
4994
79b20a6c
YH		 4995int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4996 u32 wq_attr_mask, struct ib_udata *udata)
4997{
4998 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4999 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5000 struct mlx5_ib_modify_wq ucmd = {};
5001 size_t required_cmd_sz;
5002 int curr_wq_state;
5003 int wq_state;
5004 int inlen;
5005 int err;
5006 void *rqc;
5007 void *in;
5008
5009 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5010 if (udata->inlen < required_cmd_sz)
5011 return -EINVAL;
5012
5013 if (udata->inlen > sizeof(ucmd) &&
5014 !ib_is_udata_cleared(udata, sizeof(ucmd),
5015 udata->inlen - sizeof(ucmd)))
5016 return -EOPNOTSUPP;
5017
5018 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5019 return -EFAULT;
5020
5021 if (ucmd.comp_mask || ucmd.reserved)
5022 return -EOPNOTSUPP;
5023
5024 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 5025 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5026 if (!in)
5027 return -ENOMEM;
5028
5029 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5030
5031 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5032 wq_attr->curr_wq_state : wq->state;
5033 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5034 wq_attr->wq_state : curr_wq_state;
5035 if (curr_wq_state == IB_WQS_ERR)
5036 curr_wq_state = MLX5_RQC_STATE_ERR;
5037 if (wq_state == IB_WQS_ERR)
5038 wq_state = MLX5_RQC_STATE_ERR;
5039 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5040 MLX5_SET(rqc, rqc, state, wq_state);
5041
b1f74a84
NO		 5042 if (wq_attr_mask & IB_WQ_FLAGS) {
5043 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5044 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5045 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5046 mlx5_ib_dbg(dev, "VLAN offloads are not "
5047 "supported\n");
5048 err = -EOPNOTSUPP;
5049 goto out;
5050 }
5051 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5052 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5053 MLX5_SET(rqc, rqc, vsd,
5054 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5055 }
5056 }
5057
23a6964e
MD		 5058 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5059 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5060 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5061 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
e1f24a79
PP		 5062 MLX5_SET(rqc, rqc, counter_set_id,
5063 dev->port->cnts.set_id);
23a6964e
MD		 5064 } else
5065 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5066 dev->ib_dev.name);
5067 }
5068
350d0e4c 5069 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 5070 if (!err)
5071 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5072
b1f74a84
NO		 5073out:
5074 kvfree(in);
79b20a6c
YH		 5075 return err;
5076}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git