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IB/mlx5: Add support for DC Initiator QP
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
c2e53b2c 37#include <linux/mlx5/fs.h>
e126ba97 38#include "mlx5_ib.h"
e126ba97
EC		 39
40/* not supported currently */
41static int wq_signature;
42
43enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45};
46
47enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52};
53
54enum {
55 MLX5_IB_SQ_STRIDE = 6,
e126ba97
EC		 56};
57
58static const u32 mlx5_ib_opcode[] = {
59 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 60 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
73};
74
f0313965
ES		 75struct mlx5_wqe_eth_pad {
76 u8 rsvd0[16];
77};
e126ba97 78
eb49ab0c
AV		 79enum raw_qp_set_mask_map {
80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 81 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 82};
83
0680efa2
AV		 84struct mlx5_modify_raw_qp_param {
85 u16 operation;
eb49ab0c
AV		 86
87 u32 set_mask; /* raw_qp_set_mask_map */
7d29f349 88 u32 rate_limit;
eb49ab0c 89 u8 rq_q_ctr_id;
0680efa2
AV		 90};
91
89ea94a7
MG		 92static void get_cqs(enum ib_qp_type qp_type,
93 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
94 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
95
e126ba97
EC		 96static int is_qp0(enum ib_qp_type qp_type)
97{
98 return qp_type == IB_QPT_SMI;
99}
100
e126ba97
EC		 101static int is_sqp(enum ib_qp_type qp_type)
102{
103 return is_qp0(qp_type) || is_qp1(qp_type);
104}
105
106static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
107{
108 return mlx5_buf_offset(&qp->buf, offset);
109}
110
111static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
112{
113 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
114}
115
116void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
117{
118 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
119}
120
c1395a2a
HE		 121/**
122 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
123 *
124 * @qp: QP to copy from.
125 * @send: copy from the send queue when non-zero, use the receive queue
126 * otherwise.
127 * @wqe_index: index to start copying from. For send work queues, the
128 * wqe_index is in units of MLX5_SEND_WQE_BB.
129 * For receive work queue, it is the number of work queue
130 * element in the queue.
131 * @buffer: destination buffer.
132 * @length: maximum number of bytes to copy.
133 *
134 * Copies at least a single WQE, but may copy more data.
135 *
136 * Return: the number of bytes copied, or an error code.
137 */
138int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 139 void *buffer, u32 length,
140 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 141{
142 struct ib_device *ibdev = qp->ibqp.device;
143 struct mlx5_ib_dev *dev = to_mdev(ibdev);
144 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
145 size_t offset;
146 size_t wq_end;
19098df2 147 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 148 u32 first_copy_length;
149 int wqe_length;
150 int ret;
151
152 if (wq->wqe_cnt == 0) {
153 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
154 qp->ibqp.qp_type);
155 return -EINVAL;
156 }
157
158 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
159 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
160
161 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
162 return -EINVAL;
163
164 if (offset > umem->length ||
165 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
166 return -EINVAL;
167
168 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
169 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
170 if (ret)
171 return ret;
172
173 if (send) {
174 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
175 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
176
177 wqe_length = ds * MLX5_WQE_DS_UNITS;
178 } else {
179 wqe_length = 1 << wq->wqe_shift;
180 }
181
182 if (wqe_length <= first_copy_length)
183 return first_copy_length;
184
185 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
186 wqe_length - first_copy_length);
187 if (ret)
188 return ret;
189
190 return wqe_length;
191}
192
e126ba97
EC		 193static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
194{
195 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
196 struct ib_event event;
197
19098df2 198 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
199 /* This event is only valid for trans_qps */
200 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
201 }
e126ba97
EC		 202
203 if (ibqp->event_handler) {
204 event.device = ibqp->device;
205 event.element.qp = ibqp;
206 switch (type) {
207 case MLX5_EVENT_TYPE_PATH_MIG:
208 event.event = IB_EVENT_PATH_MIG;
209 break;
210 case MLX5_EVENT_TYPE_COMM_EST:
211 event.event = IB_EVENT_COMM_EST;
212 break;
213 case MLX5_EVENT_TYPE_SQ_DRAINED:
214 event.event = IB_EVENT_SQ_DRAINED;
215 break;
216 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
217 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
218 break;
219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
220 event.event = IB_EVENT_QP_FATAL;
221 break;
222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
223 event.event = IB_EVENT_PATH_MIG_ERR;
224 break;
225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
226 event.event = IB_EVENT_QP_REQ_ERR;
227 break;
228 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
229 event.event = IB_EVENT_QP_ACCESS_ERR;
230 break;
231 default:
232 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
233 return;
234 }
235
236 ibqp->event_handler(&event, ibqp->qp_context);
237 }
238}
239
240static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
241 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
242{
243 int wqe_size;
244 int wq_size;
245
246 /* Sanity check RQ size before proceeding */
938fe83c 247 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 248 return -EINVAL;
249
250 if (!has_rq) {
251 qp->rq.max_gs = 0;
252 qp->rq.wqe_cnt = 0;
253 qp->rq.wqe_shift = 0;
0540d814
NO		 254 cap->max_recv_wr = 0;
255 cap->max_recv_sge = 0;
e126ba97
EC		 256 } else {
257 if (ucmd) {
258 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
259 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
260 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
261 qp->rq.max_post = qp->rq.wqe_cnt;
262 } else {
263 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
264 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
265 wqe_size = roundup_pow_of_two(wqe_size);
266 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
267 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
268 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 269 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 270 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
271 wqe_size,
938fe83c
SM		 272 MLX5_CAP_GEN(dev->mdev,
273 max_wqe_sz_rq));
e126ba97
EC		 274 return -EINVAL;
275 }
276 qp->rq.wqe_shift = ilog2(wqe_size);
277 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
278 qp->rq.max_post = qp->rq.wqe_cnt;
279 }
280 }
281
282 return 0;
283}
284
f0313965 285static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 286{
618af384 287 int size = 0;
e126ba97 288
f0313965 289 switch (attr->qp_type) {
e126ba97 290 case IB_QPT_XRC_INI:
b125a54b 291 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 292 /* fall through */
293 case IB_QPT_RC:
294 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 295 max(sizeof(struct mlx5_wqe_atomic_seg) +
296 sizeof(struct mlx5_wqe_raddr_seg),
297 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
298 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 299 break;
300
b125a54b
EC		 301 case IB_QPT_XRC_TGT:
302 return 0;
303
e126ba97 304 case IB_QPT_UC:
b125a54b 305 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 306 max(sizeof(struct mlx5_wqe_raddr_seg),
307 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
308 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 309 break;
310
311 case IB_QPT_UD:
f0313965
ES		 312 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
313 size += sizeof(struct mlx5_wqe_eth_pad) +
314 sizeof(struct mlx5_wqe_eth_seg);
315 /* fall through */
e126ba97 316 case IB_QPT_SMI:
d16e91da 317 case MLX5_IB_QPT_HW_GSI:
b125a54b 318 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 319 sizeof(struct mlx5_wqe_datagram_seg);
320 break;
321
322 case MLX5_IB_QPT_REG_UMR:
b125a54b 323 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 324 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
325 sizeof(struct mlx5_mkey_seg);
326 break;
327
328 default:
329 return -EINVAL;
330 }
331
332 return size;
333}
334
335static int calc_send_wqe(struct ib_qp_init_attr *attr)
336{
337 int inl_size = 0;
338 int size;
339
f0313965 340 size = sq_overhead(attr);
e126ba97
EC		 341 if (size < 0)
342 return size;
343
344 if (attr->cap.max_inline_data) {
345 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
346 attr->cap.max_inline_data;
347 }
348
349 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 350 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
351 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
352 return MLX5_SIG_WQE_SIZE;
353 else
354 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 355}
356
288c01b7
EC		 357static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
358{
359 int max_sge;
360
361 if (attr->qp_type == IB_QPT_RC)
362 max_sge = (min_t(int, wqe_size, 512) -
363 sizeof(struct mlx5_wqe_ctrl_seg) -
364 sizeof(struct mlx5_wqe_raddr_seg)) /
365 sizeof(struct mlx5_wqe_data_seg);
366 else if (attr->qp_type == IB_QPT_XRC_INI)
367 max_sge = (min_t(int, wqe_size, 512) -
368 sizeof(struct mlx5_wqe_ctrl_seg) -
369 sizeof(struct mlx5_wqe_xrc_seg) -
370 sizeof(struct mlx5_wqe_raddr_seg)) /
371 sizeof(struct mlx5_wqe_data_seg);
372 else
373 max_sge = (wqe_size - sq_overhead(attr)) /
374 sizeof(struct mlx5_wqe_data_seg);
375
376 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
377 sizeof(struct mlx5_wqe_data_seg));
378}
379
e126ba97
EC		 380static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
381 struct mlx5_ib_qp *qp)
382{
383 int wqe_size;
384 int wq_size;
385
386 if (!attr->cap.max_send_wr)
387 return 0;
388
389 wqe_size = calc_send_wqe(attr);
390 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
391 if (wqe_size < 0)
392 return wqe_size;
393
938fe83c 394 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 395 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 396 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 397 return -EINVAL;
398 }
399
f0313965
ES		 400 qp->max_inline_data = wqe_size - sq_overhead(attr) -
401 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 402 attr->cap.max_inline_data = qp->max_inline_data;
403
e1e66cc2
SG		 404 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
405 qp->signature_en = true;
406
e126ba97
EC		 407 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
408 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 409 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 410 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
411 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 412 qp->sq.wqe_cnt,
413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 414 return -ENOMEM;
415 }
e126ba97 416 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 417 qp->sq.max_gs = get_send_sge(attr, wqe_size);
418 if (qp->sq.max_gs < attr->cap.max_send_sge)
419 return -ENOMEM;
420
421 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 422 qp->sq.max_post = wq_size / wqe_size;
423 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 424
425 return wq_size;
426}
427
428static int set_user_buf_size(struct mlx5_ib_dev *dev,
429 struct mlx5_ib_qp *qp,
19098df2 430 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 431 struct mlx5_ib_qp_base *base,
432 struct ib_qp_init_attr *attr)
e126ba97
EC		 433{
434 int desc_sz = 1 << qp->sq.wqe_shift;
435
938fe83c 436 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 437 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 438 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 439 return -EINVAL;
440 }
441
442 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
443 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
444 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
445 return -EINVAL;
446 }
447
448 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
449
938fe83c 450 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 451 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 452 qp->sq.wqe_cnt,
453 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 454 return -EINVAL;
455 }
456
c2e53b2c
YH		 457 if (attr->qp_type == IB_QPT_RAW_PACKET ||
458 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 459 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
460 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
461 } else {
462 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
463 (qp->sq.wqe_cnt << 6);
464 }
e126ba97
EC		 465
466 return 0;
467}
468
469static int qp_has_rq(struct ib_qp_init_attr *attr)
470{
471 if (attr->qp_type == IB_QPT_XRC_INI ||
472 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
473 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
474 !attr->cap.max_recv_wr)
475 return 0;
476
477 return 1;
478}
479
2f5ff264 480static int first_med_bfreg(void)
c1be5232
EC		 481{
482 return 1;
483}
484
0b80c14f
EC		 485enum {
486 /* this is the first blue flame register in the array of bfregs assigned
487 * to a processes. Since we do not use it for blue flame but rather
488 * regular 64 bit doorbells, we do not need a lock for maintaiing
489 * "odd/even" order
490 */
491 NUM_NON_BLUE_FLAME_BFREGS = 1,
492};
493
b037c29a
EC		 494static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
495{
31a78a5a 496 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a
EC		 497}
498
499static int num_med_bfreg(struct mlx5_ib_dev *dev,
500 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 501{
502 int n;
503
b037c29a
EC		 504 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
505 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 506
507 return n >= 0 ? n : 0;
508}
509
b037c29a
EC		 510static int first_hi_bfreg(struct mlx5_ib_dev *dev,
511 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 512{
513 int med;
c1be5232 514
b037c29a
EC		 515 med = num_med_bfreg(dev, bfregi);
516 return ++med;
c1be5232
EC		 517}
518
b037c29a
EC		 519static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
520 struct mlx5_bfreg_info *bfregi)
e126ba97 521{
e126ba97
EC		 522 int i;
523
b037c29a
EC		 524 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
525 if (!bfregi->count[i]) {
2f5ff264 526 bfregi->count[i]++;
e126ba97
EC		 527 return i;
528 }
529 }
530
531 return -ENOMEM;
532}
533
b037c29a
EC		 534static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
535 struct mlx5_bfreg_info *bfregi)
e126ba97 536{
2f5ff264 537 int minidx = first_med_bfreg();
e126ba97
EC		 538 int i;
539
b037c29a 540 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 541 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 542 minidx = i;
0b80c14f
EC		 543 if (!bfregi->count[minidx])
544 break;
e126ba97
EC		 545 }
546
2f5ff264 547 bfregi->count[minidx]++;
e126ba97
EC		 548 return minidx;
549}
550
b037c29a
EC		 551static int alloc_bfreg(struct mlx5_ib_dev *dev,
552 struct mlx5_bfreg_info *bfregi,
2f5ff264 553 enum mlx5_ib_latency_class lat)
e126ba97 554{
2f5ff264 555 int bfregn = -EINVAL;
e126ba97 556
2f5ff264 557 mutex_lock(&bfregi->lock);
e126ba97
EC		 558 switch (lat) {
559 case MLX5_IB_LATENCY_CLASS_LOW:
0b80c14f 560 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 561 bfregn = 0;
562 bfregi->count[bfregn]++;
e126ba97
EC		 563 break;
564
565 case MLX5_IB_LATENCY_CLASS_MEDIUM:
2f5ff264
EC		 566 if (bfregi->ver < 2)
567 bfregn = -ENOMEM;
78c0f98c 568 else
b037c29a 569 bfregn = alloc_med_class_bfreg(dev, bfregi);
e126ba97
EC		 570 break;
571
572 case MLX5_IB_LATENCY_CLASS_HIGH:
2f5ff264
EC		 573 if (bfregi->ver < 2)
574 bfregn = -ENOMEM;
78c0f98c 575 else
b037c29a 576 bfregn = alloc_high_class_bfreg(dev, bfregi);
e126ba97
EC		 577 break;
578 }
2f5ff264 579 mutex_unlock(&bfregi->lock);
e126ba97 580
2f5ff264 581 return bfregn;
e126ba97
EC		 582}
583
4ed131d0 584void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 585{
2f5ff264 586 mutex_lock(&bfregi->lock);
b037c29a 587 bfregi->count[bfregn]--;
2f5ff264 588 mutex_unlock(&bfregi->lock);
e126ba97
EC		 589}
590
591static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
592{
593 switch (state) {
594 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
595 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
596 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
597 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
598 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
599 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
600 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
601 default: return -1;
602 }
603}
604
605static int to_mlx5_st(enum ib_qp_type type)
606{
607 switch (type) {
608 case IB_QPT_RC: return MLX5_QP_ST_RC;
609 case IB_QPT_UC: return MLX5_QP_ST_UC;
610 case IB_QPT_UD: return MLX5_QP_ST_UD;
611 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
612 case IB_QPT_XRC_INI:
613 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
614 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 615 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
c32a4f29 616 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
e126ba97 617 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 618 case IB_QPT_RAW_PACKET:
0fb2ed66 619 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 620 case IB_QPT_MAX:
621 default: return -EINVAL;
622 }
623}
624
89ea94a7
MG		 625static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
626 struct mlx5_ib_cq *recv_cq);
627static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
628 struct mlx5_ib_cq *recv_cq);
629
b037c29a 630static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1ee47ab3
YH		 631 struct mlx5_bfreg_info *bfregi, int bfregn,
632 bool dyn_bfreg)
e126ba97 633{
b037c29a
EC		 634 int bfregs_per_sys_page;
635 int index_of_sys_page;
636 int offset;
637
638 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
639 MLX5_NON_FP_BFREGS_PER_UAR;
640 index_of_sys_page = bfregn / bfregs_per_sys_page;
641
1ee47ab3
YH		 642 if (dyn_bfreg) {
643 index_of_sys_page += bfregi->num_static_sys_pages;
644 if (bfregn > bfregi->num_dyn_bfregs ||
645 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
646 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
647 return -EINVAL;
648 }
649 }
b037c29a 650
1ee47ab3 651 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a 652 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 653}
654
19098df2 655static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
656 struct ib_pd *pd,
657 unsigned long addr, size_t size,
658 struct ib_umem **umem,
659 int *npages, int *page_shift, int *ncont,
660 u32 *offset)
661{
662 int err;
663
664 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
665 if (IS_ERR(*umem)) {
666 mlx5_ib_dbg(dev, "umem_get failed\n");
667 return PTR_ERR(*umem);
668 }
669
762f899a 670 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 671
672 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
673 if (err) {
674 mlx5_ib_warn(dev, "bad offset\n");
675 goto err_umem;
676 }
677
678 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
679 addr, size, *npages, *page_shift, *ncont, *offset);
680
681 return 0;
682
683err_umem:
684 ib_umem_release(*umem);
685 *umem = NULL;
686
687 return err;
688}
689
fe248c3a
MG		 690static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
691 struct mlx5_ib_rwq *rwq)
79b20a6c
YH		 692{
693 struct mlx5_ib_ucontext *context;
694
fe248c3a
MG		 695 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
696 atomic_dec(&dev->delay_drop.rqs_cnt);
697
79b20a6c
YH		 698 context = to_mucontext(pd->uobject->context);
699 mlx5_ib_db_unmap_user(context, &rwq->db);
700 if (rwq->umem)
701 ib_umem_release(rwq->umem);
702}
703
704static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
705 struct mlx5_ib_rwq *rwq,
706 struct mlx5_ib_create_wq *ucmd)
707{
708 struct mlx5_ib_ucontext *context;
709 int page_shift = 0;
710 int npages;
711 u32 offset = 0;
712 int ncont = 0;
713 int err;
714
715 if (!ucmd->buf_addr)
716 return -EINVAL;
717
718 context = to_mucontext(pd->uobject->context);
719 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
720 rwq->buf_size, 0, 0);
721 if (IS_ERR(rwq->umem)) {
722 mlx5_ib_dbg(dev, "umem_get failed\n");
723 err = PTR_ERR(rwq->umem);
724 return err;
725 }
726
762f899a 727 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 728 &ncont, NULL);
729 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
730 &rwq->rq_page_offset);
731 if (err) {
732 mlx5_ib_warn(dev, "bad offset\n");
733 goto err_umem;
734 }
735
736 rwq->rq_num_pas = ncont;
737 rwq->page_shift = page_shift;
738 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
739 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
740
741 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
742 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
743 npages, page_shift, ncont, offset);
744
745 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
746 if (err) {
747 mlx5_ib_dbg(dev, "map failed\n");
748 goto err_umem;
749 }
750
751 rwq->create_type = MLX5_WQ_USER;
752 return 0;
753
754err_umem:
755 ib_umem_release(rwq->umem);
756 return err;
757}
758
b037c29a
EC		 759static int adjust_bfregn(struct mlx5_ib_dev *dev,
760 struct mlx5_bfreg_info *bfregi, int bfregn)
761{
762 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
763 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
764}
765
e126ba97
EC		 766static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
767 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 768 struct ib_qp_init_attr *attr,
09a7d9ec 769 u32 **in,
19098df2 770 struct mlx5_ib_create_qp_resp *resp, int *inlen,
771 struct mlx5_ib_qp_base *base)
e126ba97
EC		 772{
773 struct mlx5_ib_ucontext *context;
774 struct mlx5_ib_create_qp ucmd;
19098df2 775 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 776 int page_shift = 0;
1ee47ab3 777 int uar_index = 0;
e126ba97 778 int npages;
9e9c47d0 779 u32 offset = 0;
2f5ff264 780 int bfregn;
9e9c47d0 781 int ncont = 0;
09a7d9ec
SM		 782 __be64 *pas;
783 void *qpc;
e126ba97
EC		 784 int err;
785
786 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
787 if (err) {
788 mlx5_ib_dbg(dev, "copy failed\n");
789 return err;
790 }
791
792 context = to_mucontext(pd->uobject->context);
1ee47ab3
YH		 793 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
794 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
795 ucmd.bfreg_index, true);
796 if (uar_index < 0)
797 return uar_index;
798
799 bfregn = MLX5_IB_INVALID_BFREG;
800 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
801 /*
802 * TBD: should come from the verbs when we have the API
803 */
051f2630 804 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 805 bfregn = MLX5_CROSS_CHANNEL_BFREG;
1ee47ab3 806 }
051f2630 807 else {
b037c29a 808 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
2f5ff264
EC		 809 if (bfregn < 0) {
810 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
051f2630 811 mlx5_ib_dbg(dev, "reverting to medium latency\n");
b037c29a 812 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
2f5ff264
EC		 813 if (bfregn < 0) {
814 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
051f2630 815 mlx5_ib_dbg(dev, "reverting to high latency\n");
b037c29a 816 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
2f5ff264
EC		 817 if (bfregn < 0) {
818 mlx5_ib_warn(dev, "bfreg allocation failed\n");
819 return bfregn;
051f2630 820 }
c1be5232 821 }
e126ba97
EC		 822 }
823 }
824
2f5ff264 825 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
1ee47ab3
YH		 826 if (bfregn != MLX5_IB_INVALID_BFREG)
827 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
828 false);
e126ba97 829
48fea837
HE		 830 qp->rq.offset = 0;
831 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
832 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
833
0fb2ed66 834 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 835 if (err)
2f5ff264 836 goto err_bfreg;
e126ba97 837
19098df2 838 if (ucmd.buf_addr && ubuffer->buf_size) {
839 ubuffer->buf_addr = ucmd.buf_addr;
840 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
841 ubuffer->buf_size,
842 &ubuffer->umem, &npages, &page_shift,
843 &ncont, &offset);
844 if (err)
2f5ff264 845 goto err_bfreg;
9e9c47d0 846 } else {
19098df2 847 ubuffer->umem = NULL;
e126ba97 848 }
e126ba97 849
09a7d9ec
SM		 850 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
851 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 852 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 853 if (!*in) {
854 err = -ENOMEM;
855 goto err_umem;
856 }
09a7d9ec
SM		 857
858 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 859 if (ubuffer->umem)
09a7d9ec
SM		 860 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
861
862 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
863
864 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
865 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 866
09a7d9ec 867 MLX5_SET(qpc, qpc, uar_page, uar_index);
1ee47ab3
YH		 868 if (bfregn != MLX5_IB_INVALID_BFREG)
869 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
870 else
871 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
2f5ff264 872 qp->bfregn = bfregn;
e126ba97
EC		 873
874 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
875 if (err) {
876 mlx5_ib_dbg(dev, "map failed\n");
877 goto err_free;
878 }
879
880 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
881 if (err) {
882 mlx5_ib_dbg(dev, "copy failed\n");
883 goto err_unmap;
884 }
885 qp->create_type = MLX5_QP_USER;
886
887 return 0;
888
889err_unmap:
890 mlx5_ib_db_unmap_user(context, &qp->db);
891
892err_free:
479163f4 893 kvfree(*in);
e126ba97
EC		 894
895err_umem:
19098df2 896 if (ubuffer->umem)
897 ib_umem_release(ubuffer->umem);
e126ba97 898
2f5ff264 899err_bfreg:
1ee47ab3
YH		 900 if (bfregn != MLX5_IB_INVALID_BFREG)
901 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 902 return err;
903}
904
b037c29a
EC		 905static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
906 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 907{
908 struct mlx5_ib_ucontext *context;
909
910 context = to_mucontext(pd->uobject->context);
911 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 912 if (base->ubuffer.umem)
913 ib_umem_release(base->ubuffer.umem);
1ee47ab3
YH		 914
915 /*
916 * Free only the BFREGs which are handled by the kernel.
917 * BFREGs of UARs allocated dynamically are handled by user.
918 */
919 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
920 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 921}
922
923static int create_kernel_qp(struct mlx5_ib_dev *dev,
924 struct ib_qp_init_attr *init_attr,
925 struct mlx5_ib_qp *qp,
09a7d9ec 926 u32 **in, int *inlen,
19098df2 927 struct mlx5_ib_qp_base *base)
e126ba97 928{
e126ba97 929 int uar_index;
09a7d9ec 930 void *qpc;
e126ba97
EC		 931 int err;
932
f0313965
ES		 933 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
934 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c 935 IB_QP_CREATE_IPOIB_UD_LSO |
93d576af 936 IB_QP_CREATE_NETIF_QP |
b11a4f9c 937 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 938 return -EINVAL;
e126ba97
EC		 939
940 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 941 qp->bf.bfreg = &dev->fp_bfreg;
942 else
943 qp->bf.bfreg = &dev->bfreg;
e126ba97 944
d8030b0d
EC		 945 /* We need to divide by two since each register is comprised of
946 * two buffers of identical size, namely odd and even
947 */
948 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 949 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 950
951 err = calc_sq_size(dev, init_attr, qp);
952 if (err < 0) {
953 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 954 return err;
e126ba97
EC		 955 }
956
957 qp->rq.offset = 0;
958 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 959 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 960
19098df2 961 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 962 if (err) {
963 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 964 return err;
e126ba97
EC		 965 }
966
967 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 968 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
969 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 970 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 971 if (!*in) {
972 err = -ENOMEM;
973 goto err_buf;
974 }
09a7d9ec
SM		 975
976 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
977 MLX5_SET(qpc, qpc, uar_page, uar_index);
978 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
979
e126ba97 980 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 981 MLX5_SET(qpc, qpc, fre, 1);
982 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 983
b11a4f9c 984 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 985 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 986 qp->flags |= MLX5_IB_QP_SQPN_QP1;
987 }
988
09a7d9ec
SM		 989 mlx5_fill_page_array(&qp->buf,
990 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 991
9603b61d 992 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 993 if (err) {
994 mlx5_ib_dbg(dev, "err %d\n", err);
995 goto err_free;
996 }
997
b5883008
LD		 998 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
999 sizeof(*qp->sq.wrid), GFP_KERNEL);
1000 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1001 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1002 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1003 sizeof(*qp->rq.wrid), GFP_KERNEL);
1004 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1005 sizeof(*qp->sq.w_list), GFP_KERNEL);
1006 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1007 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
e126ba97
EC		 1008
1009 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1010 !qp->sq.w_list || !qp->sq.wqe_head) {
1011 err = -ENOMEM;
1012 goto err_wrid;
1013 }
1014 qp->create_type = MLX5_QP_KERNEL;
1015
1016 return 0;
1017
1018err_wrid:
b5883008
LD		 1019 kvfree(qp->sq.wqe_head);
1020 kvfree(qp->sq.w_list);
1021 kvfree(qp->sq.wrid);
1022 kvfree(qp->sq.wr_data);
1023 kvfree(qp->rq.wrid);
f4044dac 1024 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 1025
1026err_free:
479163f4 1027 kvfree(*in);
e126ba97
EC		 1028
1029err_buf:
9603b61d 1030 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1031 return err;
1032}
1033
1034static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1035{
b5883008
LD		 1036 kvfree(qp->sq.wqe_head);
1037 kvfree(qp->sq.w_list);
1038 kvfree(qp->sq.wrid);
1039 kvfree(qp->sq.wr_data);
1040 kvfree(qp->rq.wrid);
f4044dac 1041 mlx5_db_free(dev->mdev, &qp->db);
9603b61d 1042 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1043}
1044
09a7d9ec 1045static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1046{
1047 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
c32a4f29 1048 (attr->qp_type == MLX5_IB_QPT_DCI) ||
e126ba97 1049 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1050 return MLX5_SRQ_RQ;
e126ba97 1051 else if (!qp->has_rq)
09a7d9ec 1052 return MLX5_ZERO_LEN_RQ;
e126ba97 1053 else
09a7d9ec 1054 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1055}
1056
1057static int is_connected(enum ib_qp_type qp_type)
1058{
1059 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1060 return 1;
1061
1062 return 0;
1063}
1064
0fb2ed66 1065static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
c2e53b2c 1066 struct mlx5_ib_qp *qp,
0fb2ed66 1067 struct mlx5_ib_sq *sq, u32 tdn)
1068{
c4f287c4 1069 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1070 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1071
0fb2ed66 1072 MLX5_SET(tisc, tisc, transport_domain, tdn);
c2e53b2c
YH		 1073 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1074 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1075
0fb2ed66 1076 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1077}
1078
1079static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1080 struct mlx5_ib_sq *sq)
1081{
1082 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1083}
1084
1085static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1086 struct mlx5_ib_sq *sq, void *qpin,
1087 struct ib_pd *pd)
1088{
1089 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1090 __be64 *pas;
1091 void *in;
1092 void *sqc;
1093 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1094 void *wq;
1095 int inlen;
1096 int err;
1097 int page_shift = 0;
1098 int npages;
1099 int ncont = 0;
1100 u32 offset = 0;
1101
1102 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1103 &sq->ubuffer.umem, &npages, &page_shift,
1104 &ncont, &offset);
1105 if (err)
1106 return err;
1107
1108 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1b9a07ee 1109 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1110 if (!in) {
1111 err = -ENOMEM;
1112 goto err_umem;
1113 }
1114
1115 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1116 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
795b609c
BW		 1117 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1118 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
0fb2ed66 1119 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1120 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1121 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1122 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1123 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
96dc3fc5
NO		 1124 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1125 MLX5_CAP_ETH(dev->mdev, swp))
1126 MLX5_SET(sqc, sqc, allow_swp, 1);
0fb2ed66 1127
1128 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1129 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1130 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1131 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1132 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1133 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1134 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1135 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1136 MLX5_SET(wq, wq, page_offset, offset);
1137
1138 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1139 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1140
1141 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1142
1143 kvfree(in);
1144
1145 if (err)
1146 goto err_umem;
1147
1148 return 0;
1149
1150err_umem:
1151 ib_umem_release(sq->ubuffer.umem);
1152 sq->ubuffer.umem = NULL;
1153
1154 return err;
1155}
1156
1157static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1158 struct mlx5_ib_sq *sq)
1159{
1160 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1161 ib_umem_release(sq->ubuffer.umem);
1162}
1163
1164static int get_rq_pas_size(void *qpc)
1165{
1166 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1167 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1168 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1169 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1170 u32 po_quanta = 1 << (log_page_size - 6);
1171 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1172 u32 page_size = 1 << log_page_size;
1173 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1174 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1175
1176 return rq_num_pas * sizeof(u64);
1177}
1178
1179static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1180 struct mlx5_ib_rq *rq, void *qpin)
1181{
358e42ea 1182 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1183 __be64 *pas;
1184 __be64 *qp_pas;
1185 void *in;
1186 void *rqc;
1187 void *wq;
1188 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1189 int inlen;
1190 int err;
1191 u32 rq_pas_size = get_rq_pas_size(qpc);
1192
1193 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1194 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1195 if (!in)
1196 return -ENOMEM;
1197
1198 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1199 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1200 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1201 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1202 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1203 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1204 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1205 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1206
358e42ea
MD		 1207 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1208 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1209
0fb2ed66 1210 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1211 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 1212 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1213 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
0fb2ed66 1214 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1215 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1216 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1217 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1218 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1219 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1220
1221 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1222 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1223 memcpy(pas, qp_pas, rq_pas_size);
1224
1225 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1226
1227 kvfree(in);
1228
1229 return err;
1230}
1231
1232static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1233 struct mlx5_ib_rq *rq)
1234{
1235 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1236}
1237
f95ef6cb
MG		 1238static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1239{
1240 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1241 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1242 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1243}
1244
0fb2ed66 1245static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
f95ef6cb
MG		 1246 struct mlx5_ib_rq *rq, u32 tdn,
1247 bool tunnel_offload_en)
0fb2ed66 1248{
1249 u32 *in;
1250 void *tirc;
1251 int inlen;
1252 int err;
1253
1254 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1255 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1256 if (!in)
1257 return -ENOMEM;
1258
1259 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1260 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1261 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1262 MLX5_SET(tirc, tirc, transport_domain, tdn);
f95ef6cb
MG		 1263 if (tunnel_offload_en)
1264 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
0fb2ed66 1265
1266 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1267
1268 kvfree(in);
1269
1270 return err;
1271}
1272
1273static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1274 struct mlx5_ib_rq *rq)
1275{
1276 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1277}
1278
1279static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
09a7d9ec 1280 u32 *in,
0fb2ed66 1281 struct ib_pd *pd)
1282{
1283 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1284 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1285 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1286 struct ib_uobject *uobj = pd->uobject;
1287 struct ib_ucontext *ucontext = uobj->context;
1288 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1289 int err;
1290 u32 tdn = mucontext->tdn;
1291
1292 if (qp->sq.wqe_cnt) {
c2e53b2c 1293 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
0fb2ed66 1294 if (err)
1295 return err;
1296
1297 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1298 if (err)
1299 goto err_destroy_tis;
1300
1301 sq->base.container_mibqp = qp;
1d31e9c0 1302 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1303 }
1304
1305 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1306 rq->base.container_mibqp = qp;
1307
e4cc4fa7
NO		 1308 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1309 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
b1383aa6
NO		 1310 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1311 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
0fb2ed66 1312 err = create_raw_packet_qp_rq(dev, rq, in);
1313 if (err)
1314 goto err_destroy_sq;
1315
0fb2ed66 1316
f95ef6cb
MG		 1317 err = create_raw_packet_qp_tir(dev, rq, tdn,
1318 qp->tunnel_offload_en);
0fb2ed66 1319 if (err)
1320 goto err_destroy_rq;
1321 }
1322
1323 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1324 rq->base.mqp.qpn;
1325
1326 return 0;
1327
1328err_destroy_rq:
1329 destroy_raw_packet_qp_rq(dev, rq);
1330err_destroy_sq:
1331 if (!qp->sq.wqe_cnt)
1332 return err;
1333 destroy_raw_packet_qp_sq(dev, sq);
1334err_destroy_tis:
1335 destroy_raw_packet_qp_tis(dev, sq);
1336
1337 return err;
1338}
1339
1340static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1341 struct mlx5_ib_qp *qp)
1342{
1343 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1344 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1345 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1346
1347 if (qp->rq.wqe_cnt) {
1348 destroy_raw_packet_qp_tir(dev, rq);
1349 destroy_raw_packet_qp_rq(dev, rq);
1350 }
1351
1352 if (qp->sq.wqe_cnt) {
1353 destroy_raw_packet_qp_sq(dev, sq);
1354 destroy_raw_packet_qp_tis(dev, sq);
1355 }
1356}
1357
1358static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1359 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1360{
1361 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1362 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1363
1364 sq->sq = &qp->sq;
1365 rq->rq = &qp->rq;
1366 sq->doorbell = &qp->db;
1367 rq->doorbell = &qp->db;
1368}
1369
28d61370
YH		 1370static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1371{
1372 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1373}
1374
1375static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1376 struct ib_pd *pd,
1377 struct ib_qp_init_attr *init_attr,
1378 struct ib_udata *udata)
1379{
1380 struct ib_uobject *uobj = pd->uobject;
1381 struct ib_ucontext *ucontext = uobj->context;
1382 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1383 struct mlx5_ib_create_qp_resp resp = {};
1384 int inlen;
1385 int err;
1386 u32 *in;
1387 void *tirc;
1388 void *hfso;
1389 u32 selected_fields = 0;
1390 size_t min_resp_len;
1391 u32 tdn = mucontext->tdn;
1392 struct mlx5_ib_create_qp_rss ucmd = {};
1393 size_t required_cmd_sz;
1394
1395 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1396 return -EOPNOTSUPP;
1397
1398 if (init_attr->create_flags || init_attr->send_cq)
1399 return -EINVAL;
1400
2f5ff264 1401 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1402 if (udata->outlen < min_resp_len)
1403 return -EINVAL;
1404
f95ef6cb 1405 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
28d61370
YH		 1406 if (udata->inlen < required_cmd_sz) {
1407 mlx5_ib_dbg(dev, "invalid inlen\n");
1408 return -EINVAL;
1409 }
1410
1411 if (udata->inlen > sizeof(ucmd) &&
1412 !ib_is_udata_cleared(udata, sizeof(ucmd),
1413 udata->inlen - sizeof(ucmd))) {
1414 mlx5_ib_dbg(dev, "inlen is not supported\n");
1415 return -EOPNOTSUPP;
1416 }
1417
1418 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1419 mlx5_ib_dbg(dev, "copy failed\n");
1420 return -EFAULT;
1421 }
1422
1423 if (ucmd.comp_mask) {
1424 mlx5_ib_dbg(dev, "invalid comp mask\n");
1425 return -EOPNOTSUPP;
1426 }
1427
f95ef6cb
MG		 1428 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1429 mlx5_ib_dbg(dev, "invalid flags\n");
1430 return -EOPNOTSUPP;
1431 }
1432
1433 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1434 !tunnel_offload_supported(dev->mdev)) {
1435 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
28d61370
YH		 1436 return -EOPNOTSUPP;
1437 }
1438
309fa347
MG		 1439 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1440 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1441 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1442 return -EOPNOTSUPP;
1443 }
1444
28d61370
YH		 1445 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1446 if (err) {
1447 mlx5_ib_dbg(dev, "copy failed\n");
1448 return -EINVAL;
1449 }
1450
1451 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1452 in = kvzalloc(inlen, GFP_KERNEL);
28d61370
YH		 1453 if (!in)
1454 return -ENOMEM;
1455
1456 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1457 MLX5_SET(tirc, tirc, disp_type,
1458 MLX5_TIRC_DISP_TYPE_INDIRECT);
1459 MLX5_SET(tirc, tirc, indirect_table,
1460 init_attr->rwq_ind_tbl->ind_tbl_num);
1461 MLX5_SET(tirc, tirc, transport_domain, tdn);
1462
1463 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
f95ef6cb
MG		 1464
1465 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1466 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1467
309fa347
MG		 1468 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1469 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1470 else
1471 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1472
28d61370
YH		 1473 switch (ucmd.rx_hash_function) {
1474 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1475 {
1476 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1477 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1478
1479 if (len != ucmd.rx_key_len) {
1480 err = -EINVAL;
1481 goto err;
1482 }
1483
1484 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1485 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1486 memcpy(rss_key, ucmd.rx_hash_key, len);
1487 break;
1488 }
1489 default:
1490 err = -EOPNOTSUPP;
1491 goto err;
1492 }
1493
1494 if (!ucmd.rx_hash_fields_mask) {
1495 /* special case when this TIR serves as steering entry without hashing */
1496 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1497 goto create_tir;
1498 err = -EINVAL;
1499 goto err;
1500 }
1501
1502 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1503 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1504 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1505 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1506 err = -EINVAL;
1507 goto err;
1508 }
1509
1510 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1511 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1512 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1513 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1514 MLX5_L3_PROT_TYPE_IPV4);
1515 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1516 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1517 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1518 MLX5_L3_PROT_TYPE_IPV6);
1519
1520 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1521 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1522 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1523 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1524 err = -EINVAL;
1525 goto err;
1526 }
1527
1528 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1529 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1530 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1531 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1532 MLX5_L4_PROT_TYPE_TCP);
1533 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1534 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1535 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1536 MLX5_L4_PROT_TYPE_UDP);
1537
1538 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1539 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1540 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1541
1542 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1543 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1544 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1545
1546 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1547 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1548 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1549
1550 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1551 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1552 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1553
1554 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1555
1556create_tir:
1557 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1558
1559 if (err)
1560 goto err;
1561
1562 kvfree(in);
1563 /* qpn is reserved for that QP */
1564 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1565 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1566 return 0;
1567
1568err:
1569 kvfree(in);
1570 return err;
1571}
1572
e126ba97
EC		 1573static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1574 struct ib_qp_init_attr *init_attr,
1575 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1576{
1577 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1578 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1579 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1580 struct mlx5_ib_create_qp_resp resp;
89ea94a7
MG		 1581 struct mlx5_ib_cq *send_cq;
1582 struct mlx5_ib_cq *recv_cq;
1583 unsigned long flags;
cfb5e088 1584 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1585 struct mlx5_ib_create_qp ucmd;
1586 struct mlx5_ib_qp_base *base;
cfb5e088 1587 void *qpc;
09a7d9ec
SM		 1588 u32 *in;
1589 int err;
e126ba97
EC		 1590
1591 mutex_init(&qp->mutex);
1592 spin_lock_init(&qp->sq.lock);
1593 spin_lock_init(&qp->rq.lock);
1594
28d61370
YH		 1595 if (init_attr->rwq_ind_tbl) {
1596 if (!udata)
1597 return -ENOSYS;
1598
1599 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1600 return err;
1601 }
1602
f360d88a 1603 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1604 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1605 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1606 return -EINVAL;
1607 } else {
1608 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1609 }
1610 }
1611
051f2630
LR		 1612 if (init_attr->create_flags &
1613 (IB_QP_CREATE_CROSS_CHANNEL |
1614 IB_QP_CREATE_MANAGED_SEND |
1615 IB_QP_CREATE_MANAGED_RECV)) {
1616 if (!MLX5_CAP_GEN(mdev, cd)) {
1617 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1618 return -EINVAL;
1619 }
1620 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1621 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1622 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1623 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1624 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1625 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1626 }
f0313965
ES		 1627
1628 if (init_attr->qp_type == IB_QPT_UD &&
1629 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1630 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1631 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1632 return -EOPNOTSUPP;
1633 }
1634
358e42ea
MD		 1635 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1636 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1637 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1638 return -EOPNOTSUPP;
1639 }
1640 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1641 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1642 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1643 return -EOPNOTSUPP;
1644 }
1645 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1646 }
1647
e126ba97
EC		 1648 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1649 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1650
e4cc4fa7
NO		 1651 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1652 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1653 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1654 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1655 return -EOPNOTSUPP;
1656 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1657 }
1658
e126ba97
EC		 1659 if (pd && pd->uobject) {
1660 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1661 mlx5_ib_dbg(dev, "copy failed\n");
1662 return -EFAULT;
1663 }
1664
cfb5e088
HA		 1665 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1666 &ucmd, udata->inlen, &uidx);
1667 if (err)
1668 return err;
1669
e126ba97
EC		 1670 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1671 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
f95ef6cb
MG		 1672 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1673 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1674 !tunnel_offload_supported(mdev)) {
1675 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1676 return -EOPNOTSUPP;
1677 }
1678 qp->tunnel_offload_en = true;
1679 }
c2e53b2c
YH		 1680
1681 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1682 if (init_attr->qp_type != IB_QPT_UD ||
1683 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1684 MLX5_CAP_PORT_TYPE_IB) ||
1685 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1686 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1687 return -EOPNOTSUPP;
1688 }
1689
1690 qp->flags |= MLX5_IB_QP_UNDERLAY;
1691 qp->underlay_qpn = init_attr->source_qpn;
1692 }
e126ba97
EC		 1693 } else {
1694 qp->wq_sig = !!wq_signature;
1695 }
1696
c2e53b2c
YH		 1697 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1698 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1699 &qp->raw_packet_qp.rq.base :
1700 &qp->trans_qp.base;
1701
e126ba97
EC		 1702 qp->has_rq = qp_has_rq(init_attr);
1703 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1704 qp, (pd && pd->uobject) ? &ucmd : NULL);
1705 if (err) {
1706 mlx5_ib_dbg(dev, "err %d\n", err);
1707 return err;
1708 }
1709
1710 if (pd) {
1711 if (pd->uobject) {
938fe83c
SM		 1712 __u32 max_wqes =
1713 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1714 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1715 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1716 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1717 mlx5_ib_dbg(dev, "invalid rq params\n");
1718 return -EINVAL;
1719 }
938fe83c 1720 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1721 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1722 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1723 return -EINVAL;
1724 }
b11a4f9c
HE		 1725 if (init_attr->create_flags &
1726 mlx5_ib_create_qp_sqpn_qp1()) {
1727 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1728 return -EINVAL;
1729 }
0fb2ed66 1730 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1731 &resp, &inlen, base);
e126ba97
EC		 1732 if (err)
1733 mlx5_ib_dbg(dev, "err %d\n", err);
1734 } else {
19098df2 1735 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1736 base);
e126ba97
EC		 1737 if (err)
1738 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1739 }
1740
1741 if (err)
1742 return err;
1743 } else {
1b9a07ee 1744 in = kvzalloc(inlen, GFP_KERNEL);
e126ba97
EC		 1745 if (!in)
1746 return -ENOMEM;
1747
1748 qp->create_type = MLX5_QP_EMPTY;
1749 }
1750
1751 if (is_sqp(init_attr->qp_type))
1752 qp->port = init_attr->port_num;
1753
09a7d9ec
SM		 1754 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1755
1756 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1757 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1758
1759 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1760 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1761 else
09a7d9ec
SM		 1762 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1763
e126ba97
EC		 1764
1765 if (qp->wq_sig)
09a7d9ec 1766 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1767
f360d88a 1768 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1769 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1770
051f2630 1771 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1772 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1773 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1774 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1775 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1776 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1777
e126ba97
EC		 1778 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1779 int rcqe_sz;
1780 int scqe_sz;
1781
1782 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1783 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1784
1785 if (rcqe_sz == 128)
09a7d9ec 1786 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1787 else
09a7d9ec 1788 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1789
1790 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1791 if (scqe_sz == 128)
09a7d9ec 1792 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1793 else
09a7d9ec 1794 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1795 }
1796 }
1797
1798 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1799 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1800 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1801 }
1802
09a7d9ec 1803 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97 1804
3fd3307e 1805 if (qp->sq.wqe_cnt) {
09a7d9ec 1806 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
3fd3307e 1807 } else {
09a7d9ec 1808 MLX5_SET(qpc, qpc, no_sq, 1);
3fd3307e
AK		 1809 if (init_attr->srq &&
1810 init_attr->srq->srq_type == IB_SRQT_TM)
1811 MLX5_SET(qpc, qpc, offload_type,
1812 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1813 }
e126ba97
EC		 1814
1815 /* Set default resources */
1816 switch (init_attr->qp_type) {
1817 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1818 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1819 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1820 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1821 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1822 break;
1823 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1824 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1825 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1826 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1827 break;
1828 default:
1829 if (init_attr->srq) {
09a7d9ec
SM		 1830 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1831 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1832 } else {
09a7d9ec
SM		 1833 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1834 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1835 }
1836 }
1837
1838 if (init_attr->send_cq)
09a7d9ec 1839 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1840
1841 if (init_attr->recv_cq)
09a7d9ec 1842 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1843
09a7d9ec 1844 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1845
09a7d9ec
SM		 1846 /* 0xffffff means we ask to work with cqe version 0 */
1847 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1848 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1849
f0313965
ES		 1850 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1851 if (init_attr->qp_type == IB_QPT_UD &&
1852 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1853 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1854 qp->flags |= MLX5_IB_QP_LSO;
1855 }
cfb5e088 1856
b1383aa6
NO		 1857 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1858 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1859 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1860 err = -EOPNOTSUPP;
1861 goto err;
1862 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1863 MLX5_SET(qpc, qpc, end_padding_mode,
1864 MLX5_WQ_END_PAD_MODE_ALIGN);
1865 } else {
1866 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1867 }
1868 }
1869
c2e53b2c
YH		 1870 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1871 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 1872 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1873 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1874 err = create_raw_packet_qp(dev, qp, in, pd);
1875 } else {
1876 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1877 }
1878
e126ba97
EC		 1879 if (err) {
1880 mlx5_ib_dbg(dev, "create qp failed\n");
1881 goto err_create;
1882 }
1883
479163f4 1884 kvfree(in);
e126ba97 1885
19098df2 1886 base->container_mibqp = qp;
1887 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1888
89ea94a7
MG		 1889 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1890 &send_cq, &recv_cq);
1891 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1892 mlx5_ib_lock_cqs(send_cq, recv_cq);
1893 /* Maintain device to QPs access, needed for further handling via reset
1894 * flow
1895 */
1896 list_add_tail(&qp->qps_list, &dev->qp_list);
1897 /* Maintain CQ to QPs access, needed for further handling via reset flow
1898 */
1899 if (send_cq)
1900 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1901 if (recv_cq)
1902 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1903 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1904 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1905
e126ba97
EC		 1906 return 0;
1907
1908err_create:
1909 if (qp->create_type == MLX5_QP_USER)
b037c29a 1910 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 1911 else if (qp->create_type == MLX5_QP_KERNEL)
1912 destroy_qp_kernel(dev, qp);
1913
b1383aa6 1914err:
479163f4 1915 kvfree(in);
e126ba97
EC		 1916 return err;
1917}
1918
1919static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1920 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1921{
1922 if (send_cq) {
1923 if (recv_cq) {
1924 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1925 spin_lock(&send_cq->lock);
e126ba97
EC		 1926 spin_lock_nested(&recv_cq->lock,
1927 SINGLE_DEPTH_NESTING);
1928 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1929 spin_lock(&send_cq->lock);
e126ba97
EC		 1930 __acquire(&recv_cq->lock);
1931 } else {
89ea94a7 1932 spin_lock(&recv_cq->lock);
e126ba97
EC		 1933 spin_lock_nested(&send_cq->lock,
1934 SINGLE_DEPTH_NESTING);
1935 }
1936 } else {
89ea94a7 1937 spin_lock(&send_cq->lock);
6a4f139a 1938 __acquire(&recv_cq->lock);
e126ba97
EC		 1939 }
1940 } else if (recv_cq) {
89ea94a7 1941 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1942 __acquire(&send_cq->lock);
1943 } else {
1944 __acquire(&send_cq->lock);
1945 __acquire(&recv_cq->lock);
e126ba97
EC		 1946 }
1947}
1948
1949static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1950 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1951{
1952 if (send_cq) {
1953 if (recv_cq) {
1954 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1955 spin_unlock(&recv_cq->lock);
89ea94a7 1956 spin_unlock(&send_cq->lock);
e126ba97
EC		 1957 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1958 __release(&recv_cq->lock);
89ea94a7 1959 spin_unlock(&send_cq->lock);
e126ba97
EC		 1960 } else {
1961 spin_unlock(&send_cq->lock);
89ea94a7 1962 spin_unlock(&recv_cq->lock);
e126ba97
EC		 1963 }
1964 } else {
6a4f139a 1965 __release(&recv_cq->lock);
89ea94a7 1966 spin_unlock(&send_cq->lock);
e126ba97
EC		 1967 }
1968 } else if (recv_cq) {
6a4f139a 1969 __release(&send_cq->lock);
89ea94a7 1970 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 1971 } else {
1972 __release(&recv_cq->lock);
1973 __release(&send_cq->lock);
e126ba97
EC		 1974 }
1975}
1976
1977static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1978{
1979 return to_mpd(qp->ibqp.pd);
1980}
1981
89ea94a7
MG		 1982static void get_cqs(enum ib_qp_type qp_type,
1983 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 1984 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1985{
89ea94a7 1986 switch (qp_type) {
e126ba97
EC		 1987 case IB_QPT_XRC_TGT:
1988 *send_cq = NULL;
1989 *recv_cq = NULL;
1990 break;
1991 case MLX5_IB_QPT_REG_UMR:
1992 case IB_QPT_XRC_INI:
89ea94a7 1993 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 1994 *recv_cq = NULL;
1995 break;
1996
1997 case IB_QPT_SMI:
d16e91da 1998 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1999 case IB_QPT_RC:
2000 case IB_QPT_UC:
2001 case IB_QPT_UD:
2002 case IB_QPT_RAW_IPV6:
2003 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 2004 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 2005 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2006 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 2007 break;
2008
e126ba97
EC		 2009 case IB_QPT_MAX:
2010 default:
2011 *send_cq = NULL;
2012 *recv_cq = NULL;
2013 break;
2014 }
2015}
2016
ad5f8e96 2017static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2018 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2019 u8 lag_tx_affinity);
ad5f8e96 2020
e126ba97
EC		 2021static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2022{
2023 struct mlx5_ib_cq *send_cq, *recv_cq;
c2e53b2c 2024 struct mlx5_ib_qp_base *base;
89ea94a7 2025 unsigned long flags;
e126ba97
EC		 2026 int err;
2027
28d61370
YH		 2028 if (qp->ibqp.rwq_ind_tbl) {
2029 destroy_rss_raw_qp_tir(dev, qp);
2030 return;
2031 }
2032
c2e53b2c
YH		 2033 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2034 qp->flags & MLX5_IB_QP_UNDERLAY) ?
0fb2ed66 2035 &qp->raw_packet_qp.rq.base :
2036 &qp->trans_qp.base;
2037
6aec21f6 2038 if (qp->state != IB_QPS_RESET) {
c2e53b2c
YH		 2039 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2040 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
ad5f8e96 2041 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 2042 MLX5_CMD_OP_2RST_QP, 0,
2043 NULL, &base->mqp);
ad5f8e96 2044 } else {
0680efa2
AV		 2045 struct mlx5_modify_raw_qp_param raw_qp_param = {
2046 .operation = MLX5_CMD_OP_2RST_QP
2047 };
2048
13eab21f 2049 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 2050 }
2051 if (err)
427c1e7b 2052 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 2053 base->mqp.qpn);
6aec21f6 2054 }
e126ba97 2055
89ea94a7
MG		 2056 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2057 &send_cq, &recv_cq);
2058
2059 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2060 mlx5_ib_lock_cqs(send_cq, recv_cq);
2061 /* del from lists under both locks above to protect reset flow paths */
2062 list_del(&qp->qps_list);
2063 if (send_cq)
2064 list_del(&qp->cq_send_list);
2065
2066 if (recv_cq)
2067 list_del(&qp->cq_recv_list);
e126ba97
EC		 2068
2069 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 2070 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2071 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2072 if (send_cq != recv_cq)
19098df2 2073 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2074 NULL);
e126ba97 2075 }
89ea94a7
MG		 2076 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2077 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 2078
c2e53b2c
YH		 2079 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2080 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 2081 destroy_raw_packet_qp(dev, qp);
2082 } else {
2083 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2084 if (err)
2085 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2086 base->mqp.qpn);
2087 }
e126ba97 2088
e126ba97
EC		 2089 if (qp->create_type == MLX5_QP_KERNEL)
2090 destroy_qp_kernel(dev, qp);
2091 else if (qp->create_type == MLX5_QP_USER)
b037c29a 2092 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 2093}
2094
2095static const char *ib_qp_type_str(enum ib_qp_type type)
2096{
2097 switch (type) {
2098 case IB_QPT_SMI:
2099 return "IB_QPT_SMI";
2100 case IB_QPT_GSI:
2101 return "IB_QPT_GSI";
2102 case IB_QPT_RC:
2103 return "IB_QPT_RC";
2104 case IB_QPT_UC:
2105 return "IB_QPT_UC";
2106 case IB_QPT_UD:
2107 return "IB_QPT_UD";
2108 case IB_QPT_RAW_IPV6:
2109 return "IB_QPT_RAW_IPV6";
2110 case IB_QPT_RAW_ETHERTYPE:
2111 return "IB_QPT_RAW_ETHERTYPE";
2112 case IB_QPT_XRC_INI:
2113 return "IB_QPT_XRC_INI";
2114 case IB_QPT_XRC_TGT:
2115 return "IB_QPT_XRC_TGT";
2116 case IB_QPT_RAW_PACKET:
2117 return "IB_QPT_RAW_PACKET";
2118 case MLX5_IB_QPT_REG_UMR:
2119 return "MLX5_IB_QPT_REG_UMR";
b4aaa1f0
MS		 2120 case IB_QPT_DRIVER:
2121 return "IB_QPT_DRIVER";
e126ba97
EC		 2122 case IB_QPT_MAX:
2123 default:
2124 return "Invalid QP type";
2125 }
2126}
2127
b4aaa1f0
MS		 2128static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2129 struct ib_qp_init_attr *attr,
2130 struct mlx5_ib_create_qp *ucmd)
2131{
2132 struct mlx5_ib_dev *dev;
2133 struct mlx5_ib_qp *qp;
2134 int err = 0;
2135 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2136 void *dctc;
2137
2138 if (!attr->srq || !attr->recv_cq)
2139 return ERR_PTR(-EINVAL);
2140
2141 dev = to_mdev(pd->device);
2142
2143 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2144 ucmd, sizeof(*ucmd), &uidx);
2145 if (err)
2146 return ERR_PTR(err);
2147
2148 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2149 if (!qp)
2150 return ERR_PTR(-ENOMEM);
2151
2152 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2153 if (!qp->dct.in) {
2154 err = -ENOMEM;
2155 goto err_free;
2156 }
2157
2158 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2159 qp->driver_qp_type = MLX5_IB_QPT_DCT;
2160 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2161 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2162 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2163 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2164 MLX5_SET(dctc, dctc, user_index, uidx);
2165
2166 qp->state = IB_QPS_RESET;
2167
2168 return &qp->ibqp;
2169err_free:
2170 kfree(qp);
2171 return ERR_PTR(err);
2172}
2173
2174static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2175 struct ib_qp_init_attr *init_attr,
2176 struct mlx5_ib_create_qp *ucmd,
2177 struct ib_udata *udata)
2178{
2179 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2180 int err;
2181
2182 if (!udata)
2183 return -EINVAL;
2184
2185 if (udata->inlen < sizeof(*ucmd)) {
2186 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2187 return -EINVAL;
2188 }
2189 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2190 if (err)
2191 return err;
2192
2193 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2194 init_attr->qp_type = MLX5_IB_QPT_DCI;
2195 } else {
2196 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2197 init_attr->qp_type = MLX5_IB_QPT_DCT;
2198 } else {
2199 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2200 return -EINVAL;
2201 }
2202 }
2203
2204 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2205 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2206 return -EOPNOTSUPP;
2207 }
2208
2209 return 0;
2210}
2211
e126ba97 2212struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
b4aaa1f0 2213 struct ib_qp_init_attr *verbs_init_attr,
e126ba97
EC		 2214 struct ib_udata *udata)
2215{
2216 struct mlx5_ib_dev *dev;
2217 struct mlx5_ib_qp *qp;
2218 u16 xrcdn = 0;
2219 int err;
b4aaa1f0
MS		 2220 struct ib_qp_init_attr mlx_init_attr;
2221 struct ib_qp_init_attr *init_attr = verbs_init_attr;
e126ba97
EC		 2222
2223 if (pd) {
2224 dev = to_mdev(pd->device);
0fb2ed66 2225
2226 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2227 if (!pd->uobject) {
2228 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2229 return ERR_PTR(-EINVAL);
2230 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2231 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2232 return ERR_PTR(-EINVAL);
2233 }
2234 }
09f16cf5
MD		 2235 } else {
2236 /* being cautious here */
2237 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2238 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2239 pr_warn("%s: no PD for transport %s\n", __func__,
2240 ib_qp_type_str(init_attr->qp_type));
2241 return ERR_PTR(-EINVAL);
2242 }
2243 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2244 }
2245
b4aaa1f0
MS		 2246 if (init_attr->qp_type == IB_QPT_DRIVER) {
2247 struct mlx5_ib_create_qp ucmd;
2248
2249 init_attr = &mlx_init_attr;
2250 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2251 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2252 if (err)
2253 return ERR_PTR(err);
c32a4f29
MS		 2254
2255 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2256 if (init_attr->cap.max_recv_wr ||
2257 init_attr->cap.max_recv_sge) {
2258 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2259 return ERR_PTR(-EINVAL);
2260 }
2261 }
b4aaa1f0
MS		 2262 }
2263
e126ba97
EC		 2264 switch (init_attr->qp_type) {
2265 case IB_QPT_XRC_TGT:
2266 case IB_QPT_XRC_INI:
938fe83c 2267 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2268 mlx5_ib_dbg(dev, "XRC not supported\n");
2269 return ERR_PTR(-ENOSYS);
2270 }
2271 init_attr->recv_cq = NULL;
2272 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2273 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2274 init_attr->send_cq = NULL;
2275 }
2276
2277 /* fall through */
0fb2ed66 2278 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2279 case IB_QPT_RC:
2280 case IB_QPT_UC:
2281 case IB_QPT_UD:
2282 case IB_QPT_SMI:
d16e91da 2283 case MLX5_IB_QPT_HW_GSI:
e126ba97 2284 case MLX5_IB_QPT_REG_UMR:
c32a4f29 2285 case MLX5_IB_QPT_DCI:
e126ba97
EC		 2286 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2287 if (!qp)
2288 return ERR_PTR(-ENOMEM);
2289
2290 err = create_qp_common(dev, pd, init_attr, udata, qp);
2291 if (err) {
2292 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2293 kfree(qp);
2294 return ERR_PTR(err);
2295 }
2296
2297 if (is_qp0(init_attr->qp_type))
2298 qp->ibqp.qp_num = 0;
2299 else if (is_qp1(init_attr->qp_type))
2300 qp->ibqp.qp_num = 1;
2301 else
19098df2 2302 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2303
2304 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2305 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2306 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2307 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2308
19098df2 2309 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2310
2311 break;
2312
d16e91da
HE		 2313 case IB_QPT_GSI:
2314 return mlx5_ib_gsi_create_qp(pd, init_attr);
2315
e126ba97
EC		 2316 case IB_QPT_RAW_IPV6:
2317 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2318 case IB_QPT_MAX:
2319 default:
2320 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2321 init_attr->qp_type);
2322 /* Don't support raw QPs */
2323 return ERR_PTR(-EINVAL);
2324 }
2325
b4aaa1f0
MS		 2326 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2327 qp->qp_sub_type = init_attr->qp_type;
2328
e126ba97
EC		 2329 return &qp->ibqp;
2330}
2331
2332int mlx5_ib_destroy_qp(struct ib_qp *qp)
2333{
2334 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2335 struct mlx5_ib_qp *mqp = to_mqp(qp);
2336
d16e91da
HE		 2337 if (unlikely(qp->qp_type == IB_QPT_GSI))
2338 return mlx5_ib_gsi_destroy_qp(qp);
2339
e126ba97
EC		 2340 destroy_qp_common(dev, mqp);
2341
2342 kfree(mqp);
2343
2344 return 0;
2345}
2346
2347static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2348 int attr_mask)
2349{
2350 u32 hw_access_flags = 0;
2351 u8 dest_rd_atomic;
2352 u32 access_flags;
2353
2354 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2355 dest_rd_atomic = attr->max_dest_rd_atomic;
2356 else
19098df2 2357 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2358
2359 if (attr_mask & IB_QP_ACCESS_FLAGS)
2360 access_flags = attr->qp_access_flags;
2361 else
19098df2 2362 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2363
2364 if (!dest_rd_atomic)
2365 access_flags &= IB_ACCESS_REMOTE_WRITE;
2366
2367 if (access_flags & IB_ACCESS_REMOTE_READ)
2368 hw_access_flags |= MLX5_QP_BIT_RRE;
2369 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2370 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2371 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2372 hw_access_flags |= MLX5_QP_BIT_RWE;
2373
2374 return cpu_to_be32(hw_access_flags);
2375}
2376
2377enum {
2378 MLX5_PATH_FLAG_FL = 1 << 0,
2379 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2380 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2381};
2382
2383static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2384{
2385 if (rate == IB_RATE_PORT_CURRENT) {
2386 return 0;
2387 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2388 return -EINVAL;
2389 } else {
2390 while (rate != IB_RATE_2_5_GBPS &&
2391 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2392 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2393 --rate;
2394 }
2395
2396 return rate + MLX5_STAT_RATE_OFFSET;
2397}
2398
75850d0b 2399static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2400 struct mlx5_ib_sq *sq, u8 sl)
2401{
2402 void *in;
2403 void *tisc;
2404 int inlen;
2405 int err;
2406
2407 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2408 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 2409 if (!in)
2410 return -ENOMEM;
2411
2412 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2413
2414 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2415 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2416
2417 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2418
2419 kvfree(in);
2420
2421 return err;
2422}
2423
13eab21f
AH		 2424static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2425 struct mlx5_ib_sq *sq, u8 tx_affinity)
2426{
2427 void *in;
2428 void *tisc;
2429 int inlen;
2430 int err;
2431
2432 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2433 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 2434 if (!in)
2435 return -ENOMEM;
2436
2437 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2438
2439 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2440 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2441
2442 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2443
2444 kvfree(in);
2445
2446 return err;
2447}
2448
75850d0b 2449static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
90898850 2450 const struct rdma_ah_attr *ah,
e126ba97 2451 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2452 u32 path_flags, const struct ib_qp_attr *attr,
2453 bool alt)
e126ba97 2454{
d8966fcd 2455 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 2456 int err;
ed88451e 2457 enum ib_gid_type gid_type;
d8966fcd
DC		 2458 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2459 u8 sl = rdma_ah_get_sl(ah);
e126ba97 2460
e126ba97 2461 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2462 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2463 attr->pkey_index);
e126ba97 2464
d8966fcd
DC		 2465 if (ah_flags & IB_AH_GRH) {
2466 if (grh->sgid_index >=
938fe83c 2467 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2468 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 2469 grh->sgid_index,
938fe83c 2470 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2471 return -EINVAL;
2472 }
2811ba51 2473 }
44c58487
DC		 2474
2475 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 2476 if (!(ah_flags & IB_AH_GRH))
2811ba51 2477 return -EINVAL;
d8966fcd 2478 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
ed88451e
MD		 2479 &gid_type);
2480 if (err)
2481 return err;
44c58487 2482 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2b621851
MD		 2483 if (qp->ibqp.qp_type == IB_QPT_RC ||
2484 qp->ibqp.qp_type == IB_QPT_UC ||
2485 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2486 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2487 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2488 grh->sgid_index);
d8966fcd 2489 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
ed88451e 2490 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
d8966fcd 2491 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2811ba51 2492 } else {
d3ae2bde
NO		 2493 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2494 path->fl_free_ar |=
2495 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
d8966fcd
DC		 2496 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2497 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2498 if (ah_flags & IB_AH_GRH)
2811ba51 2499 path->grh_mlid |= 1 << 7;
d8966fcd 2500 path->dci_cfi_prio_sl = sl & 0xf;
2811ba51
AS		 2501 }
2502
d8966fcd
DC		 2503 if (ah_flags & IB_AH_GRH) {
2504 path->mgid_index = grh->sgid_index;
2505 path->hop_limit = grh->hop_limit;
e126ba97 2506 path->tclass_flowlabel =
d8966fcd
DC		 2507 cpu_to_be32((grh->traffic_class << 20) |
2508 (grh->flow_label));
2509 memcpy(path->rgid, grh->dgid.raw, 16);
e126ba97
EC		 2510 }
2511
d8966fcd 2512 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 2513 if (err < 0)
2514 return err;
2515 path->static_rate = err;
2516 path->port = port;
2517
e126ba97 2518 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2519 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2520
75850d0b 2521 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2522 return modify_raw_packet_eth_prio(dev->mdev,
2523 &qp->raw_packet_qp.sq,
d8966fcd 2524 sl & 0xf);
75850d0b 2525
e126ba97
EC		 2526 return 0;
2527}
2528
2529static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2530 [MLX5_QP_STATE_INIT] = {
2531 [MLX5_QP_STATE_INIT] = {
2532 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2533 MLX5_QP_OPTPAR_RAE |
2534 MLX5_QP_OPTPAR_RWE |
2535 MLX5_QP_OPTPAR_PKEY_INDEX |
2536 MLX5_QP_OPTPAR_PRI_PORT,
2537 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2538 MLX5_QP_OPTPAR_PKEY_INDEX |
2539 MLX5_QP_OPTPAR_PRI_PORT,
2540 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2541 MLX5_QP_OPTPAR_Q_KEY |
2542 MLX5_QP_OPTPAR_PRI_PORT,
2543 },
2544 [MLX5_QP_STATE_RTR] = {
2545 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2546 MLX5_QP_OPTPAR_RRE |
2547 MLX5_QP_OPTPAR_RAE |
2548 MLX5_QP_OPTPAR_RWE |
2549 MLX5_QP_OPTPAR_PKEY_INDEX,
2550 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2551 MLX5_QP_OPTPAR_RWE |
2552 MLX5_QP_OPTPAR_PKEY_INDEX,
2553 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2554 MLX5_QP_OPTPAR_Q_KEY,
2555 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2556 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2557 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2558 MLX5_QP_OPTPAR_RRE |
2559 MLX5_QP_OPTPAR_RAE |
2560 MLX5_QP_OPTPAR_RWE |
2561 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2562 },
2563 },
2564 [MLX5_QP_STATE_RTR] = {
2565 [MLX5_QP_STATE_RTS] = {
2566 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2567 MLX5_QP_OPTPAR_RRE |
2568 MLX5_QP_OPTPAR_RAE |
2569 MLX5_QP_OPTPAR_RWE |
2570 MLX5_QP_OPTPAR_PM_STATE |
2571 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2572 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2573 MLX5_QP_OPTPAR_RWE |
2574 MLX5_QP_OPTPAR_PM_STATE,
2575 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2576 },
2577 },
2578 [MLX5_QP_STATE_RTS] = {
2579 [MLX5_QP_STATE_RTS] = {
2580 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2581 MLX5_QP_OPTPAR_RAE |
2582 MLX5_QP_OPTPAR_RWE |
2583 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2584 MLX5_QP_OPTPAR_PM_STATE |
2585 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2586 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2587 MLX5_QP_OPTPAR_PM_STATE |
2588 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2589 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2590 MLX5_QP_OPTPAR_SRQN |
2591 MLX5_QP_OPTPAR_CQN_RCV,
2592 },
2593 },
2594 [MLX5_QP_STATE_SQER] = {
2595 [MLX5_QP_STATE_RTS] = {
2596 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2597 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2598 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2599 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2600 MLX5_QP_OPTPAR_RWE |
2601 MLX5_QP_OPTPAR_RAE |
2602 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2603 },
2604 },
2605};
2606
2607static int ib_nr_to_mlx5_nr(int ib_mask)
2608{
2609 switch (ib_mask) {
2610 case IB_QP_STATE:
2611 return 0;
2612 case IB_QP_CUR_STATE:
2613 return 0;
2614 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2615 return 0;
2616 case IB_QP_ACCESS_FLAGS:
2617 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2618 MLX5_QP_OPTPAR_RAE;
2619 case IB_QP_PKEY_INDEX:
2620 return MLX5_QP_OPTPAR_PKEY_INDEX;
2621 case IB_QP_PORT:
2622 return MLX5_QP_OPTPAR_PRI_PORT;
2623 case IB_QP_QKEY:
2624 return MLX5_QP_OPTPAR_Q_KEY;
2625 case IB_QP_AV:
2626 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2627 MLX5_QP_OPTPAR_PRI_PORT;
2628 case IB_QP_PATH_MTU:
2629 return 0;
2630 case IB_QP_TIMEOUT:
2631 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2632 case IB_QP_RETRY_CNT:
2633 return MLX5_QP_OPTPAR_RETRY_COUNT;
2634 case IB_QP_RNR_RETRY:
2635 return MLX5_QP_OPTPAR_RNR_RETRY;
2636 case IB_QP_RQ_PSN:
2637 return 0;
2638 case IB_QP_MAX_QP_RD_ATOMIC:
2639 return MLX5_QP_OPTPAR_SRA_MAX;
2640 case IB_QP_ALT_PATH:
2641 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2642 case IB_QP_MIN_RNR_TIMER:
2643 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2644 case IB_QP_SQ_PSN:
2645 return 0;
2646 case IB_QP_MAX_DEST_RD_ATOMIC:
2647 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2648 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2649 case IB_QP_PATH_MIG_STATE:
2650 return MLX5_QP_OPTPAR_PM_STATE;
2651 case IB_QP_CAP:
2652 return 0;
2653 case IB_QP_DEST_QPN:
2654 return 0;
2655 }
2656 return 0;
2657}
2658
2659static int ib_mask_to_mlx5_opt(int ib_mask)
2660{
2661 int result = 0;
2662 int i;
2663
2664 for (i = 0; i < 8 * sizeof(int); i++) {
2665 if ((1 << i) & ib_mask)
2666 result |= ib_nr_to_mlx5_nr(1 << i);
2667 }
2668
2669 return result;
2670}
2671
eb49ab0c
AV		 2672static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2673 struct mlx5_ib_rq *rq, int new_state,
2674 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2675{
2676 void *in;
2677 void *rqc;
2678 int inlen;
2679 int err;
2680
2681 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 2682 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2683 if (!in)
2684 return -ENOMEM;
2685
2686 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2687
2688 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2689 MLX5_SET(rqc, rqc, state, new_state);
2690
eb49ab0c
AV		 2691 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2692 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2693 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 2694 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 2695 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2696 } else
2697 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2698 dev->ib_dev.name);
2699 }
2700
2701 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 2702 if (err)
2703 goto out;
2704
2705 rq->state = new_state;
2706
2707out:
2708 kvfree(in);
2709 return err;
2710}
2711
2712static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
7d29f349
BW		 2713 struct mlx5_ib_sq *sq,
2714 int new_state,
2715 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2716{
7d29f349
BW		 2717 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2718 u32 old_rate = ibqp->rate_limit;
2719 u32 new_rate = old_rate;
2720 u16 rl_index = 0;
ad5f8e96 2721 void *in;
2722 void *sqc;
2723 int inlen;
2724 int err;
2725
2726 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 2727 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2728 if (!in)
2729 return -ENOMEM;
2730
2731 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2732
2733 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2734 MLX5_SET(sqc, sqc, state, new_state);
2735
7d29f349
BW		 2736 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2737 if (new_state != MLX5_SQC_STATE_RDY)
2738 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2739 __func__);
2740 else
2741 new_rate = raw_qp_param->rate_limit;
2742 }
2743
2744 if (old_rate != new_rate) {
2745 if (new_rate) {
2746 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2747 if (err) {
2748 pr_err("Failed configuring rate %u: %d\n",
2749 new_rate, err);
2750 goto out;
2751 }
2752 }
2753
2754 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2755 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2756 }
2757
ad5f8e96 2758 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 2759 if (err) {
2760 /* Remove new rate from table if failed */
2761 if (new_rate &&
2762 old_rate != new_rate)
2763 mlx5_rl_remove_rate(dev, new_rate);
ad5f8e96 2764 goto out;
7d29f349
BW		 2765 }
2766
2767 /* Only remove the old rate after new rate was set */
2768 if ((old_rate &&
2769 (old_rate != new_rate)) ||
2770 (new_state != MLX5_SQC_STATE_RDY))
2771 mlx5_rl_remove_rate(dev, old_rate);
ad5f8e96 2772
7d29f349 2773 ibqp->rate_limit = new_rate;
ad5f8e96 2774 sq->state = new_state;
2775
2776out:
2777 kvfree(in);
2778 return err;
2779}
2780
2781static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2782 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2783 u8 tx_affinity)
ad5f8e96 2784{
2785 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2786 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2787 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 2788 int modify_rq = !!qp->rq.wqe_cnt;
2789 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 2790 int rq_state;
2791 int sq_state;
2792 int err;
2793
0680efa2 2794 switch (raw_qp_param->operation) {
ad5f8e96 2795 case MLX5_CMD_OP_RST2INIT_QP:
2796 rq_state = MLX5_RQC_STATE_RDY;
2797 sq_state = MLX5_SQC_STATE_RDY;
2798 break;
2799 case MLX5_CMD_OP_2ERR_QP:
2800 rq_state = MLX5_RQC_STATE_ERR;
2801 sq_state = MLX5_SQC_STATE_ERR;
2802 break;
2803 case MLX5_CMD_OP_2RST_QP:
2804 rq_state = MLX5_RQC_STATE_RST;
2805 sq_state = MLX5_SQC_STATE_RST;
2806 break;
ad5f8e96 2807 case MLX5_CMD_OP_RTR2RTS_QP:
2808 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 2809 if (raw_qp_param->set_mask ==
2810 MLX5_RAW_QP_RATE_LIMIT) {
2811 modify_rq = 0;
2812 sq_state = sq->state;
2813 } else {
2814 return raw_qp_param->set_mask ? -EINVAL : 0;
2815 }
2816 break;
2817 case MLX5_CMD_OP_INIT2INIT_QP:
2818 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 2819 if (raw_qp_param->set_mask)
2820 return -EINVAL;
2821 else
2822 return 0;
ad5f8e96 2823 default:
2824 WARN_ON(1);
2825 return -EINVAL;
2826 }
2827
7d29f349
BW		 2828 if (modify_rq) {
2829 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
ad5f8e96 2830 if (err)
2831 return err;
2832 }
2833
7d29f349 2834 if (modify_sq) {
13eab21f
AH		 2835 if (tx_affinity) {
2836 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2837 tx_affinity);
2838 if (err)
2839 return err;
2840 }
2841
7d29f349 2842 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
13eab21f 2843 }
ad5f8e96 2844
2845 return 0;
2846}
2847
e126ba97
EC		 2848static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2849 const struct ib_qp_attr *attr, int attr_mask,
2850 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2851{
427c1e7b 2852 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2853 [MLX5_QP_STATE_RST] = {
2854 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2855 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2856 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2857 },
2858 [MLX5_QP_STATE_INIT] = {
2859 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2860 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2861 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2862 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2863 },
2864 [MLX5_QP_STATE_RTR] = {
2865 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2866 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2867 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2868 },
2869 [MLX5_QP_STATE_RTS] = {
2870 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2871 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2872 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2873 },
2874 [MLX5_QP_STATE_SQD] = {
2875 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2876 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2877 },
2878 [MLX5_QP_STATE_SQER] = {
2879 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2880 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2881 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2882 },
2883 [MLX5_QP_STATE_ERR] = {
2884 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2885 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2886 }
2887 };
2888
e126ba97
EC		 2889 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2890 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2891 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2892 struct mlx5_ib_cq *send_cq, *recv_cq;
2893 struct mlx5_qp_context *context;
e126ba97 2894 struct mlx5_ib_pd *pd;
eb49ab0c 2895 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 2896 enum mlx5_qp_state mlx5_cur, mlx5_new;
2897 enum mlx5_qp_optpar optpar;
e126ba97
EC		 2898 int mlx5_st;
2899 int err;
427c1e7b 2900 u16 op;
13eab21f 2901 u8 tx_affinity = 0;
e126ba97 2902
1a412fb1
SM		 2903 context = kzalloc(sizeof(*context), GFP_KERNEL);
2904 if (!context)
e126ba97
EC		 2905 return -ENOMEM;
2906
c32a4f29
MS		 2907 err = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
2908 qp->qp_sub_type : ibqp->qp_type);
158abf86
HE		 2909 if (err < 0) {
2910 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2911 goto out;
158abf86 2912 }
e126ba97
EC		 2913
2914 context->flags = cpu_to_be32(err << 16);
2915
2916 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2917 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2918 } else {
2919 switch (attr->path_mig_state) {
2920 case IB_MIG_MIGRATED:
2921 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2922 break;
2923 case IB_MIG_REARM:
2924 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2925 break;
2926 case IB_MIG_ARMED:
2927 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2928 break;
2929 }
2930 }
2931
13eab21f
AH		 2932 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2933 if ((ibqp->qp_type == IB_QPT_RC) ||
2934 (ibqp->qp_type == IB_QPT_UD &&
2935 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2936 (ibqp->qp_type == IB_QPT_UC) ||
2937 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2938 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2939 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2940 if (mlx5_lag_is_active(dev->mdev)) {
2941 tx_affinity = (unsigned int)atomic_add_return(1,
2942 &dev->roce.next_port) %
2943 MLX5_MAX_PORTS + 1;
2944 context->flags |= cpu_to_be32(tx_affinity << 24);
2945 }
2946 }
2947 }
2948
d16e91da 2949 if (is_sqp(ibqp->qp_type)) {
e126ba97 2950 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
c2e53b2c
YH		 2951 } else if ((ibqp->qp_type == IB_QPT_UD &&
2952 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
e126ba97
EC		 2953 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2954 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2955 } else if (attr_mask & IB_QP_PATH_MTU) {
2956 if (attr->path_mtu < IB_MTU_256 ||
2957 attr->path_mtu > IB_MTU_4096) {
2958 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2959 err = -EINVAL;
2960 goto out;
2961 }
938fe83c
SM		 2962 context->mtu_msgmax = (attr->path_mtu << 5) |
2963 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2964 }
2965
2966 if (attr_mask & IB_QP_DEST_QPN)
2967 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2968
2969 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 2970 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 2971
2972 /* todo implement counter_index functionality */
2973
2974 if (is_sqp(ibqp->qp_type))
2975 context->pri_path.port = qp->port;
2976
2977 if (attr_mask & IB_QP_PORT)
2978 context->pri_path.port = attr->port_num;
2979
2980 if (attr_mask & IB_QP_AV) {
75850d0b 2981 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 2982 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 2983 attr_mask, 0, attr, false);
e126ba97
EC		 2984 if (err)
2985 goto out;
2986 }
2987
2988 if (attr_mask & IB_QP_TIMEOUT)
2989 context->pri_path.ackto_lt |= attr->timeout << 3;
2990
2991 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2992 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2993 &context->alt_path,
f879ee8d
AS		 2994 attr->alt_port_num,
2995 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2996 0, attr, true);
e126ba97
EC		 2997 if (err)
2998 goto out;
2999 }
3000
3001 pd = get_pd(qp);
89ea94a7
MG		 3002 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3003 &send_cq, &recv_cq);
e126ba97
EC		 3004
3005 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3006 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3007 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3008 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3009
3010 if (attr_mask & IB_QP_RNR_RETRY)
3011 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3012
3013 if (attr_mask & IB_QP_RETRY_CNT)
3014 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3015
3016 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3017 if (attr->max_rd_atomic)
3018 context->params1 |=
3019 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3020 }
3021
3022 if (attr_mask & IB_QP_SQ_PSN)
3023 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3024
3025 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3026 if (attr->max_dest_rd_atomic)
3027 context->params2 |=
3028 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3029 }
3030
3031 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3032 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3033
3034 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3035 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3036
3037 if (attr_mask & IB_QP_RQ_PSN)
3038 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3039
3040 if (attr_mask & IB_QP_QKEY)
3041 context->qkey = cpu_to_be32(attr->qkey);
3042
3043 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3044 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3045
0837e86a
MB		 3046 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3047 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3048 qp->port) - 1;
c2e53b2c
YH		 3049
3050 /* Underlay port should be used - index 0 function per port */
3051 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3052 port_num = 0;
3053
eb49ab0c 3054 mibport = &dev->port[port_num];
0837e86a 3055 context->qp_counter_set_usr_page |=
e1f24a79 3056 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
0837e86a
MB		 3057 }
3058
e126ba97
EC		 3059 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3060 context->sq_crq_size |= cpu_to_be16(1 << 4);
3061
b11a4f9c
HE		 3062 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3063 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 3064
3065 mlx5_cur = to_mlx5_state(cur_state);
3066 mlx5_new = to_mlx5_state(new_state);
c32a4f29
MS		 3067 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3068 qp->qp_sub_type : ibqp->qp_type);
07c9113f 3069 if (mlx5_st < 0)
e126ba97
EC		 3070 goto out;
3071
427c1e7b 3072 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3073 !optab[mlx5_cur][mlx5_new])
3074 goto out;
3075
3076 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 3077 optpar = ib_mask_to_mlx5_opt(attr_mask);
3078 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 3079
c2e53b2c
YH		 3080 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3081 qp->flags & MLX5_IB_QP_UNDERLAY) {
0680efa2
AV		 3082 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3083
3084 raw_qp_param.operation = op;
eb49ab0c 3085 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
e1f24a79 3086 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
eb49ab0c
AV		 3087 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3088 }
7d29f349
BW		 3089
3090 if (attr_mask & IB_QP_RATE_LIMIT) {
3091 raw_qp_param.rate_limit = attr->rate_limit;
3092 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3093 }
3094
13eab21f 3095 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 3096 } else {
1a412fb1 3097 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 3098 &base->mqp);
0680efa2
AV		 3099 }
3100
e126ba97
EC		 3101 if (err)
3102 goto out;
3103
3104 qp->state = new_state;
3105
3106 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 3107 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 3108 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 3109 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 3110 if (attr_mask & IB_QP_PORT)
3111 qp->port = attr->port_num;
3112 if (attr_mask & IB_QP_ALT_PATH)
19098df2 3113 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 3114
3115 /*
3116 * If we moved a kernel QP to RESET, clean up all old CQ
3117 * entries and reinitialize the QP.
3118 */
3119 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 3120 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 3121 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3122 if (send_cq != recv_cq)
19098df2 3123 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 3124
3125 qp->rq.head = 0;
3126 qp->rq.tail = 0;
3127 qp->sq.head = 0;
3128 qp->sq.tail = 0;
3129 qp->sq.cur_post = 0;
3130 qp->sq.last_poll = 0;
3131 qp->db.db[MLX5_RCV_DBR] = 0;
3132 qp->db.db[MLX5_SND_DBR] = 0;
3133 }
3134
3135out:
1a412fb1 3136 kfree(context);
e126ba97
EC		 3137 return err;
3138}
3139
c32a4f29
MS		 3140static inline bool is_valid_mask(int mask, int req, int opt)
3141{
3142 if ((mask & req) != req)
3143 return false;
3144
3145 if (mask & ~(req | opt))
3146 return false;
3147
3148 return true;
3149}
3150
3151/* check valid transition for driver QP types
3152 * for now the only QP type that this function supports is DCI
3153 */
3154static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3155 enum ib_qp_attr_mask attr_mask)
3156{
3157 int req = IB_QP_STATE;
3158 int opt = 0;
3159
3160 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3161 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3162 return is_valid_mask(attr_mask, req, opt);
3163 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3164 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3165 return is_valid_mask(attr_mask, req, opt);
3166 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3167 req |= IB_QP_PATH_MTU;
3168 opt = IB_QP_PKEY_INDEX;
3169 return is_valid_mask(attr_mask, req, opt);
3170 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3171 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3172 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3173 opt = IB_QP_MIN_RNR_TIMER;
3174 return is_valid_mask(attr_mask, req, opt);
3175 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3176 opt = IB_QP_MIN_RNR_TIMER;
3177 return is_valid_mask(attr_mask, req, opt);
3178 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3179 return is_valid_mask(attr_mask, req, opt);
3180 }
3181 return false;
3182}
3183
e126ba97
EC		 3184int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3185 int attr_mask, struct ib_udata *udata)
3186{
3187 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3188 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 3189 enum ib_qp_type qp_type;
e126ba97
EC		 3190 enum ib_qp_state cur_state, new_state;
3191 int err = -EINVAL;
3192 int port;
2811ba51 3193 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 3194
28d61370
YH		 3195 if (ibqp->rwq_ind_tbl)
3196 return -ENOSYS;
3197
d16e91da
HE		 3198 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3199 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3200
c32a4f29
MS		 3201 if (ibqp->qp_type == IB_QPT_DRIVER)
3202 qp_type = qp->qp_sub_type;
3203 else
3204 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3205 IB_QPT_GSI : ibqp->qp_type;
3206
d16e91da 3207
e126ba97
EC		 3208 mutex_lock(&qp->mutex);
3209
3210 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3211 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3212
2811ba51
AS		 3213 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3214 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3215 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3216 }
3217
c2e53b2c
YH		 3218 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3219 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3220 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3221 attr_mask);
3222 goto out;
3223 }
3224 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
c32a4f29
MS		 3225 qp_type != MLX5_IB_QPT_DCI &&
3226 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 3227 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3228 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 3229 goto out;
c32a4f29
MS		 3230 } else if (qp_type == MLX5_IB_QPT_DCI &&
3231 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3232 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3233 cur_state, new_state, qp_type, attr_mask);
3234 goto out;
158abf86 3235 }
e126ba97
EC		 3236
3237 if ((attr_mask & IB_QP_PORT) &&
938fe83c 3238 (attr->port_num == 0 ||
158abf86
HE		 3239 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
3240 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3241 attr->port_num, dev->num_ports);
e126ba97 3242 goto out;
158abf86 3243 }
e126ba97
EC		 3244
3245 if (attr_mask & IB_QP_PKEY_INDEX) {
3246 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 3247 if (attr->pkey_index >=
158abf86
HE		 3248 dev->mdev->port_caps[port - 1].pkey_table_len) {
3249 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3250 attr->pkey_index);
e126ba97 3251 goto out;
158abf86 3252 }
e126ba97
EC		 3253 }
3254
3255 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 3256 attr->max_rd_atomic >
158abf86
HE		 3257 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3258 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3259 attr->max_rd_atomic);
e126ba97 3260 goto out;
158abf86 3261 }
e126ba97
EC		 3262
3263 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 3264 attr->max_dest_rd_atomic >
158abf86
HE		 3265 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3266 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3267 attr->max_dest_rd_atomic);
e126ba97 3268 goto out;
158abf86 3269 }
e126ba97
EC		 3270
3271 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3272 err = 0;
3273 goto out;
3274 }
3275
3276 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
3277
3278out:
3279 mutex_unlock(&qp->mutex);
3280 return err;
3281}
3282
3283static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3284{
3285 struct mlx5_ib_cq *cq;
3286 unsigned cur;
3287
3288 cur = wq->head - wq->tail;
3289 if (likely(cur + nreq < wq->max_post))
3290 return 0;
3291
3292 cq = to_mcq(ib_cq);
3293 spin_lock(&cq->lock);
3294 cur = wq->head - wq->tail;
3295 spin_unlock(&cq->lock);
3296
3297 return cur + nreq >= wq->max_post;
3298}
3299
3300static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3301 u64 remote_addr, u32 rkey)
3302{
3303 rseg->raddr = cpu_to_be64(remote_addr);
3304 rseg->rkey = cpu_to_be32(rkey);
3305 rseg->reserved = 0;
3306}
3307
f0313965
ES		 3308static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3309 struct ib_send_wr *wr, void *qend,
3310 struct mlx5_ib_qp *qp, int *size)
3311{
3312 void *seg = eseg;
3313
3314 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3315
3316 if (wr->send_flags & IB_SEND_IP_CSUM)
3317 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3318 MLX5_ETH_WQE_L4_CSUM;
3319
3320 seg += sizeof(struct mlx5_wqe_eth_seg);
3321 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3322
3323 if (wr->opcode == IB_WR_LSO) {
3324 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2b31f7ae 3325 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
f0313965
ES		 3326 u64 left, leftlen, copysz;
3327 void *pdata = ud_wr->header;
3328
3329 left = ud_wr->hlen;
3330 eseg->mss = cpu_to_be16(ud_wr->mss);
2b31f7ae 3331 eseg->inline_hdr.sz = cpu_to_be16(left);
f0313965
ES		 3332
3333 /*
3334 * check if there is space till the end of queue, if yes,
3335 * copy all in one shot, otherwise copy till the end of queue,
3336 * rollback and than the copy the left
3337 */
2b31f7ae 3338 leftlen = qend - (void *)eseg->inline_hdr.start;
f0313965
ES		 3339 copysz = min_t(u64, leftlen, left);
3340
3341 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3342
3343 if (likely(copysz > size_of_inl_hdr_start)) {
3344 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3345 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3346 }
3347
3348 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3349 seg = mlx5_get_send_wqe(qp, 0);
3350 left -= copysz;
3351 pdata += copysz;
3352 memcpy(seg, pdata, left);
3353 seg += ALIGN(left, 16);
3354 *size += ALIGN(left, 16) / 16;
3355 }
3356 }
3357
3358 return seg;
3359}
3360
e126ba97
EC		 3361static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3362 struct ib_send_wr *wr)
3363{
e622f2f4
CH		 3364 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3365 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3366 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3367}
3368
3369static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3370{
3371 dseg->byte_count = cpu_to_be32(sg->length);
3372 dseg->lkey = cpu_to_be32(sg->lkey);
3373 dseg->addr = cpu_to_be64(sg->addr);
3374}
3375
31616255 3376static u64 get_xlt_octo(u64 bytes)
e126ba97 3377{
31616255
AK		 3378 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3379 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3380}
3381
3382static __be64 frwr_mkey_mask(void)
3383{
3384 u64 result;
3385
3386 result = MLX5_MKEY_MASK_LEN |
3387 MLX5_MKEY_MASK_PAGE_SIZE |
3388 MLX5_MKEY_MASK_START_ADDR |
3389 MLX5_MKEY_MASK_EN_RINVAL |
3390 MLX5_MKEY_MASK_KEY |
3391 MLX5_MKEY_MASK_LR |
3392 MLX5_MKEY_MASK_LW |
3393 MLX5_MKEY_MASK_RR |
3394 MLX5_MKEY_MASK_RW |
3395 MLX5_MKEY_MASK_A |
3396 MLX5_MKEY_MASK_SMALL_FENCE |
3397 MLX5_MKEY_MASK_FREE;
3398
3399 return cpu_to_be64(result);
3400}
3401
e6631814
SG		 3402static __be64 sig_mkey_mask(void)
3403{
3404 u64 result;
3405
3406 result = MLX5_MKEY_MASK_LEN |
3407 MLX5_MKEY_MASK_PAGE_SIZE |
3408 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3409 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3410 MLX5_MKEY_MASK_EN_RINVAL |
3411 MLX5_MKEY_MASK_KEY |
3412 MLX5_MKEY_MASK_LR |
3413 MLX5_MKEY_MASK_LW |
3414 MLX5_MKEY_MASK_RR |
3415 MLX5_MKEY_MASK_RW |
3416 MLX5_MKEY_MASK_SMALL_FENCE |
3417 MLX5_MKEY_MASK_FREE |
3418 MLX5_MKEY_MASK_BSF_EN;
3419
3420 return cpu_to_be64(result);
3421}
3422
8a187ee5 3423static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3424 struct mlx5_ib_mr *mr)
8a187ee5 3425{
31616255 3426 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3427
3428 memset(umr, 0, sizeof(*umr));
b005d316 3429
8a187ee5 3430 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
31616255 3431 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3432 umr->mkey_mask = frwr_mkey_mask();
3433}
3434
dd01e66a 3435static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3436{
3437 memset(umr, 0, sizeof(*umr));
dd01e66a 3438 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3439 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3440}
3441
31616255 3442static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 3443{
3444 u64 result;
3445
31616255 3446 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 3447 MLX5_MKEY_MASK_FREE;
3448
968e78dd
HE		 3449 return cpu_to_be64(result);
3450}
3451
31616255 3452static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 3453{
3454 u64 result;
3455
3456 result = MLX5_MKEY_MASK_FREE;
3457
3458 return cpu_to_be64(result);
3459}
3460
56e11d62
NO		 3461static __be64 get_umr_update_translation_mask(void)
3462{
3463 u64 result;
3464
3465 result = MLX5_MKEY_MASK_LEN |
3466 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 3467 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 3468
3469 return cpu_to_be64(result);
3470}
3471
31616255 3472static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 3473{
3474 u64 result;
3475
31616255
AK		 3476 result = MLX5_MKEY_MASK_LR |
3477 MLX5_MKEY_MASK_LW |
56e11d62 3478 MLX5_MKEY_MASK_RR |
31616255
AK		 3479 MLX5_MKEY_MASK_RW;
3480
3481 if (atomic)
3482 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 3483
3484 return cpu_to_be64(result);
3485}
3486
3487static __be64 get_umr_update_pd_mask(void)
3488{
3489 u64 result;
3490
31616255 3491 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 3492
3493 return cpu_to_be64(result);
3494}
3495
e126ba97 3496static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
578e7264 3497 struct ib_send_wr *wr, int atomic)
e126ba97 3498{
e622f2f4 3499 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3500
3501 memset(umr, 0, sizeof(*umr));
3502
968e78dd
HE		 3503 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3504 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3505 else
3506 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3507
31616255
AK		 3508 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3509 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3510 u64 offset = get_xlt_octo(umrwr->offset);
3511
3512 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3513 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3514 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 3515 }
31616255
AK		 3516 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3517 umr->mkey_mask |= get_umr_update_translation_mask();
3518 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3519 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3520 umr->mkey_mask |= get_umr_update_pd_mask();
3521 }
3522 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3523 umr->mkey_mask |= get_umr_enable_mr_mask();
3524 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3525 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 3526
3527 if (!wr->num_sge)
968e78dd 3528 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3529}
3530
3531static u8 get_umr_flags(int acc)
3532{
3533 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3534 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3535 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3536 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3537 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3538}
3539
8a187ee5
SG		 3540static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3541 struct mlx5_ib_mr *mr,
3542 u32 key, int access)
3543{
3544 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3545
3546 memset(seg, 0, sizeof(*seg));
b005d316 3547
ec22eb53 3548 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3549 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3550 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3551 /* KLMs take twice the size of MTTs */
3552 ndescs *= 2;
3553
3554 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3555 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3556 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3557 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3558 seg->len = cpu_to_be64(mr->ibmr.length);
3559 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3560}
3561
dd01e66a 3562static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3563{
3564 memset(seg, 0, sizeof(*seg));
dd01e66a 3565 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3566}
3567
3568static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3569{
e622f2f4 3570 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3571
e126ba97 3572 memset(seg, 0, sizeof(*seg));
31616255 3573 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 3574 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 3575
968e78dd 3576 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 3577 if (umrwr->pd)
3578 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3579 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3580 !umrwr->length)
3581 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3582
3583 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 3584 seg->len = cpu_to_be64(umrwr->length);
3585 seg->log2_page_size = umrwr->page_shift;
746b5583 3586 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3587 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3588}
3589
8a187ee5
SG		 3590static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3591 struct mlx5_ib_mr *mr,
3592 struct mlx5_ib_pd *pd)
3593{
3594 int bcount = mr->desc_size * mr->ndescs;
3595
3596 dseg->addr = cpu_to_be64(mr->desc_map);
3597 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3598 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3599}
3600
e126ba97
EC		 3601static __be32 send_ieth(struct ib_send_wr *wr)
3602{
3603 switch (wr->opcode) {
3604 case IB_WR_SEND_WITH_IMM:
3605 case IB_WR_RDMA_WRITE_WITH_IMM:
3606 return wr->ex.imm_data;
3607
3608 case IB_WR_SEND_WITH_INV:
3609 return cpu_to_be32(wr->ex.invalidate_rkey);
3610
3611 default:
3612 return 0;
3613 }
3614}
3615
3616static u8 calc_sig(void *wqe, int size)
3617{
3618 u8 *p = wqe;
3619 u8 res = 0;
3620 int i;
3621
3622 for (i = 0; i < size; i++)
3623 res ^= p[i];
3624
3625 return ~res;
3626}
3627
3628static u8 wq_sig(void *wqe)
3629{
3630 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3631}
3632
3633static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3634 void *wqe, int *sz)
3635{
3636 struct mlx5_wqe_inline_seg *seg;
3637 void *qend = qp->sq.qend;
3638 void *addr;
3639 int inl = 0;
3640 int copy;
3641 int len;
3642 int i;
3643
3644 seg = wqe;
3645 wqe += sizeof(*seg);
3646 for (i = 0; i < wr->num_sge; i++) {
3647 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3648 len = wr->sg_list[i].length;
3649 inl += len;
3650
3651 if (unlikely(inl > qp->max_inline_data))
3652 return -ENOMEM;
3653
3654 if (unlikely(wqe + len > qend)) {
3655 copy = qend - wqe;
3656 memcpy(wqe, addr, copy);
3657 addr += copy;
3658 len -= copy;
3659 wqe = mlx5_get_send_wqe(qp, 0);
3660 }
3661 memcpy(wqe, addr, len);
3662 wqe += len;
3663 }
3664
3665 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3666
3667 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3668
3669 return 0;
3670}
3671
e6631814
SG		 3672static u16 prot_field_size(enum ib_signature_type type)
3673{
3674 switch (type) {
3675 case IB_SIG_TYPE_T10_DIF:
3676 return MLX5_DIF_SIZE;
3677 default:
3678 return 0;
3679 }
3680}
3681
3682static u8 bs_selector(int block_size)
3683{
3684 switch (block_size) {
3685 case 512: return 0x1;
3686 case 520: return 0x2;
3687 case 4096: return 0x3;
3688 case 4160: return 0x4;
3689 case 1073741824: return 0x5;
3690 default: return 0;
3691 }
3692}
3693
78eda2bb
SG		 3694static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3695 struct mlx5_bsf_inl *inl)
e6631814 3696{
142537f4
SG		 3697 /* Valid inline section and allow BSF refresh */
3698 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3699 MLX5_BSF_REFRESH_DIF);
3700 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3701 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3702 /* repeating block */
3703 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3704 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3705 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3706
78eda2bb
SG		 3707 if (domain->sig.dif.ref_remap)
3708 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3709
78eda2bb
SG		 3710 if (domain->sig.dif.app_escape) {
3711 if (domain->sig.dif.ref_escape)
3712 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3713 else
3714 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3715 }
3716
78eda2bb
SG		 3717 inl->dif_app_bitmask_check =
3718 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3719}
3720
3721static int mlx5_set_bsf(struct ib_mr *sig_mr,
3722 struct ib_sig_attrs *sig_attrs,
3723 struct mlx5_bsf *bsf, u32 data_size)
3724{
3725 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3726 struct mlx5_bsf_basic *basic = &bsf->basic;
3727 struct ib_sig_domain *mem = &sig_attrs->mem;
3728 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3729
c7f44fbd 3730 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3731
3732 /* Basic + Extended + Inline */
3733 basic->bsf_size_sbs = 1 << 7;
3734 /* Input domain check byte mask */
3735 basic->check_byte_mask = sig_attrs->check_mask;
3736 basic->raw_data_size = cpu_to_be32(data_size);
3737
3738 /* Memory domain */
e6631814 3739 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3740 case IB_SIG_TYPE_NONE:
3741 break;
e6631814 3742 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3743 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3744 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3745 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3746 break;
3747 default:
3748 return -EINVAL;
3749 }
e6631814 3750
78eda2bb
SG		 3751 /* Wire domain */
3752 switch (sig_attrs->wire.sig_type) {
3753 case IB_SIG_TYPE_NONE:
3754 break;
3755 case IB_SIG_TYPE_T10_DIF:
e6631814 3756 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3757 mem->sig_type == wire->sig_type) {
e6631814 3758 /* Same block structure */
142537f4 3759 basic->bsf_size_sbs |= 1 << 4;
e6631814 3760 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3761 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3762 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3763 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3764 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3765 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3766 } else
3767 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3768
142537f4 3769 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3770 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3771 break;
e6631814
SG		 3772 default:
3773 return -EINVAL;
3774 }
3775
3776 return 0;
3777}
3778
e622f2f4
CH		 3779static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3780 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3781{
e622f2f4
CH		 3782 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3783 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3784 struct mlx5_bsf *bsf;
e622f2f4
CH		 3785 u32 data_len = wr->wr.sg_list->length;
3786 u32 data_key = wr->wr.sg_list->lkey;
3787 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3788 int ret;
3789 int wqe_size;
3790
e622f2f4
CH		 3791 if (!wr->prot ||
3792 (data_key == wr->prot->lkey &&
3793 data_va == wr->prot->addr &&
3794 data_len == wr->prot->length)) {
e6631814
SG		 3795 /**
3796 * Source domain doesn't contain signature information
5c273b16 3797 * or data and protection are interleaved in memory.
e6631814
SG		 3798 * So need construct:
3799 * ------------------
3800 * | data_klm |
3801 * ------------------
3802 * | BSF |
3803 * ------------------
3804 **/
3805 struct mlx5_klm *data_klm = *seg;
3806
3807 data_klm->bcount = cpu_to_be32(data_len);
3808 data_klm->key = cpu_to_be32(data_key);
3809 data_klm->va = cpu_to_be64(data_va);
3810 wqe_size = ALIGN(sizeof(*data_klm), 64);
3811 } else {
3812 /**
3813 * Source domain contains signature information
3814 * So need construct a strided block format:
3815 * ---------------------------
3816 * | stride_block_ctrl |
3817 * ---------------------------
3818 * | data_klm |
3819 * ---------------------------
3820 * | prot_klm |
3821 * ---------------------------
3822 * | BSF |
3823 * ---------------------------
3824 **/
3825 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3826 struct mlx5_stride_block_entry *data_sentry;
3827 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3828 u32 prot_key = wr->prot->lkey;
3829 u64 prot_va = wr->prot->addr;
e6631814
SG		 3830 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3831 int prot_size;
3832
3833 sblock_ctrl = *seg;
3834 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3835 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3836
3837 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3838 if (!prot_size) {
3839 pr_err("Bad block size given: %u\n", block_size);
3840 return -EINVAL;
3841 }
3842 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3843 prot_size);
3844 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3845 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3846 sblock_ctrl->num_entries = cpu_to_be16(2);
3847
3848 data_sentry->bcount = cpu_to_be16(block_size);
3849 data_sentry->key = cpu_to_be32(data_key);
3850 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3851 data_sentry->stride = cpu_to_be16(block_size);
3852
e6631814
SG		 3853 prot_sentry->bcount = cpu_to_be16(prot_size);
3854 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3855 prot_sentry->va = cpu_to_be64(prot_va);
3856 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3857
e6631814
SG		 3858 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3859 sizeof(*prot_sentry), 64);
3860 }
3861
3862 *seg += wqe_size;
3863 *size += wqe_size / 16;
3864 if (unlikely((*seg == qp->sq.qend)))
3865 *seg = mlx5_get_send_wqe(qp, 0);
3866
3867 bsf = *seg;
3868 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3869 if (ret)
3870 return -EINVAL;
3871
3872 *seg += sizeof(*bsf);
3873 *size += sizeof(*bsf) / 16;
3874 if (unlikely((*seg == qp->sq.qend)))
3875 *seg = mlx5_get_send_wqe(qp, 0);
3876
3877 return 0;
3878}
3879
3880static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
31616255 3881 struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 3882 u32 length, u32 pdn)
3883{
e622f2f4 3884 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3885 u32 sig_key = sig_mr->rkey;
d5436ba0 3886 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3887
3888 memset(seg, 0, sizeof(*seg));
3889
e622f2f4 3890 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 3891 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 3892 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3893 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3894 MLX5_MKEY_BSF_EN | pdn);
3895 seg->len = cpu_to_be64(length);
31616255 3896 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 3897 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3898}
3899
3900static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3901 u32 size)
e6631814
SG		 3902{
3903 memset(umr, 0, sizeof(*umr));
3904
3905 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 3906 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 3907 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3908 umr->mkey_mask = sig_mkey_mask();
3909}
3910
3911
e622f2f4 3912static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3913 void **seg, int *size)
3914{
e622f2f4
CH		 3915 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3916 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 3917 u32 pdn = get_pd(qp)->pdn;
31616255 3918 u32 xlt_size;
e6631814
SG		 3919 int region_len, ret;
3920
e622f2f4
CH		 3921 if (unlikely(wr->wr.num_sge != 1) ||
3922 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3923 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3924 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3925 return -EINVAL;
3926
3927 /* length of the protected region, data + protection */
e622f2f4
CH		 3928 region_len = wr->wr.sg_list->length;
3929 if (wr->prot &&
3930 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3931 wr->prot->addr != wr->wr.sg_list->addr ||
3932 wr->prot->length != wr->wr.sg_list->length))
3933 region_len += wr->prot->length;
e6631814
SG		 3934
3935 /**
3936 * KLM octoword size - if protection was provided
3937 * then we use strided block format (3 octowords),
3938 * else we use single KLM (1 octoword)
3939 **/
31616255 3940 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 3941
31616255 3942 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 3943 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3944 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3945 if (unlikely((*seg == qp->sq.qend)))
3946 *seg = mlx5_get_send_wqe(qp, 0);
3947
31616255 3948 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 3949 *seg += sizeof(struct mlx5_mkey_seg);
3950 *size += sizeof(struct mlx5_mkey_seg) / 16;
3951 if (unlikely((*seg == qp->sq.qend)))
3952 *seg = mlx5_get_send_wqe(qp, 0);
3953
3954 ret = set_sig_data_segment(wr, qp, seg, size);
3955 if (ret)
3956 return ret;
3957
d5436ba0 3958 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3959 return 0;
3960}
3961
3962static int set_psv_wr(struct ib_sig_domain *domain,
3963 u32 psv_idx, void **seg, int *size)
3964{
3965 struct mlx5_seg_set_psv *psv_seg = *seg;
3966
3967 memset(psv_seg, 0, sizeof(*psv_seg));
3968 psv_seg->psv_num = cpu_to_be32(psv_idx);
3969 switch (domain->sig_type) {
78eda2bb
SG		 3970 case IB_SIG_TYPE_NONE:
3971 break;
e6631814
SG		 3972 case IB_SIG_TYPE_T10_DIF:
3973 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3974 domain->sig.dif.app_tag);
3975 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3976 break;
e6631814 3977 default:
12bbf1ea
LR		 3978 pr_err("Bad signature type (%d) is given.\n",
3979 domain->sig_type);
3980 return -EINVAL;
e6631814
SG		 3981 }
3982
78eda2bb
SG		 3983 *seg += sizeof(*psv_seg);
3984 *size += sizeof(*psv_seg) / 16;
3985
e6631814
SG		 3986 return 0;
3987}
3988
8a187ee5
SG		 3989static int set_reg_wr(struct mlx5_ib_qp *qp,
3990 struct ib_reg_wr *wr,
3991 void **seg, int *size)
3992{
3993 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3994 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3995
3996 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3997 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3998 "Invalid IB_SEND_INLINE send flag\n");
3999 return -EINVAL;
4000 }
4001
4002 set_reg_umr_seg(*seg, mr);
4003 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4004 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4005 if (unlikely((*seg == qp->sq.qend)))
4006 *seg = mlx5_get_send_wqe(qp, 0);
4007
4008 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4009 *seg += sizeof(struct mlx5_mkey_seg);
4010 *size += sizeof(struct mlx5_mkey_seg) / 16;
4011 if (unlikely((*seg == qp->sq.qend)))
4012 *seg = mlx5_get_send_wqe(qp, 0);
4013
4014 set_reg_data_seg(*seg, mr, pd);
4015 *seg += sizeof(struct mlx5_wqe_data_seg);
4016 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4017
4018 return 0;
4019}
4020
dd01e66a 4021static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 4022{
dd01e66a 4023 set_linv_umr_seg(*seg);
e126ba97
EC		 4024 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4025 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4026 if (unlikely((*seg == qp->sq.qend)))
4027 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 4028 set_linv_mkey_seg(*seg);
e126ba97
EC		 4029 *seg += sizeof(struct mlx5_mkey_seg);
4030 *size += sizeof(struct mlx5_mkey_seg) / 16;
4031 if (unlikely((*seg == qp->sq.qend)))
4032 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 4033}
4034
4035static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4036{
4037 __be32 *p = NULL;
4038 int tidx = idx;
4039 int i, j;
4040
4041 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4042 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4043 if ((i & 0xf) == 0) {
4044 void *buf = mlx5_get_send_wqe(qp, tidx);
4045 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4046 p = buf;
4047 j = 0;
4048 }
4049 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4050 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4051 be32_to_cpu(p[j + 3]));
4052 }
4053}
4054
6e5eadac
SG		 4055static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4056 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 4057 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 4058 int *size, int nreq)
4059{
b2a232d2
LR		 4060 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4061 return -ENOMEM;
6e5eadac
SG		 4062
4063 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4064 *seg = mlx5_get_send_wqe(qp, *idx);
4065 *ctrl = *seg;
4066 *(uint32_t *)(*seg + 8) = 0;
4067 (*ctrl)->imm = send_ieth(wr);
4068 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4069 (wr->send_flags & IB_SEND_SIGNALED ?
4070 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4071 (wr->send_flags & IB_SEND_SOLICITED ?
4072 MLX5_WQE_CTRL_SOLICITED : 0);
4073
4074 *seg += sizeof(**ctrl);
4075 *size = sizeof(**ctrl) / 16;
4076
b2a232d2 4077 return 0;
6e5eadac
SG		 4078}
4079
4080static void finish_wqe(struct mlx5_ib_qp *qp,
4081 struct mlx5_wqe_ctrl_seg *ctrl,
4082 u8 size, unsigned idx, u64 wr_id,
6e8484c5 4083 int nreq, u8 fence, u32 mlx5_opcode)
6e5eadac
SG		 4084{
4085 u8 opmod = 0;
4086
4087 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4088 mlx5_opcode | ((u32)opmod << 24));
19098df2 4089 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac 4090 ctrl->fm_ce_se |= fence;
6e5eadac
SG		 4091 if (unlikely(qp->wq_sig))
4092 ctrl->signature = wq_sig(ctrl);
4093
4094 qp->sq.wrid[idx] = wr_id;
4095 qp->sq.w_list[idx].opcode = mlx5_opcode;
4096 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4097 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4098 qp->sq.w_list[idx].next = qp->sq.cur_post;
4099}
4100
4101
e126ba97
EC		 4102int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4103 struct ib_send_wr **bad_wr)
4104{
4105 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4106 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 4107 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 4108 struct mlx5_ib_qp *qp;
e6631814 4109 struct mlx5_ib_mr *mr;
e126ba97
EC		 4110 struct mlx5_wqe_data_seg *dpseg;
4111 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 4112 struct mlx5_bf *bf;
e126ba97 4113 int uninitialized_var(size);
d16e91da 4114 void *qend;
e126ba97 4115 unsigned long flags;
e126ba97
EC		 4116 unsigned idx;
4117 int err = 0;
e126ba97
EC		 4118 int num_sge;
4119 void *seg;
4120 int nreq;
4121 int i;
4122 u8 next_fence = 0;
e126ba97
EC		 4123 u8 fence;
4124
d16e91da
HE		 4125 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4126 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4127
4128 qp = to_mqp(ibqp);
5fe9dec0 4129 bf = &qp->bf;
d16e91da
HE		 4130 qend = qp->sq.qend;
4131
e126ba97
EC		 4132 spin_lock_irqsave(&qp->sq.lock, flags);
4133
89ea94a7
MG		 4134 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4135 err = -EIO;
4136 *bad_wr = wr;
4137 nreq = 0;
4138 goto out;
4139 }
4140
e126ba97 4141 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 4142 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 4143 mlx5_ib_warn(dev, "\n");
4144 err = -EINVAL;
4145 *bad_wr = wr;
4146 goto out;
4147 }
4148
6e5eadac
SG		 4149 num_sge = wr->num_sge;
4150 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 4151 mlx5_ib_warn(dev, "\n");
24be409b 4152 err = -EINVAL;
e126ba97
EC		 4153 *bad_wr = wr;
4154 goto out;
4155 }
4156
6e5eadac
SG		 4157 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4158 if (err) {
e126ba97
EC		 4159 mlx5_ib_warn(dev, "\n");
4160 err = -ENOMEM;
4161 *bad_wr = wr;
4162 goto out;
4163 }
4164
6e8484c5
MG		 4165 if (wr->opcode == IB_WR_LOCAL_INV ||
4166 wr->opcode == IB_WR_REG_MR) {
4167 fence = dev->umr_fence;
4168 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4169 } else if (wr->send_flags & IB_SEND_FENCE) {
4170 if (qp->next_fence)
4171 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4172 else
4173 fence = MLX5_FENCE_MODE_FENCE;
4174 } else {
4175 fence = qp->next_fence;
4176 }
4177
e126ba97
EC		 4178 switch (ibqp->qp_type) {
4179 case IB_QPT_XRC_INI:
4180 xrc = seg;
e126ba97
EC		 4181 seg += sizeof(*xrc);
4182 size += sizeof(*xrc) / 16;
4183 /* fall through */
4184 case IB_QPT_RC:
4185 switch (wr->opcode) {
4186 case IB_WR_RDMA_READ:
4187 case IB_WR_RDMA_WRITE:
4188 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4189 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4190 rdma_wr(wr)->rkey);
f241e749 4191 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 4192 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4193 break;
4194
4195 case IB_WR_ATOMIC_CMP_AND_SWP:
4196 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 4197 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 4198 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4199 err = -ENOSYS;
4200 *bad_wr = wr;
4201 goto out;
e126ba97
EC		 4202
4203 case IB_WR_LOCAL_INV:
e126ba97
EC		 4204 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4205 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 4206 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 4207 num_sge = 0;
4208 break;
4209
8a187ee5 4210 case IB_WR_REG_MR:
8a187ee5
SG		 4211 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4212 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4213 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4214 if (err) {
4215 *bad_wr = wr;
4216 goto out;
4217 }
4218 num_sge = 0;
4219 break;
4220
e6631814
SG		 4221 case IB_WR_REG_SIG_MR:
4222 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 4223 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 4224
4225 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4226 err = set_sig_umr_wr(wr, qp, &seg, &size);
4227 if (err) {
4228 mlx5_ib_warn(dev, "\n");
4229 *bad_wr = wr;
4230 goto out;
4231 }
4232
6e8484c5
MG		 4233 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4234 fence, MLX5_OPCODE_UMR);
e6631814
SG		 4235 /*
4236 * SET_PSV WQEs are not signaled and solicited
4237 * on error
4238 */
4239 wr->send_flags &= ~IB_SEND_SIGNALED;
4240 wr->send_flags |= IB_SEND_SOLICITED;
4241 err = begin_wqe(qp, &seg, &ctrl, wr,
4242 &idx, &size, nreq);
4243 if (err) {
4244 mlx5_ib_warn(dev, "\n");
4245 err = -ENOMEM;
4246 *bad_wr = wr;
4247 goto out;
4248 }
4249
e622f2f4 4250 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 4251 mr->sig->psv_memory.psv_idx, &seg,
4252 &size);
4253 if (err) {
4254 mlx5_ib_warn(dev, "\n");
4255 *bad_wr = wr;
4256 goto out;
4257 }
4258
6e8484c5
MG		 4259 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4260 fence, MLX5_OPCODE_SET_PSV);
e6631814
SG		 4261 err = begin_wqe(qp, &seg, &ctrl, wr,
4262 &idx, &size, nreq);
4263 if (err) {
4264 mlx5_ib_warn(dev, "\n");
4265 err = -ENOMEM;
4266 *bad_wr = wr;
4267 goto out;
4268 }
4269
e622f2f4 4270 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 4271 mr->sig->psv_wire.psv_idx, &seg,
4272 &size);
4273 if (err) {
4274 mlx5_ib_warn(dev, "\n");
4275 *bad_wr = wr;
4276 goto out;
4277 }
4278
6e8484c5
MG		 4279 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4280 fence, MLX5_OPCODE_SET_PSV);
4281 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e6631814
SG		 4282 num_sge = 0;
4283 goto skip_psv;
4284
e126ba97
EC		 4285 default:
4286 break;
4287 }
4288 break;
4289
4290 case IB_QPT_UC:
4291 switch (wr->opcode) {
4292 case IB_WR_RDMA_WRITE:
4293 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4294 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4295 rdma_wr(wr)->rkey);
e126ba97
EC		 4296 seg += sizeof(struct mlx5_wqe_raddr_seg);
4297 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4298 break;
4299
4300 default:
4301 break;
4302 }
4303 break;
4304
e126ba97 4305 case IB_QPT_SMI:
1e0e50b6
MG		 4306 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4307 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4308 err = -EPERM;
4309 *bad_wr = wr;
4310 goto out;
4311 }
f6b1ee34 4312 /* fall through */
d16e91da 4313 case MLX5_IB_QPT_HW_GSI:
e126ba97 4314 set_datagram_seg(seg, wr);
f241e749 4315 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 4316 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4317 if (unlikely((seg == qend)))
4318 seg = mlx5_get_send_wqe(qp, 0);
4319 break;
f0313965
ES		 4320 case IB_QPT_UD:
4321 set_datagram_seg(seg, wr);
4322 seg += sizeof(struct mlx5_wqe_datagram_seg);
4323 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4324
4325 if (unlikely((seg == qend)))
4326 seg = mlx5_get_send_wqe(qp, 0);
4327
4328 /* handle qp that supports ud offload */
4329 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4330 struct mlx5_wqe_eth_pad *pad;
e126ba97 4331
f0313965
ES		 4332 pad = seg;
4333 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4334 seg += sizeof(struct mlx5_wqe_eth_pad);
4335 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4336
4337 seg = set_eth_seg(seg, wr, qend, qp, &size);
4338
4339 if (unlikely((seg == qend)))
4340 seg = mlx5_get_send_wqe(qp, 0);
4341 }
4342 break;
e126ba97
EC		 4343 case MLX5_IB_QPT_REG_UMR:
4344 if (wr->opcode != MLX5_IB_WR_UMR) {
4345 err = -EINVAL;
4346 mlx5_ib_warn(dev, "bad opcode\n");
4347 goto out;
4348 }
4349 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4350 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
578e7264 4351 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
e126ba97
EC		 4352 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4353 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4354 if (unlikely((seg == qend)))
4355 seg = mlx5_get_send_wqe(qp, 0);
4356 set_reg_mkey_segment(seg, wr);
4357 seg += sizeof(struct mlx5_mkey_seg);
4358 size += sizeof(struct mlx5_mkey_seg) / 16;
4359 if (unlikely((seg == qend)))
4360 seg = mlx5_get_send_wqe(qp, 0);
4361 break;
4362
4363 default:
4364 break;
4365 }
4366
4367 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4368 int uninitialized_var(sz);
4369
4370 err = set_data_inl_seg(qp, wr, seg, &sz);
4371 if (unlikely(err)) {
4372 mlx5_ib_warn(dev, "\n");
4373 *bad_wr = wr;
4374 goto out;
4375 }
e126ba97
EC		 4376 size += sz;
4377 } else {
4378 dpseg = seg;
4379 for (i = 0; i < num_sge; i++) {
4380 if (unlikely(dpseg == qend)) {
4381 seg = mlx5_get_send_wqe(qp, 0);
4382 dpseg = seg;
4383 }
4384 if (likely(wr->sg_list[i].length)) {
4385 set_data_ptr_seg(dpseg, wr->sg_list + i);
4386 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4387 dpseg++;
4388 }
4389 }
4390 }
4391
6e8484c5
MG		 4392 qp->next_fence = next_fence;
4393 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
6e5eadac 4394 mlx5_ib_opcode[wr->opcode]);
e6631814 4395skip_psv:
e126ba97
EC		 4396 if (0)
4397 dump_wqe(qp, idx, size);
4398 }
4399
4400out:
4401 if (likely(nreq)) {
4402 qp->sq.head += nreq;
4403
4404 /* Make sure that descriptors are written before
4405 * updating doorbell record and ringing the doorbell
4406 */
4407 wmb();
4408
4409 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4410
ada388f7
EC		 4411 /* Make sure doorbell record is visible to the HCA before
4412 * we hit doorbell */
4413 wmb();
4414
5fe9dec0
EC		 4415 /* currently we support only regular doorbells */
4416 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4417 /* Make sure doorbells don't leak out of SQ spinlock
4418 * and reach the HCA out of order.
4419 */
4420 mmiowb();
e126ba97 4421 bf->offset ^= bf->buf_size;
e126ba97
EC		 4422 }
4423
4424 spin_unlock_irqrestore(&qp->sq.lock, flags);
4425
4426 return err;
4427}
4428
4429static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4430{
4431 sig->signature = calc_sig(sig, size);
4432}
4433
4434int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4435 struct ib_recv_wr **bad_wr)
4436{
4437 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4438 struct mlx5_wqe_data_seg *scat;
4439 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4440 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4441 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4442 unsigned long flags;
4443 int err = 0;
4444 int nreq;
4445 int ind;
4446 int i;
4447
d16e91da
HE		 4448 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4449 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4450
e126ba97
EC		 4451 spin_lock_irqsave(&qp->rq.lock, flags);
4452
89ea94a7
MG		 4453 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4454 err = -EIO;
4455 *bad_wr = wr;
4456 nreq = 0;
4457 goto out;
4458 }
4459
e126ba97
EC		 4460 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4461
4462 for (nreq = 0; wr; nreq++, wr = wr->next) {
4463 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4464 err = -ENOMEM;
4465 *bad_wr = wr;
4466 goto out;
4467 }
4468
4469 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4470 err = -EINVAL;
4471 *bad_wr = wr;
4472 goto out;
4473 }
4474
4475 scat = get_recv_wqe(qp, ind);
4476 if (qp->wq_sig)
4477 scat++;
4478
4479 for (i = 0; i < wr->num_sge; i++)
4480 set_data_ptr_seg(scat + i, wr->sg_list + i);
4481
4482 if (i < qp->rq.max_gs) {
4483 scat[i].byte_count = 0;
4484 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4485 scat[i].addr = 0;
4486 }
4487
4488 if (qp->wq_sig) {
4489 sig = (struct mlx5_rwqe_sig *)scat;
4490 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4491 }
4492
4493 qp->rq.wrid[ind] = wr->wr_id;
4494
4495 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4496 }
4497
4498out:
4499 if (likely(nreq)) {
4500 qp->rq.head += nreq;
4501
4502 /* Make sure that descriptors are written before
4503 * doorbell record.
4504 */
4505 wmb();
4506
4507 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4508 }
4509
4510 spin_unlock_irqrestore(&qp->rq.lock, flags);
4511
4512 return err;
4513}
4514
4515static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4516{
4517 switch (mlx5_state) {
4518 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4519 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4520 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4521 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4522 case MLX5_QP_STATE_SQ_DRAINING:
4523 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4524 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4525 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4526 default: return -1;
4527 }
4528}
4529
4530static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4531{
4532 switch (mlx5_mig_state) {
4533 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4534 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4535 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4536 default: return -1;
4537 }
4538}
4539
4540static int to_ib_qp_access_flags(int mlx5_flags)
4541{
4542 int ib_flags = 0;
4543
4544 if (mlx5_flags & MLX5_QP_BIT_RRE)
4545 ib_flags |= IB_ACCESS_REMOTE_READ;
4546 if (mlx5_flags & MLX5_QP_BIT_RWE)
4547 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4548 if (mlx5_flags & MLX5_QP_BIT_RAE)
4549 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4550
4551 return ib_flags;
4552}
4553
38349389 4554static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
d8966fcd 4555 struct rdma_ah_attr *ah_attr,
38349389 4556 struct mlx5_qp_path *path)
e126ba97 4557{
9603b61d 4558 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97 4559
d8966fcd 4560 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 4561
44c58487 4562 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
d8966fcd
DC		 4563 rdma_ah_set_port_num(ah_attr, path->port);
4564 if (rdma_ah_get_port_num(ah_attr) == 0 ||
4565 rdma_ah_get_port_num(ah_attr) > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 4566 return;
4567
d8966fcd
DC		 4568 rdma_ah_set_port_num(ah_attr, path->port);
4569 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4570
4571 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4572 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4573 rdma_ah_set_static_rate(ah_attr,
4574 path->static_rate ? path->static_rate - 5 : 0);
4575 if (path->grh_mlid & (1 << 7)) {
4576 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4577
4578 rdma_ah_set_grh(ah_attr, NULL,
4579 tc_fl & 0xfffff,
4580 path->mgid_index,
4581 path->hop_limit,
4582 (tc_fl >> 20) & 0xff);
4583 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
e126ba97
EC		 4584 }
4585}
4586
6d2f89df 4587static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4588 struct mlx5_ib_sq *sq,
4589 u8 *sq_state)
4590{
4591 void *out;
4592 void *sqc;
4593 int inlen;
4594 int err;
4595
4596 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
1b9a07ee 4597 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4598 if (!out)
4599 return -ENOMEM;
4600
4601 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4602 if (err)
4603 goto out;
4604
4605 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4606 *sq_state = MLX5_GET(sqc, sqc, state);
4607 sq->state = *sq_state;
4608
4609out:
4610 kvfree(out);
4611 return err;
4612}
4613
4614static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4615 struct mlx5_ib_rq *rq,
4616 u8 *rq_state)
4617{
4618 void *out;
4619 void *rqc;
4620 int inlen;
4621 int err;
4622
4623 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 4624 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4625 if (!out)
4626 return -ENOMEM;
4627
4628 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4629 if (err)
4630 goto out;
4631
4632 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4633 *rq_state = MLX5_GET(rqc, rqc, state);
4634 rq->state = *rq_state;
4635
4636out:
4637 kvfree(out);
4638 return err;
4639}
4640
4641static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4642 struct mlx5_ib_qp *qp, u8 *qp_state)
4643{
4644 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4645 [MLX5_RQC_STATE_RST] = {
4646 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4647 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4648 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4649 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4650 },
4651 [MLX5_RQC_STATE_RDY] = {
4652 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4653 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4654 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4655 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4656 },
4657 [MLX5_RQC_STATE_ERR] = {
4658 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4659 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4660 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4661 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4662 },
4663 [MLX5_RQ_STATE_NA] = {
4664 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4665 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4666 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4667 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4668 },
4669 };
4670
4671 *qp_state = sqrq_trans[rq_state][sq_state];
4672
4673 if (*qp_state == MLX5_QP_STATE_BAD) {
4674 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4675 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4676 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4677 return -EINVAL;
4678 }
4679
4680 if (*qp_state == MLX5_QP_STATE)
4681 *qp_state = qp->state;
4682
4683 return 0;
4684}
4685
4686static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4687 struct mlx5_ib_qp *qp,
4688 u8 *raw_packet_qp_state)
4689{
4690 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4691 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4692 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4693 int err;
4694 u8 sq_state = MLX5_SQ_STATE_NA;
4695 u8 rq_state = MLX5_RQ_STATE_NA;
4696
4697 if (qp->sq.wqe_cnt) {
4698 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4699 if (err)
4700 return err;
4701 }
4702
4703 if (qp->rq.wqe_cnt) {
4704 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4705 if (err)
4706 return err;
4707 }
4708
4709 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4710 raw_packet_qp_state);
4711}
4712
4713static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4714 struct ib_qp_attr *qp_attr)
e126ba97 4715{
09a7d9ec 4716 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 4717 struct mlx5_qp_context *context;
4718 int mlx5_state;
09a7d9ec 4719 u32 *outb;
e126ba97
EC		 4720 int err = 0;
4721
09a7d9ec 4722 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4723 if (!outb)
4724 return -ENOMEM;
4725
19098df2 4726 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 4727 outlen);
e126ba97 4728 if (err)
6d2f89df 4729 goto out;
e126ba97 4730
09a7d9ec
SM		 4731 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4732 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4733
e126ba97
EC		 4734 mlx5_state = be32_to_cpu(context->flags) >> 28;
4735
4736 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4737 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4738 qp_attr->path_mig_state =
4739 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4740 qp_attr->qkey = be32_to_cpu(context->qkey);
4741 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4742 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4743 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4744 qp_attr->qp_access_flags =
4745 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4746
4747 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
38349389
DC		 4748 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4749 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4750 qp_attr->alt_pkey_index =
4751 be16_to_cpu(context->alt_path.pkey_index);
d8966fcd
DC		 4752 qp_attr->alt_port_num =
4753 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
e126ba97
EC		 4754 }
4755
d3ae2bde 4756 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4757 qp_attr->port_num = context->pri_path.port;
4758
4759 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4760 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4761
4762 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4763
4764 qp_attr->max_dest_rd_atomic =
4765 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4766 qp_attr->min_rnr_timer =
4767 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4768 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4769 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4770 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4771 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4772
4773out:
4774 kfree(outb);
4775 return err;
4776}
4777
4778int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4779 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4780{
4781 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4782 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4783 int err = 0;
4784 u8 raw_packet_qp_state;
4785
28d61370
YH		 4786 if (ibqp->rwq_ind_tbl)
4787 return -ENOSYS;
4788
d16e91da
HE		 4789 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4790 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4791 qp_init_attr);
4792
c2e53b2c
YH		 4793 /* Not all of output fields are applicable, make sure to zero them */
4794 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4795 memset(qp_attr, 0, sizeof(*qp_attr));
4796
6d2f89df 4797 mutex_lock(&qp->mutex);
4798
c2e53b2c
YH		 4799 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4800 qp->flags & MLX5_IB_QP_UNDERLAY) {
6d2f89df 4801 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4802 if (err)
4803 goto out;
4804 qp->state = raw_packet_qp_state;
4805 qp_attr->port_num = 1;
4806 } else {
4807 err = query_qp_attr(dev, qp, qp_attr);
4808 if (err)
4809 goto out;
4810 }
4811
4812 qp_attr->qp_state = qp->state;
e126ba97
EC		 4813 qp_attr->cur_qp_state = qp_attr->qp_state;
4814 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4815 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4816
4817 if (!ibqp->uobject) {
0540d814 4818 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4819 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4820 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4821 } else {
4822 qp_attr->cap.max_send_wr = 0;
4823 qp_attr->cap.max_send_sge = 0;
4824 }
4825
0540d814
NO		 4826 qp_init_attr->qp_type = ibqp->qp_type;
4827 qp_init_attr->recv_cq = ibqp->recv_cq;
4828 qp_init_attr->send_cq = ibqp->send_cq;
4829 qp_init_attr->srq = ibqp->srq;
4830 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4831
4832 qp_init_attr->cap = qp_attr->cap;
4833
4834 qp_init_attr->create_flags = 0;
4835 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4836 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4837
051f2630
LR		 4838 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4839 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4840 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4841 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4842 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4843 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4844 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4845 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4846
e126ba97
EC		 4847 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4848 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4849
e126ba97
EC		 4850out:
4851 mutex_unlock(&qp->mutex);
4852 return err;
4853}
4854
4855struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4856 struct ib_ucontext *context,
4857 struct ib_udata *udata)
4858{
4859 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4860 struct mlx5_ib_xrcd *xrcd;
4861 int err;
4862
938fe83c 4863 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4864 return ERR_PTR(-ENOSYS);
4865
4866 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4867 if (!xrcd)
4868 return ERR_PTR(-ENOMEM);
4869
9603b61d 4870 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4871 if (err) {
4872 kfree(xrcd);
4873 return ERR_PTR(-ENOMEM);
4874 }
4875
4876 return &xrcd->ibxrcd;
4877}
4878
4879int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4880{
4881 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4882 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4883 int err;
4884
9603b61d 4885 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4886 if (err) {
4887 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4888 return err;
4889 }
4890
4891 kfree(xrcd);
4892
4893 return 0;
4894}
79b20a6c 4895
350d0e4c
YH		 4896static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4897{
4898 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4899 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4900 struct ib_event event;
4901
4902 if (rwq->ibwq.event_handler) {
4903 event.device = rwq->ibwq.device;
4904 event.element.wq = &rwq->ibwq;
4905 switch (type) {
4906 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4907 event.event = IB_EVENT_WQ_FATAL;
4908 break;
4909 default:
4910 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4911 return;
4912 }
4913
4914 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4915 }
4916}
4917
03404e8a
MG		 4918static int set_delay_drop(struct mlx5_ib_dev *dev)
4919{
4920 int err = 0;
4921
4922 mutex_lock(&dev->delay_drop.lock);
4923 if (dev->delay_drop.activate)
4924 goto out;
4925
4926 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
4927 if (err)
4928 goto out;
4929
4930 dev->delay_drop.activate = true;
4931out:
4932 mutex_unlock(&dev->delay_drop.lock);
fe248c3a
MG		 4933
4934 if (!err)
4935 atomic_inc(&dev->delay_drop.rqs_cnt);
03404e8a
MG		 4936 return err;
4937}
4938
79b20a6c
YH		 4939static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4940 struct ib_wq_init_attr *init_attr)
4941{
4942 struct mlx5_ib_dev *dev;
4be6da1e 4943 int has_net_offloads;
79b20a6c
YH		 4944 __be64 *rq_pas0;
4945 void *in;
4946 void *rqc;
4947 void *wq;
4948 int inlen;
4949 int err;
4950
4951 dev = to_mdev(pd->device);
4952
4953 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 4954 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 4955 if (!in)
4956 return -ENOMEM;
4957
4958 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4959 MLX5_SET(rqc, rqc, mem_rq_type,
4960 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4961 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4962 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4963 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4964 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4965 wq = MLX5_ADDR_OF(rqc, rqc, wq);
ccc87087
NO		 4966 MLX5_SET(wq, wq, wq_type,
4967 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4968 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 4969 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
4970 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
4971 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
4972 err = -EOPNOTSUPP;
4973 goto out;
4974 } else {
4975 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4976 }
4977 }
79b20a6c 4978 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
ccc87087
NO		 4979 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
4980 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4981 MLX5_SET(wq, wq, log_wqe_stride_size,
4982 rwq->single_stride_log_num_of_bytes -
4983 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
4984 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
4985 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
4986 }
79b20a6c
YH		 4987 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4988 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4989 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4990 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4991 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4992 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 4993 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 4994 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 4995 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 4996 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4997 err = -EOPNOTSUPP;
4998 goto out;
4999 }
5000 } else {
5001 MLX5_SET(rqc, rqc, vsd, 1);
5002 }
4be6da1e
NO		 5003 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5004 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5005 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5006 err = -EOPNOTSUPP;
5007 goto out;
5008 }
5009 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5010 }
03404e8a
MG		 5011 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5012 if (!(dev->ib_dev.attrs.raw_packet_caps &
5013 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5014 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5015 err = -EOPNOTSUPP;
5016 goto out;
5017 }
5018 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5019 }
79b20a6c
YH		 5020 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5021 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 5022 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
03404e8a
MG		 5023 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5024 err = set_delay_drop(dev);
5025 if (err) {
5026 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5027 err);
5028 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5029 } else {
5030 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5031 }
5032 }
b1f74a84 5033out:
79b20a6c
YH		 5034 kvfree(in);
5035 return err;
5036}
5037
5038static int set_user_rq_size(struct mlx5_ib_dev *dev,
5039 struct ib_wq_init_attr *wq_init_attr,
5040 struct mlx5_ib_create_wq *ucmd,
5041 struct mlx5_ib_rwq *rwq)
5042{
5043 /* Sanity check RQ size before proceeding */
5044 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5045 return -EINVAL;
5046
5047 if (!ucmd->rq_wqe_count)
5048 return -EINVAL;
5049
5050 rwq->wqe_count = ucmd->rq_wqe_count;
5051 rwq->wqe_shift = ucmd->rq_wqe_shift;
5052 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
5053 rwq->log_rq_stride = rwq->wqe_shift;
5054 rwq->log_rq_size = ilog2(rwq->wqe_count);
5055 return 0;
5056}
5057
5058static int prepare_user_rq(struct ib_pd *pd,
5059 struct ib_wq_init_attr *init_attr,
5060 struct ib_udata *udata,
5061 struct mlx5_ib_rwq *rwq)
5062{
5063 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5064 struct mlx5_ib_create_wq ucmd = {};
5065 int err;
5066 size_t required_cmd_sz;
5067
ccc87087
NO		 5068 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5069 + sizeof(ucmd.single_stride_log_num_of_bytes);
79b20a6c
YH		 5070 if (udata->inlen < required_cmd_sz) {
5071 mlx5_ib_dbg(dev, "invalid inlen\n");
5072 return -EINVAL;
5073 }
5074
5075 if (udata->inlen > sizeof(ucmd) &&
5076 !ib_is_udata_cleared(udata, sizeof(ucmd),
5077 udata->inlen - sizeof(ucmd))) {
5078 mlx5_ib_dbg(dev, "inlen is not supported\n");
5079 return -EOPNOTSUPP;
5080 }
5081
5082 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5083 mlx5_ib_dbg(dev, "copy failed\n");
5084 return -EFAULT;
5085 }
5086
ccc87087 5087 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
79b20a6c
YH		 5088 mlx5_ib_dbg(dev, "invalid comp mask\n");
5089 return -EOPNOTSUPP;
ccc87087
NO		 5090 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5091 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5092 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5093 return -EOPNOTSUPP;
5094 }
5095 if ((ucmd.single_stride_log_num_of_bytes <
5096 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5097 (ucmd.single_stride_log_num_of_bytes >
5098 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5099 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5100 ucmd.single_stride_log_num_of_bytes,
5101 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5102 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5103 return -EINVAL;
5104 }
5105 if ((ucmd.single_wqe_log_num_of_strides >
5106 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5107 (ucmd.single_wqe_log_num_of_strides <
5108 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5109 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5110 ucmd.single_wqe_log_num_of_strides,
5111 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5112 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5113 return -EINVAL;
5114 }
5115 rwq->single_stride_log_num_of_bytes =
5116 ucmd.single_stride_log_num_of_bytes;
5117 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5118 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5119 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
79b20a6c
YH		 5120 }
5121
5122 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5123 if (err) {
5124 mlx5_ib_dbg(dev, "err %d\n", err);
5125 return err;
5126 }
5127
5128 err = create_user_rq(dev, pd, rwq, &ucmd);
5129 if (err) {
5130 mlx5_ib_dbg(dev, "err %d\n", err);
5131 if (err)
5132 return err;
5133 }
5134
5135 rwq->user_index = ucmd.user_index;
5136 return 0;
5137}
5138
5139struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5140 struct ib_wq_init_attr *init_attr,
5141 struct ib_udata *udata)
5142{
5143 struct mlx5_ib_dev *dev;
5144 struct mlx5_ib_rwq *rwq;
5145 struct mlx5_ib_create_wq_resp resp = {};
5146 size_t min_resp_len;
5147 int err;
5148
5149 if (!udata)
5150 return ERR_PTR(-ENOSYS);
5151
5152 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5153 if (udata->outlen && udata->outlen < min_resp_len)
5154 return ERR_PTR(-EINVAL);
5155
5156 dev = to_mdev(pd->device);
5157 switch (init_attr->wq_type) {
5158 case IB_WQT_RQ:
5159 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5160 if (!rwq)
5161 return ERR_PTR(-ENOMEM);
5162 err = prepare_user_rq(pd, init_attr, udata, rwq);
5163 if (err)
5164 goto err;
5165 err = create_rq(rwq, pd, init_attr);
5166 if (err)
5167 goto err_user_rq;
5168 break;
5169 default:
5170 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5171 init_attr->wq_type);
5172 return ERR_PTR(-EINVAL);
5173 }
5174
350d0e4c 5175 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 5176 rwq->ibwq.state = IB_WQS_RESET;
5177 if (udata->outlen) {
5178 resp.response_length = offsetof(typeof(resp), response_length) +
5179 sizeof(resp.response_length);
5180 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5181 if (err)
5182 goto err_copy;
5183 }
5184
350d0e4c
YH		 5185 rwq->core_qp.event = mlx5_ib_wq_event;
5186 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 5187 return &rwq->ibwq;
5188
5189err_copy:
350d0e4c 5190 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c 5191err_user_rq:
fe248c3a 5192 destroy_user_rq(dev, pd, rwq);
79b20a6c
YH		 5193err:
5194 kfree(rwq);
5195 return ERR_PTR(err);
5196}
5197
5198int mlx5_ib_destroy_wq(struct ib_wq *wq)
5199{
5200 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5201 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5202
350d0e4c 5203 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
fe248c3a 5204 destroy_user_rq(dev, wq->pd, rwq);
79b20a6c
YH		 5205 kfree(rwq);
5206
5207 return 0;
5208}
5209
c5f90929
YH		 5210struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5211 struct ib_rwq_ind_table_init_attr *init_attr,
5212 struct ib_udata *udata)
5213{
5214 struct mlx5_ib_dev *dev = to_mdev(device);
5215 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5216 int sz = 1 << init_attr->log_ind_tbl_size;
5217 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5218 size_t min_resp_len;
5219 int inlen;
5220 int err;
5221 int i;
5222 u32 *in;
5223 void *rqtc;
5224
5225 if (udata->inlen > 0 &&
5226 !ib_is_udata_cleared(udata, 0,
5227 udata->inlen))
5228 return ERR_PTR(-EOPNOTSUPP);
5229
efd7f400
MG		 5230 if (init_attr->log_ind_tbl_size >
5231 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5232 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5233 init_attr->log_ind_tbl_size,
5234 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5235 return ERR_PTR(-EINVAL);
5236 }
5237
c5f90929
YH		 5238 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5239 if (udata->outlen && udata->outlen < min_resp_len)
5240 return ERR_PTR(-EINVAL);
5241
5242 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5243 if (!rwq_ind_tbl)
5244 return ERR_PTR(-ENOMEM);
5245
5246 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 5247 in = kvzalloc(inlen, GFP_KERNEL);
c5f90929
YH		 5248 if (!in) {
5249 err = -ENOMEM;
5250 goto err;
5251 }
5252
5253 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5254
5255 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5256 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5257
5258 for (i = 0; i < sz; i++)
5259 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5260
5261 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5262 kvfree(in);
5263
5264 if (err)
5265 goto err;
5266
5267 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5268 if (udata->outlen) {
5269 resp.response_length = offsetof(typeof(resp), response_length) +
5270 sizeof(resp.response_length);
5271 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5272 if (err)
5273 goto err_copy;
5274 }
5275
5276 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5277
5278err_copy:
5279 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5280err:
5281 kfree(rwq_ind_tbl);
5282 return ERR_PTR(err);
5283}
5284
5285int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5286{
5287 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5288 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5289
5290 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5291
5292 kfree(rwq_ind_tbl);
5293 return 0;
5294}
5295
79b20a6c
YH		 5296int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5297 u32 wq_attr_mask, struct ib_udata *udata)
5298{
5299 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5300 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5301 struct mlx5_ib_modify_wq ucmd = {};
5302 size_t required_cmd_sz;
5303 int curr_wq_state;
5304 int wq_state;
5305 int inlen;
5306 int err;
5307 void *rqc;
5308 void *in;
5309
5310 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5311 if (udata->inlen < required_cmd_sz)
5312 return -EINVAL;
5313
5314 if (udata->inlen > sizeof(ucmd) &&
5315 !ib_is_udata_cleared(udata, sizeof(ucmd),
5316 udata->inlen - sizeof(ucmd)))
5317 return -EOPNOTSUPP;
5318
5319 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5320 return -EFAULT;
5321
5322 if (ucmd.comp_mask || ucmd.reserved)
5323 return -EOPNOTSUPP;
5324
5325 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 5326 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5327 if (!in)
5328 return -ENOMEM;
5329
5330 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5331
5332 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5333 wq_attr->curr_wq_state : wq->state;
5334 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5335 wq_attr->wq_state : curr_wq_state;
5336 if (curr_wq_state == IB_WQS_ERR)
5337 curr_wq_state = MLX5_RQC_STATE_ERR;
5338 if (wq_state == IB_WQS_ERR)
5339 wq_state = MLX5_RQC_STATE_ERR;
5340 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5341 MLX5_SET(rqc, rqc, state, wq_state);
5342
b1f74a84
NO		 5343 if (wq_attr_mask & IB_WQ_FLAGS) {
5344 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5345 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5346 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5347 mlx5_ib_dbg(dev, "VLAN offloads are not "
5348 "supported\n");
5349 err = -EOPNOTSUPP;
5350 goto out;
5351 }
5352 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5353 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5354 MLX5_SET(rqc, rqc, vsd,
5355 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5356 }
b1383aa6
NO		 5357
5358 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5359 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5360 err = -EOPNOTSUPP;
5361 goto out;
5362 }
b1f74a84
NO		 5363 }
5364
23a6964e
MD		 5365 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5366 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5367 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5368 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
e1f24a79
PP		 5369 MLX5_SET(rqc, rqc, counter_set_id,
5370 dev->port->cnts.set_id);
23a6964e
MD		 5371 } else
5372 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5373 dev->ib_dev.name);
5374 }
5375
350d0e4c 5376 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 5377 if (!err)
5378 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5379
b1f74a84
NO		 5380out:
5381 kvfree(in);
79b20a6c
YH		 5382 return err;
5383}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git