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net/mlx5: E-Switch, Reload IB interface when switching devlink modes
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
c2e53b2c 37#include <linux/mlx5/fs.h>
e126ba97 38#include "mlx5_ib.h"
b96c9dde 39#include "ib_rep.h"
e126ba97
EC		 40
41/* not supported currently */
42static int wq_signature;
43
44enum {
45 MLX5_IB_ACK_REQ_FREQ = 8,
46};
47
48enum {
49 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
51 MLX5_IB_LINK_TYPE_IB = 0,
52 MLX5_IB_LINK_TYPE_ETH = 1
53};
54
55enum {
56 MLX5_IB_SQ_STRIDE = 6,
e126ba97
EC		 57};
58
59static const u32 mlx5_ib_opcode[] = {
60 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 61 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
74};
75
f0313965
ES		 76struct mlx5_wqe_eth_pad {
77 u8 rsvd0[16];
78};
e126ba97 79
eb49ab0c
AV		 80enum raw_qp_set_mask_map {
81 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 82 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 83};
84
0680efa2
AV		 85struct mlx5_modify_raw_qp_param {
86 u16 operation;
eb49ab0c
AV		 87
88 u32 set_mask; /* raw_qp_set_mask_map */
7d29f349 89 u32 rate_limit;
eb49ab0c 90 u8 rq_q_ctr_id;
0680efa2
AV		 91};
92
89ea94a7
MG		 93static void get_cqs(enum ib_qp_type qp_type,
94 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
95 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
96
e126ba97
EC		 97static int is_qp0(enum ib_qp_type qp_type)
98{
99 return qp_type == IB_QPT_SMI;
100}
101
e126ba97
EC		 102static int is_sqp(enum ib_qp_type qp_type)
103{
104 return is_qp0(qp_type) || is_qp1(qp_type);
105}
106
107static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
108{
109 return mlx5_buf_offset(&qp->buf, offset);
110}
111
112static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
113{
114 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
115}
116
117void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
118{
119 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
120}
121
c1395a2a
HE		 122/**
123 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
124 *
125 * @qp: QP to copy from.
126 * @send: copy from the send queue when non-zero, use the receive queue
127 * otherwise.
128 * @wqe_index: index to start copying from. For send work queues, the
129 * wqe_index is in units of MLX5_SEND_WQE_BB.
130 * For receive work queue, it is the number of work queue
131 * element in the queue.
132 * @buffer: destination buffer.
133 * @length: maximum number of bytes to copy.
134 *
135 * Copies at least a single WQE, but may copy more data.
136 *
137 * Return: the number of bytes copied, or an error code.
138 */
139int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 140 void *buffer, u32 length,
141 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 142{
143 struct ib_device *ibdev = qp->ibqp.device;
144 struct mlx5_ib_dev *dev = to_mdev(ibdev);
145 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
146 size_t offset;
147 size_t wq_end;
19098df2 148 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 149 u32 first_copy_length;
150 int wqe_length;
151 int ret;
152
153 if (wq->wqe_cnt == 0) {
154 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
155 qp->ibqp.qp_type);
156 return -EINVAL;
157 }
158
159 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
160 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
161
162 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
163 return -EINVAL;
164
165 if (offset > umem->length ||
166 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
167 return -EINVAL;
168
169 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
170 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
171 if (ret)
172 return ret;
173
174 if (send) {
175 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
176 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
177
178 wqe_length = ds * MLX5_WQE_DS_UNITS;
179 } else {
180 wqe_length = 1 << wq->wqe_shift;
181 }
182
183 if (wqe_length <= first_copy_length)
184 return first_copy_length;
185
186 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
187 wqe_length - first_copy_length);
188 if (ret)
189 return ret;
190
191 return wqe_length;
192}
193
e126ba97
EC		 194static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
195{
196 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
197 struct ib_event event;
198
19098df2 199 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
200 /* This event is only valid for trans_qps */
201 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
202 }
e126ba97
EC		 203
204 if (ibqp->event_handler) {
205 event.device = ibqp->device;
206 event.element.qp = ibqp;
207 switch (type) {
208 case MLX5_EVENT_TYPE_PATH_MIG:
209 event.event = IB_EVENT_PATH_MIG;
210 break;
211 case MLX5_EVENT_TYPE_COMM_EST:
212 event.event = IB_EVENT_COMM_EST;
213 break;
214 case MLX5_EVENT_TYPE_SQ_DRAINED:
215 event.event = IB_EVENT_SQ_DRAINED;
216 break;
217 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
218 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
219 break;
220 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
221 event.event = IB_EVENT_QP_FATAL;
222 break;
223 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
224 event.event = IB_EVENT_PATH_MIG_ERR;
225 break;
226 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
227 event.event = IB_EVENT_QP_REQ_ERR;
228 break;
229 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
230 event.event = IB_EVENT_QP_ACCESS_ERR;
231 break;
232 default:
233 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
234 return;
235 }
236
237 ibqp->event_handler(&event, ibqp->qp_context);
238 }
239}
240
241static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
242 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
243{
244 int wqe_size;
245 int wq_size;
246
247 /* Sanity check RQ size before proceeding */
938fe83c 248 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 249 return -EINVAL;
250
251 if (!has_rq) {
252 qp->rq.max_gs = 0;
253 qp->rq.wqe_cnt = 0;
254 qp->rq.wqe_shift = 0;
0540d814
NO		 255 cap->max_recv_wr = 0;
256 cap->max_recv_sge = 0;
e126ba97
EC		 257 } else {
258 if (ucmd) {
259 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
260 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
261 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
262 qp->rq.max_post = qp->rq.wqe_cnt;
263 } else {
264 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
265 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
266 wqe_size = roundup_pow_of_two(wqe_size);
267 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
268 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
269 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 270 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 271 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
272 wqe_size,
938fe83c
SM		 273 MLX5_CAP_GEN(dev->mdev,
274 max_wqe_sz_rq));
e126ba97
EC		 275 return -EINVAL;
276 }
277 qp->rq.wqe_shift = ilog2(wqe_size);
278 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
279 qp->rq.max_post = qp->rq.wqe_cnt;
280 }
281 }
282
283 return 0;
284}
285
f0313965 286static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 287{
618af384 288 int size = 0;
e126ba97 289
f0313965 290 switch (attr->qp_type) {
e126ba97 291 case IB_QPT_XRC_INI:
b125a54b 292 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 293 /* fall through */
294 case IB_QPT_RC:
295 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 296 max(sizeof(struct mlx5_wqe_atomic_seg) +
297 sizeof(struct mlx5_wqe_raddr_seg),
298 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
299 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 300 break;
301
b125a54b
EC		 302 case IB_QPT_XRC_TGT:
303 return 0;
304
e126ba97 305 case IB_QPT_UC:
b125a54b 306 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 307 max(sizeof(struct mlx5_wqe_raddr_seg),
308 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
309 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 310 break;
311
312 case IB_QPT_UD:
f0313965
ES		 313 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
314 size += sizeof(struct mlx5_wqe_eth_pad) +
315 sizeof(struct mlx5_wqe_eth_seg);
316 /* fall through */
e126ba97 317 case IB_QPT_SMI:
d16e91da 318 case MLX5_IB_QPT_HW_GSI:
b125a54b 319 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 320 sizeof(struct mlx5_wqe_datagram_seg);
321 break;
322
323 case MLX5_IB_QPT_REG_UMR:
b125a54b 324 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 325 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
326 sizeof(struct mlx5_mkey_seg);
327 break;
328
329 default:
330 return -EINVAL;
331 }
332
333 return size;
334}
335
336static int calc_send_wqe(struct ib_qp_init_attr *attr)
337{
338 int inl_size = 0;
339 int size;
340
f0313965 341 size = sq_overhead(attr);
e126ba97
EC		 342 if (size < 0)
343 return size;
344
345 if (attr->cap.max_inline_data) {
346 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
347 attr->cap.max_inline_data;
348 }
349
350 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 351 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
352 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
353 return MLX5_SIG_WQE_SIZE;
354 else
355 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 356}
357
288c01b7
EC		 358static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
359{
360 int max_sge;
361
362 if (attr->qp_type == IB_QPT_RC)
363 max_sge = (min_t(int, wqe_size, 512) -
364 sizeof(struct mlx5_wqe_ctrl_seg) -
365 sizeof(struct mlx5_wqe_raddr_seg)) /
366 sizeof(struct mlx5_wqe_data_seg);
367 else if (attr->qp_type == IB_QPT_XRC_INI)
368 max_sge = (min_t(int, wqe_size, 512) -
369 sizeof(struct mlx5_wqe_ctrl_seg) -
370 sizeof(struct mlx5_wqe_xrc_seg) -
371 sizeof(struct mlx5_wqe_raddr_seg)) /
372 sizeof(struct mlx5_wqe_data_seg);
373 else
374 max_sge = (wqe_size - sq_overhead(attr)) /
375 sizeof(struct mlx5_wqe_data_seg);
376
377 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
378 sizeof(struct mlx5_wqe_data_seg));
379}
380
e126ba97
EC		 381static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
382 struct mlx5_ib_qp *qp)
383{
384 int wqe_size;
385 int wq_size;
386
387 if (!attr->cap.max_send_wr)
388 return 0;
389
390 wqe_size = calc_send_wqe(attr);
391 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
392 if (wqe_size < 0)
393 return wqe_size;
394
938fe83c 395 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 396 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 397 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 398 return -EINVAL;
399 }
400
f0313965
ES		 401 qp->max_inline_data = wqe_size - sq_overhead(attr) -
402 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 403 attr->cap.max_inline_data = qp->max_inline_data;
404
e1e66cc2
SG		 405 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
406 qp->signature_en = true;
407
e126ba97
EC		 408 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
409 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 410 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 411 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
412 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 413 qp->sq.wqe_cnt,
414 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 415 return -ENOMEM;
416 }
e126ba97 417 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 418 qp->sq.max_gs = get_send_sge(attr, wqe_size);
419 if (qp->sq.max_gs < attr->cap.max_send_sge)
420 return -ENOMEM;
421
422 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 423 qp->sq.max_post = wq_size / wqe_size;
424 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 425
426 return wq_size;
427}
428
429static int set_user_buf_size(struct mlx5_ib_dev *dev,
430 struct mlx5_ib_qp *qp,
19098df2 431 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 432 struct mlx5_ib_qp_base *base,
433 struct ib_qp_init_attr *attr)
e126ba97
EC		 434{
435 int desc_sz = 1 << qp->sq.wqe_shift;
436
938fe83c 437 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 438 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 439 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 440 return -EINVAL;
441 }
442
443 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
444 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
445 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
446 return -EINVAL;
447 }
448
449 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
450
938fe83c 451 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 452 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 453 qp->sq.wqe_cnt,
454 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 455 return -EINVAL;
456 }
457
c2e53b2c
YH		 458 if (attr->qp_type == IB_QPT_RAW_PACKET ||
459 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 460 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
461 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
462 } else {
463 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
464 (qp->sq.wqe_cnt << 6);
465 }
e126ba97
EC		 466
467 return 0;
468}
469
470static int qp_has_rq(struct ib_qp_init_attr *attr)
471{
472 if (attr->qp_type == IB_QPT_XRC_INI ||
473 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
474 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
475 !attr->cap.max_recv_wr)
476 return 0;
477
478 return 1;
479}
480
2f5ff264 481static int first_med_bfreg(void)
c1be5232
EC		 482{
483 return 1;
484}
485
0b80c14f
EC		 486enum {
487 /* this is the first blue flame register in the array of bfregs assigned
488 * to a processes. Since we do not use it for blue flame but rather
489 * regular 64 bit doorbells, we do not need a lock for maintaiing
490 * "odd/even" order
491 */
492 NUM_NON_BLUE_FLAME_BFREGS = 1,
493};
494
b037c29a
EC		 495static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
496{
31a78a5a 497 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a
EC		 498}
499
500static int num_med_bfreg(struct mlx5_ib_dev *dev,
501 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 502{
503 int n;
504
b037c29a
EC		 505 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
506 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 507
508 return n >= 0 ? n : 0;
509}
510
b037c29a
EC		 511static int first_hi_bfreg(struct mlx5_ib_dev *dev,
512 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 513{
514 int med;
c1be5232 515
b037c29a
EC		 516 med = num_med_bfreg(dev, bfregi);
517 return ++med;
c1be5232
EC		 518}
519
b037c29a
EC		 520static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
521 struct mlx5_bfreg_info *bfregi)
e126ba97 522{
e126ba97
EC		 523 int i;
524
b037c29a
EC		 525 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
526 if (!bfregi->count[i]) {
2f5ff264 527 bfregi->count[i]++;
e126ba97
EC		 528 return i;
529 }
530 }
531
532 return -ENOMEM;
533}
534
b037c29a
EC		 535static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
536 struct mlx5_bfreg_info *bfregi)
e126ba97 537{
2f5ff264 538 int minidx = first_med_bfreg();
e126ba97
EC		 539 int i;
540
b037c29a 541 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 542 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 543 minidx = i;
0b80c14f
EC		 544 if (!bfregi->count[minidx])
545 break;
e126ba97
EC		 546 }
547
2f5ff264 548 bfregi->count[minidx]++;
e126ba97
EC		 549 return minidx;
550}
551
b037c29a
EC		 552static int alloc_bfreg(struct mlx5_ib_dev *dev,
553 struct mlx5_bfreg_info *bfregi,
2f5ff264 554 enum mlx5_ib_latency_class lat)
e126ba97 555{
2f5ff264 556 int bfregn = -EINVAL;
e126ba97 557
2f5ff264 558 mutex_lock(&bfregi->lock);
e126ba97
EC		 559 switch (lat) {
560 case MLX5_IB_LATENCY_CLASS_LOW:
0b80c14f 561 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 562 bfregn = 0;
563 bfregi->count[bfregn]++;
e126ba97
EC		 564 break;
565
566 case MLX5_IB_LATENCY_CLASS_MEDIUM:
2f5ff264
EC		 567 if (bfregi->ver < 2)
568 bfregn = -ENOMEM;
78c0f98c 569 else
b037c29a 570 bfregn = alloc_med_class_bfreg(dev, bfregi);
e126ba97
EC		 571 break;
572
573 case MLX5_IB_LATENCY_CLASS_HIGH:
2f5ff264
EC		 574 if (bfregi->ver < 2)
575 bfregn = -ENOMEM;
78c0f98c 576 else
b037c29a 577 bfregn = alloc_high_class_bfreg(dev, bfregi);
e126ba97
EC		 578 break;
579 }
2f5ff264 580 mutex_unlock(&bfregi->lock);
e126ba97 581
2f5ff264 582 return bfregn;
e126ba97
EC		 583}
584
4ed131d0 585void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 586{
2f5ff264 587 mutex_lock(&bfregi->lock);
b037c29a 588 bfregi->count[bfregn]--;
2f5ff264 589 mutex_unlock(&bfregi->lock);
e126ba97
EC		 590}
591
592static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
593{
594 switch (state) {
595 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
596 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
597 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
598 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
599 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
600 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
601 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
602 default: return -1;
603 }
604}
605
606static int to_mlx5_st(enum ib_qp_type type)
607{
608 switch (type) {
609 case IB_QPT_RC: return MLX5_QP_ST_RC;
610 case IB_QPT_UC: return MLX5_QP_ST_UC;
611 case IB_QPT_UD: return MLX5_QP_ST_UD;
612 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
613 case IB_QPT_XRC_INI:
614 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
615 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 616 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
c32a4f29 617 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
e126ba97 618 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 619 case IB_QPT_RAW_PACKET:
0fb2ed66 620 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 621 case IB_QPT_MAX:
622 default: return -EINVAL;
623 }
624}
625
89ea94a7
MG		 626static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
627 struct mlx5_ib_cq *recv_cq);
628static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
629 struct mlx5_ib_cq *recv_cq);
630
b037c29a 631static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1ee47ab3
YH		 632 struct mlx5_bfreg_info *bfregi, int bfregn,
633 bool dyn_bfreg)
e126ba97 634{
b037c29a
EC		 635 int bfregs_per_sys_page;
636 int index_of_sys_page;
637 int offset;
638
639 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
640 MLX5_NON_FP_BFREGS_PER_UAR;
641 index_of_sys_page = bfregn / bfregs_per_sys_page;
642
1ee47ab3
YH		 643 if (dyn_bfreg) {
644 index_of_sys_page += bfregi->num_static_sys_pages;
645 if (bfregn > bfregi->num_dyn_bfregs ||
646 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
647 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
648 return -EINVAL;
649 }
650 }
b037c29a 651
1ee47ab3 652 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a 653 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 654}
655
19098df2 656static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
657 struct ib_pd *pd,
658 unsigned long addr, size_t size,
659 struct ib_umem **umem,
660 int *npages, int *page_shift, int *ncont,
661 u32 *offset)
662{
663 int err;
664
665 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
666 if (IS_ERR(*umem)) {
667 mlx5_ib_dbg(dev, "umem_get failed\n");
668 return PTR_ERR(*umem);
669 }
670
762f899a 671 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 672
673 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
674 if (err) {
675 mlx5_ib_warn(dev, "bad offset\n");
676 goto err_umem;
677 }
678
679 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
680 addr, size, *npages, *page_shift, *ncont, *offset);
681
682 return 0;
683
684err_umem:
685 ib_umem_release(*umem);
686 *umem = NULL;
687
688 return err;
689}
690
fe248c3a
MG		 691static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
692 struct mlx5_ib_rwq *rwq)
79b20a6c
YH		 693{
694 struct mlx5_ib_ucontext *context;
695
fe248c3a
MG		 696 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
697 atomic_dec(&dev->delay_drop.rqs_cnt);
698
79b20a6c
YH		 699 context = to_mucontext(pd->uobject->context);
700 mlx5_ib_db_unmap_user(context, &rwq->db);
701 if (rwq->umem)
702 ib_umem_release(rwq->umem);
703}
704
705static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
706 struct mlx5_ib_rwq *rwq,
707 struct mlx5_ib_create_wq *ucmd)
708{
709 struct mlx5_ib_ucontext *context;
710 int page_shift = 0;
711 int npages;
712 u32 offset = 0;
713 int ncont = 0;
714 int err;
715
716 if (!ucmd->buf_addr)
717 return -EINVAL;
718
719 context = to_mucontext(pd->uobject->context);
720 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
721 rwq->buf_size, 0, 0);
722 if (IS_ERR(rwq->umem)) {
723 mlx5_ib_dbg(dev, "umem_get failed\n");
724 err = PTR_ERR(rwq->umem);
725 return err;
726 }
727
762f899a 728 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 729 &ncont, NULL);
730 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
731 &rwq->rq_page_offset);
732 if (err) {
733 mlx5_ib_warn(dev, "bad offset\n");
734 goto err_umem;
735 }
736
737 rwq->rq_num_pas = ncont;
738 rwq->page_shift = page_shift;
739 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
740 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
741
742 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
743 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
744 npages, page_shift, ncont, offset);
745
746 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
747 if (err) {
748 mlx5_ib_dbg(dev, "map failed\n");
749 goto err_umem;
750 }
751
752 rwq->create_type = MLX5_WQ_USER;
753 return 0;
754
755err_umem:
756 ib_umem_release(rwq->umem);
757 return err;
758}
759
b037c29a
EC		 760static int adjust_bfregn(struct mlx5_ib_dev *dev,
761 struct mlx5_bfreg_info *bfregi, int bfregn)
762{
763 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
764 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
765}
766
e126ba97
EC		 767static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
768 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 769 struct ib_qp_init_attr *attr,
09a7d9ec 770 u32 **in,
19098df2 771 struct mlx5_ib_create_qp_resp *resp, int *inlen,
772 struct mlx5_ib_qp_base *base)
e126ba97
EC		 773{
774 struct mlx5_ib_ucontext *context;
775 struct mlx5_ib_create_qp ucmd;
19098df2 776 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 777 int page_shift = 0;
1ee47ab3 778 int uar_index = 0;
e126ba97 779 int npages;
9e9c47d0 780 u32 offset = 0;
2f5ff264 781 int bfregn;
9e9c47d0 782 int ncont = 0;
09a7d9ec
SM		 783 __be64 *pas;
784 void *qpc;
e126ba97
EC		 785 int err;
786
787 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
788 if (err) {
789 mlx5_ib_dbg(dev, "copy failed\n");
790 return err;
791 }
792
793 context = to_mucontext(pd->uobject->context);
1ee47ab3
YH		 794 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
795 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
796 ucmd.bfreg_index, true);
797 if (uar_index < 0)
798 return uar_index;
799
800 bfregn = MLX5_IB_INVALID_BFREG;
801 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
802 /*
803 * TBD: should come from the verbs when we have the API
804 */
051f2630 805 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 806 bfregn = MLX5_CROSS_CHANNEL_BFREG;
1ee47ab3 807 }
051f2630 808 else {
b037c29a 809 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
2f5ff264
EC		 810 if (bfregn < 0) {
811 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
051f2630 812 mlx5_ib_dbg(dev, "reverting to medium latency\n");
b037c29a 813 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
2f5ff264
EC		 814 if (bfregn < 0) {
815 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
051f2630 816 mlx5_ib_dbg(dev, "reverting to high latency\n");
b037c29a 817 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
2f5ff264
EC		 818 if (bfregn < 0) {
819 mlx5_ib_warn(dev, "bfreg allocation failed\n");
820 return bfregn;
051f2630 821 }
c1be5232 822 }
e126ba97
EC		 823 }
824 }
825
2f5ff264 826 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
1ee47ab3
YH		 827 if (bfregn != MLX5_IB_INVALID_BFREG)
828 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
829 false);
e126ba97 830
48fea837
HE		 831 qp->rq.offset = 0;
832 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
833 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
834
0fb2ed66 835 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 836 if (err)
2f5ff264 837 goto err_bfreg;
e126ba97 838
19098df2 839 if (ucmd.buf_addr && ubuffer->buf_size) {
840 ubuffer->buf_addr = ucmd.buf_addr;
841 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
842 ubuffer->buf_size,
843 &ubuffer->umem, &npages, &page_shift,
844 &ncont, &offset);
845 if (err)
2f5ff264 846 goto err_bfreg;
9e9c47d0 847 } else {
19098df2 848 ubuffer->umem = NULL;
e126ba97 849 }
e126ba97 850
09a7d9ec
SM		 851 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
852 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 853 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 854 if (!*in) {
855 err = -ENOMEM;
856 goto err_umem;
857 }
09a7d9ec
SM		 858
859 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 860 if (ubuffer->umem)
09a7d9ec
SM		 861 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
862
863 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
864
865 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
866 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 867
09a7d9ec 868 MLX5_SET(qpc, qpc, uar_page, uar_index);
1ee47ab3
YH		 869 if (bfregn != MLX5_IB_INVALID_BFREG)
870 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
871 else
872 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
2f5ff264 873 qp->bfregn = bfregn;
e126ba97
EC		 874
875 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
876 if (err) {
877 mlx5_ib_dbg(dev, "map failed\n");
878 goto err_free;
879 }
880
881 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
882 if (err) {
883 mlx5_ib_dbg(dev, "copy failed\n");
884 goto err_unmap;
885 }
886 qp->create_type = MLX5_QP_USER;
887
888 return 0;
889
890err_unmap:
891 mlx5_ib_db_unmap_user(context, &qp->db);
892
893err_free:
479163f4 894 kvfree(*in);
e126ba97
EC		 895
896err_umem:
19098df2 897 if (ubuffer->umem)
898 ib_umem_release(ubuffer->umem);
e126ba97 899
2f5ff264 900err_bfreg:
1ee47ab3
YH		 901 if (bfregn != MLX5_IB_INVALID_BFREG)
902 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 903 return err;
904}
905
b037c29a
EC		 906static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
907 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 908{
909 struct mlx5_ib_ucontext *context;
910
911 context = to_mucontext(pd->uobject->context);
912 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 913 if (base->ubuffer.umem)
914 ib_umem_release(base->ubuffer.umem);
1ee47ab3
YH		 915
916 /*
917 * Free only the BFREGs which are handled by the kernel.
918 * BFREGs of UARs allocated dynamically are handled by user.
919 */
920 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
921 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 922}
923
924static int create_kernel_qp(struct mlx5_ib_dev *dev,
925 struct ib_qp_init_attr *init_attr,
926 struct mlx5_ib_qp *qp,
09a7d9ec 927 u32 **in, int *inlen,
19098df2 928 struct mlx5_ib_qp_base *base)
e126ba97 929{
e126ba97 930 int uar_index;
09a7d9ec 931 void *qpc;
e126ba97
EC		 932 int err;
933
f0313965
ES		 934 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
935 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c 936 IB_QP_CREATE_IPOIB_UD_LSO |
93d576af 937 IB_QP_CREATE_NETIF_QP |
b11a4f9c 938 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 939 return -EINVAL;
e126ba97
EC		 940
941 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 942 qp->bf.bfreg = &dev->fp_bfreg;
943 else
944 qp->bf.bfreg = &dev->bfreg;
e126ba97 945
d8030b0d
EC		 946 /* We need to divide by two since each register is comprised of
947 * two buffers of identical size, namely odd and even
948 */
949 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 950 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 951
952 err = calc_sq_size(dev, init_attr, qp);
953 if (err < 0) {
954 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 955 return err;
e126ba97
EC		 956 }
957
958 qp->rq.offset = 0;
959 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 960 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 961
19098df2 962 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 963 if (err) {
964 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 965 return err;
e126ba97
EC		 966 }
967
968 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 969 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
970 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 971 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 972 if (!*in) {
973 err = -ENOMEM;
974 goto err_buf;
975 }
09a7d9ec
SM		 976
977 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
978 MLX5_SET(qpc, qpc, uar_page, uar_index);
979 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
980
e126ba97 981 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 982 MLX5_SET(qpc, qpc, fre, 1);
983 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 984
b11a4f9c 985 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 986 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 987 qp->flags |= MLX5_IB_QP_SQPN_QP1;
988 }
989
09a7d9ec
SM		 990 mlx5_fill_page_array(&qp->buf,
991 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 992
9603b61d 993 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 994 if (err) {
995 mlx5_ib_dbg(dev, "err %d\n", err);
996 goto err_free;
997 }
998
b5883008
LD		 999 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1000 sizeof(*qp->sq.wrid), GFP_KERNEL);
1001 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1002 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1003 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1004 sizeof(*qp->rq.wrid), GFP_KERNEL);
1005 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1006 sizeof(*qp->sq.w_list), GFP_KERNEL);
1007 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1008 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
e126ba97
EC		 1009
1010 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1011 !qp->sq.w_list || !qp->sq.wqe_head) {
1012 err = -ENOMEM;
1013 goto err_wrid;
1014 }
1015 qp->create_type = MLX5_QP_KERNEL;
1016
1017 return 0;
1018
1019err_wrid:
b5883008
LD		 1020 kvfree(qp->sq.wqe_head);
1021 kvfree(qp->sq.w_list);
1022 kvfree(qp->sq.wrid);
1023 kvfree(qp->sq.wr_data);
1024 kvfree(qp->rq.wrid);
f4044dac 1025 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 1026
1027err_free:
479163f4 1028 kvfree(*in);
e126ba97
EC		 1029
1030err_buf:
9603b61d 1031 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1032 return err;
1033}
1034
1035static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1036{
b5883008
LD		 1037 kvfree(qp->sq.wqe_head);
1038 kvfree(qp->sq.w_list);
1039 kvfree(qp->sq.wrid);
1040 kvfree(qp->sq.wr_data);
1041 kvfree(qp->rq.wrid);
f4044dac 1042 mlx5_db_free(dev->mdev, &qp->db);
9603b61d 1043 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1044}
1045
09a7d9ec 1046static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1047{
1048 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
c32a4f29 1049 (attr->qp_type == MLX5_IB_QPT_DCI) ||
e126ba97 1050 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1051 return MLX5_SRQ_RQ;
e126ba97 1052 else if (!qp->has_rq)
09a7d9ec 1053 return MLX5_ZERO_LEN_RQ;
e126ba97 1054 else
09a7d9ec 1055 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1056}
1057
1058static int is_connected(enum ib_qp_type qp_type)
1059{
1060 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1061 return 1;
1062
1063 return 0;
1064}
1065
0fb2ed66 1066static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
c2e53b2c 1067 struct mlx5_ib_qp *qp,
0fb2ed66 1068 struct mlx5_ib_sq *sq, u32 tdn)
1069{
c4f287c4 1070 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1071 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1072
0fb2ed66 1073 MLX5_SET(tisc, tisc, transport_domain, tdn);
c2e53b2c
YH		 1074 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1075 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1076
0fb2ed66 1077 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1078}
1079
1080static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1081 struct mlx5_ib_sq *sq)
1082{
1083 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1084}
1085
b96c9dde
MB		 1086static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1087 struct mlx5_ib_sq *sq)
1088{
1089 if (sq->flow_rule)
1090 mlx5_del_flow_rules(sq->flow_rule);
1091}
1092
0fb2ed66 1093static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1094 struct mlx5_ib_sq *sq, void *qpin,
1095 struct ib_pd *pd)
1096{
1097 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1098 __be64 *pas;
1099 void *in;
1100 void *sqc;
1101 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1102 void *wq;
1103 int inlen;
1104 int err;
1105 int page_shift = 0;
1106 int npages;
1107 int ncont = 0;
1108 u32 offset = 0;
1109
1110 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1111 &sq->ubuffer.umem, &npages, &page_shift,
1112 &ncont, &offset);
1113 if (err)
1114 return err;
1115
1116 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1b9a07ee 1117 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1118 if (!in) {
1119 err = -ENOMEM;
1120 goto err_umem;
1121 }
1122
1123 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1124 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
795b609c
BW		 1125 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1126 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
0fb2ed66 1127 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1128 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1129 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1130 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1131 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
96dc3fc5
NO		 1132 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1133 MLX5_CAP_ETH(dev->mdev, swp))
1134 MLX5_SET(sqc, sqc, allow_swp, 1);
0fb2ed66 1135
1136 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1137 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1138 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1139 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1140 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1141 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1142 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1143 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1144 MLX5_SET(wq, wq, page_offset, offset);
1145
1146 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1147 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1148
1149 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1150
1151 kvfree(in);
1152
1153 if (err)
1154 goto err_umem;
1155
b96c9dde
MB		 1156 err = create_flow_rule_vport_sq(dev, sq);
1157 if (err)
1158 goto err_flow;
1159
0fb2ed66 1160 return 0;
1161
b96c9dde
MB		 1162err_flow:
1163 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1164
0fb2ed66 1165err_umem:
1166 ib_umem_release(sq->ubuffer.umem);
1167 sq->ubuffer.umem = NULL;
1168
1169 return err;
1170}
1171
1172static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1173 struct mlx5_ib_sq *sq)
1174{
b96c9dde 1175 destroy_flow_rule_vport_sq(dev, sq);
0fb2ed66 1176 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1177 ib_umem_release(sq->ubuffer.umem);
1178}
1179
1180static int get_rq_pas_size(void *qpc)
1181{
1182 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1183 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1184 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1185 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1186 u32 po_quanta = 1 << (log_page_size - 6);
1187 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1188 u32 page_size = 1 << log_page_size;
1189 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1190 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1191
1192 return rq_num_pas * sizeof(u64);
1193}
1194
1195static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1196 struct mlx5_ib_rq *rq, void *qpin)
1197{
358e42ea 1198 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1199 __be64 *pas;
1200 __be64 *qp_pas;
1201 void *in;
1202 void *rqc;
1203 void *wq;
1204 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1205 int inlen;
1206 int err;
1207 u32 rq_pas_size = get_rq_pas_size(qpc);
1208
1209 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1210 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1211 if (!in)
1212 return -ENOMEM;
1213
1214 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1215 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1216 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1217 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1218 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1219 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1220 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1221 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1222
358e42ea
MD		 1223 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1224 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1225
0fb2ed66 1226 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1227 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 1228 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1229 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
0fb2ed66 1230 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1231 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1232 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1233 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1234 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1235 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1236
1237 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1238 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1239 memcpy(pas, qp_pas, rq_pas_size);
1240
1241 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1242
1243 kvfree(in);
1244
1245 return err;
1246}
1247
1248static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1249 struct mlx5_ib_rq *rq)
1250{
1251 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1252}
1253
f95ef6cb
MG		 1254static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1255{
1256 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1257 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1258 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1259}
1260
0fb2ed66 1261static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
f95ef6cb
MG		 1262 struct mlx5_ib_rq *rq, u32 tdn,
1263 bool tunnel_offload_en)
0fb2ed66 1264{
1265 u32 *in;
1266 void *tirc;
1267 int inlen;
1268 int err;
1269
1270 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1271 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1272 if (!in)
1273 return -ENOMEM;
1274
1275 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1276 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1277 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1278 MLX5_SET(tirc, tirc, transport_domain, tdn);
f95ef6cb
MG		 1279 if (tunnel_offload_en)
1280 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
0fb2ed66 1281
1282 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1283
1284 kvfree(in);
1285
1286 return err;
1287}
1288
1289static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1290 struct mlx5_ib_rq *rq)
1291{
1292 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1293}
1294
1295static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
09a7d9ec 1296 u32 *in,
0fb2ed66 1297 struct ib_pd *pd)
1298{
1299 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1300 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1301 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1302 struct ib_uobject *uobj = pd->uobject;
1303 struct ib_ucontext *ucontext = uobj->context;
1304 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1305 int err;
1306 u32 tdn = mucontext->tdn;
1307
1308 if (qp->sq.wqe_cnt) {
c2e53b2c 1309 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
0fb2ed66 1310 if (err)
1311 return err;
1312
1313 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1314 if (err)
1315 goto err_destroy_tis;
1316
1317 sq->base.container_mibqp = qp;
1d31e9c0 1318 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1319 }
1320
1321 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1322 rq->base.container_mibqp = qp;
1323
e4cc4fa7
NO		 1324 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1325 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
b1383aa6
NO		 1326 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1327 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
0fb2ed66 1328 err = create_raw_packet_qp_rq(dev, rq, in);
1329 if (err)
1330 goto err_destroy_sq;
1331
0fb2ed66 1332
f95ef6cb
MG		 1333 err = create_raw_packet_qp_tir(dev, rq, tdn,
1334 qp->tunnel_offload_en);
0fb2ed66 1335 if (err)
1336 goto err_destroy_rq;
1337 }
1338
1339 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1340 rq->base.mqp.qpn;
1341
1342 return 0;
1343
1344err_destroy_rq:
1345 destroy_raw_packet_qp_rq(dev, rq);
1346err_destroy_sq:
1347 if (!qp->sq.wqe_cnt)
1348 return err;
1349 destroy_raw_packet_qp_sq(dev, sq);
1350err_destroy_tis:
1351 destroy_raw_packet_qp_tis(dev, sq);
1352
1353 return err;
1354}
1355
1356static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1357 struct mlx5_ib_qp *qp)
1358{
1359 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1360 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1361 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1362
1363 if (qp->rq.wqe_cnt) {
1364 destroy_raw_packet_qp_tir(dev, rq);
1365 destroy_raw_packet_qp_rq(dev, rq);
1366 }
1367
1368 if (qp->sq.wqe_cnt) {
1369 destroy_raw_packet_qp_sq(dev, sq);
1370 destroy_raw_packet_qp_tis(dev, sq);
1371 }
1372}
1373
1374static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1375 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1376{
1377 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1378 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1379
1380 sq->sq = &qp->sq;
1381 rq->rq = &qp->rq;
1382 sq->doorbell = &qp->db;
1383 rq->doorbell = &qp->db;
1384}
1385
28d61370
YH		 1386static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1387{
1388 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1389}
1390
1391static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1392 struct ib_pd *pd,
1393 struct ib_qp_init_attr *init_attr,
1394 struct ib_udata *udata)
1395{
1396 struct ib_uobject *uobj = pd->uobject;
1397 struct ib_ucontext *ucontext = uobj->context;
1398 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1399 struct mlx5_ib_create_qp_resp resp = {};
1400 int inlen;
1401 int err;
1402 u32 *in;
1403 void *tirc;
1404 void *hfso;
1405 u32 selected_fields = 0;
1406 size_t min_resp_len;
1407 u32 tdn = mucontext->tdn;
1408 struct mlx5_ib_create_qp_rss ucmd = {};
1409 size_t required_cmd_sz;
1410
1411 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1412 return -EOPNOTSUPP;
1413
1414 if (init_attr->create_flags || init_attr->send_cq)
1415 return -EINVAL;
1416
2f5ff264 1417 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1418 if (udata->outlen < min_resp_len)
1419 return -EINVAL;
1420
f95ef6cb 1421 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
28d61370
YH		 1422 if (udata->inlen < required_cmd_sz) {
1423 mlx5_ib_dbg(dev, "invalid inlen\n");
1424 return -EINVAL;
1425 }
1426
1427 if (udata->inlen > sizeof(ucmd) &&
1428 !ib_is_udata_cleared(udata, sizeof(ucmd),
1429 udata->inlen - sizeof(ucmd))) {
1430 mlx5_ib_dbg(dev, "inlen is not supported\n");
1431 return -EOPNOTSUPP;
1432 }
1433
1434 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1435 mlx5_ib_dbg(dev, "copy failed\n");
1436 return -EFAULT;
1437 }
1438
1439 if (ucmd.comp_mask) {
1440 mlx5_ib_dbg(dev, "invalid comp mask\n");
1441 return -EOPNOTSUPP;
1442 }
1443
f95ef6cb
MG		 1444 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1445 mlx5_ib_dbg(dev, "invalid flags\n");
1446 return -EOPNOTSUPP;
1447 }
1448
1449 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1450 !tunnel_offload_supported(dev->mdev)) {
1451 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
28d61370
YH		 1452 return -EOPNOTSUPP;
1453 }
1454
309fa347
MG		 1455 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1456 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1457 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1458 return -EOPNOTSUPP;
1459 }
1460
28d61370
YH		 1461 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1462 if (err) {
1463 mlx5_ib_dbg(dev, "copy failed\n");
1464 return -EINVAL;
1465 }
1466
1467 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1468 in = kvzalloc(inlen, GFP_KERNEL);
28d61370
YH		 1469 if (!in)
1470 return -ENOMEM;
1471
1472 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1473 MLX5_SET(tirc, tirc, disp_type,
1474 MLX5_TIRC_DISP_TYPE_INDIRECT);
1475 MLX5_SET(tirc, tirc, indirect_table,
1476 init_attr->rwq_ind_tbl->ind_tbl_num);
1477 MLX5_SET(tirc, tirc, transport_domain, tdn);
1478
1479 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
f95ef6cb
MG		 1480
1481 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1482 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1483
309fa347
MG		 1484 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1485 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1486 else
1487 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1488
28d61370
YH		 1489 switch (ucmd.rx_hash_function) {
1490 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1491 {
1492 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1493 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1494
1495 if (len != ucmd.rx_key_len) {
1496 err = -EINVAL;
1497 goto err;
1498 }
1499
1500 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1501 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1502 memcpy(rss_key, ucmd.rx_hash_key, len);
1503 break;
1504 }
1505 default:
1506 err = -EOPNOTSUPP;
1507 goto err;
1508 }
1509
1510 if (!ucmd.rx_hash_fields_mask) {
1511 /* special case when this TIR serves as steering entry without hashing */
1512 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1513 goto create_tir;
1514 err = -EINVAL;
1515 goto err;
1516 }
1517
1518 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1519 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1520 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1521 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1522 err = -EINVAL;
1523 goto err;
1524 }
1525
1526 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1527 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1528 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1529 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1530 MLX5_L3_PROT_TYPE_IPV4);
1531 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1532 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1533 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1534 MLX5_L3_PROT_TYPE_IPV6);
1535
1536 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1537 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1538 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1539 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1540 err = -EINVAL;
1541 goto err;
1542 }
1543
1544 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1545 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1546 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1547 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1548 MLX5_L4_PROT_TYPE_TCP);
1549 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1550 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1551 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1552 MLX5_L4_PROT_TYPE_UDP);
1553
1554 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1555 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1556 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1557
1558 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1559 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1560 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1561
1562 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1563 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1564 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1565
1566 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1567 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1568 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1569
1570 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1571
1572create_tir:
1573 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1574
1575 if (err)
1576 goto err;
1577
1578 kvfree(in);
1579 /* qpn is reserved for that QP */
1580 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1581 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1582 return 0;
1583
1584err:
1585 kvfree(in);
1586 return err;
1587}
1588
e126ba97
EC		 1589static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1590 struct ib_qp_init_attr *init_attr,
1591 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1592{
1593 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1594 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1595 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1596 struct mlx5_ib_create_qp_resp resp;
89ea94a7
MG		 1597 struct mlx5_ib_cq *send_cq;
1598 struct mlx5_ib_cq *recv_cq;
1599 unsigned long flags;
cfb5e088 1600 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1601 struct mlx5_ib_create_qp ucmd;
1602 struct mlx5_ib_qp_base *base;
cfb5e088 1603 void *qpc;
09a7d9ec
SM		 1604 u32 *in;
1605 int err;
e126ba97
EC		 1606
1607 mutex_init(&qp->mutex);
1608 spin_lock_init(&qp->sq.lock);
1609 spin_lock_init(&qp->rq.lock);
1610
28d61370
YH		 1611 if (init_attr->rwq_ind_tbl) {
1612 if (!udata)
1613 return -ENOSYS;
1614
1615 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1616 return err;
1617 }
1618
f360d88a 1619 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1620 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1621 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1622 return -EINVAL;
1623 } else {
1624 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1625 }
1626 }
1627
051f2630
LR		 1628 if (init_attr->create_flags &
1629 (IB_QP_CREATE_CROSS_CHANNEL |
1630 IB_QP_CREATE_MANAGED_SEND |
1631 IB_QP_CREATE_MANAGED_RECV)) {
1632 if (!MLX5_CAP_GEN(mdev, cd)) {
1633 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1634 return -EINVAL;
1635 }
1636 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1637 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1638 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1639 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1640 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1641 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1642 }
f0313965
ES		 1643
1644 if (init_attr->qp_type == IB_QPT_UD &&
1645 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1646 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1647 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1648 return -EOPNOTSUPP;
1649 }
1650
358e42ea
MD		 1651 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1652 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1653 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1654 return -EOPNOTSUPP;
1655 }
1656 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1657 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1658 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1659 return -EOPNOTSUPP;
1660 }
1661 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1662 }
1663
e126ba97
EC		 1664 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1665 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1666
e4cc4fa7
NO		 1667 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1668 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1669 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1670 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1671 return -EOPNOTSUPP;
1672 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1673 }
1674
e126ba97
EC		 1675 if (pd && pd->uobject) {
1676 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1677 mlx5_ib_dbg(dev, "copy failed\n");
1678 return -EFAULT;
1679 }
1680
cfb5e088
HA		 1681 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1682 &ucmd, udata->inlen, &uidx);
1683 if (err)
1684 return err;
1685
e126ba97
EC		 1686 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1687 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
f95ef6cb
MG		 1688 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1689 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1690 !tunnel_offload_supported(mdev)) {
1691 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1692 return -EOPNOTSUPP;
1693 }
1694 qp->tunnel_offload_en = true;
1695 }
c2e53b2c
YH		 1696
1697 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1698 if (init_attr->qp_type != IB_QPT_UD ||
1699 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1700 MLX5_CAP_PORT_TYPE_IB) ||
1701 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1702 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1703 return -EOPNOTSUPP;
1704 }
1705
1706 qp->flags |= MLX5_IB_QP_UNDERLAY;
1707 qp->underlay_qpn = init_attr->source_qpn;
1708 }
e126ba97
EC		 1709 } else {
1710 qp->wq_sig = !!wq_signature;
1711 }
1712
c2e53b2c
YH		 1713 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1714 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1715 &qp->raw_packet_qp.rq.base :
1716 &qp->trans_qp.base;
1717
e126ba97
EC		 1718 qp->has_rq = qp_has_rq(init_attr);
1719 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1720 qp, (pd && pd->uobject) ? &ucmd : NULL);
1721 if (err) {
1722 mlx5_ib_dbg(dev, "err %d\n", err);
1723 return err;
1724 }
1725
1726 if (pd) {
1727 if (pd->uobject) {
938fe83c
SM		 1728 __u32 max_wqes =
1729 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1730 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1731 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1732 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1733 mlx5_ib_dbg(dev, "invalid rq params\n");
1734 return -EINVAL;
1735 }
938fe83c 1736 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1737 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1738 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1739 return -EINVAL;
1740 }
b11a4f9c
HE		 1741 if (init_attr->create_flags &
1742 mlx5_ib_create_qp_sqpn_qp1()) {
1743 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1744 return -EINVAL;
1745 }
0fb2ed66 1746 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1747 &resp, &inlen, base);
e126ba97
EC		 1748 if (err)
1749 mlx5_ib_dbg(dev, "err %d\n", err);
1750 } else {
19098df2 1751 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1752 base);
e126ba97
EC		 1753 if (err)
1754 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1755 }
1756
1757 if (err)
1758 return err;
1759 } else {
1b9a07ee 1760 in = kvzalloc(inlen, GFP_KERNEL);
e126ba97
EC		 1761 if (!in)
1762 return -ENOMEM;
1763
1764 qp->create_type = MLX5_QP_EMPTY;
1765 }
1766
1767 if (is_sqp(init_attr->qp_type))
1768 qp->port = init_attr->port_num;
1769
09a7d9ec
SM		 1770 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1771
1772 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1773 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1774
1775 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1776 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1777 else
09a7d9ec
SM		 1778 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1779
e126ba97
EC		 1780
1781 if (qp->wq_sig)
09a7d9ec 1782 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1783
f360d88a 1784 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1785 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1786
051f2630 1787 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1788 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1789 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1790 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1791 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1792 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1793
e126ba97
EC		 1794 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1795 int rcqe_sz;
1796 int scqe_sz;
1797
1798 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1799 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1800
1801 if (rcqe_sz == 128)
09a7d9ec 1802 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1803 else
09a7d9ec 1804 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1805
1806 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1807 if (scqe_sz == 128)
09a7d9ec 1808 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1809 else
09a7d9ec 1810 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1811 }
1812 }
1813
1814 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1815 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1816 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1817 }
1818
09a7d9ec 1819 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97 1820
3fd3307e 1821 if (qp->sq.wqe_cnt) {
09a7d9ec 1822 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
3fd3307e 1823 } else {
09a7d9ec 1824 MLX5_SET(qpc, qpc, no_sq, 1);
3fd3307e
AK		 1825 if (init_attr->srq &&
1826 init_attr->srq->srq_type == IB_SRQT_TM)
1827 MLX5_SET(qpc, qpc, offload_type,
1828 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1829 }
e126ba97
EC		 1830
1831 /* Set default resources */
1832 switch (init_attr->qp_type) {
1833 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1834 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1835 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1836 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1837 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1838 break;
1839 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1840 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1841 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1842 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1843 break;
1844 default:
1845 if (init_attr->srq) {
09a7d9ec
SM		 1846 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1847 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1848 } else {
09a7d9ec
SM		 1849 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1850 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1851 }
1852 }
1853
1854 if (init_attr->send_cq)
09a7d9ec 1855 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1856
1857 if (init_attr->recv_cq)
09a7d9ec 1858 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1859
09a7d9ec 1860 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1861
09a7d9ec
SM		 1862 /* 0xffffff means we ask to work with cqe version 0 */
1863 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1864 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1865
f0313965
ES		 1866 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1867 if (init_attr->qp_type == IB_QPT_UD &&
1868 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1869 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1870 qp->flags |= MLX5_IB_QP_LSO;
1871 }
cfb5e088 1872
b1383aa6
NO		 1873 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1874 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1875 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1876 err = -EOPNOTSUPP;
1877 goto err;
1878 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1879 MLX5_SET(qpc, qpc, end_padding_mode,
1880 MLX5_WQ_END_PAD_MODE_ALIGN);
1881 } else {
1882 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1883 }
1884 }
1885
c2e53b2c
YH		 1886 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1887 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 1888 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1889 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1890 err = create_raw_packet_qp(dev, qp, in, pd);
1891 } else {
1892 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1893 }
1894
e126ba97
EC		 1895 if (err) {
1896 mlx5_ib_dbg(dev, "create qp failed\n");
1897 goto err_create;
1898 }
1899
479163f4 1900 kvfree(in);
e126ba97 1901
19098df2 1902 base->container_mibqp = qp;
1903 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1904
89ea94a7
MG		 1905 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1906 &send_cq, &recv_cq);
1907 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1908 mlx5_ib_lock_cqs(send_cq, recv_cq);
1909 /* Maintain device to QPs access, needed for further handling via reset
1910 * flow
1911 */
1912 list_add_tail(&qp->qps_list, &dev->qp_list);
1913 /* Maintain CQ to QPs access, needed for further handling via reset flow
1914 */
1915 if (send_cq)
1916 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1917 if (recv_cq)
1918 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1919 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1920 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1921
e126ba97
EC		 1922 return 0;
1923
1924err_create:
1925 if (qp->create_type == MLX5_QP_USER)
b037c29a 1926 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 1927 else if (qp->create_type == MLX5_QP_KERNEL)
1928 destroy_qp_kernel(dev, qp);
1929
b1383aa6 1930err:
479163f4 1931 kvfree(in);
e126ba97
EC		 1932 return err;
1933}
1934
1935static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1936 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1937{
1938 if (send_cq) {
1939 if (recv_cq) {
1940 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1941 spin_lock(&send_cq->lock);
e126ba97
EC		 1942 spin_lock_nested(&recv_cq->lock,
1943 SINGLE_DEPTH_NESTING);
1944 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1945 spin_lock(&send_cq->lock);
e126ba97
EC		 1946 __acquire(&recv_cq->lock);
1947 } else {
89ea94a7 1948 spin_lock(&recv_cq->lock);
e126ba97
EC		 1949 spin_lock_nested(&send_cq->lock,
1950 SINGLE_DEPTH_NESTING);
1951 }
1952 } else {
89ea94a7 1953 spin_lock(&send_cq->lock);
6a4f139a 1954 __acquire(&recv_cq->lock);
e126ba97
EC		 1955 }
1956 } else if (recv_cq) {
89ea94a7 1957 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1958 __acquire(&send_cq->lock);
1959 } else {
1960 __acquire(&send_cq->lock);
1961 __acquire(&recv_cq->lock);
e126ba97
EC		 1962 }
1963}
1964
1965static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1966 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1967{
1968 if (send_cq) {
1969 if (recv_cq) {
1970 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1971 spin_unlock(&recv_cq->lock);
89ea94a7 1972 spin_unlock(&send_cq->lock);
e126ba97
EC		 1973 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1974 __release(&recv_cq->lock);
89ea94a7 1975 spin_unlock(&send_cq->lock);
e126ba97
EC		 1976 } else {
1977 spin_unlock(&send_cq->lock);
89ea94a7 1978 spin_unlock(&recv_cq->lock);
e126ba97
EC		 1979 }
1980 } else {
6a4f139a 1981 __release(&recv_cq->lock);
89ea94a7 1982 spin_unlock(&send_cq->lock);
e126ba97
EC		 1983 }
1984 } else if (recv_cq) {
6a4f139a 1985 __release(&send_cq->lock);
89ea94a7 1986 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 1987 } else {
1988 __release(&recv_cq->lock);
1989 __release(&send_cq->lock);
e126ba97
EC		 1990 }
1991}
1992
1993static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1994{
1995 return to_mpd(qp->ibqp.pd);
1996}
1997
89ea94a7
MG		 1998static void get_cqs(enum ib_qp_type qp_type,
1999 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 2000 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2001{
89ea94a7 2002 switch (qp_type) {
e126ba97
EC		 2003 case IB_QPT_XRC_TGT:
2004 *send_cq = NULL;
2005 *recv_cq = NULL;
2006 break;
2007 case MLX5_IB_QPT_REG_UMR:
2008 case IB_QPT_XRC_INI:
89ea94a7 2009 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 2010 *recv_cq = NULL;
2011 break;
2012
2013 case IB_QPT_SMI:
d16e91da 2014 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2015 case IB_QPT_RC:
2016 case IB_QPT_UC:
2017 case IB_QPT_UD:
2018 case IB_QPT_RAW_IPV6:
2019 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 2020 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 2021 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2022 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 2023 break;
2024
e126ba97
EC		 2025 case IB_QPT_MAX:
2026 default:
2027 *send_cq = NULL;
2028 *recv_cq = NULL;
2029 break;
2030 }
2031}
2032
ad5f8e96 2033static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2034 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2035 u8 lag_tx_affinity);
ad5f8e96 2036
e126ba97
EC		 2037static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2038{
2039 struct mlx5_ib_cq *send_cq, *recv_cq;
c2e53b2c 2040 struct mlx5_ib_qp_base *base;
89ea94a7 2041 unsigned long flags;
e126ba97
EC		 2042 int err;
2043
28d61370
YH		 2044 if (qp->ibqp.rwq_ind_tbl) {
2045 destroy_rss_raw_qp_tir(dev, qp);
2046 return;
2047 }
2048
c2e53b2c
YH		 2049 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2050 qp->flags & MLX5_IB_QP_UNDERLAY) ?
0fb2ed66 2051 &qp->raw_packet_qp.rq.base :
2052 &qp->trans_qp.base;
2053
6aec21f6 2054 if (qp->state != IB_QPS_RESET) {
c2e53b2c
YH		 2055 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2056 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
ad5f8e96 2057 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 2058 MLX5_CMD_OP_2RST_QP, 0,
2059 NULL, &base->mqp);
ad5f8e96 2060 } else {
0680efa2
AV		 2061 struct mlx5_modify_raw_qp_param raw_qp_param = {
2062 .operation = MLX5_CMD_OP_2RST_QP
2063 };
2064
13eab21f 2065 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 2066 }
2067 if (err)
427c1e7b 2068 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 2069 base->mqp.qpn);
6aec21f6 2070 }
e126ba97 2071
89ea94a7
MG		 2072 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2073 &send_cq, &recv_cq);
2074
2075 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2076 mlx5_ib_lock_cqs(send_cq, recv_cq);
2077 /* del from lists under both locks above to protect reset flow paths */
2078 list_del(&qp->qps_list);
2079 if (send_cq)
2080 list_del(&qp->cq_send_list);
2081
2082 if (recv_cq)
2083 list_del(&qp->cq_recv_list);
e126ba97
EC		 2084
2085 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 2086 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2087 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2088 if (send_cq != recv_cq)
19098df2 2089 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2090 NULL);
e126ba97 2091 }
89ea94a7
MG		 2092 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2093 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 2094
c2e53b2c
YH		 2095 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2096 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 2097 destroy_raw_packet_qp(dev, qp);
2098 } else {
2099 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2100 if (err)
2101 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2102 base->mqp.qpn);
2103 }
e126ba97 2104
e126ba97
EC		 2105 if (qp->create_type == MLX5_QP_KERNEL)
2106 destroy_qp_kernel(dev, qp);
2107 else if (qp->create_type == MLX5_QP_USER)
b037c29a 2108 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 2109}
2110
2111static const char *ib_qp_type_str(enum ib_qp_type type)
2112{
2113 switch (type) {
2114 case IB_QPT_SMI:
2115 return "IB_QPT_SMI";
2116 case IB_QPT_GSI:
2117 return "IB_QPT_GSI";
2118 case IB_QPT_RC:
2119 return "IB_QPT_RC";
2120 case IB_QPT_UC:
2121 return "IB_QPT_UC";
2122 case IB_QPT_UD:
2123 return "IB_QPT_UD";
2124 case IB_QPT_RAW_IPV6:
2125 return "IB_QPT_RAW_IPV6";
2126 case IB_QPT_RAW_ETHERTYPE:
2127 return "IB_QPT_RAW_ETHERTYPE";
2128 case IB_QPT_XRC_INI:
2129 return "IB_QPT_XRC_INI";
2130 case IB_QPT_XRC_TGT:
2131 return "IB_QPT_XRC_TGT";
2132 case IB_QPT_RAW_PACKET:
2133 return "IB_QPT_RAW_PACKET";
2134 case MLX5_IB_QPT_REG_UMR:
2135 return "MLX5_IB_QPT_REG_UMR";
b4aaa1f0
MS		 2136 case IB_QPT_DRIVER:
2137 return "IB_QPT_DRIVER";
e126ba97
EC		 2138 case IB_QPT_MAX:
2139 default:
2140 return "Invalid QP type";
2141 }
2142}
2143
b4aaa1f0
MS		 2144static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2145 struct ib_qp_init_attr *attr,
2146 struct mlx5_ib_create_qp *ucmd)
2147{
2148 struct mlx5_ib_dev *dev;
2149 struct mlx5_ib_qp *qp;
2150 int err = 0;
2151 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2152 void *dctc;
2153
2154 if (!attr->srq || !attr->recv_cq)
2155 return ERR_PTR(-EINVAL);
2156
2157 dev = to_mdev(pd->device);
2158
2159 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2160 ucmd, sizeof(*ucmd), &uidx);
2161 if (err)
2162 return ERR_PTR(err);
2163
2164 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2165 if (!qp)
2166 return ERR_PTR(-ENOMEM);
2167
2168 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2169 if (!qp->dct.in) {
2170 err = -ENOMEM;
2171 goto err_free;
2172 }
2173
2174 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
776a3906 2175 qp->qp_sub_type = MLX5_IB_QPT_DCT;
b4aaa1f0
MS		 2176 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2177 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2178 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2179 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2180 MLX5_SET(dctc, dctc, user_index, uidx);
2181
2182 qp->state = IB_QPS_RESET;
2183
2184 return &qp->ibqp;
2185err_free:
2186 kfree(qp);
2187 return ERR_PTR(err);
2188}
2189
2190static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2191 struct ib_qp_init_attr *init_attr,
2192 struct mlx5_ib_create_qp *ucmd,
2193 struct ib_udata *udata)
2194{
2195 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2196 int err;
2197
2198 if (!udata)
2199 return -EINVAL;
2200
2201 if (udata->inlen < sizeof(*ucmd)) {
2202 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2203 return -EINVAL;
2204 }
2205 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2206 if (err)
2207 return err;
2208
2209 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2210 init_attr->qp_type = MLX5_IB_QPT_DCI;
2211 } else {
2212 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2213 init_attr->qp_type = MLX5_IB_QPT_DCT;
2214 } else {
2215 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2216 return -EINVAL;
2217 }
2218 }
2219
2220 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2221 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2222 return -EOPNOTSUPP;
2223 }
2224
2225 return 0;
2226}
2227
e126ba97 2228struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
b4aaa1f0 2229 struct ib_qp_init_attr *verbs_init_attr,
e126ba97
EC		 2230 struct ib_udata *udata)
2231{
2232 struct mlx5_ib_dev *dev;
2233 struct mlx5_ib_qp *qp;
2234 u16 xrcdn = 0;
2235 int err;
b4aaa1f0
MS		 2236 struct ib_qp_init_attr mlx_init_attr;
2237 struct ib_qp_init_attr *init_attr = verbs_init_attr;
e126ba97
EC		 2238
2239 if (pd) {
2240 dev = to_mdev(pd->device);
0fb2ed66 2241
2242 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2243 if (!pd->uobject) {
2244 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2245 return ERR_PTR(-EINVAL);
2246 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2247 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2248 return ERR_PTR(-EINVAL);
2249 }
2250 }
09f16cf5
MD		 2251 } else {
2252 /* being cautious here */
2253 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2254 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2255 pr_warn("%s: no PD for transport %s\n", __func__,
2256 ib_qp_type_str(init_attr->qp_type));
2257 return ERR_PTR(-EINVAL);
2258 }
2259 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2260 }
2261
b4aaa1f0
MS		 2262 if (init_attr->qp_type == IB_QPT_DRIVER) {
2263 struct mlx5_ib_create_qp ucmd;
2264
2265 init_attr = &mlx_init_attr;
2266 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2267 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2268 if (err)
2269 return ERR_PTR(err);
c32a4f29
MS		 2270
2271 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2272 if (init_attr->cap.max_recv_wr ||
2273 init_attr->cap.max_recv_sge) {
2274 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2275 return ERR_PTR(-EINVAL);
2276 }
776a3906
MS		 2277 } else {
2278 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
c32a4f29 2279 }
b4aaa1f0
MS		 2280 }
2281
e126ba97
EC		 2282 switch (init_attr->qp_type) {
2283 case IB_QPT_XRC_TGT:
2284 case IB_QPT_XRC_INI:
938fe83c 2285 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2286 mlx5_ib_dbg(dev, "XRC not supported\n");
2287 return ERR_PTR(-ENOSYS);
2288 }
2289 init_attr->recv_cq = NULL;
2290 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2291 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2292 init_attr->send_cq = NULL;
2293 }
2294
2295 /* fall through */
0fb2ed66 2296 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2297 case IB_QPT_RC:
2298 case IB_QPT_UC:
2299 case IB_QPT_UD:
2300 case IB_QPT_SMI:
d16e91da 2301 case MLX5_IB_QPT_HW_GSI:
e126ba97 2302 case MLX5_IB_QPT_REG_UMR:
c32a4f29 2303 case MLX5_IB_QPT_DCI:
e126ba97
EC		 2304 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2305 if (!qp)
2306 return ERR_PTR(-ENOMEM);
2307
2308 err = create_qp_common(dev, pd, init_attr, udata, qp);
2309 if (err) {
2310 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2311 kfree(qp);
2312 return ERR_PTR(err);
2313 }
2314
2315 if (is_qp0(init_attr->qp_type))
2316 qp->ibqp.qp_num = 0;
2317 else if (is_qp1(init_attr->qp_type))
2318 qp->ibqp.qp_num = 1;
2319 else
19098df2 2320 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2321
2322 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2323 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2324 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2325 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2326
19098df2 2327 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2328
2329 break;
2330
d16e91da
HE		 2331 case IB_QPT_GSI:
2332 return mlx5_ib_gsi_create_qp(pd, init_attr);
2333
e126ba97
EC		 2334 case IB_QPT_RAW_IPV6:
2335 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2336 case IB_QPT_MAX:
2337 default:
2338 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2339 init_attr->qp_type);
2340 /* Don't support raw QPs */
2341 return ERR_PTR(-EINVAL);
2342 }
2343
b4aaa1f0
MS		 2344 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2345 qp->qp_sub_type = init_attr->qp_type;
2346
e126ba97
EC		 2347 return &qp->ibqp;
2348}
2349
776a3906
MS		 2350static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2351{
2352 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2353
2354 if (mqp->state == IB_QPS_RTR) {
2355 int err;
2356
2357 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2358 if (err) {
2359 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2360 return err;
2361 }
2362 }
2363
2364 kfree(mqp->dct.in);
2365 kfree(mqp);
2366 return 0;
2367}
2368
e126ba97
EC		 2369int mlx5_ib_destroy_qp(struct ib_qp *qp)
2370{
2371 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2372 struct mlx5_ib_qp *mqp = to_mqp(qp);
2373
d16e91da
HE		 2374 if (unlikely(qp->qp_type == IB_QPT_GSI))
2375 return mlx5_ib_gsi_destroy_qp(qp);
2376
776a3906
MS		 2377 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2378 return mlx5_ib_destroy_dct(mqp);
2379
e126ba97
EC		 2380 destroy_qp_common(dev, mqp);
2381
2382 kfree(mqp);
2383
2384 return 0;
2385}
2386
2387static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2388 int attr_mask)
2389{
2390 u32 hw_access_flags = 0;
2391 u8 dest_rd_atomic;
2392 u32 access_flags;
2393
2394 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2395 dest_rd_atomic = attr->max_dest_rd_atomic;
2396 else
19098df2 2397 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2398
2399 if (attr_mask & IB_QP_ACCESS_FLAGS)
2400 access_flags = attr->qp_access_flags;
2401 else
19098df2 2402 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2403
2404 if (!dest_rd_atomic)
2405 access_flags &= IB_ACCESS_REMOTE_WRITE;
2406
2407 if (access_flags & IB_ACCESS_REMOTE_READ)
2408 hw_access_flags |= MLX5_QP_BIT_RRE;
2409 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2410 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2411 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2412 hw_access_flags |= MLX5_QP_BIT_RWE;
2413
2414 return cpu_to_be32(hw_access_flags);
2415}
2416
2417enum {
2418 MLX5_PATH_FLAG_FL = 1 << 0,
2419 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2420 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2421};
2422
2423static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2424{
2425 if (rate == IB_RATE_PORT_CURRENT) {
2426 return 0;
2427 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2428 return -EINVAL;
2429 } else {
2430 while (rate != IB_RATE_2_5_GBPS &&
2431 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2432 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2433 --rate;
2434 }
2435
2436 return rate + MLX5_STAT_RATE_OFFSET;
2437}
2438
75850d0b 2439static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2440 struct mlx5_ib_sq *sq, u8 sl)
2441{
2442 void *in;
2443 void *tisc;
2444 int inlen;
2445 int err;
2446
2447 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2448 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 2449 if (!in)
2450 return -ENOMEM;
2451
2452 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2453
2454 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2455 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2456
2457 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2458
2459 kvfree(in);
2460
2461 return err;
2462}
2463
13eab21f
AH		 2464static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2465 struct mlx5_ib_sq *sq, u8 tx_affinity)
2466{
2467 void *in;
2468 void *tisc;
2469 int inlen;
2470 int err;
2471
2472 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2473 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 2474 if (!in)
2475 return -ENOMEM;
2476
2477 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2478
2479 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2480 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2481
2482 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2483
2484 kvfree(in);
2485
2486 return err;
2487}
2488
75850d0b 2489static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
90898850 2490 const struct rdma_ah_attr *ah,
e126ba97 2491 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2492 u32 path_flags, const struct ib_qp_attr *attr,
2493 bool alt)
e126ba97 2494{
d8966fcd 2495 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 2496 int err;
ed88451e 2497 enum ib_gid_type gid_type;
d8966fcd
DC		 2498 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2499 u8 sl = rdma_ah_get_sl(ah);
e126ba97 2500
e126ba97 2501 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2502 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2503 attr->pkey_index);
e126ba97 2504
d8966fcd
DC		 2505 if (ah_flags & IB_AH_GRH) {
2506 if (grh->sgid_index >=
938fe83c 2507 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2508 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 2509 grh->sgid_index,
938fe83c 2510 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2511 return -EINVAL;
2512 }
2811ba51 2513 }
44c58487
DC		 2514
2515 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 2516 if (!(ah_flags & IB_AH_GRH))
2811ba51 2517 return -EINVAL;
d8966fcd 2518 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
ed88451e
MD		 2519 &gid_type);
2520 if (err)
2521 return err;
44c58487 2522 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2b621851
MD		 2523 if (qp->ibqp.qp_type == IB_QPT_RC ||
2524 qp->ibqp.qp_type == IB_QPT_UC ||
2525 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2526 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2527 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2528 grh->sgid_index);
d8966fcd 2529 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
ed88451e 2530 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
d8966fcd 2531 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2811ba51 2532 } else {
d3ae2bde
NO		 2533 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2534 path->fl_free_ar |=
2535 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
d8966fcd
DC		 2536 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2537 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2538 if (ah_flags & IB_AH_GRH)
2811ba51 2539 path->grh_mlid |= 1 << 7;
d8966fcd 2540 path->dci_cfi_prio_sl = sl & 0xf;
2811ba51
AS		 2541 }
2542
d8966fcd
DC		 2543 if (ah_flags & IB_AH_GRH) {
2544 path->mgid_index = grh->sgid_index;
2545 path->hop_limit = grh->hop_limit;
e126ba97 2546 path->tclass_flowlabel =
d8966fcd
DC		 2547 cpu_to_be32((grh->traffic_class << 20) |
2548 (grh->flow_label));
2549 memcpy(path->rgid, grh->dgid.raw, 16);
e126ba97
EC		 2550 }
2551
d8966fcd 2552 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 2553 if (err < 0)
2554 return err;
2555 path->static_rate = err;
2556 path->port = port;
2557
e126ba97 2558 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2559 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2560
75850d0b 2561 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2562 return modify_raw_packet_eth_prio(dev->mdev,
2563 &qp->raw_packet_qp.sq,
d8966fcd 2564 sl & 0xf);
75850d0b 2565
e126ba97
EC		 2566 return 0;
2567}
2568
2569static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2570 [MLX5_QP_STATE_INIT] = {
2571 [MLX5_QP_STATE_INIT] = {
2572 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2573 MLX5_QP_OPTPAR_RAE |
2574 MLX5_QP_OPTPAR_RWE |
2575 MLX5_QP_OPTPAR_PKEY_INDEX |
2576 MLX5_QP_OPTPAR_PRI_PORT,
2577 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2578 MLX5_QP_OPTPAR_PKEY_INDEX |
2579 MLX5_QP_OPTPAR_PRI_PORT,
2580 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2581 MLX5_QP_OPTPAR_Q_KEY |
2582 MLX5_QP_OPTPAR_PRI_PORT,
2583 },
2584 [MLX5_QP_STATE_RTR] = {
2585 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2586 MLX5_QP_OPTPAR_RRE |
2587 MLX5_QP_OPTPAR_RAE |
2588 MLX5_QP_OPTPAR_RWE |
2589 MLX5_QP_OPTPAR_PKEY_INDEX,
2590 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2591 MLX5_QP_OPTPAR_RWE |
2592 MLX5_QP_OPTPAR_PKEY_INDEX,
2593 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2594 MLX5_QP_OPTPAR_Q_KEY,
2595 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2596 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2597 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2598 MLX5_QP_OPTPAR_RRE |
2599 MLX5_QP_OPTPAR_RAE |
2600 MLX5_QP_OPTPAR_RWE |
2601 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2602 },
2603 },
2604 [MLX5_QP_STATE_RTR] = {
2605 [MLX5_QP_STATE_RTS] = {
2606 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2607 MLX5_QP_OPTPAR_RRE |
2608 MLX5_QP_OPTPAR_RAE |
2609 MLX5_QP_OPTPAR_RWE |
2610 MLX5_QP_OPTPAR_PM_STATE |
2611 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2612 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2613 MLX5_QP_OPTPAR_RWE |
2614 MLX5_QP_OPTPAR_PM_STATE,
2615 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2616 },
2617 },
2618 [MLX5_QP_STATE_RTS] = {
2619 [MLX5_QP_STATE_RTS] = {
2620 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2621 MLX5_QP_OPTPAR_RAE |
2622 MLX5_QP_OPTPAR_RWE |
2623 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2624 MLX5_QP_OPTPAR_PM_STATE |
2625 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2626 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2627 MLX5_QP_OPTPAR_PM_STATE |
2628 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2629 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2630 MLX5_QP_OPTPAR_SRQN |
2631 MLX5_QP_OPTPAR_CQN_RCV,
2632 },
2633 },
2634 [MLX5_QP_STATE_SQER] = {
2635 [MLX5_QP_STATE_RTS] = {
2636 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2637 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2638 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2639 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2640 MLX5_QP_OPTPAR_RWE |
2641 MLX5_QP_OPTPAR_RAE |
2642 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2643 },
2644 },
2645};
2646
2647static int ib_nr_to_mlx5_nr(int ib_mask)
2648{
2649 switch (ib_mask) {
2650 case IB_QP_STATE:
2651 return 0;
2652 case IB_QP_CUR_STATE:
2653 return 0;
2654 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2655 return 0;
2656 case IB_QP_ACCESS_FLAGS:
2657 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2658 MLX5_QP_OPTPAR_RAE;
2659 case IB_QP_PKEY_INDEX:
2660 return MLX5_QP_OPTPAR_PKEY_INDEX;
2661 case IB_QP_PORT:
2662 return MLX5_QP_OPTPAR_PRI_PORT;
2663 case IB_QP_QKEY:
2664 return MLX5_QP_OPTPAR_Q_KEY;
2665 case IB_QP_AV:
2666 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2667 MLX5_QP_OPTPAR_PRI_PORT;
2668 case IB_QP_PATH_MTU:
2669 return 0;
2670 case IB_QP_TIMEOUT:
2671 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2672 case IB_QP_RETRY_CNT:
2673 return MLX5_QP_OPTPAR_RETRY_COUNT;
2674 case IB_QP_RNR_RETRY:
2675 return MLX5_QP_OPTPAR_RNR_RETRY;
2676 case IB_QP_RQ_PSN:
2677 return 0;
2678 case IB_QP_MAX_QP_RD_ATOMIC:
2679 return MLX5_QP_OPTPAR_SRA_MAX;
2680 case IB_QP_ALT_PATH:
2681 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2682 case IB_QP_MIN_RNR_TIMER:
2683 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2684 case IB_QP_SQ_PSN:
2685 return 0;
2686 case IB_QP_MAX_DEST_RD_ATOMIC:
2687 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2688 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2689 case IB_QP_PATH_MIG_STATE:
2690 return MLX5_QP_OPTPAR_PM_STATE;
2691 case IB_QP_CAP:
2692 return 0;
2693 case IB_QP_DEST_QPN:
2694 return 0;
2695 }
2696 return 0;
2697}
2698
2699static int ib_mask_to_mlx5_opt(int ib_mask)
2700{
2701 int result = 0;
2702 int i;
2703
2704 for (i = 0; i < 8 * sizeof(int); i++) {
2705 if ((1 << i) & ib_mask)
2706 result |= ib_nr_to_mlx5_nr(1 << i);
2707 }
2708
2709 return result;
2710}
2711
eb49ab0c
AV		 2712static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2713 struct mlx5_ib_rq *rq, int new_state,
2714 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2715{
2716 void *in;
2717 void *rqc;
2718 int inlen;
2719 int err;
2720
2721 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 2722 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2723 if (!in)
2724 return -ENOMEM;
2725
2726 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2727
2728 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2729 MLX5_SET(rqc, rqc, state, new_state);
2730
eb49ab0c
AV		 2731 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2732 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2733 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 2734 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 2735 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2736 } else
2737 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2738 dev->ib_dev.name);
2739 }
2740
2741 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 2742 if (err)
2743 goto out;
2744
2745 rq->state = new_state;
2746
2747out:
2748 kvfree(in);
2749 return err;
2750}
2751
2752static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
7d29f349
BW		 2753 struct mlx5_ib_sq *sq,
2754 int new_state,
2755 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2756{
7d29f349
BW		 2757 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2758 u32 old_rate = ibqp->rate_limit;
2759 u32 new_rate = old_rate;
2760 u16 rl_index = 0;
ad5f8e96 2761 void *in;
2762 void *sqc;
2763 int inlen;
2764 int err;
2765
2766 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 2767 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2768 if (!in)
2769 return -ENOMEM;
2770
2771 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2772
2773 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2774 MLX5_SET(sqc, sqc, state, new_state);
2775
7d29f349
BW		 2776 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2777 if (new_state != MLX5_SQC_STATE_RDY)
2778 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2779 __func__);
2780 else
2781 new_rate = raw_qp_param->rate_limit;
2782 }
2783
2784 if (old_rate != new_rate) {
2785 if (new_rate) {
2786 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2787 if (err) {
2788 pr_err("Failed configuring rate %u: %d\n",
2789 new_rate, err);
2790 goto out;
2791 }
2792 }
2793
2794 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2795 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2796 }
2797
ad5f8e96 2798 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 2799 if (err) {
2800 /* Remove new rate from table if failed */
2801 if (new_rate &&
2802 old_rate != new_rate)
2803 mlx5_rl_remove_rate(dev, new_rate);
ad5f8e96 2804 goto out;
7d29f349
BW		 2805 }
2806
2807 /* Only remove the old rate after new rate was set */
2808 if ((old_rate &&
2809 (old_rate != new_rate)) ||
2810 (new_state != MLX5_SQC_STATE_RDY))
2811 mlx5_rl_remove_rate(dev, old_rate);
ad5f8e96 2812
7d29f349 2813 ibqp->rate_limit = new_rate;
ad5f8e96 2814 sq->state = new_state;
2815
2816out:
2817 kvfree(in);
2818 return err;
2819}
2820
2821static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2822 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2823 u8 tx_affinity)
ad5f8e96 2824{
2825 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2826 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2827 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 2828 int modify_rq = !!qp->rq.wqe_cnt;
2829 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 2830 int rq_state;
2831 int sq_state;
2832 int err;
2833
0680efa2 2834 switch (raw_qp_param->operation) {
ad5f8e96 2835 case MLX5_CMD_OP_RST2INIT_QP:
2836 rq_state = MLX5_RQC_STATE_RDY;
2837 sq_state = MLX5_SQC_STATE_RDY;
2838 break;
2839 case MLX5_CMD_OP_2ERR_QP:
2840 rq_state = MLX5_RQC_STATE_ERR;
2841 sq_state = MLX5_SQC_STATE_ERR;
2842 break;
2843 case MLX5_CMD_OP_2RST_QP:
2844 rq_state = MLX5_RQC_STATE_RST;
2845 sq_state = MLX5_SQC_STATE_RST;
2846 break;
ad5f8e96 2847 case MLX5_CMD_OP_RTR2RTS_QP:
2848 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 2849 if (raw_qp_param->set_mask ==
2850 MLX5_RAW_QP_RATE_LIMIT) {
2851 modify_rq = 0;
2852 sq_state = sq->state;
2853 } else {
2854 return raw_qp_param->set_mask ? -EINVAL : 0;
2855 }
2856 break;
2857 case MLX5_CMD_OP_INIT2INIT_QP:
2858 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 2859 if (raw_qp_param->set_mask)
2860 return -EINVAL;
2861 else
2862 return 0;
ad5f8e96 2863 default:
2864 WARN_ON(1);
2865 return -EINVAL;
2866 }
2867
7d29f349
BW		 2868 if (modify_rq) {
2869 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
ad5f8e96 2870 if (err)
2871 return err;
2872 }
2873
7d29f349 2874 if (modify_sq) {
13eab21f
AH		 2875 if (tx_affinity) {
2876 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2877 tx_affinity);
2878 if (err)
2879 return err;
2880 }
2881
7d29f349 2882 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
13eab21f 2883 }
ad5f8e96 2884
2885 return 0;
2886}
2887
e126ba97
EC		 2888static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2889 const struct ib_qp_attr *attr, int attr_mask,
2890 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2891{
427c1e7b 2892 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2893 [MLX5_QP_STATE_RST] = {
2894 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2895 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2896 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2897 },
2898 [MLX5_QP_STATE_INIT] = {
2899 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2900 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2901 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2902 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2903 },
2904 [MLX5_QP_STATE_RTR] = {
2905 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2906 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2907 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2908 },
2909 [MLX5_QP_STATE_RTS] = {
2910 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2911 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2912 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2913 },
2914 [MLX5_QP_STATE_SQD] = {
2915 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2916 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2917 },
2918 [MLX5_QP_STATE_SQER] = {
2919 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2920 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2921 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2922 },
2923 [MLX5_QP_STATE_ERR] = {
2924 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2925 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2926 }
2927 };
2928
e126ba97
EC		 2929 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2930 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2931 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2932 struct mlx5_ib_cq *send_cq, *recv_cq;
2933 struct mlx5_qp_context *context;
e126ba97 2934 struct mlx5_ib_pd *pd;
eb49ab0c 2935 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 2936 enum mlx5_qp_state mlx5_cur, mlx5_new;
2937 enum mlx5_qp_optpar optpar;
e126ba97
EC		 2938 int mlx5_st;
2939 int err;
427c1e7b 2940 u16 op;
13eab21f 2941 u8 tx_affinity = 0;
e126ba97 2942
1a412fb1
SM		 2943 context = kzalloc(sizeof(*context), GFP_KERNEL);
2944 if (!context)
e126ba97
EC		 2945 return -ENOMEM;
2946
c32a4f29
MS		 2947 err = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
2948 qp->qp_sub_type : ibqp->qp_type);
158abf86
HE		 2949 if (err < 0) {
2950 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2951 goto out;
158abf86 2952 }
e126ba97
EC		 2953
2954 context->flags = cpu_to_be32(err << 16);
2955
2956 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2957 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2958 } else {
2959 switch (attr->path_mig_state) {
2960 case IB_MIG_MIGRATED:
2961 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2962 break;
2963 case IB_MIG_REARM:
2964 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2965 break;
2966 case IB_MIG_ARMED:
2967 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2968 break;
2969 }
2970 }
2971
13eab21f
AH		 2972 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2973 if ((ibqp->qp_type == IB_QPT_RC) ||
2974 (ibqp->qp_type == IB_QPT_UD &&
2975 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2976 (ibqp->qp_type == IB_QPT_UC) ||
2977 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2978 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2979 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2980 if (mlx5_lag_is_active(dev->mdev)) {
7fd8aefb 2981 u8 p = mlx5_core_native_port_num(dev->mdev);
13eab21f 2982 tx_affinity = (unsigned int)atomic_add_return(1,
7fd8aefb 2983 &dev->roce[p].next_port) %
13eab21f
AH		 2984 MLX5_MAX_PORTS + 1;
2985 context->flags |= cpu_to_be32(tx_affinity << 24);
2986 }
2987 }
2988 }
2989
d16e91da 2990 if (is_sqp(ibqp->qp_type)) {
e126ba97 2991 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
c2e53b2c
YH		 2992 } else if ((ibqp->qp_type == IB_QPT_UD &&
2993 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
e126ba97
EC		 2994 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2995 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2996 } else if (attr_mask & IB_QP_PATH_MTU) {
2997 if (attr->path_mtu < IB_MTU_256 ||
2998 attr->path_mtu > IB_MTU_4096) {
2999 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3000 err = -EINVAL;
3001 goto out;
3002 }
938fe83c
SM		 3003 context->mtu_msgmax = (attr->path_mtu << 5) |
3004 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 3005 }
3006
3007 if (attr_mask & IB_QP_DEST_QPN)
3008 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3009
3010 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 3011 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 3012
3013 /* todo implement counter_index functionality */
3014
3015 if (is_sqp(ibqp->qp_type))
3016 context->pri_path.port = qp->port;
3017
3018 if (attr_mask & IB_QP_PORT)
3019 context->pri_path.port = attr->port_num;
3020
3021 if (attr_mask & IB_QP_AV) {
75850d0b 3022 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 3023 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 3024 attr_mask, 0, attr, false);
e126ba97
EC		 3025 if (err)
3026 goto out;
3027 }
3028
3029 if (attr_mask & IB_QP_TIMEOUT)
3030 context->pri_path.ackto_lt |= attr->timeout << 3;
3031
3032 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 3033 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3034 &context->alt_path,
f879ee8d
AS		 3035 attr->alt_port_num,
3036 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3037 0, attr, true);
e126ba97
EC		 3038 if (err)
3039 goto out;
3040 }
3041
3042 pd = get_pd(qp);
89ea94a7
MG		 3043 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3044 &send_cq, &recv_cq);
e126ba97
EC		 3045
3046 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3047 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3048 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3049 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3050
3051 if (attr_mask & IB_QP_RNR_RETRY)
3052 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3053
3054 if (attr_mask & IB_QP_RETRY_CNT)
3055 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3056
3057 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3058 if (attr->max_rd_atomic)
3059 context->params1 |=
3060 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3061 }
3062
3063 if (attr_mask & IB_QP_SQ_PSN)
3064 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3065
3066 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3067 if (attr->max_dest_rd_atomic)
3068 context->params2 |=
3069 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3070 }
3071
3072 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3073 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3074
3075 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3076 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3077
3078 if (attr_mask & IB_QP_RQ_PSN)
3079 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3080
3081 if (attr_mask & IB_QP_QKEY)
3082 context->qkey = cpu_to_be32(attr->qkey);
3083
3084 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3085 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3086
0837e86a
MB		 3087 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3088 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3089 qp->port) - 1;
c2e53b2c
YH		 3090
3091 /* Underlay port should be used - index 0 function per port */
3092 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3093 port_num = 0;
3094
eb49ab0c 3095 mibport = &dev->port[port_num];
0837e86a 3096 context->qp_counter_set_usr_page |=
e1f24a79 3097 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
0837e86a
MB		 3098 }
3099
e126ba97
EC		 3100 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3101 context->sq_crq_size |= cpu_to_be16(1 << 4);
3102
b11a4f9c
HE		 3103 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3104 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 3105
3106 mlx5_cur = to_mlx5_state(cur_state);
3107 mlx5_new = to_mlx5_state(new_state);
c32a4f29
MS		 3108 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3109 qp->qp_sub_type : ibqp->qp_type);
07c9113f 3110 if (mlx5_st < 0)
e126ba97
EC		 3111 goto out;
3112
427c1e7b 3113 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3114 !optab[mlx5_cur][mlx5_new])
3115 goto out;
3116
3117 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 3118 optpar = ib_mask_to_mlx5_opt(attr_mask);
3119 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 3120
c2e53b2c
YH		 3121 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3122 qp->flags & MLX5_IB_QP_UNDERLAY) {
0680efa2
AV		 3123 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3124
3125 raw_qp_param.operation = op;
eb49ab0c 3126 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
e1f24a79 3127 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
eb49ab0c
AV		 3128 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3129 }
7d29f349
BW		 3130
3131 if (attr_mask & IB_QP_RATE_LIMIT) {
3132 raw_qp_param.rate_limit = attr->rate_limit;
3133 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3134 }
3135
13eab21f 3136 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 3137 } else {
1a412fb1 3138 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 3139 &base->mqp);
0680efa2
AV		 3140 }
3141
e126ba97
EC		 3142 if (err)
3143 goto out;
3144
3145 qp->state = new_state;
3146
3147 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 3148 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 3149 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 3150 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 3151 if (attr_mask & IB_QP_PORT)
3152 qp->port = attr->port_num;
3153 if (attr_mask & IB_QP_ALT_PATH)
19098df2 3154 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 3155
3156 /*
3157 * If we moved a kernel QP to RESET, clean up all old CQ
3158 * entries and reinitialize the QP.
3159 */
3160 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 3161 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 3162 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3163 if (send_cq != recv_cq)
19098df2 3164 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 3165
3166 qp->rq.head = 0;
3167 qp->rq.tail = 0;
3168 qp->sq.head = 0;
3169 qp->sq.tail = 0;
3170 qp->sq.cur_post = 0;
3171 qp->sq.last_poll = 0;
3172 qp->db.db[MLX5_RCV_DBR] = 0;
3173 qp->db.db[MLX5_SND_DBR] = 0;
3174 }
3175
3176out:
1a412fb1 3177 kfree(context);
e126ba97
EC		 3178 return err;
3179}
3180
c32a4f29
MS		 3181static inline bool is_valid_mask(int mask, int req, int opt)
3182{
3183 if ((mask & req) != req)
3184 return false;
3185
3186 if (mask & ~(req | opt))
3187 return false;
3188
3189 return true;
3190}
3191
3192/* check valid transition for driver QP types
3193 * for now the only QP type that this function supports is DCI
3194 */
3195static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3196 enum ib_qp_attr_mask attr_mask)
3197{
3198 int req = IB_QP_STATE;
3199 int opt = 0;
3200
3201 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3202 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3203 return is_valid_mask(attr_mask, req, opt);
3204 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3205 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3206 return is_valid_mask(attr_mask, req, opt);
3207 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3208 req |= IB_QP_PATH_MTU;
3209 opt = IB_QP_PKEY_INDEX;
3210 return is_valid_mask(attr_mask, req, opt);
3211 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3212 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3213 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3214 opt = IB_QP_MIN_RNR_TIMER;
3215 return is_valid_mask(attr_mask, req, opt);
3216 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3217 opt = IB_QP_MIN_RNR_TIMER;
3218 return is_valid_mask(attr_mask, req, opt);
3219 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3220 return is_valid_mask(attr_mask, req, opt);
3221 }
3222 return false;
3223}
3224
776a3906
MS		 3225/* mlx5_ib_modify_dct: modify a DCT QP
3226 * valid transitions are:
3227 * RESET to INIT: must set access_flags, pkey_index and port
3228 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3229 * mtu, gid_index and hop_limit
3230 * Other transitions and attributes are illegal
3231 */
3232static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3233 int attr_mask, struct ib_udata *udata)
3234{
3235 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3236 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3237 enum ib_qp_state cur_state, new_state;
3238 int err = 0;
3239 int required = IB_QP_STATE;
3240 void *dctc;
3241
3242 if (!(attr_mask & IB_QP_STATE))
3243 return -EINVAL;
3244
3245 cur_state = qp->state;
3246 new_state = attr->qp_state;
3247
3248 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3249 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3250 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3251 if (!is_valid_mask(attr_mask, required, 0))
3252 return -EINVAL;
3253
3254 if (attr->port_num == 0 ||
3255 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3256 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3257 attr->port_num, dev->num_ports);
3258 return -EINVAL;
3259 }
3260 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3261 MLX5_SET(dctc, dctc, rre, 1);
3262 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3263 MLX5_SET(dctc, dctc, rwe, 1);
3264 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3265 if (!mlx5_ib_dc_atomic_is_supported(dev))
3266 return -EOPNOTSUPP;
3267 MLX5_SET(dctc, dctc, rae, 1);
3268 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3269 }
3270 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3271 MLX5_SET(dctc, dctc, port, attr->port_num);
3272 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3273
3274 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3275 struct mlx5_ib_modify_qp_resp resp = {};
3276 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3277 sizeof(resp.dctn);
3278
3279 if (udata->outlen < min_resp_len)
3280 return -EINVAL;
3281 resp.response_length = min_resp_len;
3282
3283 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3284 if (!is_valid_mask(attr_mask, required, 0))
3285 return -EINVAL;
3286 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3287 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3288 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3289 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3290 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3291 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3292
3293 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3294 MLX5_ST_SZ_BYTES(create_dct_in));
3295 if (err)
3296 return err;
3297 resp.dctn = qp->dct.mdct.mqp.qpn;
3298 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3299 if (err) {
3300 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3301 return err;
3302 }
3303 } else {
3304 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3305 return -EINVAL;
3306 }
3307 if (err)
3308 qp->state = IB_QPS_ERR;
3309 else
3310 qp->state = new_state;
3311 return err;
3312}
3313
e126ba97
EC		 3314int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3315 int attr_mask, struct ib_udata *udata)
3316{
3317 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3318 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 3319 enum ib_qp_type qp_type;
e126ba97
EC		 3320 enum ib_qp_state cur_state, new_state;
3321 int err = -EINVAL;
3322 int port;
2811ba51 3323 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 3324
28d61370
YH		 3325 if (ibqp->rwq_ind_tbl)
3326 return -ENOSYS;
3327
d16e91da
HE		 3328 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3329 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3330
c32a4f29
MS		 3331 if (ibqp->qp_type == IB_QPT_DRIVER)
3332 qp_type = qp->qp_sub_type;
3333 else
3334 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3335 IB_QPT_GSI : ibqp->qp_type;
3336
776a3906
MS		 3337 if (qp_type == MLX5_IB_QPT_DCT)
3338 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
d16e91da 3339
e126ba97
EC		 3340 mutex_lock(&qp->mutex);
3341
3342 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3343 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3344
2811ba51
AS		 3345 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3346 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3347 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3348 }
3349
c2e53b2c
YH		 3350 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3351 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3352 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3353 attr_mask);
3354 goto out;
3355 }
3356 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
c32a4f29
MS		 3357 qp_type != MLX5_IB_QPT_DCI &&
3358 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 3359 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3360 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 3361 goto out;
c32a4f29
MS		 3362 } else if (qp_type == MLX5_IB_QPT_DCI &&
3363 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3364 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3365 cur_state, new_state, qp_type, attr_mask);
3366 goto out;
158abf86 3367 }
e126ba97
EC		 3368
3369 if ((attr_mask & IB_QP_PORT) &&
938fe83c 3370 (attr->port_num == 0 ||
508562d6 3371 attr->port_num > dev->num_ports)) {
158abf86
HE		 3372 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3373 attr->port_num, dev->num_ports);
e126ba97 3374 goto out;
158abf86 3375 }
e126ba97
EC		 3376
3377 if (attr_mask & IB_QP_PKEY_INDEX) {
3378 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 3379 if (attr->pkey_index >=
158abf86
HE		 3380 dev->mdev->port_caps[port - 1].pkey_table_len) {
3381 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3382 attr->pkey_index);
e126ba97 3383 goto out;
158abf86 3384 }
e126ba97
EC		 3385 }
3386
3387 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 3388 attr->max_rd_atomic >
158abf86
HE		 3389 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3390 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3391 attr->max_rd_atomic);
e126ba97 3392 goto out;
158abf86 3393 }
e126ba97
EC		 3394
3395 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 3396 attr->max_dest_rd_atomic >
158abf86
HE		 3397 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3398 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3399 attr->max_dest_rd_atomic);
e126ba97 3400 goto out;
158abf86 3401 }
e126ba97
EC		 3402
3403 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3404 err = 0;
3405 goto out;
3406 }
3407
3408 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
3409
3410out:
3411 mutex_unlock(&qp->mutex);
3412 return err;
3413}
3414
3415static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3416{
3417 struct mlx5_ib_cq *cq;
3418 unsigned cur;
3419
3420 cur = wq->head - wq->tail;
3421 if (likely(cur + nreq < wq->max_post))
3422 return 0;
3423
3424 cq = to_mcq(ib_cq);
3425 spin_lock(&cq->lock);
3426 cur = wq->head - wq->tail;
3427 spin_unlock(&cq->lock);
3428
3429 return cur + nreq >= wq->max_post;
3430}
3431
3432static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3433 u64 remote_addr, u32 rkey)
3434{
3435 rseg->raddr = cpu_to_be64(remote_addr);
3436 rseg->rkey = cpu_to_be32(rkey);
3437 rseg->reserved = 0;
3438}
3439
f0313965
ES		 3440static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3441 struct ib_send_wr *wr, void *qend,
3442 struct mlx5_ib_qp *qp, int *size)
3443{
3444 void *seg = eseg;
3445
3446 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3447
3448 if (wr->send_flags & IB_SEND_IP_CSUM)
3449 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3450 MLX5_ETH_WQE_L4_CSUM;
3451
3452 seg += sizeof(struct mlx5_wqe_eth_seg);
3453 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3454
3455 if (wr->opcode == IB_WR_LSO) {
3456 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2b31f7ae 3457 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
f0313965
ES		 3458 u64 left, leftlen, copysz;
3459 void *pdata = ud_wr->header;
3460
3461 left = ud_wr->hlen;
3462 eseg->mss = cpu_to_be16(ud_wr->mss);
2b31f7ae 3463 eseg->inline_hdr.sz = cpu_to_be16(left);
f0313965
ES		 3464
3465 /*
3466 * check if there is space till the end of queue, if yes,
3467 * copy all in one shot, otherwise copy till the end of queue,
3468 * rollback and than the copy the left
3469 */
2b31f7ae 3470 leftlen = qend - (void *)eseg->inline_hdr.start;
f0313965
ES		 3471 copysz = min_t(u64, leftlen, left);
3472
3473 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3474
3475 if (likely(copysz > size_of_inl_hdr_start)) {
3476 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3477 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3478 }
3479
3480 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3481 seg = mlx5_get_send_wqe(qp, 0);
3482 left -= copysz;
3483 pdata += copysz;
3484 memcpy(seg, pdata, left);
3485 seg += ALIGN(left, 16);
3486 *size += ALIGN(left, 16) / 16;
3487 }
3488 }
3489
3490 return seg;
3491}
3492
e126ba97
EC		 3493static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3494 struct ib_send_wr *wr)
3495{
e622f2f4
CH		 3496 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3497 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3498 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3499}
3500
3501static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3502{
3503 dseg->byte_count = cpu_to_be32(sg->length);
3504 dseg->lkey = cpu_to_be32(sg->lkey);
3505 dseg->addr = cpu_to_be64(sg->addr);
3506}
3507
31616255 3508static u64 get_xlt_octo(u64 bytes)
e126ba97 3509{
31616255
AK		 3510 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3511 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3512}
3513
3514static __be64 frwr_mkey_mask(void)
3515{
3516 u64 result;
3517
3518 result = MLX5_MKEY_MASK_LEN |
3519 MLX5_MKEY_MASK_PAGE_SIZE |
3520 MLX5_MKEY_MASK_START_ADDR |
3521 MLX5_MKEY_MASK_EN_RINVAL |
3522 MLX5_MKEY_MASK_KEY |
3523 MLX5_MKEY_MASK_LR |
3524 MLX5_MKEY_MASK_LW |
3525 MLX5_MKEY_MASK_RR |
3526 MLX5_MKEY_MASK_RW |
3527 MLX5_MKEY_MASK_A |
3528 MLX5_MKEY_MASK_SMALL_FENCE |
3529 MLX5_MKEY_MASK_FREE;
3530
3531 return cpu_to_be64(result);
3532}
3533
e6631814
SG		 3534static __be64 sig_mkey_mask(void)
3535{
3536 u64 result;
3537
3538 result = MLX5_MKEY_MASK_LEN |
3539 MLX5_MKEY_MASK_PAGE_SIZE |
3540 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3541 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3542 MLX5_MKEY_MASK_EN_RINVAL |
3543 MLX5_MKEY_MASK_KEY |
3544 MLX5_MKEY_MASK_LR |
3545 MLX5_MKEY_MASK_LW |
3546 MLX5_MKEY_MASK_RR |
3547 MLX5_MKEY_MASK_RW |
3548 MLX5_MKEY_MASK_SMALL_FENCE |
3549 MLX5_MKEY_MASK_FREE |
3550 MLX5_MKEY_MASK_BSF_EN;
3551
3552 return cpu_to_be64(result);
3553}
3554
8a187ee5 3555static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3556 struct mlx5_ib_mr *mr)
8a187ee5 3557{
31616255 3558 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3559
3560 memset(umr, 0, sizeof(*umr));
b005d316 3561
8a187ee5 3562 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
31616255 3563 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3564 umr->mkey_mask = frwr_mkey_mask();
3565}
3566
dd01e66a 3567static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3568{
3569 memset(umr, 0, sizeof(*umr));
dd01e66a 3570 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3571 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3572}
3573
31616255 3574static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 3575{
3576 u64 result;
3577
31616255 3578 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 3579 MLX5_MKEY_MASK_FREE;
3580
968e78dd
HE		 3581 return cpu_to_be64(result);
3582}
3583
31616255 3584static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 3585{
3586 u64 result;
3587
3588 result = MLX5_MKEY_MASK_FREE;
3589
3590 return cpu_to_be64(result);
3591}
3592
56e11d62
NO		 3593static __be64 get_umr_update_translation_mask(void)
3594{
3595 u64 result;
3596
3597 result = MLX5_MKEY_MASK_LEN |
3598 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 3599 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 3600
3601 return cpu_to_be64(result);
3602}
3603
31616255 3604static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 3605{
3606 u64 result;
3607
31616255
AK		 3608 result = MLX5_MKEY_MASK_LR |
3609 MLX5_MKEY_MASK_LW |
56e11d62 3610 MLX5_MKEY_MASK_RR |
31616255
AK		 3611 MLX5_MKEY_MASK_RW;
3612
3613 if (atomic)
3614 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 3615
3616 return cpu_to_be64(result);
3617}
3618
3619static __be64 get_umr_update_pd_mask(void)
3620{
3621 u64 result;
3622
31616255 3623 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 3624
3625 return cpu_to_be64(result);
3626}
3627
e126ba97 3628static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
578e7264 3629 struct ib_send_wr *wr, int atomic)
e126ba97 3630{
e622f2f4 3631 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3632
3633 memset(umr, 0, sizeof(*umr));
3634
968e78dd
HE		 3635 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3636 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3637 else
3638 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3639
31616255
AK		 3640 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3641 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3642 u64 offset = get_xlt_octo(umrwr->offset);
3643
3644 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3645 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3646 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 3647 }
31616255
AK		 3648 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3649 umr->mkey_mask |= get_umr_update_translation_mask();
3650 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3651 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3652 umr->mkey_mask |= get_umr_update_pd_mask();
3653 }
3654 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3655 umr->mkey_mask |= get_umr_enable_mr_mask();
3656 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3657 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 3658
3659 if (!wr->num_sge)
968e78dd 3660 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3661}
3662
3663static u8 get_umr_flags(int acc)
3664{
3665 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3666 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3667 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3668 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3669 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3670}
3671
8a187ee5
SG		 3672static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3673 struct mlx5_ib_mr *mr,
3674 u32 key, int access)
3675{
3676 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3677
3678 memset(seg, 0, sizeof(*seg));
b005d316 3679
ec22eb53 3680 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3681 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3682 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3683 /* KLMs take twice the size of MTTs */
3684 ndescs *= 2;
3685
3686 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3687 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3688 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3689 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3690 seg->len = cpu_to_be64(mr->ibmr.length);
3691 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3692}
3693
dd01e66a 3694static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3695{
3696 memset(seg, 0, sizeof(*seg));
dd01e66a 3697 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3698}
3699
3700static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3701{
e622f2f4 3702 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3703
e126ba97 3704 memset(seg, 0, sizeof(*seg));
31616255 3705 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 3706 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 3707
968e78dd 3708 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 3709 if (umrwr->pd)
3710 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3711 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3712 !umrwr->length)
3713 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3714
3715 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 3716 seg->len = cpu_to_be64(umrwr->length);
3717 seg->log2_page_size = umrwr->page_shift;
746b5583 3718 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3719 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3720}
3721
8a187ee5
SG		 3722static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3723 struct mlx5_ib_mr *mr,
3724 struct mlx5_ib_pd *pd)
3725{
3726 int bcount = mr->desc_size * mr->ndescs;
3727
3728 dseg->addr = cpu_to_be64(mr->desc_map);
3729 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3730 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3731}
3732
e126ba97
EC		 3733static __be32 send_ieth(struct ib_send_wr *wr)
3734{
3735 switch (wr->opcode) {
3736 case IB_WR_SEND_WITH_IMM:
3737 case IB_WR_RDMA_WRITE_WITH_IMM:
3738 return wr->ex.imm_data;
3739
3740 case IB_WR_SEND_WITH_INV:
3741 return cpu_to_be32(wr->ex.invalidate_rkey);
3742
3743 default:
3744 return 0;
3745 }
3746}
3747
3748static u8 calc_sig(void *wqe, int size)
3749{
3750 u8 *p = wqe;
3751 u8 res = 0;
3752 int i;
3753
3754 for (i = 0; i < size; i++)
3755 res ^= p[i];
3756
3757 return ~res;
3758}
3759
3760static u8 wq_sig(void *wqe)
3761{
3762 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3763}
3764
3765static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3766 void *wqe, int *sz)
3767{
3768 struct mlx5_wqe_inline_seg *seg;
3769 void *qend = qp->sq.qend;
3770 void *addr;
3771 int inl = 0;
3772 int copy;
3773 int len;
3774 int i;
3775
3776 seg = wqe;
3777 wqe += sizeof(*seg);
3778 for (i = 0; i < wr->num_sge; i++) {
3779 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3780 len = wr->sg_list[i].length;
3781 inl += len;
3782
3783 if (unlikely(inl > qp->max_inline_data))
3784 return -ENOMEM;
3785
3786 if (unlikely(wqe + len > qend)) {
3787 copy = qend - wqe;
3788 memcpy(wqe, addr, copy);
3789 addr += copy;
3790 len -= copy;
3791 wqe = mlx5_get_send_wqe(qp, 0);
3792 }
3793 memcpy(wqe, addr, len);
3794 wqe += len;
3795 }
3796
3797 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3798
3799 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3800
3801 return 0;
3802}
3803
e6631814
SG		 3804static u16 prot_field_size(enum ib_signature_type type)
3805{
3806 switch (type) {
3807 case IB_SIG_TYPE_T10_DIF:
3808 return MLX5_DIF_SIZE;
3809 default:
3810 return 0;
3811 }
3812}
3813
3814static u8 bs_selector(int block_size)
3815{
3816 switch (block_size) {
3817 case 512: return 0x1;
3818 case 520: return 0x2;
3819 case 4096: return 0x3;
3820 case 4160: return 0x4;
3821 case 1073741824: return 0x5;
3822 default: return 0;
3823 }
3824}
3825
78eda2bb
SG		 3826static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3827 struct mlx5_bsf_inl *inl)
e6631814 3828{
142537f4
SG		 3829 /* Valid inline section and allow BSF refresh */
3830 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3831 MLX5_BSF_REFRESH_DIF);
3832 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3833 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3834 /* repeating block */
3835 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3836 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3837 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3838
78eda2bb
SG		 3839 if (domain->sig.dif.ref_remap)
3840 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3841
78eda2bb
SG		 3842 if (domain->sig.dif.app_escape) {
3843 if (domain->sig.dif.ref_escape)
3844 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3845 else
3846 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3847 }
3848
78eda2bb
SG		 3849 inl->dif_app_bitmask_check =
3850 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3851}
3852
3853static int mlx5_set_bsf(struct ib_mr *sig_mr,
3854 struct ib_sig_attrs *sig_attrs,
3855 struct mlx5_bsf *bsf, u32 data_size)
3856{
3857 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3858 struct mlx5_bsf_basic *basic = &bsf->basic;
3859 struct ib_sig_domain *mem = &sig_attrs->mem;
3860 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3861
c7f44fbd 3862 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3863
3864 /* Basic + Extended + Inline */
3865 basic->bsf_size_sbs = 1 << 7;
3866 /* Input domain check byte mask */
3867 basic->check_byte_mask = sig_attrs->check_mask;
3868 basic->raw_data_size = cpu_to_be32(data_size);
3869
3870 /* Memory domain */
e6631814 3871 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3872 case IB_SIG_TYPE_NONE:
3873 break;
e6631814 3874 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3875 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3876 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3877 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3878 break;
3879 default:
3880 return -EINVAL;
3881 }
e6631814 3882
78eda2bb
SG		 3883 /* Wire domain */
3884 switch (sig_attrs->wire.sig_type) {
3885 case IB_SIG_TYPE_NONE:
3886 break;
3887 case IB_SIG_TYPE_T10_DIF:
e6631814 3888 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3889 mem->sig_type == wire->sig_type) {
e6631814 3890 /* Same block structure */
142537f4 3891 basic->bsf_size_sbs |= 1 << 4;
e6631814 3892 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3893 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3894 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3895 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3896 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3897 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3898 } else
3899 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3900
142537f4 3901 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3902 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3903 break;
e6631814
SG		 3904 default:
3905 return -EINVAL;
3906 }
3907
3908 return 0;
3909}
3910
e622f2f4
CH		 3911static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3912 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3913{
e622f2f4
CH		 3914 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3915 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3916 struct mlx5_bsf *bsf;
e622f2f4
CH		 3917 u32 data_len = wr->wr.sg_list->length;
3918 u32 data_key = wr->wr.sg_list->lkey;
3919 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3920 int ret;
3921 int wqe_size;
3922
e622f2f4
CH		 3923 if (!wr->prot ||
3924 (data_key == wr->prot->lkey &&
3925 data_va == wr->prot->addr &&
3926 data_len == wr->prot->length)) {
e6631814
SG		 3927 /**
3928 * Source domain doesn't contain signature information
5c273b16 3929 * or data and protection are interleaved in memory.
e6631814
SG		 3930 * So need construct:
3931 * ------------------
3932 * | data_klm |
3933 * ------------------
3934 * | BSF |
3935 * ------------------
3936 **/
3937 struct mlx5_klm *data_klm = *seg;
3938
3939 data_klm->bcount = cpu_to_be32(data_len);
3940 data_klm->key = cpu_to_be32(data_key);
3941 data_klm->va = cpu_to_be64(data_va);
3942 wqe_size = ALIGN(sizeof(*data_klm), 64);
3943 } else {
3944 /**
3945 * Source domain contains signature information
3946 * So need construct a strided block format:
3947 * ---------------------------
3948 * | stride_block_ctrl |
3949 * ---------------------------
3950 * | data_klm |
3951 * ---------------------------
3952 * | prot_klm |
3953 * ---------------------------
3954 * | BSF |
3955 * ---------------------------
3956 **/
3957 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3958 struct mlx5_stride_block_entry *data_sentry;
3959 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3960 u32 prot_key = wr->prot->lkey;
3961 u64 prot_va = wr->prot->addr;
e6631814
SG		 3962 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3963 int prot_size;
3964
3965 sblock_ctrl = *seg;
3966 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3967 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3968
3969 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3970 if (!prot_size) {
3971 pr_err("Bad block size given: %u\n", block_size);
3972 return -EINVAL;
3973 }
3974 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3975 prot_size);
3976 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3977 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3978 sblock_ctrl->num_entries = cpu_to_be16(2);
3979
3980 data_sentry->bcount = cpu_to_be16(block_size);
3981 data_sentry->key = cpu_to_be32(data_key);
3982 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3983 data_sentry->stride = cpu_to_be16(block_size);
3984
e6631814
SG		 3985 prot_sentry->bcount = cpu_to_be16(prot_size);
3986 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3987 prot_sentry->va = cpu_to_be64(prot_va);
3988 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3989
e6631814
SG		 3990 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3991 sizeof(*prot_sentry), 64);
3992 }
3993
3994 *seg += wqe_size;
3995 *size += wqe_size / 16;
3996 if (unlikely((*seg == qp->sq.qend)))
3997 *seg = mlx5_get_send_wqe(qp, 0);
3998
3999 bsf = *seg;
4000 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4001 if (ret)
4002 return -EINVAL;
4003
4004 *seg += sizeof(*bsf);
4005 *size += sizeof(*bsf) / 16;
4006 if (unlikely((*seg == qp->sq.qend)))
4007 *seg = mlx5_get_send_wqe(qp, 0);
4008
4009 return 0;
4010}
4011
4012static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
31616255 4013 struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 4014 u32 length, u32 pdn)
4015{
e622f2f4 4016 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 4017 u32 sig_key = sig_mr->rkey;
d5436ba0 4018 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 4019
4020 memset(seg, 0, sizeof(*seg));
4021
e622f2f4 4022 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 4023 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 4024 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 4025 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 4026 MLX5_MKEY_BSF_EN | pdn);
4027 seg->len = cpu_to_be64(length);
31616255 4028 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 4029 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4030}
4031
4032static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 4033 u32 size)
e6631814
SG		 4034{
4035 memset(umr, 0, sizeof(*umr));
4036
4037 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 4038 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 4039 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4040 umr->mkey_mask = sig_mkey_mask();
4041}
4042
4043
e622f2f4 4044static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 4045 void **seg, int *size)
4046{
e622f2f4
CH		 4047 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4048 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 4049 u32 pdn = get_pd(qp)->pdn;
31616255 4050 u32 xlt_size;
e6631814
SG		 4051 int region_len, ret;
4052
e622f2f4
CH		 4053 if (unlikely(wr->wr.num_sge != 1) ||
4054 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 4055 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4056 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 4057 return -EINVAL;
4058
4059 /* length of the protected region, data + protection */
e622f2f4
CH		 4060 region_len = wr->wr.sg_list->length;
4061 if (wr->prot &&
4062 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4063 wr->prot->addr != wr->wr.sg_list->addr ||
4064 wr->prot->length != wr->wr.sg_list->length))
4065 region_len += wr->prot->length;
e6631814
SG		 4066
4067 /**
4068 * KLM octoword size - if protection was provided
4069 * then we use strided block format (3 octowords),
4070 * else we use single KLM (1 octoword)
4071 **/
31616255 4072 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 4073
31616255 4074 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 4075 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4076 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4077 if (unlikely((*seg == qp->sq.qend)))
4078 *seg = mlx5_get_send_wqe(qp, 0);
4079
31616255 4080 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 4081 *seg += sizeof(struct mlx5_mkey_seg);
4082 *size += sizeof(struct mlx5_mkey_seg) / 16;
4083 if (unlikely((*seg == qp->sq.qend)))
4084 *seg = mlx5_get_send_wqe(qp, 0);
4085
4086 ret = set_sig_data_segment(wr, qp, seg, size);
4087 if (ret)
4088 return ret;
4089
d5436ba0 4090 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 4091 return 0;
4092}
4093
4094static int set_psv_wr(struct ib_sig_domain *domain,
4095 u32 psv_idx, void **seg, int *size)
4096{
4097 struct mlx5_seg_set_psv *psv_seg = *seg;
4098
4099 memset(psv_seg, 0, sizeof(*psv_seg));
4100 psv_seg->psv_num = cpu_to_be32(psv_idx);
4101 switch (domain->sig_type) {
78eda2bb
SG		 4102 case IB_SIG_TYPE_NONE:
4103 break;
e6631814
SG		 4104 case IB_SIG_TYPE_T10_DIF:
4105 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4106 domain->sig.dif.app_tag);
4107 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 4108 break;
e6631814 4109 default:
12bbf1ea
LR		 4110 pr_err("Bad signature type (%d) is given.\n",
4111 domain->sig_type);
4112 return -EINVAL;
e6631814
SG		 4113 }
4114
78eda2bb
SG		 4115 *seg += sizeof(*psv_seg);
4116 *size += sizeof(*psv_seg) / 16;
4117
e6631814
SG		 4118 return 0;
4119}
4120
8a187ee5
SG		 4121static int set_reg_wr(struct mlx5_ib_qp *qp,
4122 struct ib_reg_wr *wr,
4123 void **seg, int *size)
4124{
4125 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4126 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4127
4128 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4129 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4130 "Invalid IB_SEND_INLINE send flag\n");
4131 return -EINVAL;
4132 }
4133
4134 set_reg_umr_seg(*seg, mr);
4135 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4136 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4137 if (unlikely((*seg == qp->sq.qend)))
4138 *seg = mlx5_get_send_wqe(qp, 0);
4139
4140 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4141 *seg += sizeof(struct mlx5_mkey_seg);
4142 *size += sizeof(struct mlx5_mkey_seg) / 16;
4143 if (unlikely((*seg == qp->sq.qend)))
4144 *seg = mlx5_get_send_wqe(qp, 0);
4145
4146 set_reg_data_seg(*seg, mr, pd);
4147 *seg += sizeof(struct mlx5_wqe_data_seg);
4148 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4149
4150 return 0;
4151}
4152
dd01e66a 4153static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 4154{
dd01e66a 4155 set_linv_umr_seg(*seg);
e126ba97
EC		 4156 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4157 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4158 if (unlikely((*seg == qp->sq.qend)))
4159 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 4160 set_linv_mkey_seg(*seg);
e126ba97
EC		 4161 *seg += sizeof(struct mlx5_mkey_seg);
4162 *size += sizeof(struct mlx5_mkey_seg) / 16;
4163 if (unlikely((*seg == qp->sq.qend)))
4164 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 4165}
4166
4167static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4168{
4169 __be32 *p = NULL;
4170 int tidx = idx;
4171 int i, j;
4172
4173 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4174 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4175 if ((i & 0xf) == 0) {
4176 void *buf = mlx5_get_send_wqe(qp, tidx);
4177 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4178 p = buf;
4179 j = 0;
4180 }
4181 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4182 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4183 be32_to_cpu(p[j + 3]));
4184 }
4185}
4186
6e5eadac
SG		 4187static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4188 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 4189 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 4190 int *size, int nreq)
4191{
b2a232d2
LR		 4192 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4193 return -ENOMEM;
6e5eadac
SG		 4194
4195 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4196 *seg = mlx5_get_send_wqe(qp, *idx);
4197 *ctrl = *seg;
4198 *(uint32_t *)(*seg + 8) = 0;
4199 (*ctrl)->imm = send_ieth(wr);
4200 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4201 (wr->send_flags & IB_SEND_SIGNALED ?
4202 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4203 (wr->send_flags & IB_SEND_SOLICITED ?
4204 MLX5_WQE_CTRL_SOLICITED : 0);
4205
4206 *seg += sizeof(**ctrl);
4207 *size = sizeof(**ctrl) / 16;
4208
b2a232d2 4209 return 0;
6e5eadac
SG		 4210}
4211
4212static void finish_wqe(struct mlx5_ib_qp *qp,
4213 struct mlx5_wqe_ctrl_seg *ctrl,
4214 u8 size, unsigned idx, u64 wr_id,
6e8484c5 4215 int nreq, u8 fence, u32 mlx5_opcode)
6e5eadac
SG		 4216{
4217 u8 opmod = 0;
4218
4219 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4220 mlx5_opcode | ((u32)opmod << 24));
19098df2 4221 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac 4222 ctrl->fm_ce_se |= fence;
6e5eadac
SG		 4223 if (unlikely(qp->wq_sig))
4224 ctrl->signature = wq_sig(ctrl);
4225
4226 qp->sq.wrid[idx] = wr_id;
4227 qp->sq.w_list[idx].opcode = mlx5_opcode;
4228 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4229 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4230 qp->sq.w_list[idx].next = qp->sq.cur_post;
4231}
4232
4233
e126ba97
EC		 4234int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4235 struct ib_send_wr **bad_wr)
4236{
4237 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4238 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 4239 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 4240 struct mlx5_ib_qp *qp;
e6631814 4241 struct mlx5_ib_mr *mr;
e126ba97
EC		 4242 struct mlx5_wqe_data_seg *dpseg;
4243 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 4244 struct mlx5_bf *bf;
e126ba97 4245 int uninitialized_var(size);
d16e91da 4246 void *qend;
e126ba97 4247 unsigned long flags;
e126ba97
EC		 4248 unsigned idx;
4249 int err = 0;
e126ba97
EC		 4250 int num_sge;
4251 void *seg;
4252 int nreq;
4253 int i;
4254 u8 next_fence = 0;
e126ba97
EC		 4255 u8 fence;
4256
d16e91da
HE		 4257 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4258 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4259
4260 qp = to_mqp(ibqp);
5fe9dec0 4261 bf = &qp->bf;
d16e91da
HE		 4262 qend = qp->sq.qend;
4263
e126ba97
EC		 4264 spin_lock_irqsave(&qp->sq.lock, flags);
4265
89ea94a7
MG		 4266 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4267 err = -EIO;
4268 *bad_wr = wr;
4269 nreq = 0;
4270 goto out;
4271 }
4272
e126ba97 4273 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 4274 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 4275 mlx5_ib_warn(dev, "\n");
4276 err = -EINVAL;
4277 *bad_wr = wr;
4278 goto out;
4279 }
4280
6e5eadac
SG		 4281 num_sge = wr->num_sge;
4282 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 4283 mlx5_ib_warn(dev, "\n");
24be409b 4284 err = -EINVAL;
e126ba97
EC		 4285 *bad_wr = wr;
4286 goto out;
4287 }
4288
6e5eadac
SG		 4289 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4290 if (err) {
e126ba97
EC		 4291 mlx5_ib_warn(dev, "\n");
4292 err = -ENOMEM;
4293 *bad_wr = wr;
4294 goto out;
4295 }
4296
6e8484c5
MG		 4297 if (wr->opcode == IB_WR_LOCAL_INV ||
4298 wr->opcode == IB_WR_REG_MR) {
4299 fence = dev->umr_fence;
4300 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4301 } else if (wr->send_flags & IB_SEND_FENCE) {
4302 if (qp->next_fence)
4303 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4304 else
4305 fence = MLX5_FENCE_MODE_FENCE;
4306 } else {
4307 fence = qp->next_fence;
4308 }
4309
e126ba97
EC		 4310 switch (ibqp->qp_type) {
4311 case IB_QPT_XRC_INI:
4312 xrc = seg;
e126ba97
EC		 4313 seg += sizeof(*xrc);
4314 size += sizeof(*xrc) / 16;
4315 /* fall through */
4316 case IB_QPT_RC:
4317 switch (wr->opcode) {
4318 case IB_WR_RDMA_READ:
4319 case IB_WR_RDMA_WRITE:
4320 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4321 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4322 rdma_wr(wr)->rkey);
f241e749 4323 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 4324 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4325 break;
4326
4327 case IB_WR_ATOMIC_CMP_AND_SWP:
4328 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 4329 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 4330 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4331 err = -ENOSYS;
4332 *bad_wr = wr;
4333 goto out;
e126ba97
EC		 4334
4335 case IB_WR_LOCAL_INV:
e126ba97
EC		 4336 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4337 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 4338 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 4339 num_sge = 0;
4340 break;
4341
8a187ee5 4342 case IB_WR_REG_MR:
8a187ee5
SG		 4343 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4344 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4345 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4346 if (err) {
4347 *bad_wr = wr;
4348 goto out;
4349 }
4350 num_sge = 0;
4351 break;
4352
e6631814
SG		 4353 case IB_WR_REG_SIG_MR:
4354 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 4355 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 4356
4357 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4358 err = set_sig_umr_wr(wr, qp, &seg, &size);
4359 if (err) {
4360 mlx5_ib_warn(dev, "\n");
4361 *bad_wr = wr;
4362 goto out;
4363 }
4364
6e8484c5
MG		 4365 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4366 fence, MLX5_OPCODE_UMR);
e6631814
SG		 4367 /*
4368 * SET_PSV WQEs are not signaled and solicited
4369 * on error
4370 */
4371 wr->send_flags &= ~IB_SEND_SIGNALED;
4372 wr->send_flags |= IB_SEND_SOLICITED;
4373 err = begin_wqe(qp, &seg, &ctrl, wr,
4374 &idx, &size, nreq);
4375 if (err) {
4376 mlx5_ib_warn(dev, "\n");
4377 err = -ENOMEM;
4378 *bad_wr = wr;
4379 goto out;
4380 }
4381
e622f2f4 4382 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 4383 mr->sig->psv_memory.psv_idx, &seg,
4384 &size);
4385 if (err) {
4386 mlx5_ib_warn(dev, "\n");
4387 *bad_wr = wr;
4388 goto out;
4389 }
4390
6e8484c5
MG		 4391 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4392 fence, MLX5_OPCODE_SET_PSV);
e6631814
SG		 4393 err = begin_wqe(qp, &seg, &ctrl, wr,
4394 &idx, &size, nreq);
4395 if (err) {
4396 mlx5_ib_warn(dev, "\n");
4397 err = -ENOMEM;
4398 *bad_wr = wr;
4399 goto out;
4400 }
4401
e622f2f4 4402 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 4403 mr->sig->psv_wire.psv_idx, &seg,
4404 &size);
4405 if (err) {
4406 mlx5_ib_warn(dev, "\n");
4407 *bad_wr = wr;
4408 goto out;
4409 }
4410
6e8484c5
MG		 4411 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4412 fence, MLX5_OPCODE_SET_PSV);
4413 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e6631814
SG		 4414 num_sge = 0;
4415 goto skip_psv;
4416
e126ba97
EC		 4417 default:
4418 break;
4419 }
4420 break;
4421
4422 case IB_QPT_UC:
4423 switch (wr->opcode) {
4424 case IB_WR_RDMA_WRITE:
4425 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4426 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4427 rdma_wr(wr)->rkey);
e126ba97
EC		 4428 seg += sizeof(struct mlx5_wqe_raddr_seg);
4429 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4430 break;
4431
4432 default:
4433 break;
4434 }
4435 break;
4436
e126ba97 4437 case IB_QPT_SMI:
1e0e50b6
MG		 4438 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4439 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4440 err = -EPERM;
4441 *bad_wr = wr;
4442 goto out;
4443 }
f6b1ee34 4444 /* fall through */
d16e91da 4445 case MLX5_IB_QPT_HW_GSI:
e126ba97 4446 set_datagram_seg(seg, wr);
f241e749 4447 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 4448 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4449 if (unlikely((seg == qend)))
4450 seg = mlx5_get_send_wqe(qp, 0);
4451 break;
f0313965
ES		 4452 case IB_QPT_UD:
4453 set_datagram_seg(seg, wr);
4454 seg += sizeof(struct mlx5_wqe_datagram_seg);
4455 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4456
4457 if (unlikely((seg == qend)))
4458 seg = mlx5_get_send_wqe(qp, 0);
4459
4460 /* handle qp that supports ud offload */
4461 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4462 struct mlx5_wqe_eth_pad *pad;
e126ba97 4463
f0313965
ES		 4464 pad = seg;
4465 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4466 seg += sizeof(struct mlx5_wqe_eth_pad);
4467 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4468
4469 seg = set_eth_seg(seg, wr, qend, qp, &size);
4470
4471 if (unlikely((seg == qend)))
4472 seg = mlx5_get_send_wqe(qp, 0);
4473 }
4474 break;
e126ba97
EC		 4475 case MLX5_IB_QPT_REG_UMR:
4476 if (wr->opcode != MLX5_IB_WR_UMR) {
4477 err = -EINVAL;
4478 mlx5_ib_warn(dev, "bad opcode\n");
4479 goto out;
4480 }
4481 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4482 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
578e7264 4483 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
e126ba97
EC		 4484 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4485 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4486 if (unlikely((seg == qend)))
4487 seg = mlx5_get_send_wqe(qp, 0);
4488 set_reg_mkey_segment(seg, wr);
4489 seg += sizeof(struct mlx5_mkey_seg);
4490 size += sizeof(struct mlx5_mkey_seg) / 16;
4491 if (unlikely((seg == qend)))
4492 seg = mlx5_get_send_wqe(qp, 0);
4493 break;
4494
4495 default:
4496 break;
4497 }
4498
4499 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4500 int uninitialized_var(sz);
4501
4502 err = set_data_inl_seg(qp, wr, seg, &sz);
4503 if (unlikely(err)) {
4504 mlx5_ib_warn(dev, "\n");
4505 *bad_wr = wr;
4506 goto out;
4507 }
e126ba97
EC		 4508 size += sz;
4509 } else {
4510 dpseg = seg;
4511 for (i = 0; i < num_sge; i++) {
4512 if (unlikely(dpseg == qend)) {
4513 seg = mlx5_get_send_wqe(qp, 0);
4514 dpseg = seg;
4515 }
4516 if (likely(wr->sg_list[i].length)) {
4517 set_data_ptr_seg(dpseg, wr->sg_list + i);
4518 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4519 dpseg++;
4520 }
4521 }
4522 }
4523
6e8484c5
MG		 4524 qp->next_fence = next_fence;
4525 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
6e5eadac 4526 mlx5_ib_opcode[wr->opcode]);
e6631814 4527skip_psv:
e126ba97
EC		 4528 if (0)
4529 dump_wqe(qp, idx, size);
4530 }
4531
4532out:
4533 if (likely(nreq)) {
4534 qp->sq.head += nreq;
4535
4536 /* Make sure that descriptors are written before
4537 * updating doorbell record and ringing the doorbell
4538 */
4539 wmb();
4540
4541 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4542
ada388f7
EC		 4543 /* Make sure doorbell record is visible to the HCA before
4544 * we hit doorbell */
4545 wmb();
4546
5fe9dec0
EC		 4547 /* currently we support only regular doorbells */
4548 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4549 /* Make sure doorbells don't leak out of SQ spinlock
4550 * and reach the HCA out of order.
4551 */
4552 mmiowb();
e126ba97 4553 bf->offset ^= bf->buf_size;
e126ba97
EC		 4554 }
4555
4556 spin_unlock_irqrestore(&qp->sq.lock, flags);
4557
4558 return err;
4559}
4560
4561static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4562{
4563 sig->signature = calc_sig(sig, size);
4564}
4565
4566int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4567 struct ib_recv_wr **bad_wr)
4568{
4569 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4570 struct mlx5_wqe_data_seg *scat;
4571 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4572 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4573 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4574 unsigned long flags;
4575 int err = 0;
4576 int nreq;
4577 int ind;
4578 int i;
4579
d16e91da
HE		 4580 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4581 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4582
e126ba97
EC		 4583 spin_lock_irqsave(&qp->rq.lock, flags);
4584
89ea94a7
MG		 4585 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4586 err = -EIO;
4587 *bad_wr = wr;
4588 nreq = 0;
4589 goto out;
4590 }
4591
e126ba97
EC		 4592 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4593
4594 for (nreq = 0; wr; nreq++, wr = wr->next) {
4595 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4596 err = -ENOMEM;
4597 *bad_wr = wr;
4598 goto out;
4599 }
4600
4601 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4602 err = -EINVAL;
4603 *bad_wr = wr;
4604 goto out;
4605 }
4606
4607 scat = get_recv_wqe(qp, ind);
4608 if (qp->wq_sig)
4609 scat++;
4610
4611 for (i = 0; i < wr->num_sge; i++)
4612 set_data_ptr_seg(scat + i, wr->sg_list + i);
4613
4614 if (i < qp->rq.max_gs) {
4615 scat[i].byte_count = 0;
4616 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4617 scat[i].addr = 0;
4618 }
4619
4620 if (qp->wq_sig) {
4621 sig = (struct mlx5_rwqe_sig *)scat;
4622 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4623 }
4624
4625 qp->rq.wrid[ind] = wr->wr_id;
4626
4627 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4628 }
4629
4630out:
4631 if (likely(nreq)) {
4632 qp->rq.head += nreq;
4633
4634 /* Make sure that descriptors are written before
4635 * doorbell record.
4636 */
4637 wmb();
4638
4639 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4640 }
4641
4642 spin_unlock_irqrestore(&qp->rq.lock, flags);
4643
4644 return err;
4645}
4646
4647static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4648{
4649 switch (mlx5_state) {
4650 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4651 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4652 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4653 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4654 case MLX5_QP_STATE_SQ_DRAINING:
4655 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4656 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4657 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4658 default: return -1;
4659 }
4660}
4661
4662static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4663{
4664 switch (mlx5_mig_state) {
4665 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4666 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4667 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4668 default: return -1;
4669 }
4670}
4671
4672static int to_ib_qp_access_flags(int mlx5_flags)
4673{
4674 int ib_flags = 0;
4675
4676 if (mlx5_flags & MLX5_QP_BIT_RRE)
4677 ib_flags |= IB_ACCESS_REMOTE_READ;
4678 if (mlx5_flags & MLX5_QP_BIT_RWE)
4679 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4680 if (mlx5_flags & MLX5_QP_BIT_RAE)
4681 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4682
4683 return ib_flags;
4684}
4685
38349389 4686static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
d8966fcd 4687 struct rdma_ah_attr *ah_attr,
38349389 4688 struct mlx5_qp_path *path)
e126ba97 4689{
e126ba97 4690
d8966fcd 4691 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 4692
e7996a9a 4693 if (!path->port || path->port > ibdev->num_ports)
e126ba97
EC		 4694 return;
4695
ae59c3f0
LR		 4696 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4697
d8966fcd
DC		 4698 rdma_ah_set_port_num(ah_attr, path->port);
4699 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4700
4701 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4702 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4703 rdma_ah_set_static_rate(ah_attr,
4704 path->static_rate ? path->static_rate - 5 : 0);
4705 if (path->grh_mlid & (1 << 7)) {
4706 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4707
4708 rdma_ah_set_grh(ah_attr, NULL,
4709 tc_fl & 0xfffff,
4710 path->mgid_index,
4711 path->hop_limit,
4712 (tc_fl >> 20) & 0xff);
4713 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
e126ba97
EC		 4714 }
4715}
4716
6d2f89df 4717static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4718 struct mlx5_ib_sq *sq,
4719 u8 *sq_state)
4720{
4721 void *out;
4722 void *sqc;
4723 int inlen;
4724 int err;
4725
4726 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
1b9a07ee 4727 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4728 if (!out)
4729 return -ENOMEM;
4730
4731 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4732 if (err)
4733 goto out;
4734
4735 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4736 *sq_state = MLX5_GET(sqc, sqc, state);
4737 sq->state = *sq_state;
4738
4739out:
4740 kvfree(out);
4741 return err;
4742}
4743
4744static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4745 struct mlx5_ib_rq *rq,
4746 u8 *rq_state)
4747{
4748 void *out;
4749 void *rqc;
4750 int inlen;
4751 int err;
4752
4753 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 4754 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4755 if (!out)
4756 return -ENOMEM;
4757
4758 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4759 if (err)
4760 goto out;
4761
4762 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4763 *rq_state = MLX5_GET(rqc, rqc, state);
4764 rq->state = *rq_state;
4765
4766out:
4767 kvfree(out);
4768 return err;
4769}
4770
4771static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4772 struct mlx5_ib_qp *qp, u8 *qp_state)
4773{
4774 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4775 [MLX5_RQC_STATE_RST] = {
4776 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4777 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4778 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4779 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4780 },
4781 [MLX5_RQC_STATE_RDY] = {
4782 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4783 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4784 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4785 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4786 },
4787 [MLX5_RQC_STATE_ERR] = {
4788 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4789 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4790 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4791 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4792 },
4793 [MLX5_RQ_STATE_NA] = {
4794 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4795 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4796 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4797 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4798 },
4799 };
4800
4801 *qp_state = sqrq_trans[rq_state][sq_state];
4802
4803 if (*qp_state == MLX5_QP_STATE_BAD) {
4804 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4805 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4806 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4807 return -EINVAL;
4808 }
4809
4810 if (*qp_state == MLX5_QP_STATE)
4811 *qp_state = qp->state;
4812
4813 return 0;
4814}
4815
4816static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4817 struct mlx5_ib_qp *qp,
4818 u8 *raw_packet_qp_state)
4819{
4820 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4821 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4822 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4823 int err;
4824 u8 sq_state = MLX5_SQ_STATE_NA;
4825 u8 rq_state = MLX5_RQ_STATE_NA;
4826
4827 if (qp->sq.wqe_cnt) {
4828 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4829 if (err)
4830 return err;
4831 }
4832
4833 if (qp->rq.wqe_cnt) {
4834 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4835 if (err)
4836 return err;
4837 }
4838
4839 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4840 raw_packet_qp_state);
4841}
4842
4843static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4844 struct ib_qp_attr *qp_attr)
e126ba97 4845{
09a7d9ec 4846 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 4847 struct mlx5_qp_context *context;
4848 int mlx5_state;
09a7d9ec 4849 u32 *outb;
e126ba97
EC		 4850 int err = 0;
4851
09a7d9ec 4852 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4853 if (!outb)
4854 return -ENOMEM;
4855
19098df2 4856 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 4857 outlen);
e126ba97 4858 if (err)
6d2f89df 4859 goto out;
e126ba97 4860
09a7d9ec
SM		 4861 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4862 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4863
e126ba97
EC		 4864 mlx5_state = be32_to_cpu(context->flags) >> 28;
4865
4866 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4867 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4868 qp_attr->path_mig_state =
4869 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4870 qp_attr->qkey = be32_to_cpu(context->qkey);
4871 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4872 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4873 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4874 qp_attr->qp_access_flags =
4875 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4876
4877 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
38349389
DC		 4878 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4879 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4880 qp_attr->alt_pkey_index =
4881 be16_to_cpu(context->alt_path.pkey_index);
d8966fcd
DC		 4882 qp_attr->alt_port_num =
4883 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
e126ba97
EC		 4884 }
4885
d3ae2bde 4886 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4887 qp_attr->port_num = context->pri_path.port;
4888
4889 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4890 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4891
4892 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4893
4894 qp_attr->max_dest_rd_atomic =
4895 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4896 qp_attr->min_rnr_timer =
4897 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4898 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4899 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4900 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4901 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4902
4903out:
4904 kfree(outb);
4905 return err;
4906}
4907
776a3906
MS		 4908static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
4909 struct ib_qp_attr *qp_attr, int qp_attr_mask,
4910 struct ib_qp_init_attr *qp_init_attr)
4911{
4912 struct mlx5_core_dct *dct = &mqp->dct.mdct;
4913 u32 *out;
4914 u32 access_flags = 0;
4915 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
4916 void *dctc;
4917 int err;
4918 int supported_mask = IB_QP_STATE |
4919 IB_QP_ACCESS_FLAGS |
4920 IB_QP_PORT |
4921 IB_QP_MIN_RNR_TIMER |
4922 IB_QP_AV |
4923 IB_QP_PATH_MTU |
4924 IB_QP_PKEY_INDEX;
4925
4926 if (qp_attr_mask & ~supported_mask)
4927 return -EINVAL;
4928 if (mqp->state != IB_QPS_RTR)
4929 return -EINVAL;
4930
4931 out = kzalloc(outlen, GFP_KERNEL);
4932 if (!out)
4933 return -ENOMEM;
4934
4935 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
4936 if (err)
4937 goto out;
4938
4939 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
4940
4941 if (qp_attr_mask & IB_QP_STATE)
4942 qp_attr->qp_state = IB_QPS_RTR;
4943
4944 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
4945 if (MLX5_GET(dctc, dctc, rre))
4946 access_flags |= IB_ACCESS_REMOTE_READ;
4947 if (MLX5_GET(dctc, dctc, rwe))
4948 access_flags |= IB_ACCESS_REMOTE_WRITE;
4949 if (MLX5_GET(dctc, dctc, rae))
4950 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
4951 qp_attr->qp_access_flags = access_flags;
4952 }
4953
4954 if (qp_attr_mask & IB_QP_PORT)
4955 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
4956 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
4957 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
4958 if (qp_attr_mask & IB_QP_AV) {
4959 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
4960 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
4961 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
4962 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
4963 }
4964 if (qp_attr_mask & IB_QP_PATH_MTU)
4965 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
4966 if (qp_attr_mask & IB_QP_PKEY_INDEX)
4967 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
4968out:
4969 kfree(out);
4970 return err;
4971}
4972
6d2f89df 4973int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4974 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4975{
4976 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4977 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4978 int err = 0;
4979 u8 raw_packet_qp_state;
4980
28d61370
YH		 4981 if (ibqp->rwq_ind_tbl)
4982 return -ENOSYS;
4983
d16e91da
HE		 4984 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4985 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4986 qp_init_attr);
4987
c2e53b2c
YH		 4988 /* Not all of output fields are applicable, make sure to zero them */
4989 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4990 memset(qp_attr, 0, sizeof(*qp_attr));
4991
776a3906
MS		 4992 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
4993 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
4994 qp_attr_mask, qp_init_attr);
4995
6d2f89df 4996 mutex_lock(&qp->mutex);
4997
c2e53b2c
YH		 4998 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4999 qp->flags & MLX5_IB_QP_UNDERLAY) {
6d2f89df 5000 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5001 if (err)
5002 goto out;
5003 qp->state = raw_packet_qp_state;
5004 qp_attr->port_num = 1;
5005 } else {
5006 err = query_qp_attr(dev, qp, qp_attr);
5007 if (err)
5008 goto out;
5009 }
5010
5011 qp_attr->qp_state = qp->state;
e126ba97
EC		 5012 qp_attr->cur_qp_state = qp_attr->qp_state;
5013 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5014 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5015
5016 if (!ibqp->uobject) {
0540d814 5017 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 5018 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 5019 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 5020 } else {
5021 qp_attr->cap.max_send_wr = 0;
5022 qp_attr->cap.max_send_sge = 0;
5023 }
5024
0540d814
NO		 5025 qp_init_attr->qp_type = ibqp->qp_type;
5026 qp_init_attr->recv_cq = ibqp->recv_cq;
5027 qp_init_attr->send_cq = ibqp->send_cq;
5028 qp_init_attr->srq = ibqp->srq;
5029 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 5030
5031 qp_init_attr->cap = qp_attr->cap;
5032
5033 qp_init_attr->create_flags = 0;
5034 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5035 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5036
051f2630
LR		 5037 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5038 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5039 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5040 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5041 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5042 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 5043 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5044 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 5045
e126ba97
EC		 5046 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5047 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5048
e126ba97
EC		 5049out:
5050 mutex_unlock(&qp->mutex);
5051 return err;
5052}
5053
5054struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5055 struct ib_ucontext *context,
5056 struct ib_udata *udata)
5057{
5058 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5059 struct mlx5_ib_xrcd *xrcd;
5060 int err;
5061
938fe83c 5062 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 5063 return ERR_PTR(-ENOSYS);
5064
5065 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5066 if (!xrcd)
5067 return ERR_PTR(-ENOMEM);
5068
9603b61d 5069 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 5070 if (err) {
5071 kfree(xrcd);
5072 return ERR_PTR(-ENOMEM);
5073 }
5074
5075 return &xrcd->ibxrcd;
5076}
5077
5078int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5079{
5080 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5081 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5082 int err;
5083
9603b61d 5084 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
b081808a 5085 if (err)
e126ba97 5086 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
e126ba97
EC		 5087
5088 kfree(xrcd);
e126ba97
EC		 5089 return 0;
5090}
79b20a6c 5091
350d0e4c
YH		 5092static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5093{
5094 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5095 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5096 struct ib_event event;
5097
5098 if (rwq->ibwq.event_handler) {
5099 event.device = rwq->ibwq.device;
5100 event.element.wq = &rwq->ibwq;
5101 switch (type) {
5102 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5103 event.event = IB_EVENT_WQ_FATAL;
5104 break;
5105 default:
5106 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5107 return;
5108 }
5109
5110 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5111 }
5112}
5113
03404e8a
MG		 5114static int set_delay_drop(struct mlx5_ib_dev *dev)
5115{
5116 int err = 0;
5117
5118 mutex_lock(&dev->delay_drop.lock);
5119 if (dev->delay_drop.activate)
5120 goto out;
5121
5122 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5123 if (err)
5124 goto out;
5125
5126 dev->delay_drop.activate = true;
5127out:
5128 mutex_unlock(&dev->delay_drop.lock);
fe248c3a
MG		 5129
5130 if (!err)
5131 atomic_inc(&dev->delay_drop.rqs_cnt);
03404e8a
MG		 5132 return err;
5133}
5134
79b20a6c
YH		 5135static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5136 struct ib_wq_init_attr *init_attr)
5137{
5138 struct mlx5_ib_dev *dev;
4be6da1e 5139 int has_net_offloads;
79b20a6c
YH		 5140 __be64 *rq_pas0;
5141 void *in;
5142 void *rqc;
5143 void *wq;
5144 int inlen;
5145 int err;
5146
5147 dev = to_mdev(pd->device);
5148
5149 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 5150 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5151 if (!in)
5152 return -ENOMEM;
5153
5154 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5155 MLX5_SET(rqc, rqc, mem_rq_type,
5156 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5157 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5158 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5159 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5160 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5161 wq = MLX5_ADDR_OF(rqc, rqc, wq);
ccc87087
NO		 5162 MLX5_SET(wq, wq, wq_type,
5163 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5164 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 5165 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5166 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5167 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5168 err = -EOPNOTSUPP;
5169 goto out;
5170 } else {
5171 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5172 }
5173 }
79b20a6c 5174 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
ccc87087
NO		 5175 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5176 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5177 MLX5_SET(wq, wq, log_wqe_stride_size,
5178 rwq->single_stride_log_num_of_bytes -
5179 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5180 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5181 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5182 }
79b20a6c
YH		 5183 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5184 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5185 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5186 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5187 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5188 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 5189 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 5190 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 5191 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 5192 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5193 err = -EOPNOTSUPP;
5194 goto out;
5195 }
5196 } else {
5197 MLX5_SET(rqc, rqc, vsd, 1);
5198 }
4be6da1e
NO		 5199 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5200 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5201 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5202 err = -EOPNOTSUPP;
5203 goto out;
5204 }
5205 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5206 }
03404e8a
MG		 5207 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5208 if (!(dev->ib_dev.attrs.raw_packet_caps &
5209 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5210 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5211 err = -EOPNOTSUPP;
5212 goto out;
5213 }
5214 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5215 }
79b20a6c
YH		 5216 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5217 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 5218 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
03404e8a
MG		 5219 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5220 err = set_delay_drop(dev);
5221 if (err) {
5222 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5223 err);
5224 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5225 } else {
5226 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5227 }
5228 }
b1f74a84 5229out:
79b20a6c
YH		 5230 kvfree(in);
5231 return err;
5232}
5233
5234static int set_user_rq_size(struct mlx5_ib_dev *dev,
5235 struct ib_wq_init_attr *wq_init_attr,
5236 struct mlx5_ib_create_wq *ucmd,
5237 struct mlx5_ib_rwq *rwq)
5238{
5239 /* Sanity check RQ size before proceeding */
5240 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5241 return -EINVAL;
5242
5243 if (!ucmd->rq_wqe_count)
5244 return -EINVAL;
5245
5246 rwq->wqe_count = ucmd->rq_wqe_count;
5247 rwq->wqe_shift = ucmd->rq_wqe_shift;
5248 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
5249 rwq->log_rq_stride = rwq->wqe_shift;
5250 rwq->log_rq_size = ilog2(rwq->wqe_count);
5251 return 0;
5252}
5253
5254static int prepare_user_rq(struct ib_pd *pd,
5255 struct ib_wq_init_attr *init_attr,
5256 struct ib_udata *udata,
5257 struct mlx5_ib_rwq *rwq)
5258{
5259 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5260 struct mlx5_ib_create_wq ucmd = {};
5261 int err;
5262 size_t required_cmd_sz;
5263
ccc87087
NO		 5264 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5265 + sizeof(ucmd.single_stride_log_num_of_bytes);
79b20a6c
YH		 5266 if (udata->inlen < required_cmd_sz) {
5267 mlx5_ib_dbg(dev, "invalid inlen\n");
5268 return -EINVAL;
5269 }
5270
5271 if (udata->inlen > sizeof(ucmd) &&
5272 !ib_is_udata_cleared(udata, sizeof(ucmd),
5273 udata->inlen - sizeof(ucmd))) {
5274 mlx5_ib_dbg(dev, "inlen is not supported\n");
5275 return -EOPNOTSUPP;
5276 }
5277
5278 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5279 mlx5_ib_dbg(dev, "copy failed\n");
5280 return -EFAULT;
5281 }
5282
ccc87087 5283 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
79b20a6c
YH		 5284 mlx5_ib_dbg(dev, "invalid comp mask\n");
5285 return -EOPNOTSUPP;
ccc87087
NO		 5286 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5287 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5288 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5289 return -EOPNOTSUPP;
5290 }
5291 if ((ucmd.single_stride_log_num_of_bytes <
5292 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5293 (ucmd.single_stride_log_num_of_bytes >
5294 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5295 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5296 ucmd.single_stride_log_num_of_bytes,
5297 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5298 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5299 return -EINVAL;
5300 }
5301 if ((ucmd.single_wqe_log_num_of_strides >
5302 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5303 (ucmd.single_wqe_log_num_of_strides <
5304 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5305 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5306 ucmd.single_wqe_log_num_of_strides,
5307 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5308 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5309 return -EINVAL;
5310 }
5311 rwq->single_stride_log_num_of_bytes =
5312 ucmd.single_stride_log_num_of_bytes;
5313 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5314 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5315 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
79b20a6c
YH		 5316 }
5317
5318 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5319 if (err) {
5320 mlx5_ib_dbg(dev, "err %d\n", err);
5321 return err;
5322 }
5323
5324 err = create_user_rq(dev, pd, rwq, &ucmd);
5325 if (err) {
5326 mlx5_ib_dbg(dev, "err %d\n", err);
5327 if (err)
5328 return err;
5329 }
5330
5331 rwq->user_index = ucmd.user_index;
5332 return 0;
5333}
5334
5335struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5336 struct ib_wq_init_attr *init_attr,
5337 struct ib_udata *udata)
5338{
5339 struct mlx5_ib_dev *dev;
5340 struct mlx5_ib_rwq *rwq;
5341 struct mlx5_ib_create_wq_resp resp = {};
5342 size_t min_resp_len;
5343 int err;
5344
5345 if (!udata)
5346 return ERR_PTR(-ENOSYS);
5347
5348 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5349 if (udata->outlen && udata->outlen < min_resp_len)
5350 return ERR_PTR(-EINVAL);
5351
5352 dev = to_mdev(pd->device);
5353 switch (init_attr->wq_type) {
5354 case IB_WQT_RQ:
5355 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5356 if (!rwq)
5357 return ERR_PTR(-ENOMEM);
5358 err = prepare_user_rq(pd, init_attr, udata, rwq);
5359 if (err)
5360 goto err;
5361 err = create_rq(rwq, pd, init_attr);
5362 if (err)
5363 goto err_user_rq;
5364 break;
5365 default:
5366 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5367 init_attr->wq_type);
5368 return ERR_PTR(-EINVAL);
5369 }
5370
350d0e4c 5371 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 5372 rwq->ibwq.state = IB_WQS_RESET;
5373 if (udata->outlen) {
5374 resp.response_length = offsetof(typeof(resp), response_length) +
5375 sizeof(resp.response_length);
5376 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5377 if (err)
5378 goto err_copy;
5379 }
5380
350d0e4c
YH		 5381 rwq->core_qp.event = mlx5_ib_wq_event;
5382 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 5383 return &rwq->ibwq;
5384
5385err_copy:
350d0e4c 5386 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c 5387err_user_rq:
fe248c3a 5388 destroy_user_rq(dev, pd, rwq);
79b20a6c
YH		 5389err:
5390 kfree(rwq);
5391 return ERR_PTR(err);
5392}
5393
5394int mlx5_ib_destroy_wq(struct ib_wq *wq)
5395{
5396 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5397 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5398
350d0e4c 5399 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
fe248c3a 5400 destroy_user_rq(dev, wq->pd, rwq);
79b20a6c
YH		 5401 kfree(rwq);
5402
5403 return 0;
5404}
5405
c5f90929
YH		 5406struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5407 struct ib_rwq_ind_table_init_attr *init_attr,
5408 struct ib_udata *udata)
5409{
5410 struct mlx5_ib_dev *dev = to_mdev(device);
5411 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5412 int sz = 1 << init_attr->log_ind_tbl_size;
5413 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5414 size_t min_resp_len;
5415 int inlen;
5416 int err;
5417 int i;
5418 u32 *in;
5419 void *rqtc;
5420
5421 if (udata->inlen > 0 &&
5422 !ib_is_udata_cleared(udata, 0,
5423 udata->inlen))
5424 return ERR_PTR(-EOPNOTSUPP);
5425
efd7f400
MG		 5426 if (init_attr->log_ind_tbl_size >
5427 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5428 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5429 init_attr->log_ind_tbl_size,
5430 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5431 return ERR_PTR(-EINVAL);
5432 }
5433
c5f90929
YH		 5434 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5435 if (udata->outlen && udata->outlen < min_resp_len)
5436 return ERR_PTR(-EINVAL);
5437
5438 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5439 if (!rwq_ind_tbl)
5440 return ERR_PTR(-ENOMEM);
5441
5442 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 5443 in = kvzalloc(inlen, GFP_KERNEL);
c5f90929
YH		 5444 if (!in) {
5445 err = -ENOMEM;
5446 goto err;
5447 }
5448
5449 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5450
5451 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5452 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5453
5454 for (i = 0; i < sz; i++)
5455 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5456
5457 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5458 kvfree(in);
5459
5460 if (err)
5461 goto err;
5462
5463 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5464 if (udata->outlen) {
5465 resp.response_length = offsetof(typeof(resp), response_length) +
5466 sizeof(resp.response_length);
5467 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5468 if (err)
5469 goto err_copy;
5470 }
5471
5472 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5473
5474err_copy:
5475 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5476err:
5477 kfree(rwq_ind_tbl);
5478 return ERR_PTR(err);
5479}
5480
5481int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5482{
5483 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5484 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5485
5486 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5487
5488 kfree(rwq_ind_tbl);
5489 return 0;
5490}
5491
79b20a6c
YH		 5492int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5493 u32 wq_attr_mask, struct ib_udata *udata)
5494{
5495 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5496 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5497 struct mlx5_ib_modify_wq ucmd = {};
5498 size_t required_cmd_sz;
5499 int curr_wq_state;
5500 int wq_state;
5501 int inlen;
5502 int err;
5503 void *rqc;
5504 void *in;
5505
5506 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5507 if (udata->inlen < required_cmd_sz)
5508 return -EINVAL;
5509
5510 if (udata->inlen > sizeof(ucmd) &&
5511 !ib_is_udata_cleared(udata, sizeof(ucmd),
5512 udata->inlen - sizeof(ucmd)))
5513 return -EOPNOTSUPP;
5514
5515 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5516 return -EFAULT;
5517
5518 if (ucmd.comp_mask || ucmd.reserved)
5519 return -EOPNOTSUPP;
5520
5521 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 5522 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5523 if (!in)
5524 return -ENOMEM;
5525
5526 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5527
5528 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5529 wq_attr->curr_wq_state : wq->state;
5530 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5531 wq_attr->wq_state : curr_wq_state;
5532 if (curr_wq_state == IB_WQS_ERR)
5533 curr_wq_state = MLX5_RQC_STATE_ERR;
5534 if (wq_state == IB_WQS_ERR)
5535 wq_state = MLX5_RQC_STATE_ERR;
5536 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5537 MLX5_SET(rqc, rqc, state, wq_state);
5538
b1f74a84
NO		 5539 if (wq_attr_mask & IB_WQ_FLAGS) {
5540 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5541 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5542 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5543 mlx5_ib_dbg(dev, "VLAN offloads are not "
5544 "supported\n");
5545 err = -EOPNOTSUPP;
5546 goto out;
5547 }
5548 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5549 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5550 MLX5_SET(rqc, rqc, vsd,
5551 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5552 }
b1383aa6
NO		 5553
5554 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5555 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5556 err = -EOPNOTSUPP;
5557 goto out;
5558 }
b1f74a84
NO		 5559 }
5560
23a6964e
MD		 5561 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5562 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5563 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5564 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
e1f24a79
PP		 5565 MLX5_SET(rqc, rqc, counter_set_id,
5566 dev->port->cnts.set_id);
23a6964e
MD		 5567 } else
5568 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5569 dev->ib_dev.name);
5570 }
5571
350d0e4c 5572 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 5573 if (!err)
5574 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5575
b1f74a84
NO		 5576out:
5577 kvfree(in);
79b20a6c
YH		 5578 return err;
5579}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git