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IB/mlx5: Expose vlan offloads capabilities
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
e126ba97 37#include "mlx5_ib.h"
e126ba97
EC		 38
39/* not supported currently */
40static int wq_signature;
41
42enum {
43 MLX5_IB_ACK_REQ_FREQ = 8,
44};
45
46enum {
47 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
48 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
49 MLX5_IB_LINK_TYPE_IB = 0,
50 MLX5_IB_LINK_TYPE_ETH = 1
51};
52
53enum {
54 MLX5_IB_SQ_STRIDE = 6,
e126ba97
EC		 55};
56
57static const u32 mlx5_ib_opcode[] = {
58 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 59 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 60 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
61 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
62 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
63 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
64 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
65 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
66 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
67 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 68 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 69 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
70 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
71 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
72};
73
f0313965
ES		 74struct mlx5_wqe_eth_pad {
75 u8 rsvd0[16];
76};
e126ba97 77
eb49ab0c
AV		 78enum raw_qp_set_mask_map {
79 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 80 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 81};
82
0680efa2
AV		 83struct mlx5_modify_raw_qp_param {
84 u16 operation;
eb49ab0c
AV		 85
86 u32 set_mask; /* raw_qp_set_mask_map */
7d29f349 87 u32 rate_limit;
eb49ab0c 88 u8 rq_q_ctr_id;
0680efa2
AV		 89};
90
89ea94a7
MG		 91static void get_cqs(enum ib_qp_type qp_type,
92 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
93 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
94
e126ba97
EC		 95static int is_qp0(enum ib_qp_type qp_type)
96{
97 return qp_type == IB_QPT_SMI;
98}
99
e126ba97
EC		 100static int is_sqp(enum ib_qp_type qp_type)
101{
102 return is_qp0(qp_type) || is_qp1(qp_type);
103}
104
105static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
106{
107 return mlx5_buf_offset(&qp->buf, offset);
108}
109
110static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
111{
112 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
113}
114
115void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
116{
117 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
118}
119
c1395a2a
HE		 120/**
121 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
122 *
123 * @qp: QP to copy from.
124 * @send: copy from the send queue when non-zero, use the receive queue
125 * otherwise.
126 * @wqe_index: index to start copying from. For send work queues, the
127 * wqe_index is in units of MLX5_SEND_WQE_BB.
128 * For receive work queue, it is the number of work queue
129 * element in the queue.
130 * @buffer: destination buffer.
131 * @length: maximum number of bytes to copy.
132 *
133 * Copies at least a single WQE, but may copy more data.
134 *
135 * Return: the number of bytes copied, or an error code.
136 */
137int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 138 void *buffer, u32 length,
139 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 140{
141 struct ib_device *ibdev = qp->ibqp.device;
142 struct mlx5_ib_dev *dev = to_mdev(ibdev);
143 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
144 size_t offset;
145 size_t wq_end;
19098df2 146 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 147 u32 first_copy_length;
148 int wqe_length;
149 int ret;
150
151 if (wq->wqe_cnt == 0) {
152 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
153 qp->ibqp.qp_type);
154 return -EINVAL;
155 }
156
157 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
158 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
159
160 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
161 return -EINVAL;
162
163 if (offset > umem->length ||
164 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
165 return -EINVAL;
166
167 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
168 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
169 if (ret)
170 return ret;
171
172 if (send) {
173 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
174 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
175
176 wqe_length = ds * MLX5_WQE_DS_UNITS;
177 } else {
178 wqe_length = 1 << wq->wqe_shift;
179 }
180
181 if (wqe_length <= first_copy_length)
182 return first_copy_length;
183
184 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
185 wqe_length - first_copy_length);
186 if (ret)
187 return ret;
188
189 return wqe_length;
190}
191
e126ba97
EC		 192static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
193{
194 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
195 struct ib_event event;
196
19098df2 197 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
198 /* This event is only valid for trans_qps */
199 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
200 }
e126ba97
EC		 201
202 if (ibqp->event_handler) {
203 event.device = ibqp->device;
204 event.element.qp = ibqp;
205 switch (type) {
206 case MLX5_EVENT_TYPE_PATH_MIG:
207 event.event = IB_EVENT_PATH_MIG;
208 break;
209 case MLX5_EVENT_TYPE_COMM_EST:
210 event.event = IB_EVENT_COMM_EST;
211 break;
212 case MLX5_EVENT_TYPE_SQ_DRAINED:
213 event.event = IB_EVENT_SQ_DRAINED;
214 break;
215 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
216 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
217 break;
218 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
219 event.event = IB_EVENT_QP_FATAL;
220 break;
221 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
222 event.event = IB_EVENT_PATH_MIG_ERR;
223 break;
224 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
225 event.event = IB_EVENT_QP_REQ_ERR;
226 break;
227 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
228 event.event = IB_EVENT_QP_ACCESS_ERR;
229 break;
230 default:
231 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
232 return;
233 }
234
235 ibqp->event_handler(&event, ibqp->qp_context);
236 }
237}
238
239static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
240 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
241{
242 int wqe_size;
243 int wq_size;
244
245 /* Sanity check RQ size before proceeding */
938fe83c 246 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 247 return -EINVAL;
248
249 if (!has_rq) {
250 qp->rq.max_gs = 0;
251 qp->rq.wqe_cnt = 0;
252 qp->rq.wqe_shift = 0;
0540d814
NO		 253 cap->max_recv_wr = 0;
254 cap->max_recv_sge = 0;
e126ba97
EC		 255 } else {
256 if (ucmd) {
257 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
258 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
259 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
260 qp->rq.max_post = qp->rq.wqe_cnt;
261 } else {
262 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
263 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
264 wqe_size = roundup_pow_of_two(wqe_size);
265 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
266 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
267 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 268 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 269 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
270 wqe_size,
938fe83c
SM		 271 MLX5_CAP_GEN(dev->mdev,
272 max_wqe_sz_rq));
e126ba97
EC		 273 return -EINVAL;
274 }
275 qp->rq.wqe_shift = ilog2(wqe_size);
276 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
277 qp->rq.max_post = qp->rq.wqe_cnt;
278 }
279 }
280
281 return 0;
282}
283
f0313965 284static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 285{
618af384 286 int size = 0;
e126ba97 287
f0313965 288 switch (attr->qp_type) {
e126ba97 289 case IB_QPT_XRC_INI:
b125a54b 290 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 291 /* fall through */
292 case IB_QPT_RC:
293 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 294 max(sizeof(struct mlx5_wqe_atomic_seg) +
295 sizeof(struct mlx5_wqe_raddr_seg),
296 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
297 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 298 break;
299
b125a54b
EC		 300 case IB_QPT_XRC_TGT:
301 return 0;
302
e126ba97 303 case IB_QPT_UC:
b125a54b 304 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 305 max(sizeof(struct mlx5_wqe_raddr_seg),
306 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
307 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 308 break;
309
310 case IB_QPT_UD:
f0313965
ES		 311 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
312 size += sizeof(struct mlx5_wqe_eth_pad) +
313 sizeof(struct mlx5_wqe_eth_seg);
314 /* fall through */
e126ba97 315 case IB_QPT_SMI:
d16e91da 316 case MLX5_IB_QPT_HW_GSI:
b125a54b 317 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 318 sizeof(struct mlx5_wqe_datagram_seg);
319 break;
320
321 case MLX5_IB_QPT_REG_UMR:
b125a54b 322 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 323 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
324 sizeof(struct mlx5_mkey_seg);
325 break;
326
327 default:
328 return -EINVAL;
329 }
330
331 return size;
332}
333
334static int calc_send_wqe(struct ib_qp_init_attr *attr)
335{
336 int inl_size = 0;
337 int size;
338
f0313965 339 size = sq_overhead(attr);
e126ba97
EC		 340 if (size < 0)
341 return size;
342
343 if (attr->cap.max_inline_data) {
344 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
345 attr->cap.max_inline_data;
346 }
347
348 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 349 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
350 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
351 return MLX5_SIG_WQE_SIZE;
352 else
353 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 354}
355
288c01b7
EC		 356static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
357{
358 int max_sge;
359
360 if (attr->qp_type == IB_QPT_RC)
361 max_sge = (min_t(int, wqe_size, 512) -
362 sizeof(struct mlx5_wqe_ctrl_seg) -
363 sizeof(struct mlx5_wqe_raddr_seg)) /
364 sizeof(struct mlx5_wqe_data_seg);
365 else if (attr->qp_type == IB_QPT_XRC_INI)
366 max_sge = (min_t(int, wqe_size, 512) -
367 sizeof(struct mlx5_wqe_ctrl_seg) -
368 sizeof(struct mlx5_wqe_xrc_seg) -
369 sizeof(struct mlx5_wqe_raddr_seg)) /
370 sizeof(struct mlx5_wqe_data_seg);
371 else
372 max_sge = (wqe_size - sq_overhead(attr)) /
373 sizeof(struct mlx5_wqe_data_seg);
374
375 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
376 sizeof(struct mlx5_wqe_data_seg));
377}
378
e126ba97
EC		 379static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
380 struct mlx5_ib_qp *qp)
381{
382 int wqe_size;
383 int wq_size;
384
385 if (!attr->cap.max_send_wr)
386 return 0;
387
388 wqe_size = calc_send_wqe(attr);
389 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
390 if (wqe_size < 0)
391 return wqe_size;
392
938fe83c 393 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 394 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 395 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 396 return -EINVAL;
397 }
398
f0313965
ES		 399 qp->max_inline_data = wqe_size - sq_overhead(attr) -
400 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 401 attr->cap.max_inline_data = qp->max_inline_data;
402
e1e66cc2
SG		 403 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
404 qp->signature_en = true;
405
e126ba97
EC		 406 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
407 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 408 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 409 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
410 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 411 qp->sq.wqe_cnt,
412 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 413 return -ENOMEM;
414 }
e126ba97 415 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 416 qp->sq.max_gs = get_send_sge(attr, wqe_size);
417 if (qp->sq.max_gs < attr->cap.max_send_sge)
418 return -ENOMEM;
419
420 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 421 qp->sq.max_post = wq_size / wqe_size;
422 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 423
424 return wq_size;
425}
426
427static int set_user_buf_size(struct mlx5_ib_dev *dev,
428 struct mlx5_ib_qp *qp,
19098df2 429 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 430 struct mlx5_ib_qp_base *base,
431 struct ib_qp_init_attr *attr)
e126ba97
EC		 432{
433 int desc_sz = 1 << qp->sq.wqe_shift;
434
938fe83c 435 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 436 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 437 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 438 return -EINVAL;
439 }
440
441 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
442 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
443 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
444 return -EINVAL;
445 }
446
447 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
448
938fe83c 449 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 450 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 451 qp->sq.wqe_cnt,
452 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 453 return -EINVAL;
454 }
455
0fb2ed66 456 if (attr->qp_type == IB_QPT_RAW_PACKET) {
457 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
458 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
459 } else {
460 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
461 (qp->sq.wqe_cnt << 6);
462 }
e126ba97
EC		 463
464 return 0;
465}
466
467static int qp_has_rq(struct ib_qp_init_attr *attr)
468{
469 if (attr->qp_type == IB_QPT_XRC_INI ||
470 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
471 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
472 !attr->cap.max_recv_wr)
473 return 0;
474
475 return 1;
476}
477
2f5ff264 478static int first_med_bfreg(void)
c1be5232
EC		 479{
480 return 1;
481}
482
0b80c14f
EC		 483enum {
484 /* this is the first blue flame register in the array of bfregs assigned
485 * to a processes. Since we do not use it for blue flame but rather
486 * regular 64 bit doorbells, we do not need a lock for maintaiing
487 * "odd/even" order
488 */
489 NUM_NON_BLUE_FLAME_BFREGS = 1,
490};
491
b037c29a
EC		 492static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
493{
494 return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
495}
496
497static int num_med_bfreg(struct mlx5_ib_dev *dev,
498 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 499{
500 int n;
501
b037c29a
EC		 502 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
503 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 504
505 return n >= 0 ? n : 0;
506}
507
b037c29a
EC		 508static int first_hi_bfreg(struct mlx5_ib_dev *dev,
509 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 510{
511 int med;
c1be5232 512
b037c29a
EC		 513 med = num_med_bfreg(dev, bfregi);
514 return ++med;
c1be5232
EC		 515}
516
b037c29a
EC		 517static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
518 struct mlx5_bfreg_info *bfregi)
e126ba97 519{
e126ba97
EC		 520 int i;
521
b037c29a
EC		 522 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
523 if (!bfregi->count[i]) {
2f5ff264 524 bfregi->count[i]++;
e126ba97
EC		 525 return i;
526 }
527 }
528
529 return -ENOMEM;
530}
531
b037c29a
EC		 532static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
533 struct mlx5_bfreg_info *bfregi)
e126ba97 534{
2f5ff264 535 int minidx = first_med_bfreg();
e126ba97
EC		 536 int i;
537
b037c29a 538 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 539 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 540 minidx = i;
0b80c14f
EC		 541 if (!bfregi->count[minidx])
542 break;
e126ba97
EC		 543 }
544
2f5ff264 545 bfregi->count[minidx]++;
e126ba97
EC		 546 return minidx;
547}
548
b037c29a
EC		 549static int alloc_bfreg(struct mlx5_ib_dev *dev,
550 struct mlx5_bfreg_info *bfregi,
2f5ff264 551 enum mlx5_ib_latency_class lat)
e126ba97 552{
2f5ff264 553 int bfregn = -EINVAL;
e126ba97 554
2f5ff264 555 mutex_lock(&bfregi->lock);
e126ba97
EC		 556 switch (lat) {
557 case MLX5_IB_LATENCY_CLASS_LOW:
0b80c14f 558 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 559 bfregn = 0;
560 bfregi->count[bfregn]++;
e126ba97
EC		 561 break;
562
563 case MLX5_IB_LATENCY_CLASS_MEDIUM:
2f5ff264
EC		 564 if (bfregi->ver < 2)
565 bfregn = -ENOMEM;
78c0f98c 566 else
b037c29a 567 bfregn = alloc_med_class_bfreg(dev, bfregi);
e126ba97
EC		 568 break;
569
570 case MLX5_IB_LATENCY_CLASS_HIGH:
2f5ff264
EC		 571 if (bfregi->ver < 2)
572 bfregn = -ENOMEM;
78c0f98c 573 else
b037c29a 574 bfregn = alloc_high_class_bfreg(dev, bfregi);
e126ba97
EC		 575 break;
576 }
2f5ff264 577 mutex_unlock(&bfregi->lock);
e126ba97 578
2f5ff264 579 return bfregn;
e126ba97
EC		 580}
581
b037c29a 582static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 583{
2f5ff264 584 mutex_lock(&bfregi->lock);
b037c29a 585 bfregi->count[bfregn]--;
2f5ff264 586 mutex_unlock(&bfregi->lock);
e126ba97
EC		 587}
588
589static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
590{
591 switch (state) {
592 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
593 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
594 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
595 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
596 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
597 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
598 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
599 default: return -1;
600 }
601}
602
603static int to_mlx5_st(enum ib_qp_type type)
604{
605 switch (type) {
606 case IB_QPT_RC: return MLX5_QP_ST_RC;
607 case IB_QPT_UC: return MLX5_QP_ST_UC;
608 case IB_QPT_UD: return MLX5_QP_ST_UD;
609 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
610 case IB_QPT_XRC_INI:
611 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
612 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 613 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
e126ba97 614 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 615 case IB_QPT_RAW_PACKET:
0fb2ed66 616 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 617 case IB_QPT_MAX:
618 default: return -EINVAL;
619 }
620}
621
89ea94a7
MG		 622static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
623 struct mlx5_ib_cq *recv_cq);
624static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
625 struct mlx5_ib_cq *recv_cq);
626
b037c29a
EC		 627static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
628 struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 629{
b037c29a
EC		 630 int bfregs_per_sys_page;
631 int index_of_sys_page;
632 int offset;
633
634 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
635 MLX5_NON_FP_BFREGS_PER_UAR;
636 index_of_sys_page = bfregn / bfregs_per_sys_page;
637
638 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
639
640 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 641}
642
19098df2 643static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
644 struct ib_pd *pd,
645 unsigned long addr, size_t size,
646 struct ib_umem **umem,
647 int *npages, int *page_shift, int *ncont,
648 u32 *offset)
649{
650 int err;
651
652 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
653 if (IS_ERR(*umem)) {
654 mlx5_ib_dbg(dev, "umem_get failed\n");
655 return PTR_ERR(*umem);
656 }
657
762f899a 658 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 659
660 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
661 if (err) {
662 mlx5_ib_warn(dev, "bad offset\n");
663 goto err_umem;
664 }
665
666 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
667 addr, size, *npages, *page_shift, *ncont, *offset);
668
669 return 0;
670
671err_umem:
672 ib_umem_release(*umem);
673 *umem = NULL;
674
675 return err;
676}
677
79b20a6c
YH		 678static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
679{
680 struct mlx5_ib_ucontext *context;
681
682 context = to_mucontext(pd->uobject->context);
683 mlx5_ib_db_unmap_user(context, &rwq->db);
684 if (rwq->umem)
685 ib_umem_release(rwq->umem);
686}
687
688static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
689 struct mlx5_ib_rwq *rwq,
690 struct mlx5_ib_create_wq *ucmd)
691{
692 struct mlx5_ib_ucontext *context;
693 int page_shift = 0;
694 int npages;
695 u32 offset = 0;
696 int ncont = 0;
697 int err;
698
699 if (!ucmd->buf_addr)
700 return -EINVAL;
701
702 context = to_mucontext(pd->uobject->context);
703 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
704 rwq->buf_size, 0, 0);
705 if (IS_ERR(rwq->umem)) {
706 mlx5_ib_dbg(dev, "umem_get failed\n");
707 err = PTR_ERR(rwq->umem);
708 return err;
709 }
710
762f899a 711 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 712 &ncont, NULL);
713 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
714 &rwq->rq_page_offset);
715 if (err) {
716 mlx5_ib_warn(dev, "bad offset\n");
717 goto err_umem;
718 }
719
720 rwq->rq_num_pas = ncont;
721 rwq->page_shift = page_shift;
722 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
723 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
724
725 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
726 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
727 npages, page_shift, ncont, offset);
728
729 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
730 if (err) {
731 mlx5_ib_dbg(dev, "map failed\n");
732 goto err_umem;
733 }
734
735 rwq->create_type = MLX5_WQ_USER;
736 return 0;
737
738err_umem:
739 ib_umem_release(rwq->umem);
740 return err;
741}
742
b037c29a
EC		 743static int adjust_bfregn(struct mlx5_ib_dev *dev,
744 struct mlx5_bfreg_info *bfregi, int bfregn)
745{
746 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
747 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
748}
749
e126ba97
EC		 750static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
751 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 752 struct ib_qp_init_attr *attr,
09a7d9ec 753 u32 **in,
19098df2 754 struct mlx5_ib_create_qp_resp *resp, int *inlen,
755 struct mlx5_ib_qp_base *base)
e126ba97
EC		 756{
757 struct mlx5_ib_ucontext *context;
758 struct mlx5_ib_create_qp ucmd;
19098df2 759 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 760 int page_shift = 0;
e126ba97
EC		 761 int uar_index;
762 int npages;
9e9c47d0 763 u32 offset = 0;
2f5ff264 764 int bfregn;
9e9c47d0 765 int ncont = 0;
09a7d9ec
SM		 766 __be64 *pas;
767 void *qpc;
e126ba97
EC		 768 int err;
769
770 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
771 if (err) {
772 mlx5_ib_dbg(dev, "copy failed\n");
773 return err;
774 }
775
776 context = to_mucontext(pd->uobject->context);
777 /*
778 * TBD: should come from the verbs when we have the API
779 */
051f2630
LR		 780 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
781 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 782 bfregn = MLX5_CROSS_CHANNEL_BFREG;
051f2630 783 else {
b037c29a 784 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
2f5ff264
EC		 785 if (bfregn < 0) {
786 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
051f2630 787 mlx5_ib_dbg(dev, "reverting to medium latency\n");
b037c29a 788 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
2f5ff264
EC		 789 if (bfregn < 0) {
790 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
051f2630 791 mlx5_ib_dbg(dev, "reverting to high latency\n");
b037c29a 792 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
2f5ff264
EC		 793 if (bfregn < 0) {
794 mlx5_ib_warn(dev, "bfreg allocation failed\n");
795 return bfregn;
051f2630 796 }
c1be5232 797 }
e126ba97
EC		 798 }
799 }
800
b037c29a 801 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn);
2f5ff264 802 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
e126ba97 803
48fea837
HE		 804 qp->rq.offset = 0;
805 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
806 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
807
0fb2ed66 808 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 809 if (err)
2f5ff264 810 goto err_bfreg;
e126ba97 811
19098df2 812 if (ucmd.buf_addr && ubuffer->buf_size) {
813 ubuffer->buf_addr = ucmd.buf_addr;
814 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
815 ubuffer->buf_size,
816 &ubuffer->umem, &npages, &page_shift,
817 &ncont, &offset);
818 if (err)
2f5ff264 819 goto err_bfreg;
9e9c47d0 820 } else {
19098df2 821 ubuffer->umem = NULL;
e126ba97 822 }
e126ba97 823
09a7d9ec
SM		 824 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
825 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
e126ba97
EC		 826 *in = mlx5_vzalloc(*inlen);
827 if (!*in) {
828 err = -ENOMEM;
829 goto err_umem;
830 }
09a7d9ec
SM		 831
832 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 833 if (ubuffer->umem)
09a7d9ec
SM		 834 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
835
836 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
837
838 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
839 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 840
09a7d9ec 841 MLX5_SET(qpc, qpc, uar_page, uar_index);
b037c29a 842 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
2f5ff264 843 qp->bfregn = bfregn;
e126ba97
EC		 844
845 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
846 if (err) {
847 mlx5_ib_dbg(dev, "map failed\n");
848 goto err_free;
849 }
850
851 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
852 if (err) {
853 mlx5_ib_dbg(dev, "copy failed\n");
854 goto err_unmap;
855 }
856 qp->create_type = MLX5_QP_USER;
857
858 return 0;
859
860err_unmap:
861 mlx5_ib_db_unmap_user(context, &qp->db);
862
863err_free:
479163f4 864 kvfree(*in);
e126ba97
EC		 865
866err_umem:
19098df2 867 if (ubuffer->umem)
868 ib_umem_release(ubuffer->umem);
e126ba97 869
2f5ff264 870err_bfreg:
b037c29a 871 free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 872 return err;
873}
874
b037c29a
EC		 875static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
876 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 877{
878 struct mlx5_ib_ucontext *context;
879
880 context = to_mucontext(pd->uobject->context);
881 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 882 if (base->ubuffer.umem)
883 ib_umem_release(base->ubuffer.umem);
b037c29a 884 free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 885}
886
887static int create_kernel_qp(struct mlx5_ib_dev *dev,
888 struct ib_qp_init_attr *init_attr,
889 struct mlx5_ib_qp *qp,
09a7d9ec 890 u32 **in, int *inlen,
19098df2 891 struct mlx5_ib_qp_base *base)
e126ba97 892{
e126ba97 893 int uar_index;
09a7d9ec 894 void *qpc;
e126ba97
EC		 895 int err;
896
f0313965
ES		 897 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
898 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c
HE		 899 IB_QP_CREATE_IPOIB_UD_LSO |
900 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 901 return -EINVAL;
e126ba97
EC		 902
903 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 904 qp->bf.bfreg = &dev->fp_bfreg;
905 else
906 qp->bf.bfreg = &dev->bfreg;
e126ba97 907
5fe9dec0
EC		 908 qp->bf.buf_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
909 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 910
911 err = calc_sq_size(dev, init_attr, qp);
912 if (err < 0) {
913 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 914 return err;
e126ba97
EC		 915 }
916
917 qp->rq.offset = 0;
918 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 919 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 920
19098df2 921 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 922 if (err) {
923 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 924 return err;
e126ba97
EC		 925 }
926
927 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 928 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
929 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
e126ba97
EC		 930 *in = mlx5_vzalloc(*inlen);
931 if (!*in) {
932 err = -ENOMEM;
933 goto err_buf;
934 }
09a7d9ec
SM		 935
936 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
937 MLX5_SET(qpc, qpc, uar_page, uar_index);
938 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
939
e126ba97 940 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 941 MLX5_SET(qpc, qpc, fre, 1);
942 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 943
b11a4f9c 944 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 945 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 946 qp->flags |= MLX5_IB_QP_SQPN_QP1;
947 }
948
09a7d9ec
SM		 949 mlx5_fill_page_array(&qp->buf,
950 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 951
9603b61d 952 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 953 if (err) {
954 mlx5_ib_dbg(dev, "err %d\n", err);
955 goto err_free;
956 }
957
e126ba97
EC		 958 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
959 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
960 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
961 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
962 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
963
964 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
965 !qp->sq.w_list || !qp->sq.wqe_head) {
966 err = -ENOMEM;
967 goto err_wrid;
968 }
969 qp->create_type = MLX5_QP_KERNEL;
970
971 return 0;
972
973err_wrid:
e126ba97
EC		 974 kfree(qp->sq.wqe_head);
975 kfree(qp->sq.w_list);
976 kfree(qp->sq.wrid);
977 kfree(qp->sq.wr_data);
978 kfree(qp->rq.wrid);
f4044dac 979 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 980
981err_free:
479163f4 982 kvfree(*in);
e126ba97
EC		 983
984err_buf:
9603b61d 985 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 986 return err;
987}
988
989static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
990{
e126ba97
EC		 991 kfree(qp->sq.wqe_head);
992 kfree(qp->sq.w_list);
993 kfree(qp->sq.wrid);
994 kfree(qp->sq.wr_data);
995 kfree(qp->rq.wrid);
f4044dac 996 mlx5_db_free(dev->mdev, &qp->db);
9603b61d 997 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 998}
999
09a7d9ec 1000static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1001{
1002 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1003 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1004 return MLX5_SRQ_RQ;
e126ba97 1005 else if (!qp->has_rq)
09a7d9ec 1006 return MLX5_ZERO_LEN_RQ;
e126ba97 1007 else
09a7d9ec 1008 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1009}
1010
1011static int is_connected(enum ib_qp_type qp_type)
1012{
1013 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1014 return 1;
1015
1016 return 0;
1017}
1018
0fb2ed66 1019static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1020 struct mlx5_ib_sq *sq, u32 tdn)
1021{
c4f287c4 1022 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1023 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1024
0fb2ed66 1025 MLX5_SET(tisc, tisc, transport_domain, tdn);
0fb2ed66 1026 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1027}
1028
1029static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1030 struct mlx5_ib_sq *sq)
1031{
1032 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1033}
1034
1035static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1036 struct mlx5_ib_sq *sq, void *qpin,
1037 struct ib_pd *pd)
1038{
1039 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1040 __be64 *pas;
1041 void *in;
1042 void *sqc;
1043 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1044 void *wq;
1045 int inlen;
1046 int err;
1047 int page_shift = 0;
1048 int npages;
1049 int ncont = 0;
1050 u32 offset = 0;
1051
1052 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1053 &sq->ubuffer.umem, &npages, &page_shift,
1054 &ncont, &offset);
1055 if (err)
1056 return err;
1057
1058 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1059 in = mlx5_vzalloc(inlen);
1060 if (!in) {
1061 err = -ENOMEM;
1062 goto err_umem;
1063 }
1064
1065 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1066 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1067 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1068 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1069 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1070 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1071 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1072
1073 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1074 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1075 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1076 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1077 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1078 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1079 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1080 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1081 MLX5_SET(wq, wq, page_offset, offset);
1082
1083 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1084 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1085
1086 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1087
1088 kvfree(in);
1089
1090 if (err)
1091 goto err_umem;
1092
1093 return 0;
1094
1095err_umem:
1096 ib_umem_release(sq->ubuffer.umem);
1097 sq->ubuffer.umem = NULL;
1098
1099 return err;
1100}
1101
1102static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1103 struct mlx5_ib_sq *sq)
1104{
1105 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1106 ib_umem_release(sq->ubuffer.umem);
1107}
1108
1109static int get_rq_pas_size(void *qpc)
1110{
1111 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1112 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1113 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1114 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1115 u32 po_quanta = 1 << (log_page_size - 6);
1116 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1117 u32 page_size = 1 << log_page_size;
1118 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1119 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1120
1121 return rq_num_pas * sizeof(u64);
1122}
1123
1124static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1125 struct mlx5_ib_rq *rq, void *qpin)
1126{
358e42ea 1127 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1128 __be64 *pas;
1129 __be64 *qp_pas;
1130 void *in;
1131 void *rqc;
1132 void *wq;
1133 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1134 int inlen;
1135 int err;
1136 u32 rq_pas_size = get_rq_pas_size(qpc);
1137
1138 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1139 in = mlx5_vzalloc(inlen);
1140 if (!in)
1141 return -ENOMEM;
1142
1143 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1144 MLX5_SET(rqc, rqc, vsd, 1);
1145 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1146 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1147 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1148 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1149 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1150
358e42ea
MD		 1151 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1152 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1153
0fb2ed66 1154 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1155 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1156 MLX5_SET(wq, wq, end_padding_mode,
01581fb8 1157 MLX5_GET(qpc, qpc, end_padding_mode));
0fb2ed66 1158 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1159 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1160 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1161 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1162 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1163 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1164
1165 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1166 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1167 memcpy(pas, qp_pas, rq_pas_size);
1168
1169 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1170
1171 kvfree(in);
1172
1173 return err;
1174}
1175
1176static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1177 struct mlx5_ib_rq *rq)
1178{
1179 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1180}
1181
1182static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1183 struct mlx5_ib_rq *rq, u32 tdn)
1184{
1185 u32 *in;
1186 void *tirc;
1187 int inlen;
1188 int err;
1189
1190 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1191 in = mlx5_vzalloc(inlen);
1192 if (!in)
1193 return -ENOMEM;
1194
1195 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1196 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1197 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1198 MLX5_SET(tirc, tirc, transport_domain, tdn);
1199
1200 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1201
1202 kvfree(in);
1203
1204 return err;
1205}
1206
1207static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1208 struct mlx5_ib_rq *rq)
1209{
1210 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1211}
1212
1213static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
09a7d9ec 1214 u32 *in,
0fb2ed66 1215 struct ib_pd *pd)
1216{
1217 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1218 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1219 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1220 struct ib_uobject *uobj = pd->uobject;
1221 struct ib_ucontext *ucontext = uobj->context;
1222 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1223 int err;
1224 u32 tdn = mucontext->tdn;
1225
1226 if (qp->sq.wqe_cnt) {
1227 err = create_raw_packet_qp_tis(dev, sq, tdn);
1228 if (err)
1229 return err;
1230
1231 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1232 if (err)
1233 goto err_destroy_tis;
1234
1235 sq->base.container_mibqp = qp;
1236 }
1237
1238 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1239 rq->base.container_mibqp = qp;
1240
0fb2ed66 1241 err = create_raw_packet_qp_rq(dev, rq, in);
1242 if (err)
1243 goto err_destroy_sq;
1244
0fb2ed66 1245
1246 err = create_raw_packet_qp_tir(dev, rq, tdn);
1247 if (err)
1248 goto err_destroy_rq;
1249 }
1250
1251 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1252 rq->base.mqp.qpn;
1253
1254 return 0;
1255
1256err_destroy_rq:
1257 destroy_raw_packet_qp_rq(dev, rq);
1258err_destroy_sq:
1259 if (!qp->sq.wqe_cnt)
1260 return err;
1261 destroy_raw_packet_qp_sq(dev, sq);
1262err_destroy_tis:
1263 destroy_raw_packet_qp_tis(dev, sq);
1264
1265 return err;
1266}
1267
1268static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1269 struct mlx5_ib_qp *qp)
1270{
1271 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1272 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1273 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1274
1275 if (qp->rq.wqe_cnt) {
1276 destroy_raw_packet_qp_tir(dev, rq);
1277 destroy_raw_packet_qp_rq(dev, rq);
1278 }
1279
1280 if (qp->sq.wqe_cnt) {
1281 destroy_raw_packet_qp_sq(dev, sq);
1282 destroy_raw_packet_qp_tis(dev, sq);
1283 }
1284}
1285
1286static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1287 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1288{
1289 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1290 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1291
1292 sq->sq = &qp->sq;
1293 rq->rq = &qp->rq;
1294 sq->doorbell = &qp->db;
1295 rq->doorbell = &qp->db;
1296}
1297
28d61370
YH		 1298static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1299{
1300 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1301}
1302
1303static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1304 struct ib_pd *pd,
1305 struct ib_qp_init_attr *init_attr,
1306 struct ib_udata *udata)
1307{
1308 struct ib_uobject *uobj = pd->uobject;
1309 struct ib_ucontext *ucontext = uobj->context;
1310 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1311 struct mlx5_ib_create_qp_resp resp = {};
1312 int inlen;
1313 int err;
1314 u32 *in;
1315 void *tirc;
1316 void *hfso;
1317 u32 selected_fields = 0;
1318 size_t min_resp_len;
1319 u32 tdn = mucontext->tdn;
1320 struct mlx5_ib_create_qp_rss ucmd = {};
1321 size_t required_cmd_sz;
1322
1323 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1324 return -EOPNOTSUPP;
1325
1326 if (init_attr->create_flags || init_attr->send_cq)
1327 return -EINVAL;
1328
2f5ff264 1329 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1330 if (udata->outlen < min_resp_len)
1331 return -EINVAL;
1332
1333 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1334 if (udata->inlen < required_cmd_sz) {
1335 mlx5_ib_dbg(dev, "invalid inlen\n");
1336 return -EINVAL;
1337 }
1338
1339 if (udata->inlen > sizeof(ucmd) &&
1340 !ib_is_udata_cleared(udata, sizeof(ucmd),
1341 udata->inlen - sizeof(ucmd))) {
1342 mlx5_ib_dbg(dev, "inlen is not supported\n");
1343 return -EOPNOTSUPP;
1344 }
1345
1346 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1347 mlx5_ib_dbg(dev, "copy failed\n");
1348 return -EFAULT;
1349 }
1350
1351 if (ucmd.comp_mask) {
1352 mlx5_ib_dbg(dev, "invalid comp mask\n");
1353 return -EOPNOTSUPP;
1354 }
1355
1356 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1357 mlx5_ib_dbg(dev, "invalid reserved\n");
1358 return -EOPNOTSUPP;
1359 }
1360
1361 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1362 if (err) {
1363 mlx5_ib_dbg(dev, "copy failed\n");
1364 return -EINVAL;
1365 }
1366
1367 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1368 in = mlx5_vzalloc(inlen);
1369 if (!in)
1370 return -ENOMEM;
1371
1372 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1373 MLX5_SET(tirc, tirc, disp_type,
1374 MLX5_TIRC_DISP_TYPE_INDIRECT);
1375 MLX5_SET(tirc, tirc, indirect_table,
1376 init_attr->rwq_ind_tbl->ind_tbl_num);
1377 MLX5_SET(tirc, tirc, transport_domain, tdn);
1378
1379 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1380 switch (ucmd.rx_hash_function) {
1381 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1382 {
1383 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1384 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1385
1386 if (len != ucmd.rx_key_len) {
1387 err = -EINVAL;
1388 goto err;
1389 }
1390
1391 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1392 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1393 memcpy(rss_key, ucmd.rx_hash_key, len);
1394 break;
1395 }
1396 default:
1397 err = -EOPNOTSUPP;
1398 goto err;
1399 }
1400
1401 if (!ucmd.rx_hash_fields_mask) {
1402 /* special case when this TIR serves as steering entry without hashing */
1403 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1404 goto create_tir;
1405 err = -EINVAL;
1406 goto err;
1407 }
1408
1409 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1410 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1411 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1412 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1413 err = -EINVAL;
1414 goto err;
1415 }
1416
1417 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1418 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1419 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1420 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1421 MLX5_L3_PROT_TYPE_IPV4);
1422 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1423 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1424 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1425 MLX5_L3_PROT_TYPE_IPV6);
1426
1427 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1428 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1429 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1430 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1431 err = -EINVAL;
1432 goto err;
1433 }
1434
1435 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1436 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1437 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1438 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1439 MLX5_L4_PROT_TYPE_TCP);
1440 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1441 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1442 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1443 MLX5_L4_PROT_TYPE_UDP);
1444
1445 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1446 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1447 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1448
1449 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1450 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1451 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1452
1453 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1454 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1455 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1456
1457 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1458 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1459 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1460
1461 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1462
1463create_tir:
1464 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1465
1466 if (err)
1467 goto err;
1468
1469 kvfree(in);
1470 /* qpn is reserved for that QP */
1471 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1472 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1473 return 0;
1474
1475err:
1476 kvfree(in);
1477 return err;
1478}
1479
e126ba97
EC		 1480static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1481 struct ib_qp_init_attr *init_attr,
1482 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1483{
1484 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1485 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1486 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1487 struct mlx5_ib_create_qp_resp resp;
89ea94a7
MG		 1488 struct mlx5_ib_cq *send_cq;
1489 struct mlx5_ib_cq *recv_cq;
1490 unsigned long flags;
cfb5e088 1491 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1492 struct mlx5_ib_create_qp ucmd;
1493 struct mlx5_ib_qp_base *base;
cfb5e088 1494 void *qpc;
09a7d9ec
SM		 1495 u32 *in;
1496 int err;
e126ba97 1497
0fb2ed66 1498 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1499 &qp->raw_packet_qp.rq.base :
1500 &qp->trans_qp.base;
1501
e126ba97
EC		 1502 mutex_init(&qp->mutex);
1503 spin_lock_init(&qp->sq.lock);
1504 spin_lock_init(&qp->rq.lock);
1505
28d61370
YH		 1506 if (init_attr->rwq_ind_tbl) {
1507 if (!udata)
1508 return -ENOSYS;
1509
1510 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1511 return err;
1512 }
1513
f360d88a 1514 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1515 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1516 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1517 return -EINVAL;
1518 } else {
1519 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1520 }
1521 }
1522
051f2630
LR		 1523 if (init_attr->create_flags &
1524 (IB_QP_CREATE_CROSS_CHANNEL |
1525 IB_QP_CREATE_MANAGED_SEND |
1526 IB_QP_CREATE_MANAGED_RECV)) {
1527 if (!MLX5_CAP_GEN(mdev, cd)) {
1528 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1529 return -EINVAL;
1530 }
1531 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1532 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1533 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1534 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1535 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1536 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1537 }
f0313965
ES		 1538
1539 if (init_attr->qp_type == IB_QPT_UD &&
1540 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1541 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1542 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1543 return -EOPNOTSUPP;
1544 }
1545
358e42ea
MD		 1546 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1547 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1548 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1549 return -EOPNOTSUPP;
1550 }
1551 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1552 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1553 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1554 return -EOPNOTSUPP;
1555 }
1556 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1557 }
1558
e126ba97
EC		 1559 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1560 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1561
1562 if (pd && pd->uobject) {
1563 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1564 mlx5_ib_dbg(dev, "copy failed\n");
1565 return -EFAULT;
1566 }
1567
cfb5e088
HA		 1568 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1569 &ucmd, udata->inlen, &uidx);
1570 if (err)
1571 return err;
1572
e126ba97
EC		 1573 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1574 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1575 } else {
1576 qp->wq_sig = !!wq_signature;
1577 }
1578
1579 qp->has_rq = qp_has_rq(init_attr);
1580 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1581 qp, (pd && pd->uobject) ? &ucmd : NULL);
1582 if (err) {
1583 mlx5_ib_dbg(dev, "err %d\n", err);
1584 return err;
1585 }
1586
1587 if (pd) {
1588 if (pd->uobject) {
938fe83c
SM		 1589 __u32 max_wqes =
1590 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1591 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1592 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1593 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1594 mlx5_ib_dbg(dev, "invalid rq params\n");
1595 return -EINVAL;
1596 }
938fe83c 1597 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1598 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1599 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1600 return -EINVAL;
1601 }
b11a4f9c
HE		 1602 if (init_attr->create_flags &
1603 mlx5_ib_create_qp_sqpn_qp1()) {
1604 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1605 return -EINVAL;
1606 }
0fb2ed66 1607 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1608 &resp, &inlen, base);
e126ba97
EC		 1609 if (err)
1610 mlx5_ib_dbg(dev, "err %d\n", err);
1611 } else {
19098df2 1612 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1613 base);
e126ba97
EC		 1614 if (err)
1615 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1616 }
1617
1618 if (err)
1619 return err;
1620 } else {
09a7d9ec 1621 in = mlx5_vzalloc(inlen);
e126ba97
EC		 1622 if (!in)
1623 return -ENOMEM;
1624
1625 qp->create_type = MLX5_QP_EMPTY;
1626 }
1627
1628 if (is_sqp(init_attr->qp_type))
1629 qp->port = init_attr->port_num;
1630
09a7d9ec
SM		 1631 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1632
1633 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1634 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1635
1636 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1637 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1638 else
09a7d9ec
SM		 1639 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1640
e126ba97
EC		 1641
1642 if (qp->wq_sig)
09a7d9ec 1643 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1644
f360d88a 1645 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1646 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1647
051f2630 1648 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1649 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1650 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1651 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1652 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1653 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1654
e126ba97
EC		 1655 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1656 int rcqe_sz;
1657 int scqe_sz;
1658
1659 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1660 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1661
1662 if (rcqe_sz == 128)
09a7d9ec 1663 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1664 else
09a7d9ec 1665 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1666
1667 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1668 if (scqe_sz == 128)
09a7d9ec 1669 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1670 else
09a7d9ec 1671 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1672 }
1673 }
1674
1675 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1676 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1677 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1678 }
1679
09a7d9ec 1680 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97
EC		 1681
1682 if (qp->sq.wqe_cnt)
09a7d9ec 1683 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
e126ba97 1684 else
09a7d9ec 1685 MLX5_SET(qpc, qpc, no_sq, 1);
e126ba97
EC		 1686
1687 /* Set default resources */
1688 switch (init_attr->qp_type) {
1689 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1690 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1691 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1692 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1693 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1694 break;
1695 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1696 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1697 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1698 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1699 break;
1700 default:
1701 if (init_attr->srq) {
09a7d9ec
SM		 1702 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1703 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1704 } else {
09a7d9ec
SM		 1705 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1706 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1707 }
1708 }
1709
1710 if (init_attr->send_cq)
09a7d9ec 1711 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1712
1713 if (init_attr->recv_cq)
09a7d9ec 1714 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1715
09a7d9ec 1716 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1717
09a7d9ec
SM		 1718 /* 0xffffff means we ask to work with cqe version 0 */
1719 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1720 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1721
f0313965
ES		 1722 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1723 if (init_attr->qp_type == IB_QPT_UD &&
1724 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1725 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1726 qp->flags |= MLX5_IB_QP_LSO;
1727 }
cfb5e088 1728
0fb2ed66 1729 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1730 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1731 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1732 err = create_raw_packet_qp(dev, qp, in, pd);
1733 } else {
1734 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1735 }
1736
e126ba97
EC		 1737 if (err) {
1738 mlx5_ib_dbg(dev, "create qp failed\n");
1739 goto err_create;
1740 }
1741
479163f4 1742 kvfree(in);
e126ba97 1743
19098df2 1744 base->container_mibqp = qp;
1745 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1746
89ea94a7
MG		 1747 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1748 &send_cq, &recv_cq);
1749 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1750 mlx5_ib_lock_cqs(send_cq, recv_cq);
1751 /* Maintain device to QPs access, needed for further handling via reset
1752 * flow
1753 */
1754 list_add_tail(&qp->qps_list, &dev->qp_list);
1755 /* Maintain CQ to QPs access, needed for further handling via reset flow
1756 */
1757 if (send_cq)
1758 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1759 if (recv_cq)
1760 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1761 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1762 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1763
e126ba97
EC		 1764 return 0;
1765
1766err_create:
1767 if (qp->create_type == MLX5_QP_USER)
b037c29a 1768 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 1769 else if (qp->create_type == MLX5_QP_KERNEL)
1770 destroy_qp_kernel(dev, qp);
1771
479163f4 1772 kvfree(in);
e126ba97
EC		 1773 return err;
1774}
1775
1776static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1777 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1778{
1779 if (send_cq) {
1780 if (recv_cq) {
1781 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1782 spin_lock(&send_cq->lock);
e126ba97
EC		 1783 spin_lock_nested(&recv_cq->lock,
1784 SINGLE_DEPTH_NESTING);
1785 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1786 spin_lock(&send_cq->lock);
e126ba97
EC		 1787 __acquire(&recv_cq->lock);
1788 } else {
89ea94a7 1789 spin_lock(&recv_cq->lock);
e126ba97
EC		 1790 spin_lock_nested(&send_cq->lock,
1791 SINGLE_DEPTH_NESTING);
1792 }
1793 } else {
89ea94a7 1794 spin_lock(&send_cq->lock);
6a4f139a 1795 __acquire(&recv_cq->lock);
e126ba97
EC		 1796 }
1797 } else if (recv_cq) {
89ea94a7 1798 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1799 __acquire(&send_cq->lock);
1800 } else {
1801 __acquire(&send_cq->lock);
1802 __acquire(&recv_cq->lock);
e126ba97
EC		 1803 }
1804}
1805
1806static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1807 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1808{
1809 if (send_cq) {
1810 if (recv_cq) {
1811 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1812 spin_unlock(&recv_cq->lock);
89ea94a7 1813 spin_unlock(&send_cq->lock);
e126ba97
EC		 1814 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1815 __release(&recv_cq->lock);
89ea94a7 1816 spin_unlock(&send_cq->lock);
e126ba97
EC		 1817 } else {
1818 spin_unlock(&send_cq->lock);
89ea94a7 1819 spin_unlock(&recv_cq->lock);
e126ba97
EC		 1820 }
1821 } else {
6a4f139a 1822 __release(&recv_cq->lock);
89ea94a7 1823 spin_unlock(&send_cq->lock);
e126ba97
EC		 1824 }
1825 } else if (recv_cq) {
6a4f139a 1826 __release(&send_cq->lock);
89ea94a7 1827 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 1828 } else {
1829 __release(&recv_cq->lock);
1830 __release(&send_cq->lock);
e126ba97
EC		 1831 }
1832}
1833
1834static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1835{
1836 return to_mpd(qp->ibqp.pd);
1837}
1838
89ea94a7
MG		 1839static void get_cqs(enum ib_qp_type qp_type,
1840 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 1841 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1842{
89ea94a7 1843 switch (qp_type) {
e126ba97
EC		 1844 case IB_QPT_XRC_TGT:
1845 *send_cq = NULL;
1846 *recv_cq = NULL;
1847 break;
1848 case MLX5_IB_QPT_REG_UMR:
1849 case IB_QPT_XRC_INI:
89ea94a7 1850 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 1851 *recv_cq = NULL;
1852 break;
1853
1854 case IB_QPT_SMI:
d16e91da 1855 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 1856 case IB_QPT_RC:
1857 case IB_QPT_UC:
1858 case IB_QPT_UD:
1859 case IB_QPT_RAW_IPV6:
1860 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 1861 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 1862 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1863 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 1864 break;
1865
e126ba97
EC		 1866 case IB_QPT_MAX:
1867 default:
1868 *send_cq = NULL;
1869 *recv_cq = NULL;
1870 break;
1871 }
1872}
1873
ad5f8e96 1874static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 1875 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1876 u8 lag_tx_affinity);
ad5f8e96 1877
e126ba97
EC		 1878static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1879{
1880 struct mlx5_ib_cq *send_cq, *recv_cq;
19098df2 1881 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
89ea94a7 1882 unsigned long flags;
e126ba97
EC		 1883 int err;
1884
28d61370
YH		 1885 if (qp->ibqp.rwq_ind_tbl) {
1886 destroy_rss_raw_qp_tir(dev, qp);
1887 return;
1888 }
1889
0fb2ed66 1890 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1891 &qp->raw_packet_qp.rq.base :
1892 &qp->trans_qp.base;
1893
6aec21f6 1894 if (qp->state != IB_QPS_RESET) {
ad5f8e96 1895 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
ad5f8e96 1896 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 1897 MLX5_CMD_OP_2RST_QP, 0,
1898 NULL, &base->mqp);
ad5f8e96 1899 } else {
0680efa2
AV		 1900 struct mlx5_modify_raw_qp_param raw_qp_param = {
1901 .operation = MLX5_CMD_OP_2RST_QP
1902 };
1903
13eab21f 1904 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 1905 }
1906 if (err)
427c1e7b 1907 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 1908 base->mqp.qpn);
6aec21f6 1909 }
e126ba97 1910
89ea94a7
MG		 1911 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1912 &send_cq, &recv_cq);
1913
1914 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1915 mlx5_ib_lock_cqs(send_cq, recv_cq);
1916 /* del from lists under both locks above to protect reset flow paths */
1917 list_del(&qp->qps_list);
1918 if (send_cq)
1919 list_del(&qp->cq_send_list);
1920
1921 if (recv_cq)
1922 list_del(&qp->cq_recv_list);
e126ba97
EC		 1923
1924 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 1925 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 1926 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1927 if (send_cq != recv_cq)
19098df2 1928 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1929 NULL);
e126ba97 1930 }
89ea94a7
MG		 1931 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1932 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 1933
0fb2ed66 1934 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1935 destroy_raw_packet_qp(dev, qp);
1936 } else {
1937 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1938 if (err)
1939 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1940 base->mqp.qpn);
1941 }
e126ba97 1942
e126ba97
EC		 1943 if (qp->create_type == MLX5_QP_KERNEL)
1944 destroy_qp_kernel(dev, qp);
1945 else if (qp->create_type == MLX5_QP_USER)
b037c29a 1946 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 1947}
1948
1949static const char *ib_qp_type_str(enum ib_qp_type type)
1950{
1951 switch (type) {
1952 case IB_QPT_SMI:
1953 return "IB_QPT_SMI";
1954 case IB_QPT_GSI:
1955 return "IB_QPT_GSI";
1956 case IB_QPT_RC:
1957 return "IB_QPT_RC";
1958 case IB_QPT_UC:
1959 return "IB_QPT_UC";
1960 case IB_QPT_UD:
1961 return "IB_QPT_UD";
1962 case IB_QPT_RAW_IPV6:
1963 return "IB_QPT_RAW_IPV6";
1964 case IB_QPT_RAW_ETHERTYPE:
1965 return "IB_QPT_RAW_ETHERTYPE";
1966 case IB_QPT_XRC_INI:
1967 return "IB_QPT_XRC_INI";
1968 case IB_QPT_XRC_TGT:
1969 return "IB_QPT_XRC_TGT";
1970 case IB_QPT_RAW_PACKET:
1971 return "IB_QPT_RAW_PACKET";
1972 case MLX5_IB_QPT_REG_UMR:
1973 return "MLX5_IB_QPT_REG_UMR";
1974 case IB_QPT_MAX:
1975 default:
1976 return "Invalid QP type";
1977 }
1978}
1979
1980struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1981 struct ib_qp_init_attr *init_attr,
1982 struct ib_udata *udata)
1983{
1984 struct mlx5_ib_dev *dev;
1985 struct mlx5_ib_qp *qp;
1986 u16 xrcdn = 0;
1987 int err;
1988
1989 if (pd) {
1990 dev = to_mdev(pd->device);
0fb2ed66 1991
1992 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1993 if (!pd->uobject) {
1994 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1995 return ERR_PTR(-EINVAL);
1996 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1997 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1998 return ERR_PTR(-EINVAL);
1999 }
2000 }
09f16cf5
MD		 2001 } else {
2002 /* being cautious here */
2003 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2004 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2005 pr_warn("%s: no PD for transport %s\n", __func__,
2006 ib_qp_type_str(init_attr->qp_type));
2007 return ERR_PTR(-EINVAL);
2008 }
2009 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2010 }
2011
2012 switch (init_attr->qp_type) {
2013 case IB_QPT_XRC_TGT:
2014 case IB_QPT_XRC_INI:
938fe83c 2015 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2016 mlx5_ib_dbg(dev, "XRC not supported\n");
2017 return ERR_PTR(-ENOSYS);
2018 }
2019 init_attr->recv_cq = NULL;
2020 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2021 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2022 init_attr->send_cq = NULL;
2023 }
2024
2025 /* fall through */
0fb2ed66 2026 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2027 case IB_QPT_RC:
2028 case IB_QPT_UC:
2029 case IB_QPT_UD:
2030 case IB_QPT_SMI:
d16e91da 2031 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2032 case MLX5_IB_QPT_REG_UMR:
2033 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2034 if (!qp)
2035 return ERR_PTR(-ENOMEM);
2036
2037 err = create_qp_common(dev, pd, init_attr, udata, qp);
2038 if (err) {
2039 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2040 kfree(qp);
2041 return ERR_PTR(err);
2042 }
2043
2044 if (is_qp0(init_attr->qp_type))
2045 qp->ibqp.qp_num = 0;
2046 else if (is_qp1(init_attr->qp_type))
2047 qp->ibqp.qp_num = 1;
2048 else
19098df2 2049 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2050
2051 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2052 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2053 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2054 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2055
19098df2 2056 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2057
2058 break;
2059
d16e91da
HE		 2060 case IB_QPT_GSI:
2061 return mlx5_ib_gsi_create_qp(pd, init_attr);
2062
e126ba97
EC		 2063 case IB_QPT_RAW_IPV6:
2064 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2065 case IB_QPT_MAX:
2066 default:
2067 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2068 init_attr->qp_type);
2069 /* Don't support raw QPs */
2070 return ERR_PTR(-EINVAL);
2071 }
2072
2073 return &qp->ibqp;
2074}
2075
2076int mlx5_ib_destroy_qp(struct ib_qp *qp)
2077{
2078 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2079 struct mlx5_ib_qp *mqp = to_mqp(qp);
2080
d16e91da
HE		 2081 if (unlikely(qp->qp_type == IB_QPT_GSI))
2082 return mlx5_ib_gsi_destroy_qp(qp);
2083
e126ba97
EC		 2084 destroy_qp_common(dev, mqp);
2085
2086 kfree(mqp);
2087
2088 return 0;
2089}
2090
2091static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2092 int attr_mask)
2093{
2094 u32 hw_access_flags = 0;
2095 u8 dest_rd_atomic;
2096 u32 access_flags;
2097
2098 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2099 dest_rd_atomic = attr->max_dest_rd_atomic;
2100 else
19098df2 2101 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2102
2103 if (attr_mask & IB_QP_ACCESS_FLAGS)
2104 access_flags = attr->qp_access_flags;
2105 else
19098df2 2106 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2107
2108 if (!dest_rd_atomic)
2109 access_flags &= IB_ACCESS_REMOTE_WRITE;
2110
2111 if (access_flags & IB_ACCESS_REMOTE_READ)
2112 hw_access_flags |= MLX5_QP_BIT_RRE;
2113 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2114 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2115 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2116 hw_access_flags |= MLX5_QP_BIT_RWE;
2117
2118 return cpu_to_be32(hw_access_flags);
2119}
2120
2121enum {
2122 MLX5_PATH_FLAG_FL = 1 << 0,
2123 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2124 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2125};
2126
2127static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2128{
2129 if (rate == IB_RATE_PORT_CURRENT) {
2130 return 0;
2131 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2132 return -EINVAL;
2133 } else {
2134 while (rate != IB_RATE_2_5_GBPS &&
2135 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2136 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2137 --rate;
2138 }
2139
2140 return rate + MLX5_STAT_RATE_OFFSET;
2141}
2142
75850d0b 2143static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2144 struct mlx5_ib_sq *sq, u8 sl)
2145{
2146 void *in;
2147 void *tisc;
2148 int inlen;
2149 int err;
2150
2151 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2152 in = mlx5_vzalloc(inlen);
2153 if (!in)
2154 return -ENOMEM;
2155
2156 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2157
2158 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2159 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2160
2161 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2162
2163 kvfree(in);
2164
2165 return err;
2166}
2167
13eab21f
AH		 2168static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2169 struct mlx5_ib_sq *sq, u8 tx_affinity)
2170{
2171 void *in;
2172 void *tisc;
2173 int inlen;
2174 int err;
2175
2176 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2177 in = mlx5_vzalloc(inlen);
2178 if (!in)
2179 return -ENOMEM;
2180
2181 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2182
2183 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2184 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2185
2186 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2187
2188 kvfree(in);
2189
2190 return err;
2191}
2192
75850d0b 2193static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2194 const struct ib_ah_attr *ah,
e126ba97 2195 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2196 u32 path_flags, const struct ib_qp_attr *attr,
2197 bool alt)
e126ba97 2198{
2811ba51 2199 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
e126ba97 2200 int err;
ed88451e 2201 enum ib_gid_type gid_type;
e126ba97 2202
e126ba97 2203 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2204 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2205 attr->pkey_index);
e126ba97 2206
e126ba97 2207 if (ah->ah_flags & IB_AH_GRH) {
938fe83c
SM		 2208 if (ah->grh.sgid_index >=
2209 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2210 pr_err("sgid_index (%u) too large. max is %d\n",
938fe83c
SM		 2211 ah->grh.sgid_index,
2212 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2213 return -EINVAL;
2214 }
2811ba51
AS		 2215 }
2216
2217 if (ll == IB_LINK_LAYER_ETHERNET) {
2218 if (!(ah->ah_flags & IB_AH_GRH))
2219 return -EINVAL;
ed88451e
MD		 2220 err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index,
2221 &gid_type);
2222 if (err)
2223 return err;
2811ba51
AS		 2224 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2225 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2226 ah->grh.sgid_index);
2227 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
ed88451e
MD		 2228 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2229 path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f;
2811ba51 2230 } else {
d3ae2bde
NO		 2231 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2232 path->fl_free_ar |=
2233 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2811ba51
AS		 2234 path->rlid = cpu_to_be16(ah->dlid);
2235 path->grh_mlid = ah->src_path_bits & 0x7f;
2236 if (ah->ah_flags & IB_AH_GRH)
2237 path->grh_mlid |= 1 << 7;
2238 path->dci_cfi_prio_sl = ah->sl & 0xf;
2239 }
2240
2241 if (ah->ah_flags & IB_AH_GRH) {
e126ba97
EC		 2242 path->mgid_index = ah->grh.sgid_index;
2243 path->hop_limit = ah->grh.hop_limit;
2244 path->tclass_flowlabel =
2245 cpu_to_be32((ah->grh.traffic_class << 20) |
2246 (ah->grh.flow_label));
2247 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2248 }
2249
2250 err = ib_rate_to_mlx5(dev, ah->static_rate);
2251 if (err < 0)
2252 return err;
2253 path->static_rate = err;
2254 path->port = port;
2255
e126ba97 2256 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2257 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2258
75850d0b 2259 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2260 return modify_raw_packet_eth_prio(dev->mdev,
2261 &qp->raw_packet_qp.sq,
2262 ah->sl & 0xf);
2263
e126ba97
EC		 2264 return 0;
2265}
2266
2267static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2268 [MLX5_QP_STATE_INIT] = {
2269 [MLX5_QP_STATE_INIT] = {
2270 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2271 MLX5_QP_OPTPAR_RAE |
2272 MLX5_QP_OPTPAR_RWE |
2273 MLX5_QP_OPTPAR_PKEY_INDEX |
2274 MLX5_QP_OPTPAR_PRI_PORT,
2275 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2276 MLX5_QP_OPTPAR_PKEY_INDEX |
2277 MLX5_QP_OPTPAR_PRI_PORT,
2278 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2279 MLX5_QP_OPTPAR_Q_KEY |
2280 MLX5_QP_OPTPAR_PRI_PORT,
2281 },
2282 [MLX5_QP_STATE_RTR] = {
2283 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2284 MLX5_QP_OPTPAR_RRE |
2285 MLX5_QP_OPTPAR_RAE |
2286 MLX5_QP_OPTPAR_RWE |
2287 MLX5_QP_OPTPAR_PKEY_INDEX,
2288 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2289 MLX5_QP_OPTPAR_RWE |
2290 MLX5_QP_OPTPAR_PKEY_INDEX,
2291 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2292 MLX5_QP_OPTPAR_Q_KEY,
2293 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2294 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2295 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2296 MLX5_QP_OPTPAR_RRE |
2297 MLX5_QP_OPTPAR_RAE |
2298 MLX5_QP_OPTPAR_RWE |
2299 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2300 },
2301 },
2302 [MLX5_QP_STATE_RTR] = {
2303 [MLX5_QP_STATE_RTS] = {
2304 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2305 MLX5_QP_OPTPAR_RRE |
2306 MLX5_QP_OPTPAR_RAE |
2307 MLX5_QP_OPTPAR_RWE |
2308 MLX5_QP_OPTPAR_PM_STATE |
2309 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2310 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2311 MLX5_QP_OPTPAR_RWE |
2312 MLX5_QP_OPTPAR_PM_STATE,
2313 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2314 },
2315 },
2316 [MLX5_QP_STATE_RTS] = {
2317 [MLX5_QP_STATE_RTS] = {
2318 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2319 MLX5_QP_OPTPAR_RAE |
2320 MLX5_QP_OPTPAR_RWE |
2321 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2322 MLX5_QP_OPTPAR_PM_STATE |
2323 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2324 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2325 MLX5_QP_OPTPAR_PM_STATE |
2326 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2327 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2328 MLX5_QP_OPTPAR_SRQN |
2329 MLX5_QP_OPTPAR_CQN_RCV,
2330 },
2331 },
2332 [MLX5_QP_STATE_SQER] = {
2333 [MLX5_QP_STATE_RTS] = {
2334 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2335 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2336 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2337 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2338 MLX5_QP_OPTPAR_RWE |
2339 MLX5_QP_OPTPAR_RAE |
2340 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2341 },
2342 },
2343};
2344
2345static int ib_nr_to_mlx5_nr(int ib_mask)
2346{
2347 switch (ib_mask) {
2348 case IB_QP_STATE:
2349 return 0;
2350 case IB_QP_CUR_STATE:
2351 return 0;
2352 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2353 return 0;
2354 case IB_QP_ACCESS_FLAGS:
2355 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2356 MLX5_QP_OPTPAR_RAE;
2357 case IB_QP_PKEY_INDEX:
2358 return MLX5_QP_OPTPAR_PKEY_INDEX;
2359 case IB_QP_PORT:
2360 return MLX5_QP_OPTPAR_PRI_PORT;
2361 case IB_QP_QKEY:
2362 return MLX5_QP_OPTPAR_Q_KEY;
2363 case IB_QP_AV:
2364 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2365 MLX5_QP_OPTPAR_PRI_PORT;
2366 case IB_QP_PATH_MTU:
2367 return 0;
2368 case IB_QP_TIMEOUT:
2369 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2370 case IB_QP_RETRY_CNT:
2371 return MLX5_QP_OPTPAR_RETRY_COUNT;
2372 case IB_QP_RNR_RETRY:
2373 return MLX5_QP_OPTPAR_RNR_RETRY;
2374 case IB_QP_RQ_PSN:
2375 return 0;
2376 case IB_QP_MAX_QP_RD_ATOMIC:
2377 return MLX5_QP_OPTPAR_SRA_MAX;
2378 case IB_QP_ALT_PATH:
2379 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2380 case IB_QP_MIN_RNR_TIMER:
2381 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2382 case IB_QP_SQ_PSN:
2383 return 0;
2384 case IB_QP_MAX_DEST_RD_ATOMIC:
2385 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2386 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2387 case IB_QP_PATH_MIG_STATE:
2388 return MLX5_QP_OPTPAR_PM_STATE;
2389 case IB_QP_CAP:
2390 return 0;
2391 case IB_QP_DEST_QPN:
2392 return 0;
2393 }
2394 return 0;
2395}
2396
2397static int ib_mask_to_mlx5_opt(int ib_mask)
2398{
2399 int result = 0;
2400 int i;
2401
2402 for (i = 0; i < 8 * sizeof(int); i++) {
2403 if ((1 << i) & ib_mask)
2404 result |= ib_nr_to_mlx5_nr(1 << i);
2405 }
2406
2407 return result;
2408}
2409
eb49ab0c
AV		 2410static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2411 struct mlx5_ib_rq *rq, int new_state,
2412 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2413{
2414 void *in;
2415 void *rqc;
2416 int inlen;
2417 int err;
2418
2419 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2420 in = mlx5_vzalloc(inlen);
2421 if (!in)
2422 return -ENOMEM;
2423
2424 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2425
2426 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2427 MLX5_SET(rqc, rqc, state, new_state);
2428
eb49ab0c
AV		 2429 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2430 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2431 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 2432 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 2433 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2434 } else
2435 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2436 dev->ib_dev.name);
2437 }
2438
2439 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 2440 if (err)
2441 goto out;
2442
2443 rq->state = new_state;
2444
2445out:
2446 kvfree(in);
2447 return err;
2448}
2449
2450static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
7d29f349
BW		 2451 struct mlx5_ib_sq *sq,
2452 int new_state,
2453 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2454{
7d29f349
BW		 2455 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2456 u32 old_rate = ibqp->rate_limit;
2457 u32 new_rate = old_rate;
2458 u16 rl_index = 0;
ad5f8e96 2459 void *in;
2460 void *sqc;
2461 int inlen;
2462 int err;
2463
2464 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2465 in = mlx5_vzalloc(inlen);
2466 if (!in)
2467 return -ENOMEM;
2468
2469 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2470
2471 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2472 MLX5_SET(sqc, sqc, state, new_state);
2473
7d29f349
BW		 2474 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2475 if (new_state != MLX5_SQC_STATE_RDY)
2476 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2477 __func__);
2478 else
2479 new_rate = raw_qp_param->rate_limit;
2480 }
2481
2482 if (old_rate != new_rate) {
2483 if (new_rate) {
2484 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2485 if (err) {
2486 pr_err("Failed configuring rate %u: %d\n",
2487 new_rate, err);
2488 goto out;
2489 }
2490 }
2491
2492 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2493 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2494 }
2495
ad5f8e96 2496 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 2497 if (err) {
2498 /* Remove new rate from table if failed */
2499 if (new_rate &&
2500 old_rate != new_rate)
2501 mlx5_rl_remove_rate(dev, new_rate);
ad5f8e96 2502 goto out;
7d29f349
BW		 2503 }
2504
2505 /* Only remove the old rate after new rate was set */
2506 if ((old_rate &&
2507 (old_rate != new_rate)) ||
2508 (new_state != MLX5_SQC_STATE_RDY))
2509 mlx5_rl_remove_rate(dev, old_rate);
ad5f8e96 2510
7d29f349 2511 ibqp->rate_limit = new_rate;
ad5f8e96 2512 sq->state = new_state;
2513
2514out:
2515 kvfree(in);
2516 return err;
2517}
2518
2519static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2520 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2521 u8 tx_affinity)
ad5f8e96 2522{
2523 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2524 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2525 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 2526 int modify_rq = !!qp->rq.wqe_cnt;
2527 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 2528 int rq_state;
2529 int sq_state;
2530 int err;
2531
0680efa2 2532 switch (raw_qp_param->operation) {
ad5f8e96 2533 case MLX5_CMD_OP_RST2INIT_QP:
2534 rq_state = MLX5_RQC_STATE_RDY;
2535 sq_state = MLX5_SQC_STATE_RDY;
2536 break;
2537 case MLX5_CMD_OP_2ERR_QP:
2538 rq_state = MLX5_RQC_STATE_ERR;
2539 sq_state = MLX5_SQC_STATE_ERR;
2540 break;
2541 case MLX5_CMD_OP_2RST_QP:
2542 rq_state = MLX5_RQC_STATE_RST;
2543 sq_state = MLX5_SQC_STATE_RST;
2544 break;
ad5f8e96 2545 case MLX5_CMD_OP_RTR2RTS_QP:
2546 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 2547 if (raw_qp_param->set_mask ==
2548 MLX5_RAW_QP_RATE_LIMIT) {
2549 modify_rq = 0;
2550 sq_state = sq->state;
2551 } else {
2552 return raw_qp_param->set_mask ? -EINVAL : 0;
2553 }
2554 break;
2555 case MLX5_CMD_OP_INIT2INIT_QP:
2556 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 2557 if (raw_qp_param->set_mask)
2558 return -EINVAL;
2559 else
2560 return 0;
ad5f8e96 2561 default:
2562 WARN_ON(1);
2563 return -EINVAL;
2564 }
2565
7d29f349
BW		 2566 if (modify_rq) {
2567 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
ad5f8e96 2568 if (err)
2569 return err;
2570 }
2571
7d29f349 2572 if (modify_sq) {
13eab21f
AH		 2573 if (tx_affinity) {
2574 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2575 tx_affinity);
2576 if (err)
2577 return err;
2578 }
2579
7d29f349 2580 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
13eab21f 2581 }
ad5f8e96 2582
2583 return 0;
2584}
2585
e126ba97
EC		 2586static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2587 const struct ib_qp_attr *attr, int attr_mask,
2588 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2589{
427c1e7b 2590 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2591 [MLX5_QP_STATE_RST] = {
2592 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2593 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2594 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2595 },
2596 [MLX5_QP_STATE_INIT] = {
2597 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2598 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2599 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2600 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2601 },
2602 [MLX5_QP_STATE_RTR] = {
2603 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2604 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2605 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2606 },
2607 [MLX5_QP_STATE_RTS] = {
2608 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2609 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2610 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2611 },
2612 [MLX5_QP_STATE_SQD] = {
2613 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2614 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2615 },
2616 [MLX5_QP_STATE_SQER] = {
2617 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2618 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2619 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2620 },
2621 [MLX5_QP_STATE_ERR] = {
2622 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2623 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2624 }
2625 };
2626
e126ba97
EC		 2627 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2628 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2629 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2630 struct mlx5_ib_cq *send_cq, *recv_cq;
2631 struct mlx5_qp_context *context;
e126ba97 2632 struct mlx5_ib_pd *pd;
eb49ab0c 2633 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 2634 enum mlx5_qp_state mlx5_cur, mlx5_new;
2635 enum mlx5_qp_optpar optpar;
e126ba97
EC		 2636 int mlx5_st;
2637 int err;
427c1e7b 2638 u16 op;
13eab21f 2639 u8 tx_affinity = 0;
e126ba97 2640
1a412fb1
SM		 2641 context = kzalloc(sizeof(*context), GFP_KERNEL);
2642 if (!context)
e126ba97
EC		 2643 return -ENOMEM;
2644
e126ba97 2645 err = to_mlx5_st(ibqp->qp_type);
158abf86
HE		 2646 if (err < 0) {
2647 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
e126ba97 2648 goto out;
158abf86 2649 }
e126ba97
EC		 2650
2651 context->flags = cpu_to_be32(err << 16);
2652
2653 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2654 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2655 } else {
2656 switch (attr->path_mig_state) {
2657 case IB_MIG_MIGRATED:
2658 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2659 break;
2660 case IB_MIG_REARM:
2661 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2662 break;
2663 case IB_MIG_ARMED:
2664 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2665 break;
2666 }
2667 }
2668
13eab21f
AH		 2669 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2670 if ((ibqp->qp_type == IB_QPT_RC) ||
2671 (ibqp->qp_type == IB_QPT_UD &&
2672 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2673 (ibqp->qp_type == IB_QPT_UC) ||
2674 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2675 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2676 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2677 if (mlx5_lag_is_active(dev->mdev)) {
2678 tx_affinity = (unsigned int)atomic_add_return(1,
2679 &dev->roce.next_port) %
2680 MLX5_MAX_PORTS + 1;
2681 context->flags |= cpu_to_be32(tx_affinity << 24);
2682 }
2683 }
2684 }
2685
d16e91da 2686 if (is_sqp(ibqp->qp_type)) {
e126ba97
EC		 2687 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2688 } else if (ibqp->qp_type == IB_QPT_UD ||
2689 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2690 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2691 } else if (attr_mask & IB_QP_PATH_MTU) {
2692 if (attr->path_mtu < IB_MTU_256 ||
2693 attr->path_mtu > IB_MTU_4096) {
2694 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2695 err = -EINVAL;
2696 goto out;
2697 }
938fe83c
SM		 2698 context->mtu_msgmax = (attr->path_mtu << 5) |
2699 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 2700 }
2701
2702 if (attr_mask & IB_QP_DEST_QPN)
2703 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2704
2705 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 2706 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 2707
2708 /* todo implement counter_index functionality */
2709
2710 if (is_sqp(ibqp->qp_type))
2711 context->pri_path.port = qp->port;
2712
2713 if (attr_mask & IB_QP_PORT)
2714 context->pri_path.port = attr->port_num;
2715
2716 if (attr_mask & IB_QP_AV) {
75850d0b 2717 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 2718 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 2719 attr_mask, 0, attr, false);
e126ba97
EC		 2720 if (err)
2721 goto out;
2722 }
2723
2724 if (attr_mask & IB_QP_TIMEOUT)
2725 context->pri_path.ackto_lt |= attr->timeout << 3;
2726
2727 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 2728 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2729 &context->alt_path,
f879ee8d
AS		 2730 attr->alt_port_num,
2731 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2732 0, attr, true);
e126ba97
EC		 2733 if (err)
2734 goto out;
2735 }
2736
2737 pd = get_pd(qp);
89ea94a7
MG		 2738 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2739 &send_cq, &recv_cq);
e126ba97
EC		 2740
2741 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2742 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2743 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2744 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2745
2746 if (attr_mask & IB_QP_RNR_RETRY)
2747 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2748
2749 if (attr_mask & IB_QP_RETRY_CNT)
2750 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2751
2752 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2753 if (attr->max_rd_atomic)
2754 context->params1 |=
2755 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2756 }
2757
2758 if (attr_mask & IB_QP_SQ_PSN)
2759 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2760
2761 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2762 if (attr->max_dest_rd_atomic)
2763 context->params2 |=
2764 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2765 }
2766
2767 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2768 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2769
2770 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2771 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2772
2773 if (attr_mask & IB_QP_RQ_PSN)
2774 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2775
2776 if (attr_mask & IB_QP_QKEY)
2777 context->qkey = cpu_to_be32(attr->qkey);
2778
2779 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2780 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2781
0837e86a
MB		 2782 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2783 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2784 qp->port) - 1;
eb49ab0c 2785 mibport = &dev->port[port_num];
0837e86a 2786 context->qp_counter_set_usr_page |=
7c16f477 2787 cpu_to_be32((u32)(mibport->q_cnts.set_id) << 24);
0837e86a
MB		 2788 }
2789
e126ba97
EC		 2790 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2791 context->sq_crq_size |= cpu_to_be16(1 << 4);
2792
b11a4f9c
HE		 2793 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2794 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 2795
2796 mlx5_cur = to_mlx5_state(cur_state);
2797 mlx5_new = to_mlx5_state(new_state);
2798 mlx5_st = to_mlx5_st(ibqp->qp_type);
07c9113f 2799 if (mlx5_st < 0)
e126ba97
EC		 2800 goto out;
2801
427c1e7b 2802 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2803 !optab[mlx5_cur][mlx5_new])
2804 goto out;
2805
2806 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 2807 optpar = ib_mask_to_mlx5_opt(attr_mask);
2808 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 2809
0680efa2
AV		 2810 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2811 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2812
2813 raw_qp_param.operation = op;
eb49ab0c 2814 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
7c16f477 2815 raw_qp_param.rq_q_ctr_id = mibport->q_cnts.set_id;
eb49ab0c
AV		 2816 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2817 }
7d29f349
BW		 2818
2819 if (attr_mask & IB_QP_RATE_LIMIT) {
2820 raw_qp_param.rate_limit = attr->rate_limit;
2821 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2822 }
2823
13eab21f 2824 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 2825 } else {
1a412fb1 2826 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 2827 &base->mqp);
0680efa2
AV		 2828 }
2829
e126ba97
EC		 2830 if (err)
2831 goto out;
2832
2833 qp->state = new_state;
2834
2835 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 2836 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 2837 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 2838 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 2839 if (attr_mask & IB_QP_PORT)
2840 qp->port = attr->port_num;
2841 if (attr_mask & IB_QP_ALT_PATH)
19098df2 2842 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 2843
2844 /*
2845 * If we moved a kernel QP to RESET, clean up all old CQ
2846 * entries and reinitialize the QP.
2847 */
2848 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
19098df2 2849 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2850 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2851 if (send_cq != recv_cq)
19098df2 2852 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 2853
2854 qp->rq.head = 0;
2855 qp->rq.tail = 0;
2856 qp->sq.head = 0;
2857 qp->sq.tail = 0;
2858 qp->sq.cur_post = 0;
2859 qp->sq.last_poll = 0;
2860 qp->db.db[MLX5_RCV_DBR] = 0;
2861 qp->db.db[MLX5_SND_DBR] = 0;
2862 }
2863
2864out:
1a412fb1 2865 kfree(context);
e126ba97
EC		 2866 return err;
2867}
2868
2869int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2870 int attr_mask, struct ib_udata *udata)
2871{
2872 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2873 struct mlx5_ib_qp *qp = to_mqp(ibqp);
d16e91da 2874 enum ib_qp_type qp_type;
e126ba97
EC		 2875 enum ib_qp_state cur_state, new_state;
2876 int err = -EINVAL;
2877 int port;
2811ba51 2878 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 2879
28d61370
YH		 2880 if (ibqp->rwq_ind_tbl)
2881 return -ENOSYS;
2882
d16e91da
HE		 2883 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2884 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2885
2886 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2887 IB_QPT_GSI : ibqp->qp_type;
2888
e126ba97
EC		 2889 mutex_lock(&qp->mutex);
2890
2891 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2892 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2893
2811ba51
AS		 2894 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2895 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2896 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2897 }
2898
d16e91da
HE		 2899 if (qp_type != MLX5_IB_QPT_REG_UMR &&
2900 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 2901 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2902 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 2903 goto out;
158abf86 2904 }
e126ba97
EC		 2905
2906 if ((attr_mask & IB_QP_PORT) &&
938fe83c 2907 (attr->port_num == 0 ||
158abf86
HE		 2908 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2909 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2910 attr->port_num, dev->num_ports);
e126ba97 2911 goto out;
158abf86 2912 }
e126ba97
EC		 2913
2914 if (attr_mask & IB_QP_PKEY_INDEX) {
2915 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 2916 if (attr->pkey_index >=
158abf86
HE		 2917 dev->mdev->port_caps[port - 1].pkey_table_len) {
2918 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2919 attr->pkey_index);
e126ba97 2920 goto out;
158abf86 2921 }
e126ba97
EC		 2922 }
2923
2924 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 2925 attr->max_rd_atomic >
158abf86
HE		 2926 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2927 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2928 attr->max_rd_atomic);
e126ba97 2929 goto out;
158abf86 2930 }
e126ba97
EC		 2931
2932 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 2933 attr->max_dest_rd_atomic >
158abf86
HE		 2934 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2935 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2936 attr->max_dest_rd_atomic);
e126ba97 2937 goto out;
158abf86 2938 }
e126ba97
EC		 2939
2940 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2941 err = 0;
2942 goto out;
2943 }
2944
2945 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2946
2947out:
2948 mutex_unlock(&qp->mutex);
2949 return err;
2950}
2951
2952static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2953{
2954 struct mlx5_ib_cq *cq;
2955 unsigned cur;
2956
2957 cur = wq->head - wq->tail;
2958 if (likely(cur + nreq < wq->max_post))
2959 return 0;
2960
2961 cq = to_mcq(ib_cq);
2962 spin_lock(&cq->lock);
2963 cur = wq->head - wq->tail;
2964 spin_unlock(&cq->lock);
2965
2966 return cur + nreq >= wq->max_post;
2967}
2968
2969static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2970 u64 remote_addr, u32 rkey)
2971{
2972 rseg->raddr = cpu_to_be64(remote_addr);
2973 rseg->rkey = cpu_to_be32(rkey);
2974 rseg->reserved = 0;
2975}
2976
f0313965
ES		 2977static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2978 struct ib_send_wr *wr, void *qend,
2979 struct mlx5_ib_qp *qp, int *size)
2980{
2981 void *seg = eseg;
2982
2983 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2984
2985 if (wr->send_flags & IB_SEND_IP_CSUM)
2986 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2987 MLX5_ETH_WQE_L4_CSUM;
2988
2989 seg += sizeof(struct mlx5_wqe_eth_seg);
2990 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2991
2992 if (wr->opcode == IB_WR_LSO) {
2993 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2994 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2995 u64 left, leftlen, copysz;
2996 void *pdata = ud_wr->header;
2997
2998 left = ud_wr->hlen;
2999 eseg->mss = cpu_to_be16(ud_wr->mss);
3000 eseg->inline_hdr_sz = cpu_to_be16(left);
3001
3002 /*
3003 * check if there is space till the end of queue, if yes,
3004 * copy all in one shot, otherwise copy till the end of queue,
3005 * rollback and than the copy the left
3006 */
3007 leftlen = qend - (void *)eseg->inline_hdr_start;
3008 copysz = min_t(u64, leftlen, left);
3009
3010 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3011
3012 if (likely(copysz > size_of_inl_hdr_start)) {
3013 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3014 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3015 }
3016
3017 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3018 seg = mlx5_get_send_wqe(qp, 0);
3019 left -= copysz;
3020 pdata += copysz;
3021 memcpy(seg, pdata, left);
3022 seg += ALIGN(left, 16);
3023 *size += ALIGN(left, 16) / 16;
3024 }
3025 }
3026
3027 return seg;
3028}
3029
e126ba97
EC		 3030static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3031 struct ib_send_wr *wr)
3032{
e622f2f4
CH		 3033 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3034 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3035 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3036}
3037
3038static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3039{
3040 dseg->byte_count = cpu_to_be32(sg->length);
3041 dseg->lkey = cpu_to_be32(sg->lkey);
3042 dseg->addr = cpu_to_be64(sg->addr);
3043}
3044
31616255 3045static u64 get_xlt_octo(u64 bytes)
e126ba97 3046{
31616255
AK		 3047 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3048 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3049}
3050
3051static __be64 frwr_mkey_mask(void)
3052{
3053 u64 result;
3054
3055 result = MLX5_MKEY_MASK_LEN |
3056 MLX5_MKEY_MASK_PAGE_SIZE |
3057 MLX5_MKEY_MASK_START_ADDR |
3058 MLX5_MKEY_MASK_EN_RINVAL |
3059 MLX5_MKEY_MASK_KEY |
3060 MLX5_MKEY_MASK_LR |
3061 MLX5_MKEY_MASK_LW |
3062 MLX5_MKEY_MASK_RR |
3063 MLX5_MKEY_MASK_RW |
3064 MLX5_MKEY_MASK_A |
3065 MLX5_MKEY_MASK_SMALL_FENCE |
3066 MLX5_MKEY_MASK_FREE;
3067
3068 return cpu_to_be64(result);
3069}
3070
e6631814
SG		 3071static __be64 sig_mkey_mask(void)
3072{
3073 u64 result;
3074
3075 result = MLX5_MKEY_MASK_LEN |
3076 MLX5_MKEY_MASK_PAGE_SIZE |
3077 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3078 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3079 MLX5_MKEY_MASK_EN_RINVAL |
3080 MLX5_MKEY_MASK_KEY |
3081 MLX5_MKEY_MASK_LR |
3082 MLX5_MKEY_MASK_LW |
3083 MLX5_MKEY_MASK_RR |
3084 MLX5_MKEY_MASK_RW |
3085 MLX5_MKEY_MASK_SMALL_FENCE |
3086 MLX5_MKEY_MASK_FREE |
3087 MLX5_MKEY_MASK_BSF_EN;
3088
3089 return cpu_to_be64(result);
3090}
3091
8a187ee5 3092static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3093 struct mlx5_ib_mr *mr)
8a187ee5 3094{
31616255 3095 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3096
3097 memset(umr, 0, sizeof(*umr));
b005d316 3098
8a187ee5 3099 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
31616255 3100 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3101 umr->mkey_mask = frwr_mkey_mask();
3102}
3103
dd01e66a 3104static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3105{
3106 memset(umr, 0, sizeof(*umr));
dd01e66a 3107 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3108 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3109}
3110
31616255 3111static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 3112{
3113 u64 result;
3114
31616255 3115 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 3116 MLX5_MKEY_MASK_FREE;
3117
968e78dd
HE		 3118 return cpu_to_be64(result);
3119}
3120
31616255 3121static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 3122{
3123 u64 result;
3124
3125 result = MLX5_MKEY_MASK_FREE;
3126
3127 return cpu_to_be64(result);
3128}
3129
56e11d62
NO		 3130static __be64 get_umr_update_translation_mask(void)
3131{
3132 u64 result;
3133
3134 result = MLX5_MKEY_MASK_LEN |
3135 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 3136 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 3137
3138 return cpu_to_be64(result);
3139}
3140
31616255 3141static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 3142{
3143 u64 result;
3144
31616255
AK		 3145 result = MLX5_MKEY_MASK_LR |
3146 MLX5_MKEY_MASK_LW |
56e11d62 3147 MLX5_MKEY_MASK_RR |
31616255
AK		 3148 MLX5_MKEY_MASK_RW;
3149
3150 if (atomic)
3151 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 3152
3153 return cpu_to_be64(result);
3154}
3155
3156static __be64 get_umr_update_pd_mask(void)
3157{
3158 u64 result;
3159
31616255 3160 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 3161
3162 return cpu_to_be64(result);
3163}
3164
e126ba97 3165static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
578e7264 3166 struct ib_send_wr *wr, int atomic)
e126ba97 3167{
e622f2f4 3168 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3169
3170 memset(umr, 0, sizeof(*umr));
3171
968e78dd
HE		 3172 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3173 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3174 else
3175 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3176
31616255
AK		 3177 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3178 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3179 u64 offset = get_xlt_octo(umrwr->offset);
3180
3181 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3182 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3183 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 3184 }
31616255
AK		 3185 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3186 umr->mkey_mask |= get_umr_update_translation_mask();
3187 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3188 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3189 umr->mkey_mask |= get_umr_update_pd_mask();
3190 }
3191 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3192 umr->mkey_mask |= get_umr_enable_mr_mask();
3193 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3194 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 3195
3196 if (!wr->num_sge)
968e78dd 3197 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3198}
3199
3200static u8 get_umr_flags(int acc)
3201{
3202 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3203 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3204 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3205 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3206 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3207}
3208
8a187ee5
SG		 3209static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3210 struct mlx5_ib_mr *mr,
3211 u32 key, int access)
3212{
3213 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3214
3215 memset(seg, 0, sizeof(*seg));
b005d316 3216
ec22eb53 3217 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3218 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3219 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3220 /* KLMs take twice the size of MTTs */
3221 ndescs *= 2;
3222
3223 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3224 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3225 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3226 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3227 seg->len = cpu_to_be64(mr->ibmr.length);
3228 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3229}
3230
dd01e66a 3231static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3232{
3233 memset(seg, 0, sizeof(*seg));
dd01e66a 3234 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3235}
3236
3237static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3238{
e622f2f4 3239 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3240
e126ba97 3241 memset(seg, 0, sizeof(*seg));
31616255 3242 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 3243 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 3244
968e78dd 3245 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 3246 if (umrwr->pd)
3247 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3248 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3249 !umrwr->length)
3250 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3251
3252 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 3253 seg->len = cpu_to_be64(umrwr->length);
3254 seg->log2_page_size = umrwr->page_shift;
746b5583 3255 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3256 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3257}
3258
8a187ee5
SG		 3259static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3260 struct mlx5_ib_mr *mr,
3261 struct mlx5_ib_pd *pd)
3262{
3263 int bcount = mr->desc_size * mr->ndescs;
3264
3265 dseg->addr = cpu_to_be64(mr->desc_map);
3266 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3267 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3268}
3269
e126ba97
EC		 3270static __be32 send_ieth(struct ib_send_wr *wr)
3271{
3272 switch (wr->opcode) {
3273 case IB_WR_SEND_WITH_IMM:
3274 case IB_WR_RDMA_WRITE_WITH_IMM:
3275 return wr->ex.imm_data;
3276
3277 case IB_WR_SEND_WITH_INV:
3278 return cpu_to_be32(wr->ex.invalidate_rkey);
3279
3280 default:
3281 return 0;
3282 }
3283}
3284
3285static u8 calc_sig(void *wqe, int size)
3286{
3287 u8 *p = wqe;
3288 u8 res = 0;
3289 int i;
3290
3291 for (i = 0; i < size; i++)
3292 res ^= p[i];
3293
3294 return ~res;
3295}
3296
3297static u8 wq_sig(void *wqe)
3298{
3299 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3300}
3301
3302static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3303 void *wqe, int *sz)
3304{
3305 struct mlx5_wqe_inline_seg *seg;
3306 void *qend = qp->sq.qend;
3307 void *addr;
3308 int inl = 0;
3309 int copy;
3310 int len;
3311 int i;
3312
3313 seg = wqe;
3314 wqe += sizeof(*seg);
3315 for (i = 0; i < wr->num_sge; i++) {
3316 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3317 len = wr->sg_list[i].length;
3318 inl += len;
3319
3320 if (unlikely(inl > qp->max_inline_data))
3321 return -ENOMEM;
3322
3323 if (unlikely(wqe + len > qend)) {
3324 copy = qend - wqe;
3325 memcpy(wqe, addr, copy);
3326 addr += copy;
3327 len -= copy;
3328 wqe = mlx5_get_send_wqe(qp, 0);
3329 }
3330 memcpy(wqe, addr, len);
3331 wqe += len;
3332 }
3333
3334 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3335
3336 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3337
3338 return 0;
3339}
3340
e6631814
SG		 3341static u16 prot_field_size(enum ib_signature_type type)
3342{
3343 switch (type) {
3344 case IB_SIG_TYPE_T10_DIF:
3345 return MLX5_DIF_SIZE;
3346 default:
3347 return 0;
3348 }
3349}
3350
3351static u8 bs_selector(int block_size)
3352{
3353 switch (block_size) {
3354 case 512: return 0x1;
3355 case 520: return 0x2;
3356 case 4096: return 0x3;
3357 case 4160: return 0x4;
3358 case 1073741824: return 0x5;
3359 default: return 0;
3360 }
3361}
3362
78eda2bb
SG		 3363static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3364 struct mlx5_bsf_inl *inl)
e6631814 3365{
142537f4
SG		 3366 /* Valid inline section and allow BSF refresh */
3367 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3368 MLX5_BSF_REFRESH_DIF);
3369 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3370 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3371 /* repeating block */
3372 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3373 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3374 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3375
78eda2bb
SG		 3376 if (domain->sig.dif.ref_remap)
3377 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3378
78eda2bb
SG		 3379 if (domain->sig.dif.app_escape) {
3380 if (domain->sig.dif.ref_escape)
3381 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3382 else
3383 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3384 }
3385
78eda2bb
SG		 3386 inl->dif_app_bitmask_check =
3387 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3388}
3389
3390static int mlx5_set_bsf(struct ib_mr *sig_mr,
3391 struct ib_sig_attrs *sig_attrs,
3392 struct mlx5_bsf *bsf, u32 data_size)
3393{
3394 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3395 struct mlx5_bsf_basic *basic = &bsf->basic;
3396 struct ib_sig_domain *mem = &sig_attrs->mem;
3397 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3398
c7f44fbd 3399 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3400
3401 /* Basic + Extended + Inline */
3402 basic->bsf_size_sbs = 1 << 7;
3403 /* Input domain check byte mask */
3404 basic->check_byte_mask = sig_attrs->check_mask;
3405 basic->raw_data_size = cpu_to_be32(data_size);
3406
3407 /* Memory domain */
e6631814 3408 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3409 case IB_SIG_TYPE_NONE:
3410 break;
e6631814 3411 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3412 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3413 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3414 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3415 break;
3416 default:
3417 return -EINVAL;
3418 }
e6631814 3419
78eda2bb
SG		 3420 /* Wire domain */
3421 switch (sig_attrs->wire.sig_type) {
3422 case IB_SIG_TYPE_NONE:
3423 break;
3424 case IB_SIG_TYPE_T10_DIF:
e6631814 3425 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3426 mem->sig_type == wire->sig_type) {
e6631814 3427 /* Same block structure */
142537f4 3428 basic->bsf_size_sbs |= 1 << 4;
e6631814 3429 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3430 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3431 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3432 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3433 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3434 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3435 } else
3436 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3437
142537f4 3438 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3439 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3440 break;
e6631814
SG		 3441 default:
3442 return -EINVAL;
3443 }
3444
3445 return 0;
3446}
3447
e622f2f4
CH		 3448static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3449 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3450{
e622f2f4
CH		 3451 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3452 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3453 struct mlx5_bsf *bsf;
e622f2f4
CH		 3454 u32 data_len = wr->wr.sg_list->length;
3455 u32 data_key = wr->wr.sg_list->lkey;
3456 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3457 int ret;
3458 int wqe_size;
3459
e622f2f4
CH		 3460 if (!wr->prot ||
3461 (data_key == wr->prot->lkey &&
3462 data_va == wr->prot->addr &&
3463 data_len == wr->prot->length)) {
e6631814
SG		 3464 /**
3465 * Source domain doesn't contain signature information
5c273b16 3466 * or data and protection are interleaved in memory.
e6631814
SG		 3467 * So need construct:
3468 * ------------------
3469 * | data_klm |
3470 * ------------------
3471 * | BSF |
3472 * ------------------
3473 **/
3474 struct mlx5_klm *data_klm = *seg;
3475
3476 data_klm->bcount = cpu_to_be32(data_len);
3477 data_klm->key = cpu_to_be32(data_key);
3478 data_klm->va = cpu_to_be64(data_va);
3479 wqe_size = ALIGN(sizeof(*data_klm), 64);
3480 } else {
3481 /**
3482 * Source domain contains signature information
3483 * So need construct a strided block format:
3484 * ---------------------------
3485 * | stride_block_ctrl |
3486 * ---------------------------
3487 * | data_klm |
3488 * ---------------------------
3489 * | prot_klm |
3490 * ---------------------------
3491 * | BSF |
3492 * ---------------------------
3493 **/
3494 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3495 struct mlx5_stride_block_entry *data_sentry;
3496 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 3497 u32 prot_key = wr->prot->lkey;
3498 u64 prot_va = wr->prot->addr;
e6631814
SG		 3499 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3500 int prot_size;
3501
3502 sblock_ctrl = *seg;
3503 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3504 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3505
3506 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3507 if (!prot_size) {
3508 pr_err("Bad block size given: %u\n", block_size);
3509 return -EINVAL;
3510 }
3511 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3512 prot_size);
3513 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3514 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3515 sblock_ctrl->num_entries = cpu_to_be16(2);
3516
3517 data_sentry->bcount = cpu_to_be16(block_size);
3518 data_sentry->key = cpu_to_be32(data_key);
3519 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 3520 data_sentry->stride = cpu_to_be16(block_size);
3521
e6631814
SG		 3522 prot_sentry->bcount = cpu_to_be16(prot_size);
3523 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 3524 prot_sentry->va = cpu_to_be64(prot_va);
3525 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 3526
e6631814
SG		 3527 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3528 sizeof(*prot_sentry), 64);
3529 }
3530
3531 *seg += wqe_size;
3532 *size += wqe_size / 16;
3533 if (unlikely((*seg == qp->sq.qend)))
3534 *seg = mlx5_get_send_wqe(qp, 0);
3535
3536 bsf = *seg;
3537 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3538 if (ret)
3539 return -EINVAL;
3540
3541 *seg += sizeof(*bsf);
3542 *size += sizeof(*bsf) / 16;
3543 if (unlikely((*seg == qp->sq.qend)))
3544 *seg = mlx5_get_send_wqe(qp, 0);
3545
3546 return 0;
3547}
3548
3549static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
31616255 3550 struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 3551 u32 length, u32 pdn)
3552{
e622f2f4 3553 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3554 u32 sig_key = sig_mr->rkey;
d5436ba0 3555 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 3556
3557 memset(seg, 0, sizeof(*seg));
3558
e622f2f4 3559 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 3560 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 3561 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 3562 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 3563 MLX5_MKEY_BSF_EN | pdn);
3564 seg->len = cpu_to_be64(length);
31616255 3565 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 3566 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3567}
3568
3569static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3570 u32 size)
e6631814
SG		 3571{
3572 memset(umr, 0, sizeof(*umr));
3573
3574 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 3575 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 3576 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3577 umr->mkey_mask = sig_mkey_mask();
3578}
3579
3580
e622f2f4 3581static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 3582 void **seg, int *size)
3583{
e622f2f4
CH		 3584 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3585 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 3586 u32 pdn = get_pd(qp)->pdn;
31616255 3587 u32 xlt_size;
e6631814
SG		 3588 int region_len, ret;
3589
e622f2f4
CH		 3590 if (unlikely(wr->wr.num_sge != 1) ||
3591 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 3592 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3593 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 3594 return -EINVAL;
3595
3596 /* length of the protected region, data + protection */
e622f2f4
CH		 3597 region_len = wr->wr.sg_list->length;
3598 if (wr->prot &&
3599 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3600 wr->prot->addr != wr->wr.sg_list->addr ||
3601 wr->prot->length != wr->wr.sg_list->length))
3602 region_len += wr->prot->length;
e6631814
SG		 3603
3604 /**
3605 * KLM octoword size - if protection was provided
3606 * then we use strided block format (3 octowords),
3607 * else we use single KLM (1 octoword)
3608 **/
31616255 3609 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 3610
31616255 3611 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 3612 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3613 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3614 if (unlikely((*seg == qp->sq.qend)))
3615 *seg = mlx5_get_send_wqe(qp, 0);
3616
31616255 3617 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 3618 *seg += sizeof(struct mlx5_mkey_seg);
3619 *size += sizeof(struct mlx5_mkey_seg) / 16;
3620 if (unlikely((*seg == qp->sq.qend)))
3621 *seg = mlx5_get_send_wqe(qp, 0);
3622
3623 ret = set_sig_data_segment(wr, qp, seg, size);
3624 if (ret)
3625 return ret;
3626
d5436ba0 3627 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 3628 return 0;
3629}
3630
3631static int set_psv_wr(struct ib_sig_domain *domain,
3632 u32 psv_idx, void **seg, int *size)
3633{
3634 struct mlx5_seg_set_psv *psv_seg = *seg;
3635
3636 memset(psv_seg, 0, sizeof(*psv_seg));
3637 psv_seg->psv_num = cpu_to_be32(psv_idx);
3638 switch (domain->sig_type) {
78eda2bb
SG		 3639 case IB_SIG_TYPE_NONE:
3640 break;
e6631814
SG		 3641 case IB_SIG_TYPE_T10_DIF:
3642 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3643 domain->sig.dif.app_tag);
3644 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 3645 break;
e6631814 3646 default:
12bbf1ea
LR		 3647 pr_err("Bad signature type (%d) is given.\n",
3648 domain->sig_type);
3649 return -EINVAL;
e6631814
SG		 3650 }
3651
78eda2bb
SG		 3652 *seg += sizeof(*psv_seg);
3653 *size += sizeof(*psv_seg) / 16;
3654
e6631814
SG		 3655 return 0;
3656}
3657
8a187ee5
SG		 3658static int set_reg_wr(struct mlx5_ib_qp *qp,
3659 struct ib_reg_wr *wr,
3660 void **seg, int *size)
3661{
3662 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3663 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3664
3665 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3666 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3667 "Invalid IB_SEND_INLINE send flag\n");
3668 return -EINVAL;
3669 }
3670
3671 set_reg_umr_seg(*seg, mr);
3672 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3673 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3674 if (unlikely((*seg == qp->sq.qend)))
3675 *seg = mlx5_get_send_wqe(qp, 0);
3676
3677 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3678 *seg += sizeof(struct mlx5_mkey_seg);
3679 *size += sizeof(struct mlx5_mkey_seg) / 16;
3680 if (unlikely((*seg == qp->sq.qend)))
3681 *seg = mlx5_get_send_wqe(qp, 0);
3682
3683 set_reg_data_seg(*seg, mr, pd);
3684 *seg += sizeof(struct mlx5_wqe_data_seg);
3685 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3686
3687 return 0;
3688}
3689
dd01e66a 3690static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 3691{
dd01e66a 3692 set_linv_umr_seg(*seg);
e126ba97
EC		 3693 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3694 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3695 if (unlikely((*seg == qp->sq.qend)))
3696 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 3697 set_linv_mkey_seg(*seg);
e126ba97
EC		 3698 *seg += sizeof(struct mlx5_mkey_seg);
3699 *size += sizeof(struct mlx5_mkey_seg) / 16;
3700 if (unlikely((*seg == qp->sq.qend)))
3701 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 3702}
3703
3704static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3705{
3706 __be32 *p = NULL;
3707 int tidx = idx;
3708 int i, j;
3709
3710 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3711 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3712 if ((i & 0xf) == 0) {
3713 void *buf = mlx5_get_send_wqe(qp, tidx);
3714 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3715 p = buf;
3716 j = 0;
3717 }
3718 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3719 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3720 be32_to_cpu(p[j + 3]));
3721 }
3722}
3723
e126ba97
EC		 3724static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3725{
3726 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3727 wr->send_flags & IB_SEND_FENCE))
3728 return MLX5_FENCE_MODE_STRONG_ORDERING;
3729
3730 if (unlikely(fence)) {
3731 if (wr->send_flags & IB_SEND_FENCE)
3732 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3733 else
3734 return fence;
c9b25495
EC		 3735 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3736 return MLX5_FENCE_MODE_FENCE;
e126ba97 3737 }
c9b25495
EC		 3738
3739 return 0;
e126ba97
EC		 3740}
3741
6e5eadac
SG		 3742static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3743 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 3744 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 3745 int *size, int nreq)
3746{
b2a232d2
LR		 3747 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3748 return -ENOMEM;
6e5eadac
SG		 3749
3750 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3751 *seg = mlx5_get_send_wqe(qp, *idx);
3752 *ctrl = *seg;
3753 *(uint32_t *)(*seg + 8) = 0;
3754 (*ctrl)->imm = send_ieth(wr);
3755 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3756 (wr->send_flags & IB_SEND_SIGNALED ?
3757 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3758 (wr->send_flags & IB_SEND_SOLICITED ?
3759 MLX5_WQE_CTRL_SOLICITED : 0);
3760
3761 *seg += sizeof(**ctrl);
3762 *size = sizeof(**ctrl) / 16;
3763
b2a232d2 3764 return 0;
6e5eadac
SG		 3765}
3766
3767static void finish_wqe(struct mlx5_ib_qp *qp,
3768 struct mlx5_wqe_ctrl_seg *ctrl,
3769 u8 size, unsigned idx, u64 wr_id,
3770 int nreq, u8 fence, u8 next_fence,
3771 u32 mlx5_opcode)
3772{
3773 u8 opmod = 0;
3774
3775 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3776 mlx5_opcode | ((u32)opmod << 24));
19098df2 3777 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac
SG		 3778 ctrl->fm_ce_se |= fence;
3779 qp->fm_cache = next_fence;
3780 if (unlikely(qp->wq_sig))
3781 ctrl->signature = wq_sig(ctrl);
3782
3783 qp->sq.wrid[idx] = wr_id;
3784 qp->sq.w_list[idx].opcode = mlx5_opcode;
3785 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3786 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3787 qp->sq.w_list[idx].next = qp->sq.cur_post;
3788}
3789
3790
e126ba97
EC		 3791int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3792 struct ib_send_wr **bad_wr)
3793{
3794 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3795 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 3796 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 3797 struct mlx5_ib_qp *qp;
e6631814 3798 struct mlx5_ib_mr *mr;
e126ba97
EC		 3799 struct mlx5_wqe_data_seg *dpseg;
3800 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 3801 struct mlx5_bf *bf;
e126ba97 3802 int uninitialized_var(size);
d16e91da 3803 void *qend;
e126ba97 3804 unsigned long flags;
e126ba97
EC		 3805 unsigned idx;
3806 int err = 0;
3807 int inl = 0;
3808 int num_sge;
3809 void *seg;
3810 int nreq;
3811 int i;
3812 u8 next_fence = 0;
e126ba97
EC		 3813 u8 fence;
3814
d16e91da
HE		 3815 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3816 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3817
3818 qp = to_mqp(ibqp);
5fe9dec0 3819 bf = &qp->bf;
d16e91da
HE		 3820 qend = qp->sq.qend;
3821
e126ba97
EC		 3822 spin_lock_irqsave(&qp->sq.lock, flags);
3823
89ea94a7
MG		 3824 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3825 err = -EIO;
3826 *bad_wr = wr;
3827 nreq = 0;
3828 goto out;
3829 }
3830
e126ba97 3831 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 3832 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 3833 mlx5_ib_warn(dev, "\n");
3834 err = -EINVAL;
3835 *bad_wr = wr;
3836 goto out;
3837 }
3838
6e5eadac
SG		 3839 fence = qp->fm_cache;
3840 num_sge = wr->num_sge;
3841 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 3842 mlx5_ib_warn(dev, "\n");
24be409b 3843 err = -EINVAL;
e126ba97
EC		 3844 *bad_wr = wr;
3845 goto out;
3846 }
3847
6e5eadac
SG		 3848 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3849 if (err) {
e126ba97
EC		 3850 mlx5_ib_warn(dev, "\n");
3851 err = -ENOMEM;
3852 *bad_wr = wr;
3853 goto out;
3854 }
3855
e126ba97
EC		 3856 switch (ibqp->qp_type) {
3857 case IB_QPT_XRC_INI:
3858 xrc = seg;
e126ba97
EC		 3859 seg += sizeof(*xrc);
3860 size += sizeof(*xrc) / 16;
3861 /* fall through */
3862 case IB_QPT_RC:
3863 switch (wr->opcode) {
3864 case IB_WR_RDMA_READ:
3865 case IB_WR_RDMA_WRITE:
3866 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3867 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3868 rdma_wr(wr)->rkey);
f241e749 3869 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 3870 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3871 break;
3872
3873 case IB_WR_ATOMIC_CMP_AND_SWP:
3874 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 3875 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 3876 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3877 err = -ENOSYS;
3878 *bad_wr = wr;
3879 goto out;
e126ba97
EC		 3880
3881 case IB_WR_LOCAL_INV:
3882 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3883 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3884 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 3885 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 3886 num_sge = 0;
3887 break;
3888
8a187ee5
SG		 3889 case IB_WR_REG_MR:
3890 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3891 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3892 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3893 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3894 if (err) {
3895 *bad_wr = wr;
3896 goto out;
3897 }
3898 num_sge = 0;
3899 break;
3900
e6631814
SG		 3901 case IB_WR_REG_SIG_MR:
3902 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 3903 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 3904
3905 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3906 err = set_sig_umr_wr(wr, qp, &seg, &size);
3907 if (err) {
3908 mlx5_ib_warn(dev, "\n");
3909 *bad_wr = wr;
3910 goto out;
3911 }
3912
3913 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3914 nreq, get_fence(fence, wr),
3915 next_fence, MLX5_OPCODE_UMR);
3916 /*
3917 * SET_PSV WQEs are not signaled and solicited
3918 * on error
3919 */
3920 wr->send_flags &= ~IB_SEND_SIGNALED;
3921 wr->send_flags |= IB_SEND_SOLICITED;
3922 err = begin_wqe(qp, &seg, &ctrl, wr,
3923 &idx, &size, nreq);
3924 if (err) {
3925 mlx5_ib_warn(dev, "\n");
3926 err = -ENOMEM;
3927 *bad_wr = wr;
3928 goto out;
3929 }
3930
e622f2f4 3931 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 3932 mr->sig->psv_memory.psv_idx, &seg,
3933 &size);
3934 if (err) {
3935 mlx5_ib_warn(dev, "\n");
3936 *bad_wr = wr;
3937 goto out;
3938 }
3939
3940 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3941 nreq, get_fence(fence, wr),
3942 next_fence, MLX5_OPCODE_SET_PSV);
3943 err = begin_wqe(qp, &seg, &ctrl, wr,
3944 &idx, &size, nreq);
3945 if (err) {
3946 mlx5_ib_warn(dev, "\n");
3947 err = -ENOMEM;
3948 *bad_wr = wr;
3949 goto out;
3950 }
3951
3952 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e622f2f4 3953 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 3954 mr->sig->psv_wire.psv_idx, &seg,
3955 &size);
3956 if (err) {
3957 mlx5_ib_warn(dev, "\n");
3958 *bad_wr = wr;
3959 goto out;
3960 }
3961
3962 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3963 nreq, get_fence(fence, wr),
3964 next_fence, MLX5_OPCODE_SET_PSV);
3965 num_sge = 0;
3966 goto skip_psv;
3967
e126ba97
EC		 3968 default:
3969 break;
3970 }
3971 break;
3972
3973 case IB_QPT_UC:
3974 switch (wr->opcode) {
3975 case IB_WR_RDMA_WRITE:
3976 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3977 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3978 rdma_wr(wr)->rkey);
e126ba97
EC		 3979 seg += sizeof(struct mlx5_wqe_raddr_seg);
3980 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3981 break;
3982
3983 default:
3984 break;
3985 }
3986 break;
3987
e126ba97 3988 case IB_QPT_SMI:
1e0e50b6
MG		 3989 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
3990 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
3991 err = -EPERM;
3992 *bad_wr = wr;
3993 goto out;
3994 }
d16e91da 3995 case MLX5_IB_QPT_HW_GSI:
e126ba97 3996 set_datagram_seg(seg, wr);
f241e749 3997 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 3998 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3999 if (unlikely((seg == qend)))
4000 seg = mlx5_get_send_wqe(qp, 0);
4001 break;
f0313965
ES		 4002 case IB_QPT_UD:
4003 set_datagram_seg(seg, wr);
4004 seg += sizeof(struct mlx5_wqe_datagram_seg);
4005 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4006
4007 if (unlikely((seg == qend)))
4008 seg = mlx5_get_send_wqe(qp, 0);
4009
4010 /* handle qp that supports ud offload */
4011 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4012 struct mlx5_wqe_eth_pad *pad;
e126ba97 4013
f0313965
ES		 4014 pad = seg;
4015 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4016 seg += sizeof(struct mlx5_wqe_eth_pad);
4017 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4018
4019 seg = set_eth_seg(seg, wr, qend, qp, &size);
4020
4021 if (unlikely((seg == qend)))
4022 seg = mlx5_get_send_wqe(qp, 0);
4023 }
4024 break;
e126ba97
EC		 4025 case MLX5_IB_QPT_REG_UMR:
4026 if (wr->opcode != MLX5_IB_WR_UMR) {
4027 err = -EINVAL;
4028 mlx5_ib_warn(dev, "bad opcode\n");
4029 goto out;
4030 }
4031 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4032 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
578e7264 4033 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
e126ba97
EC		 4034 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4035 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4036 if (unlikely((seg == qend)))
4037 seg = mlx5_get_send_wqe(qp, 0);
4038 set_reg_mkey_segment(seg, wr);
4039 seg += sizeof(struct mlx5_mkey_seg);
4040 size += sizeof(struct mlx5_mkey_seg) / 16;
4041 if (unlikely((seg == qend)))
4042 seg = mlx5_get_send_wqe(qp, 0);
4043 break;
4044
4045 default:
4046 break;
4047 }
4048
4049 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4050 int uninitialized_var(sz);
4051
4052 err = set_data_inl_seg(qp, wr, seg, &sz);
4053 if (unlikely(err)) {
4054 mlx5_ib_warn(dev, "\n");
4055 *bad_wr = wr;
4056 goto out;
4057 }
4058 inl = 1;
4059 size += sz;
4060 } else {
4061 dpseg = seg;
4062 for (i = 0; i < num_sge; i++) {
4063 if (unlikely(dpseg == qend)) {
4064 seg = mlx5_get_send_wqe(qp, 0);
4065 dpseg = seg;
4066 }
4067 if (likely(wr->sg_list[i].length)) {
4068 set_data_ptr_seg(dpseg, wr->sg_list + i);
4069 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4070 dpseg++;
4071 }
4072 }
4073 }
4074
6e5eadac
SG		 4075 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4076 get_fence(fence, wr), next_fence,
4077 mlx5_ib_opcode[wr->opcode]);
e6631814 4078skip_psv:
e126ba97
EC		 4079 if (0)
4080 dump_wqe(qp, idx, size);
4081 }
4082
4083out:
4084 if (likely(nreq)) {
4085 qp->sq.head += nreq;
4086
4087 /* Make sure that descriptors are written before
4088 * updating doorbell record and ringing the doorbell
4089 */
4090 wmb();
4091
4092 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4093
ada388f7
EC		 4094 /* Make sure doorbell record is visible to the HCA before
4095 * we hit doorbell */
4096 wmb();
4097
5fe9dec0
EC		 4098 /* currently we support only regular doorbells */
4099 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4100 /* Make sure doorbells don't leak out of SQ spinlock
4101 * and reach the HCA out of order.
4102 */
4103 mmiowb();
e126ba97 4104 bf->offset ^= bf->buf_size;
e126ba97
EC		 4105 }
4106
4107 spin_unlock_irqrestore(&qp->sq.lock, flags);
4108
4109 return err;
4110}
4111
4112static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4113{
4114 sig->signature = calc_sig(sig, size);
4115}
4116
4117int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4118 struct ib_recv_wr **bad_wr)
4119{
4120 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4121 struct mlx5_wqe_data_seg *scat;
4122 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4123 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4124 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4125 unsigned long flags;
4126 int err = 0;
4127 int nreq;
4128 int ind;
4129 int i;
4130
d16e91da
HE		 4131 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4132 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4133
e126ba97
EC		 4134 spin_lock_irqsave(&qp->rq.lock, flags);
4135
89ea94a7
MG		 4136 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4137 err = -EIO;
4138 *bad_wr = wr;
4139 nreq = 0;
4140 goto out;
4141 }
4142
e126ba97
EC		 4143 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4144
4145 for (nreq = 0; wr; nreq++, wr = wr->next) {
4146 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4147 err = -ENOMEM;
4148 *bad_wr = wr;
4149 goto out;
4150 }
4151
4152 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4153 err = -EINVAL;
4154 *bad_wr = wr;
4155 goto out;
4156 }
4157
4158 scat = get_recv_wqe(qp, ind);
4159 if (qp->wq_sig)
4160 scat++;
4161
4162 for (i = 0; i < wr->num_sge; i++)
4163 set_data_ptr_seg(scat + i, wr->sg_list + i);
4164
4165 if (i < qp->rq.max_gs) {
4166 scat[i].byte_count = 0;
4167 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4168 scat[i].addr = 0;
4169 }
4170
4171 if (qp->wq_sig) {
4172 sig = (struct mlx5_rwqe_sig *)scat;
4173 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4174 }
4175
4176 qp->rq.wrid[ind] = wr->wr_id;
4177
4178 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4179 }
4180
4181out:
4182 if (likely(nreq)) {
4183 qp->rq.head += nreq;
4184
4185 /* Make sure that descriptors are written before
4186 * doorbell record.
4187 */
4188 wmb();
4189
4190 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4191 }
4192
4193 spin_unlock_irqrestore(&qp->rq.lock, flags);
4194
4195 return err;
4196}
4197
4198static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4199{
4200 switch (mlx5_state) {
4201 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4202 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4203 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4204 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4205 case MLX5_QP_STATE_SQ_DRAINING:
4206 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4207 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4208 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4209 default: return -1;
4210 }
4211}
4212
4213static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4214{
4215 switch (mlx5_mig_state) {
4216 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4217 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4218 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4219 default: return -1;
4220 }
4221}
4222
4223static int to_ib_qp_access_flags(int mlx5_flags)
4224{
4225 int ib_flags = 0;
4226
4227 if (mlx5_flags & MLX5_QP_BIT_RRE)
4228 ib_flags |= IB_ACCESS_REMOTE_READ;
4229 if (mlx5_flags & MLX5_QP_BIT_RWE)
4230 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4231 if (mlx5_flags & MLX5_QP_BIT_RAE)
4232 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4233
4234 return ib_flags;
4235}
4236
4237static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4238 struct mlx5_qp_path *path)
4239{
9603b61d 4240 struct mlx5_core_dev *dev = ibdev->mdev;
e126ba97
EC		 4241
4242 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4243 ib_ah_attr->port_num = path->port;
4244
c7a08ac7 4245 if (ib_ah_attr->port_num == 0 ||
938fe83c 4246 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
e126ba97
EC		 4247 return;
4248
2811ba51 4249 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
e126ba97
EC		 4250
4251 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
4252 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4253 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
4254 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4255 if (ib_ah_attr->ah_flags) {
4256 ib_ah_attr->grh.sgid_index = path->mgid_index;
4257 ib_ah_attr->grh.hop_limit = path->hop_limit;
4258 ib_ah_attr->grh.traffic_class =
4259 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4260 ib_ah_attr->grh.flow_label =
4261 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4262 memcpy(ib_ah_attr->grh.dgid.raw,
4263 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4264 }
4265}
4266
6d2f89df 4267static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4268 struct mlx5_ib_sq *sq,
4269 u8 *sq_state)
4270{
4271 void *out;
4272 void *sqc;
4273 int inlen;
4274 int err;
4275
4276 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4277 out = mlx5_vzalloc(inlen);
4278 if (!out)
4279 return -ENOMEM;
4280
4281 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4282 if (err)
4283 goto out;
4284
4285 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4286 *sq_state = MLX5_GET(sqc, sqc, state);
4287 sq->state = *sq_state;
4288
4289out:
4290 kvfree(out);
4291 return err;
4292}
4293
4294static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4295 struct mlx5_ib_rq *rq,
4296 u8 *rq_state)
4297{
4298 void *out;
4299 void *rqc;
4300 int inlen;
4301 int err;
4302
4303 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4304 out = mlx5_vzalloc(inlen);
4305 if (!out)
4306 return -ENOMEM;
4307
4308 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4309 if (err)
4310 goto out;
4311
4312 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4313 *rq_state = MLX5_GET(rqc, rqc, state);
4314 rq->state = *rq_state;
4315
4316out:
4317 kvfree(out);
4318 return err;
4319}
4320
4321static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4322 struct mlx5_ib_qp *qp, u8 *qp_state)
4323{
4324 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4325 [MLX5_RQC_STATE_RST] = {
4326 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4327 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4328 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4329 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4330 },
4331 [MLX5_RQC_STATE_RDY] = {
4332 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4333 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4334 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4335 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4336 },
4337 [MLX5_RQC_STATE_ERR] = {
4338 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4339 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4340 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4341 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4342 },
4343 [MLX5_RQ_STATE_NA] = {
4344 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4345 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4346 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4347 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4348 },
4349 };
4350
4351 *qp_state = sqrq_trans[rq_state][sq_state];
4352
4353 if (*qp_state == MLX5_QP_STATE_BAD) {
4354 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4355 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4356 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4357 return -EINVAL;
4358 }
4359
4360 if (*qp_state == MLX5_QP_STATE)
4361 *qp_state = qp->state;
4362
4363 return 0;
4364}
4365
4366static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4367 struct mlx5_ib_qp *qp,
4368 u8 *raw_packet_qp_state)
4369{
4370 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4371 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4372 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4373 int err;
4374 u8 sq_state = MLX5_SQ_STATE_NA;
4375 u8 rq_state = MLX5_RQ_STATE_NA;
4376
4377 if (qp->sq.wqe_cnt) {
4378 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4379 if (err)
4380 return err;
4381 }
4382
4383 if (qp->rq.wqe_cnt) {
4384 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4385 if (err)
4386 return err;
4387 }
4388
4389 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4390 raw_packet_qp_state);
4391}
4392
4393static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4394 struct ib_qp_attr *qp_attr)
e126ba97 4395{
09a7d9ec 4396 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 4397 struct mlx5_qp_context *context;
4398 int mlx5_state;
09a7d9ec 4399 u32 *outb;
e126ba97
EC		 4400 int err = 0;
4401
09a7d9ec 4402 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4403 if (!outb)
4404 return -ENOMEM;
4405
19098df2 4406 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 4407 outlen);
e126ba97 4408 if (err)
6d2f89df 4409 goto out;
e126ba97 4410
09a7d9ec
SM		 4411 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4412 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4413
e126ba97
EC		 4414 mlx5_state = be32_to_cpu(context->flags) >> 28;
4415
4416 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4417 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4418 qp_attr->path_mig_state =
4419 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4420 qp_attr->qkey = be32_to_cpu(context->qkey);
4421 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4422 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4423 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4424 qp_attr->qp_access_flags =
4425 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4426
4427 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4428 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4429 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4430 qp_attr->alt_pkey_index =
4431 be16_to_cpu(context->alt_path.pkey_index);
e126ba97
EC		 4432 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
4433 }
4434
d3ae2bde 4435 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4436 qp_attr->port_num = context->pri_path.port;
4437
4438 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4439 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4440
4441 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4442
4443 qp_attr->max_dest_rd_atomic =
4444 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4445 qp_attr->min_rnr_timer =
4446 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4447 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4448 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4449 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4450 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4451
4452out:
4453 kfree(outb);
4454 return err;
4455}
4456
4457int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4458 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4459{
4460 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4461 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4462 int err = 0;
4463 u8 raw_packet_qp_state;
4464
28d61370
YH		 4465 if (ibqp->rwq_ind_tbl)
4466 return -ENOSYS;
4467
d16e91da
HE		 4468 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4469 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4470 qp_init_attr);
4471
6d2f89df 4472 mutex_lock(&qp->mutex);
4473
4474 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4475 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4476 if (err)
4477 goto out;
4478 qp->state = raw_packet_qp_state;
4479 qp_attr->port_num = 1;
4480 } else {
4481 err = query_qp_attr(dev, qp, qp_attr);
4482 if (err)
4483 goto out;
4484 }
4485
4486 qp_attr->qp_state = qp->state;
e126ba97
EC		 4487 qp_attr->cur_qp_state = qp_attr->qp_state;
4488 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4489 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4490
4491 if (!ibqp->uobject) {
0540d814 4492 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 4493 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 4494 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 4495 } else {
4496 qp_attr->cap.max_send_wr = 0;
4497 qp_attr->cap.max_send_sge = 0;
4498 }
4499
0540d814
NO		 4500 qp_init_attr->qp_type = ibqp->qp_type;
4501 qp_init_attr->recv_cq = ibqp->recv_cq;
4502 qp_init_attr->send_cq = ibqp->send_cq;
4503 qp_init_attr->srq = ibqp->srq;
4504 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 4505
4506 qp_init_attr->cap = qp_attr->cap;
4507
4508 qp_init_attr->create_flags = 0;
4509 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4510 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4511
051f2630
LR		 4512 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4513 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4514 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4515 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4516 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4517 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 4518 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4519 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 4520
e126ba97
EC		 4521 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4522 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4523
e126ba97
EC		 4524out:
4525 mutex_unlock(&qp->mutex);
4526 return err;
4527}
4528
4529struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4530 struct ib_ucontext *context,
4531 struct ib_udata *udata)
4532{
4533 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4534 struct mlx5_ib_xrcd *xrcd;
4535 int err;
4536
938fe83c 4537 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 4538 return ERR_PTR(-ENOSYS);
4539
4540 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4541 if (!xrcd)
4542 return ERR_PTR(-ENOMEM);
4543
9603b61d 4544 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 4545 if (err) {
4546 kfree(xrcd);
4547 return ERR_PTR(-ENOMEM);
4548 }
4549
4550 return &xrcd->ibxrcd;
4551}
4552
4553int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4554{
4555 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4556 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4557 int err;
4558
9603b61d 4559 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
e126ba97
EC		 4560 if (err) {
4561 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4562 return err;
4563 }
4564
4565 kfree(xrcd);
4566
4567 return 0;
4568}
79b20a6c 4569
350d0e4c
YH		 4570static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4571{
4572 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4573 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4574 struct ib_event event;
4575
4576 if (rwq->ibwq.event_handler) {
4577 event.device = rwq->ibwq.device;
4578 event.element.wq = &rwq->ibwq;
4579 switch (type) {
4580 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4581 event.event = IB_EVENT_WQ_FATAL;
4582 break;
4583 default:
4584 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4585 return;
4586 }
4587
4588 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4589 }
4590}
4591
79b20a6c
YH		 4592static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4593 struct ib_wq_init_attr *init_attr)
4594{
4595 struct mlx5_ib_dev *dev;
4596 __be64 *rq_pas0;
4597 void *in;
4598 void *rqc;
4599 void *wq;
4600 int inlen;
4601 int err;
4602
4603 dev = to_mdev(pd->device);
4604
4605 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4606 in = mlx5_vzalloc(inlen);
4607 if (!in)
4608 return -ENOMEM;
4609
4610 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4611 MLX5_SET(rqc, rqc, mem_rq_type,
4612 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4613 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4614 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4615 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4616 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4617 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4618 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4619 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4620 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4621 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4622 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4623 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4624 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4625 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4626 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4627 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4628 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 4629 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
79b20a6c
YH		 4630 kvfree(in);
4631 return err;
4632}
4633
4634static int set_user_rq_size(struct mlx5_ib_dev *dev,
4635 struct ib_wq_init_attr *wq_init_attr,
4636 struct mlx5_ib_create_wq *ucmd,
4637 struct mlx5_ib_rwq *rwq)
4638{
4639 /* Sanity check RQ size before proceeding */
4640 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4641 return -EINVAL;
4642
4643 if (!ucmd->rq_wqe_count)
4644 return -EINVAL;
4645
4646 rwq->wqe_count = ucmd->rq_wqe_count;
4647 rwq->wqe_shift = ucmd->rq_wqe_shift;
4648 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4649 rwq->log_rq_stride = rwq->wqe_shift;
4650 rwq->log_rq_size = ilog2(rwq->wqe_count);
4651 return 0;
4652}
4653
4654static int prepare_user_rq(struct ib_pd *pd,
4655 struct ib_wq_init_attr *init_attr,
4656 struct ib_udata *udata,
4657 struct mlx5_ib_rwq *rwq)
4658{
4659 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4660 struct mlx5_ib_create_wq ucmd = {};
4661 int err;
4662 size_t required_cmd_sz;
4663
4664 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4665 if (udata->inlen < required_cmd_sz) {
4666 mlx5_ib_dbg(dev, "invalid inlen\n");
4667 return -EINVAL;
4668 }
4669
4670 if (udata->inlen > sizeof(ucmd) &&
4671 !ib_is_udata_cleared(udata, sizeof(ucmd),
4672 udata->inlen - sizeof(ucmd))) {
4673 mlx5_ib_dbg(dev, "inlen is not supported\n");
4674 return -EOPNOTSUPP;
4675 }
4676
4677 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4678 mlx5_ib_dbg(dev, "copy failed\n");
4679 return -EFAULT;
4680 }
4681
4682 if (ucmd.comp_mask) {
4683 mlx5_ib_dbg(dev, "invalid comp mask\n");
4684 return -EOPNOTSUPP;
4685 }
4686
4687 if (ucmd.reserved) {
4688 mlx5_ib_dbg(dev, "invalid reserved\n");
4689 return -EOPNOTSUPP;
4690 }
4691
4692 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4693 if (err) {
4694 mlx5_ib_dbg(dev, "err %d\n", err);
4695 return err;
4696 }
4697
4698 err = create_user_rq(dev, pd, rwq, &ucmd);
4699 if (err) {
4700 mlx5_ib_dbg(dev, "err %d\n", err);
4701 if (err)
4702 return err;
4703 }
4704
4705 rwq->user_index = ucmd.user_index;
4706 return 0;
4707}
4708
4709struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4710 struct ib_wq_init_attr *init_attr,
4711 struct ib_udata *udata)
4712{
4713 struct mlx5_ib_dev *dev;
4714 struct mlx5_ib_rwq *rwq;
4715 struct mlx5_ib_create_wq_resp resp = {};
4716 size_t min_resp_len;
4717 int err;
4718
4719 if (!udata)
4720 return ERR_PTR(-ENOSYS);
4721
4722 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4723 if (udata->outlen && udata->outlen < min_resp_len)
4724 return ERR_PTR(-EINVAL);
4725
4726 dev = to_mdev(pd->device);
4727 switch (init_attr->wq_type) {
4728 case IB_WQT_RQ:
4729 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4730 if (!rwq)
4731 return ERR_PTR(-ENOMEM);
4732 err = prepare_user_rq(pd, init_attr, udata, rwq);
4733 if (err)
4734 goto err;
4735 err = create_rq(rwq, pd, init_attr);
4736 if (err)
4737 goto err_user_rq;
4738 break;
4739 default:
4740 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4741 init_attr->wq_type);
4742 return ERR_PTR(-EINVAL);
4743 }
4744
350d0e4c 4745 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 4746 rwq->ibwq.state = IB_WQS_RESET;
4747 if (udata->outlen) {
4748 resp.response_length = offsetof(typeof(resp), response_length) +
4749 sizeof(resp.response_length);
4750 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4751 if (err)
4752 goto err_copy;
4753 }
4754
350d0e4c
YH		 4755 rwq->core_qp.event = mlx5_ib_wq_event;
4756 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 4757 return &rwq->ibwq;
4758
4759err_copy:
350d0e4c 4760 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c
YH		 4761err_user_rq:
4762 destroy_user_rq(pd, rwq);
4763err:
4764 kfree(rwq);
4765 return ERR_PTR(err);
4766}
4767
4768int mlx5_ib_destroy_wq(struct ib_wq *wq)
4769{
4770 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4771 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4772
350d0e4c 4773 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c
YH		 4774 destroy_user_rq(wq->pd, rwq);
4775 kfree(rwq);
4776
4777 return 0;
4778}
4779
c5f90929
YH		 4780struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4781 struct ib_rwq_ind_table_init_attr *init_attr,
4782 struct ib_udata *udata)
4783{
4784 struct mlx5_ib_dev *dev = to_mdev(device);
4785 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4786 int sz = 1 << init_attr->log_ind_tbl_size;
4787 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4788 size_t min_resp_len;
4789 int inlen;
4790 int err;
4791 int i;
4792 u32 *in;
4793 void *rqtc;
4794
4795 if (udata->inlen > 0 &&
4796 !ib_is_udata_cleared(udata, 0,
4797 udata->inlen))
4798 return ERR_PTR(-EOPNOTSUPP);
4799
efd7f400
MG		 4800 if (init_attr->log_ind_tbl_size >
4801 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4802 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4803 init_attr->log_ind_tbl_size,
4804 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4805 return ERR_PTR(-EINVAL);
4806 }
4807
c5f90929
YH		 4808 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4809 if (udata->outlen && udata->outlen < min_resp_len)
4810 return ERR_PTR(-EINVAL);
4811
4812 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4813 if (!rwq_ind_tbl)
4814 return ERR_PTR(-ENOMEM);
4815
4816 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4817 in = mlx5_vzalloc(inlen);
4818 if (!in) {
4819 err = -ENOMEM;
4820 goto err;
4821 }
4822
4823 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4824
4825 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4826 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4827
4828 for (i = 0; i < sz; i++)
4829 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4830
4831 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4832 kvfree(in);
4833
4834 if (err)
4835 goto err;
4836
4837 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4838 if (udata->outlen) {
4839 resp.response_length = offsetof(typeof(resp), response_length) +
4840 sizeof(resp.response_length);
4841 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4842 if (err)
4843 goto err_copy;
4844 }
4845
4846 return &rwq_ind_tbl->ib_rwq_ind_tbl;
4847
4848err_copy:
4849 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4850err:
4851 kfree(rwq_ind_tbl);
4852 return ERR_PTR(err);
4853}
4854
4855int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4856{
4857 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4858 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4859
4860 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4861
4862 kfree(rwq_ind_tbl);
4863 return 0;
4864}
4865
79b20a6c
YH		 4866int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4867 u32 wq_attr_mask, struct ib_udata *udata)
4868{
4869 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4870 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4871 struct mlx5_ib_modify_wq ucmd = {};
4872 size_t required_cmd_sz;
4873 int curr_wq_state;
4874 int wq_state;
4875 int inlen;
4876 int err;
4877 void *rqc;
4878 void *in;
4879
4880 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4881 if (udata->inlen < required_cmd_sz)
4882 return -EINVAL;
4883
4884 if (udata->inlen > sizeof(ucmd) &&
4885 !ib_is_udata_cleared(udata, sizeof(ucmd),
4886 udata->inlen - sizeof(ucmd)))
4887 return -EOPNOTSUPP;
4888
4889 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4890 return -EFAULT;
4891
4892 if (ucmd.comp_mask || ucmd.reserved)
4893 return -EOPNOTSUPP;
4894
4895 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4896 in = mlx5_vzalloc(inlen);
4897 if (!in)
4898 return -ENOMEM;
4899
4900 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4901
4902 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4903 wq_attr->curr_wq_state : wq->state;
4904 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4905 wq_attr->wq_state : curr_wq_state;
4906 if (curr_wq_state == IB_WQS_ERR)
4907 curr_wq_state = MLX5_RQC_STATE_ERR;
4908 if (wq_state == IB_WQS_ERR)
4909 wq_state = MLX5_RQC_STATE_ERR;
4910 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4911 MLX5_SET(rqc, rqc, state, wq_state);
4912
23a6964e
MD		 4913 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
4914 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
4915 MLX5_SET64(modify_rq_in, in, modify_bitmask,
4916 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
4917 MLX5_SET(rqc, rqc, counter_set_id, dev->port->q_cnts.set_id);
4918 } else
4919 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
4920 dev->ib_dev.name);
4921 }
4922
350d0e4c 4923 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 4924 kvfree(in);
4925 if (!err)
4926 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4927
4928 return err;
4929}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git