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IB/mlx5: Enable ECN capable bits for UD RoCE v2 QPs
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
2811ba51 35#include <rdma/ib_cache.h>
cfb5e088 36#include <rdma/ib_user_verbs.h>
c2e53b2c 37#include <linux/mlx5/fs.h>
e126ba97 38#include "mlx5_ib.h"
b96c9dde 39#include "ib_rep.h"
e126ba97
EC		 40
41/* not supported currently */
42static int wq_signature;
43
44enum {
45 MLX5_IB_ACK_REQ_FREQ = 8,
46};
47
48enum {
49 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
51 MLX5_IB_LINK_TYPE_IB = 0,
52 MLX5_IB_LINK_TYPE_ETH = 1
53};
54
55enum {
56 MLX5_IB_SQ_STRIDE = 6,
e126ba97
EC		 57};
58
59static const u32 mlx5_ib_opcode[] = {
60 [IB_WR_SEND] = MLX5_OPCODE_SEND,
f0313965 61 [IB_WR_LSO] = MLX5_OPCODE_LSO,
e126ba97
EC		 62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
8a187ee5 70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
e126ba97
EC		 71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
74};
75
f0313965
ES		 76struct mlx5_wqe_eth_pad {
77 u8 rsvd0[16];
78};
e126ba97 79
eb49ab0c
AV		 80enum raw_qp_set_mask_map {
81 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
7d29f349 82 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
eb49ab0c
AV		 83};
84
0680efa2
AV		 85struct mlx5_modify_raw_qp_param {
86 u16 operation;
eb49ab0c
AV		 87
88 u32 set_mask; /* raw_qp_set_mask_map */
61147f39
BW		 89
90 struct mlx5_rate_limit rl;
91
eb49ab0c 92 u8 rq_q_ctr_id;
0680efa2
AV		 93};
94
89ea94a7
MG		 95static void get_cqs(enum ib_qp_type qp_type,
96 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
97 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
98
e126ba97
EC		 99static int is_qp0(enum ib_qp_type qp_type)
100{
101 return qp_type == IB_QPT_SMI;
102}
103
e126ba97
EC		 104static int is_sqp(enum ib_qp_type qp_type)
105{
106 return is_qp0(qp_type) || is_qp1(qp_type);
107}
108
109static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
110{
111 return mlx5_buf_offset(&qp->buf, offset);
112}
113
114static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
115{
116 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
117}
118
119void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
120{
121 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
122}
123
c1395a2a
HE		 124/**
125 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
126 *
127 * @qp: QP to copy from.
128 * @send: copy from the send queue when non-zero, use the receive queue
129 * otherwise.
130 * @wqe_index: index to start copying from. For send work queues, the
131 * wqe_index is in units of MLX5_SEND_WQE_BB.
132 * For receive work queue, it is the number of work queue
133 * element in the queue.
134 * @buffer: destination buffer.
135 * @length: maximum number of bytes to copy.
136 *
137 * Copies at least a single WQE, but may copy more data.
138 *
139 * Return: the number of bytes copied, or an error code.
140 */
141int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
19098df2 142 void *buffer, u32 length,
143 struct mlx5_ib_qp_base *base)
c1395a2a
HE		 144{
145 struct ib_device *ibdev = qp->ibqp.device;
146 struct mlx5_ib_dev *dev = to_mdev(ibdev);
147 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
148 size_t offset;
149 size_t wq_end;
19098df2 150 struct ib_umem *umem = base->ubuffer.umem;
c1395a2a
HE		 151 u32 first_copy_length;
152 int wqe_length;
153 int ret;
154
155 if (wq->wqe_cnt == 0) {
156 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
157 qp->ibqp.qp_type);
158 return -EINVAL;
159 }
160
161 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
162 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
163
164 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
165 return -EINVAL;
166
167 if (offset > umem->length ||
168 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
169 return -EINVAL;
170
171 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
172 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
173 if (ret)
174 return ret;
175
176 if (send) {
177 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
178 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
179
180 wqe_length = ds * MLX5_WQE_DS_UNITS;
181 } else {
182 wqe_length = 1 << wq->wqe_shift;
183 }
184
185 if (wqe_length <= first_copy_length)
186 return first_copy_length;
187
188 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
189 wqe_length - first_copy_length);
190 if (ret)
191 return ret;
192
193 return wqe_length;
194}
195
e126ba97
EC		 196static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
197{
198 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
199 struct ib_event event;
200
19098df2 201 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
202 /* This event is only valid for trans_qps */
203 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
204 }
e126ba97
EC		 205
206 if (ibqp->event_handler) {
207 event.device = ibqp->device;
208 event.element.qp = ibqp;
209 switch (type) {
210 case MLX5_EVENT_TYPE_PATH_MIG:
211 event.event = IB_EVENT_PATH_MIG;
212 break;
213 case MLX5_EVENT_TYPE_COMM_EST:
214 event.event = IB_EVENT_COMM_EST;
215 break;
216 case MLX5_EVENT_TYPE_SQ_DRAINED:
217 event.event = IB_EVENT_SQ_DRAINED;
218 break;
219 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
220 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
221 break;
222 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
223 event.event = IB_EVENT_QP_FATAL;
224 break;
225 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
226 event.event = IB_EVENT_PATH_MIG_ERR;
227 break;
228 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
229 event.event = IB_EVENT_QP_REQ_ERR;
230 break;
231 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
232 event.event = IB_EVENT_QP_ACCESS_ERR;
233 break;
234 default:
235 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
236 return;
237 }
238
239 ibqp->event_handler(&event, ibqp->qp_context);
240 }
241}
242
243static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
244 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
245{
246 int wqe_size;
247 int wq_size;
248
249 /* Sanity check RQ size before proceeding */
938fe83c 250 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
e126ba97
EC		 251 return -EINVAL;
252
253 if (!has_rq) {
254 qp->rq.max_gs = 0;
255 qp->rq.wqe_cnt = 0;
256 qp->rq.wqe_shift = 0;
0540d814
NO		 257 cap->max_recv_wr = 0;
258 cap->max_recv_sge = 0;
e126ba97
EC		 259 } else {
260 if (ucmd) {
261 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
262 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
263 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
264 qp->rq.max_post = qp->rq.wqe_cnt;
265 } else {
266 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
267 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
268 wqe_size = roundup_pow_of_two(wqe_size);
269 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
270 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
271 qp->rq.wqe_cnt = wq_size / wqe_size;
938fe83c 272 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
e126ba97
EC		 273 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
274 wqe_size,
938fe83c
SM		 275 MLX5_CAP_GEN(dev->mdev,
276 max_wqe_sz_rq));
e126ba97
EC		 277 return -EINVAL;
278 }
279 qp->rq.wqe_shift = ilog2(wqe_size);
280 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
281 qp->rq.max_post = qp->rq.wqe_cnt;
282 }
283 }
284
285 return 0;
286}
287
f0313965 288static int sq_overhead(struct ib_qp_init_attr *attr)
e126ba97 289{
618af384 290 int size = 0;
e126ba97 291
f0313965 292 switch (attr->qp_type) {
e126ba97 293 case IB_QPT_XRC_INI:
b125a54b 294 size += sizeof(struct mlx5_wqe_xrc_seg);
e126ba97
EC		 295 /* fall through */
296 case IB_QPT_RC:
297 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 298 max(sizeof(struct mlx5_wqe_atomic_seg) +
299 sizeof(struct mlx5_wqe_raddr_seg),
300 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
301 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 302 break;
303
b125a54b
EC		 304 case IB_QPT_XRC_TGT:
305 return 0;
306
e126ba97 307 case IB_QPT_UC:
b125a54b 308 size += sizeof(struct mlx5_wqe_ctrl_seg) +
75c1657e
LR		 309 max(sizeof(struct mlx5_wqe_raddr_seg),
310 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
311 sizeof(struct mlx5_mkey_seg));
e126ba97
EC		 312 break;
313
314 case IB_QPT_UD:
f0313965
ES		 315 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
316 size += sizeof(struct mlx5_wqe_eth_pad) +
317 sizeof(struct mlx5_wqe_eth_seg);
318 /* fall through */
e126ba97 319 case IB_QPT_SMI:
d16e91da 320 case MLX5_IB_QPT_HW_GSI:
b125a54b 321 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 322 sizeof(struct mlx5_wqe_datagram_seg);
323 break;
324
325 case MLX5_IB_QPT_REG_UMR:
b125a54b 326 size += sizeof(struct mlx5_wqe_ctrl_seg) +
e126ba97
EC		 327 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
328 sizeof(struct mlx5_mkey_seg);
329 break;
330
331 default:
332 return -EINVAL;
333 }
334
335 return size;
336}
337
338static int calc_send_wqe(struct ib_qp_init_attr *attr)
339{
340 int inl_size = 0;
341 int size;
342
f0313965 343 size = sq_overhead(attr);
e126ba97
EC		 344 if (size < 0)
345 return size;
346
347 if (attr->cap.max_inline_data) {
348 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
349 attr->cap.max_inline_data;
350 }
351
352 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
e1e66cc2
SG		 353 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
354 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
355 return MLX5_SIG_WQE_SIZE;
356 else
357 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
e126ba97
EC		 358}
359
288c01b7
EC		 360static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
361{
362 int max_sge;
363
364 if (attr->qp_type == IB_QPT_RC)
365 max_sge = (min_t(int, wqe_size, 512) -
366 sizeof(struct mlx5_wqe_ctrl_seg) -
367 sizeof(struct mlx5_wqe_raddr_seg)) /
368 sizeof(struct mlx5_wqe_data_seg);
369 else if (attr->qp_type == IB_QPT_XRC_INI)
370 max_sge = (min_t(int, wqe_size, 512) -
371 sizeof(struct mlx5_wqe_ctrl_seg) -
372 sizeof(struct mlx5_wqe_xrc_seg) -
373 sizeof(struct mlx5_wqe_raddr_seg)) /
374 sizeof(struct mlx5_wqe_data_seg);
375 else
376 max_sge = (wqe_size - sq_overhead(attr)) /
377 sizeof(struct mlx5_wqe_data_seg);
378
379 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
380 sizeof(struct mlx5_wqe_data_seg));
381}
382
e126ba97
EC		 383static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
384 struct mlx5_ib_qp *qp)
385{
386 int wqe_size;
387 int wq_size;
388
389 if (!attr->cap.max_send_wr)
390 return 0;
391
392 wqe_size = calc_send_wqe(attr);
393 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
394 if (wqe_size < 0)
395 return wqe_size;
396
938fe83c 397 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
b125a54b 398 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
938fe83c 399 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 400 return -EINVAL;
401 }
402
f0313965
ES		 403 qp->max_inline_data = wqe_size - sq_overhead(attr) -
404 sizeof(struct mlx5_wqe_inline_seg);
e126ba97
EC		 405 attr->cap.max_inline_data = qp->max_inline_data;
406
e1e66cc2
SG		 407 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
408 qp->signature_en = true;
409
e126ba97
EC		 410 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
411 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
938fe83c 412 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
1974ab9d
BVA		 413 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
414 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
938fe83c
SM		 415 qp->sq.wqe_cnt,
416 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
b125a54b
EC		 417 return -ENOMEM;
418 }
e126ba97 419 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
288c01b7
EC		 420 qp->sq.max_gs = get_send_sge(attr, wqe_size);
421 if (qp->sq.max_gs < attr->cap.max_send_sge)
422 return -ENOMEM;
423
424 attr->cap.max_send_sge = qp->sq.max_gs;
b125a54b
EC		 425 qp->sq.max_post = wq_size / wqe_size;
426 attr->cap.max_send_wr = qp->sq.max_post;
e126ba97
EC		 427
428 return wq_size;
429}
430
431static int set_user_buf_size(struct mlx5_ib_dev *dev,
432 struct mlx5_ib_qp *qp,
19098df2 433 struct mlx5_ib_create_qp *ucmd,
0fb2ed66 434 struct mlx5_ib_qp_base *base,
435 struct ib_qp_init_attr *attr)
e126ba97
EC		 436{
437 int desc_sz = 1 << qp->sq.wqe_shift;
438
938fe83c 439 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
e126ba97 440 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
938fe83c 441 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
e126ba97
EC		 442 return -EINVAL;
443 }
444
445 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
446 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
447 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
448 return -EINVAL;
449 }
450
451 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
452
938fe83c 453 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
e126ba97 454 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
938fe83c
SM		 455 qp->sq.wqe_cnt,
456 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
e126ba97
EC		 457 return -EINVAL;
458 }
459
c2e53b2c
YH		 460 if (attr->qp_type == IB_QPT_RAW_PACKET ||
461 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 462 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
463 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
464 } else {
465 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
466 (qp->sq.wqe_cnt << 6);
467 }
e126ba97
EC		 468
469 return 0;
470}
471
472static int qp_has_rq(struct ib_qp_init_attr *attr)
473{
474 if (attr->qp_type == IB_QPT_XRC_INI ||
475 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
476 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
477 !attr->cap.max_recv_wr)
478 return 0;
479
480 return 1;
481}
482
2f5ff264 483static int first_med_bfreg(void)
c1be5232
EC		 484{
485 return 1;
486}
487
0b80c14f
EC		 488enum {
489 /* this is the first blue flame register in the array of bfregs assigned
490 * to a processes. Since we do not use it for blue flame but rather
491 * regular 64 bit doorbells, we do not need a lock for maintaiing
492 * "odd/even" order
493 */
494 NUM_NON_BLUE_FLAME_BFREGS = 1,
495};
496
b037c29a
EC		 497static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
498{
31a78a5a 499 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a
EC		 500}
501
502static int num_med_bfreg(struct mlx5_ib_dev *dev,
503 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 504{
505 int n;
506
b037c29a
EC		 507 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
508 NUM_NON_BLUE_FLAME_BFREGS;
c1be5232
EC		 509
510 return n >= 0 ? n : 0;
511}
512
b037c29a
EC		 513static int first_hi_bfreg(struct mlx5_ib_dev *dev,
514 struct mlx5_bfreg_info *bfregi)
c1be5232
EC		 515{
516 int med;
c1be5232 517
b037c29a
EC		 518 med = num_med_bfreg(dev, bfregi);
519 return ++med;
c1be5232
EC		 520}
521
b037c29a
EC		 522static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
523 struct mlx5_bfreg_info *bfregi)
e126ba97 524{
e126ba97
EC		 525 int i;
526
b037c29a
EC		 527 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
528 if (!bfregi->count[i]) {
2f5ff264 529 bfregi->count[i]++;
e126ba97
EC		 530 return i;
531 }
532 }
533
534 return -ENOMEM;
535}
536
b037c29a
EC		 537static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
538 struct mlx5_bfreg_info *bfregi)
e126ba97 539{
2f5ff264 540 int minidx = first_med_bfreg();
e126ba97
EC		 541 int i;
542
b037c29a 543 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
2f5ff264 544 if (bfregi->count[i] < bfregi->count[minidx])
e126ba97 545 minidx = i;
0b80c14f
EC		 546 if (!bfregi->count[minidx])
547 break;
e126ba97
EC		 548 }
549
2f5ff264 550 bfregi->count[minidx]++;
e126ba97
EC		 551 return minidx;
552}
553
b037c29a
EC		 554static int alloc_bfreg(struct mlx5_ib_dev *dev,
555 struct mlx5_bfreg_info *bfregi,
2f5ff264 556 enum mlx5_ib_latency_class lat)
e126ba97 557{
2f5ff264 558 int bfregn = -EINVAL;
e126ba97 559
2f5ff264 560 mutex_lock(&bfregi->lock);
e126ba97
EC		 561 switch (lat) {
562 case MLX5_IB_LATENCY_CLASS_LOW:
0b80c14f 563 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
2f5ff264
EC		 564 bfregn = 0;
565 bfregi->count[bfregn]++;
e126ba97
EC		 566 break;
567
568 case MLX5_IB_LATENCY_CLASS_MEDIUM:
2f5ff264
EC		 569 if (bfregi->ver < 2)
570 bfregn = -ENOMEM;
78c0f98c 571 else
b037c29a 572 bfregn = alloc_med_class_bfreg(dev, bfregi);
e126ba97
EC		 573 break;
574
575 case MLX5_IB_LATENCY_CLASS_HIGH:
2f5ff264
EC		 576 if (bfregi->ver < 2)
577 bfregn = -ENOMEM;
78c0f98c 578 else
b037c29a 579 bfregn = alloc_high_class_bfreg(dev, bfregi);
e126ba97
EC		 580 break;
581 }
2f5ff264 582 mutex_unlock(&bfregi->lock);
e126ba97 583
2f5ff264 584 return bfregn;
e126ba97
EC		 585}
586
4ed131d0 587void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
e126ba97 588{
2f5ff264 589 mutex_lock(&bfregi->lock);
b037c29a 590 bfregi->count[bfregn]--;
2f5ff264 591 mutex_unlock(&bfregi->lock);
e126ba97
EC		 592}
593
594static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
595{
596 switch (state) {
597 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
598 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
599 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
600 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
601 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
602 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
603 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
604 default: return -1;
605 }
606}
607
608static int to_mlx5_st(enum ib_qp_type type)
609{
610 switch (type) {
611 case IB_QPT_RC: return MLX5_QP_ST_RC;
612 case IB_QPT_UC: return MLX5_QP_ST_UC;
613 case IB_QPT_UD: return MLX5_QP_ST_UD;
614 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
615 case IB_QPT_XRC_INI:
616 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
617 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
d16e91da 618 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
c32a4f29 619 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
e126ba97 620 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
e126ba97 621 case IB_QPT_RAW_PACKET:
0fb2ed66 622 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
e126ba97
EC		 623 case IB_QPT_MAX:
624 default: return -EINVAL;
625 }
626}
627
89ea94a7
MG		 628static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
629 struct mlx5_ib_cq *recv_cq);
630static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
631 struct mlx5_ib_cq *recv_cq);
632
b037c29a 633static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1ee47ab3
YH		 634 struct mlx5_bfreg_info *bfregi, int bfregn,
635 bool dyn_bfreg)
e126ba97 636{
b037c29a
EC		 637 int bfregs_per_sys_page;
638 int index_of_sys_page;
639 int offset;
640
641 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
642 MLX5_NON_FP_BFREGS_PER_UAR;
643 index_of_sys_page = bfregn / bfregs_per_sys_page;
644
1ee47ab3
YH		 645 if (dyn_bfreg) {
646 index_of_sys_page += bfregi->num_static_sys_pages;
647 if (bfregn > bfregi->num_dyn_bfregs ||
648 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
649 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
650 return -EINVAL;
651 }
652 }
b037c29a 653
1ee47ab3 654 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
b037c29a 655 return bfregi->sys_pages[index_of_sys_page] + offset;
e126ba97
EC		 656}
657
19098df2 658static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
659 struct ib_pd *pd,
660 unsigned long addr, size_t size,
661 struct ib_umem **umem,
662 int *npages, int *page_shift, int *ncont,
663 u32 *offset)
664{
665 int err;
666
667 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
668 if (IS_ERR(*umem)) {
669 mlx5_ib_dbg(dev, "umem_get failed\n");
670 return PTR_ERR(*umem);
671 }
672
762f899a 673 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
19098df2 674
675 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
676 if (err) {
677 mlx5_ib_warn(dev, "bad offset\n");
678 goto err_umem;
679 }
680
681 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
682 addr, size, *npages, *page_shift, *ncont, *offset);
683
684 return 0;
685
686err_umem:
687 ib_umem_release(*umem);
688 *umem = NULL;
689
690 return err;
691}
692
fe248c3a
MG		 693static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
694 struct mlx5_ib_rwq *rwq)
79b20a6c
YH		 695{
696 struct mlx5_ib_ucontext *context;
697
fe248c3a
MG		 698 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
699 atomic_dec(&dev->delay_drop.rqs_cnt);
700
79b20a6c
YH		 701 context = to_mucontext(pd->uobject->context);
702 mlx5_ib_db_unmap_user(context, &rwq->db);
703 if (rwq->umem)
704 ib_umem_release(rwq->umem);
705}
706
707static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
708 struct mlx5_ib_rwq *rwq,
709 struct mlx5_ib_create_wq *ucmd)
710{
711 struct mlx5_ib_ucontext *context;
712 int page_shift = 0;
713 int npages;
714 u32 offset = 0;
715 int ncont = 0;
716 int err;
717
718 if (!ucmd->buf_addr)
719 return -EINVAL;
720
721 context = to_mucontext(pd->uobject->context);
722 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
723 rwq->buf_size, 0, 0);
724 if (IS_ERR(rwq->umem)) {
725 mlx5_ib_dbg(dev, "umem_get failed\n");
726 err = PTR_ERR(rwq->umem);
727 return err;
728 }
729
762f899a 730 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
79b20a6c
YH		 731 &ncont, NULL);
732 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
733 &rwq->rq_page_offset);
734 if (err) {
735 mlx5_ib_warn(dev, "bad offset\n");
736 goto err_umem;
737 }
738
739 rwq->rq_num_pas = ncont;
740 rwq->page_shift = page_shift;
741 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
742 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
743
744 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
745 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
746 npages, page_shift, ncont, offset);
747
748 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
749 if (err) {
750 mlx5_ib_dbg(dev, "map failed\n");
751 goto err_umem;
752 }
753
754 rwq->create_type = MLX5_WQ_USER;
755 return 0;
756
757err_umem:
758 ib_umem_release(rwq->umem);
759 return err;
760}
761
b037c29a
EC		 762static int adjust_bfregn(struct mlx5_ib_dev *dev,
763 struct mlx5_bfreg_info *bfregi, int bfregn)
764{
765 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
766 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
767}
768
e126ba97
EC		 769static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
770 struct mlx5_ib_qp *qp, struct ib_udata *udata,
0fb2ed66 771 struct ib_qp_init_attr *attr,
09a7d9ec 772 u32 **in,
19098df2 773 struct mlx5_ib_create_qp_resp *resp, int *inlen,
774 struct mlx5_ib_qp_base *base)
e126ba97
EC		 775{
776 struct mlx5_ib_ucontext *context;
777 struct mlx5_ib_create_qp ucmd;
19098df2 778 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
9e9c47d0 779 int page_shift = 0;
1ee47ab3 780 int uar_index = 0;
e126ba97 781 int npages;
9e9c47d0 782 u32 offset = 0;
2f5ff264 783 int bfregn;
9e9c47d0 784 int ncont = 0;
09a7d9ec
SM		 785 __be64 *pas;
786 void *qpc;
e126ba97
EC		 787 int err;
788
789 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
790 if (err) {
791 mlx5_ib_dbg(dev, "copy failed\n");
792 return err;
793 }
794
795 context = to_mucontext(pd->uobject->context);
1ee47ab3
YH		 796 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
797 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
798 ucmd.bfreg_index, true);
799 if (uar_index < 0)
800 return uar_index;
801
802 bfregn = MLX5_IB_INVALID_BFREG;
803 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
804 /*
805 * TBD: should come from the verbs when we have the API
806 */
051f2630 807 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
2f5ff264 808 bfregn = MLX5_CROSS_CHANNEL_BFREG;
1ee47ab3 809 }
051f2630 810 else {
b037c29a 811 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
2f5ff264
EC		 812 if (bfregn < 0) {
813 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
051f2630 814 mlx5_ib_dbg(dev, "reverting to medium latency\n");
b037c29a 815 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
2f5ff264
EC		 816 if (bfregn < 0) {
817 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
051f2630 818 mlx5_ib_dbg(dev, "reverting to high latency\n");
b037c29a 819 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
2f5ff264
EC		 820 if (bfregn < 0) {
821 mlx5_ib_warn(dev, "bfreg allocation failed\n");
822 return bfregn;
051f2630 823 }
c1be5232 824 }
e126ba97
EC		 825 }
826 }
827
2f5ff264 828 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
1ee47ab3
YH		 829 if (bfregn != MLX5_IB_INVALID_BFREG)
830 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
831 false);
e126ba97 832
48fea837
HE		 833 qp->rq.offset = 0;
834 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
835 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
836
0fb2ed66 837 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
e126ba97 838 if (err)
2f5ff264 839 goto err_bfreg;
e126ba97 840
19098df2 841 if (ucmd.buf_addr && ubuffer->buf_size) {
842 ubuffer->buf_addr = ucmd.buf_addr;
843 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
844 ubuffer->buf_size,
845 &ubuffer->umem, &npages, &page_shift,
846 &ncont, &offset);
847 if (err)
2f5ff264 848 goto err_bfreg;
9e9c47d0 849 } else {
19098df2 850 ubuffer->umem = NULL;
e126ba97 851 }
e126ba97 852
09a7d9ec
SM		 853 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
854 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
1b9a07ee 855 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 856 if (!*in) {
857 err = -ENOMEM;
858 goto err_umem;
859 }
09a7d9ec
SM		 860
861 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
19098df2 862 if (ubuffer->umem)
09a7d9ec
SM		 863 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
864
865 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
866
867 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
868 MLX5_SET(qpc, qpc, page_offset, offset);
e126ba97 869
09a7d9ec 870 MLX5_SET(qpc, qpc, uar_page, uar_index);
1ee47ab3
YH		 871 if (bfregn != MLX5_IB_INVALID_BFREG)
872 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
873 else
874 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
2f5ff264 875 qp->bfregn = bfregn;
e126ba97
EC		 876
877 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
878 if (err) {
879 mlx5_ib_dbg(dev, "map failed\n");
880 goto err_free;
881 }
882
883 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
884 if (err) {
885 mlx5_ib_dbg(dev, "copy failed\n");
886 goto err_unmap;
887 }
888 qp->create_type = MLX5_QP_USER;
889
890 return 0;
891
892err_unmap:
893 mlx5_ib_db_unmap_user(context, &qp->db);
894
895err_free:
479163f4 896 kvfree(*in);
e126ba97
EC		 897
898err_umem:
19098df2 899 if (ubuffer->umem)
900 ib_umem_release(ubuffer->umem);
e126ba97 901
2f5ff264 902err_bfreg:
1ee47ab3
YH		 903 if (bfregn != MLX5_IB_INVALID_BFREG)
904 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
e126ba97
EC		 905 return err;
906}
907
b037c29a
EC		 908static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
909 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
e126ba97
EC		 910{
911 struct mlx5_ib_ucontext *context;
912
913 context = to_mucontext(pd->uobject->context);
914 mlx5_ib_db_unmap_user(context, &qp->db);
19098df2 915 if (base->ubuffer.umem)
916 ib_umem_release(base->ubuffer.umem);
1ee47ab3
YH		 917
918 /*
919 * Free only the BFREGs which are handled by the kernel.
920 * BFREGs of UARs allocated dynamically are handled by user.
921 */
922 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
923 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
e126ba97
EC		 924}
925
926static int create_kernel_qp(struct mlx5_ib_dev *dev,
927 struct ib_qp_init_attr *init_attr,
928 struct mlx5_ib_qp *qp,
09a7d9ec 929 u32 **in, int *inlen,
19098df2 930 struct mlx5_ib_qp_base *base)
e126ba97 931{
e126ba97 932 int uar_index;
09a7d9ec 933 void *qpc;
e126ba97
EC		 934 int err;
935
f0313965
ES		 936 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
937 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
b11a4f9c 938 IB_QP_CREATE_IPOIB_UD_LSO |
93d576af 939 IB_QP_CREATE_NETIF_QP |
b11a4f9c 940 mlx5_ib_create_qp_sqpn_qp1()))
1a4c3a3d 941 return -EINVAL;
e126ba97
EC		 942
943 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
5fe9dec0
EC		 944 qp->bf.bfreg = &dev->fp_bfreg;
945 else
946 qp->bf.bfreg = &dev->bfreg;
e126ba97 947
d8030b0d
EC		 948 /* We need to divide by two since each register is comprised of
949 * two buffers of identical size, namely odd and even
950 */
951 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
5fe9dec0 952 uar_index = qp->bf.bfreg->index;
e126ba97
EC		 953
954 err = calc_sq_size(dev, init_attr, qp);
955 if (err < 0) {
956 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 957 return err;
e126ba97
EC		 958 }
959
960 qp->rq.offset = 0;
961 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
19098df2 962 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
e126ba97 963
19098df2 964 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
e126ba97
EC		 965 if (err) {
966 mlx5_ib_dbg(dev, "err %d\n", err);
5fe9dec0 967 return err;
e126ba97
EC		 968 }
969
970 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
09a7d9ec
SM		 971 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
972 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
1b9a07ee 973 *in = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 974 if (!*in) {
975 err = -ENOMEM;
976 goto err_buf;
977 }
09a7d9ec
SM		 978
979 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
980 MLX5_SET(qpc, qpc, uar_page, uar_index);
981 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
982
e126ba97 983 /* Set "fast registration enabled" for all kernel QPs */
09a7d9ec
SM		 984 MLX5_SET(qpc, qpc, fre, 1);
985 MLX5_SET(qpc, qpc, rlky, 1);
e126ba97 986
b11a4f9c 987 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
09a7d9ec 988 MLX5_SET(qpc, qpc, deth_sqpn, 1);
b11a4f9c
HE		 989 qp->flags |= MLX5_IB_QP_SQPN_QP1;
990 }
991
09a7d9ec
SM		 992 mlx5_fill_page_array(&qp->buf,
993 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
e126ba97 994
9603b61d 995 err = mlx5_db_alloc(dev->mdev, &qp->db);
e126ba97
EC		 996 if (err) {
997 mlx5_ib_dbg(dev, "err %d\n", err);
998 goto err_free;
999 }
1000
b5883008
LD		 1001 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1002 sizeof(*qp->sq.wrid), GFP_KERNEL);
1003 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1004 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1005 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1006 sizeof(*qp->rq.wrid), GFP_KERNEL);
1007 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1008 sizeof(*qp->sq.w_list), GFP_KERNEL);
1009 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1010 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
e126ba97
EC		 1011
1012 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1013 !qp->sq.w_list || !qp->sq.wqe_head) {
1014 err = -ENOMEM;
1015 goto err_wrid;
1016 }
1017 qp->create_type = MLX5_QP_KERNEL;
1018
1019 return 0;
1020
1021err_wrid:
b5883008
LD		 1022 kvfree(qp->sq.wqe_head);
1023 kvfree(qp->sq.w_list);
1024 kvfree(qp->sq.wrid);
1025 kvfree(qp->sq.wr_data);
1026 kvfree(qp->rq.wrid);
f4044dac 1027 mlx5_db_free(dev->mdev, &qp->db);
e126ba97
EC		 1028
1029err_free:
479163f4 1030 kvfree(*in);
e126ba97
EC		 1031
1032err_buf:
9603b61d 1033 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1034 return err;
1035}
1036
1037static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1038{
b5883008
LD		 1039 kvfree(qp->sq.wqe_head);
1040 kvfree(qp->sq.w_list);
1041 kvfree(qp->sq.wrid);
1042 kvfree(qp->sq.wr_data);
1043 kvfree(qp->rq.wrid);
f4044dac 1044 mlx5_db_free(dev->mdev, &qp->db);
9603b61d 1045 mlx5_buf_free(dev->mdev, &qp->buf);
e126ba97
EC		 1046}
1047
09a7d9ec 1048static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
e126ba97
EC		 1049{
1050 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
c32a4f29 1051 (attr->qp_type == MLX5_IB_QPT_DCI) ||
e126ba97 1052 (attr->qp_type == IB_QPT_XRC_INI))
09a7d9ec 1053 return MLX5_SRQ_RQ;
e126ba97 1054 else if (!qp->has_rq)
09a7d9ec 1055 return MLX5_ZERO_LEN_RQ;
e126ba97 1056 else
09a7d9ec 1057 return MLX5_NON_ZERO_RQ;
e126ba97
EC		 1058}
1059
1060static int is_connected(enum ib_qp_type qp_type)
1061{
1062 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1063 return 1;
1064
1065 return 0;
1066}
1067
0fb2ed66 1068static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
c2e53b2c 1069 struct mlx5_ib_qp *qp,
0fb2ed66 1070 struct mlx5_ib_sq *sq, u32 tdn)
1071{
c4f287c4 1072 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
0fb2ed66 1073 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1074
0fb2ed66 1075 MLX5_SET(tisc, tisc, transport_domain, tdn);
c2e53b2c
YH		 1076 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1077 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1078
0fb2ed66 1079 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1080}
1081
1082static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1083 struct mlx5_ib_sq *sq)
1084{
1085 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1086}
1087
b96c9dde
MB		 1088static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1089 struct mlx5_ib_sq *sq)
1090{
1091 if (sq->flow_rule)
1092 mlx5_del_flow_rules(sq->flow_rule);
1093}
1094
0fb2ed66 1095static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1096 struct mlx5_ib_sq *sq, void *qpin,
1097 struct ib_pd *pd)
1098{
1099 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1100 __be64 *pas;
1101 void *in;
1102 void *sqc;
1103 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1104 void *wq;
1105 int inlen;
1106 int err;
1107 int page_shift = 0;
1108 int npages;
1109 int ncont = 0;
1110 u32 offset = 0;
1111
1112 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1113 &sq->ubuffer.umem, &npages, &page_shift,
1114 &ncont, &offset);
1115 if (err)
1116 return err;
1117
1118 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1b9a07ee 1119 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1120 if (!in) {
1121 err = -ENOMEM;
1122 goto err_umem;
1123 }
1124
1125 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1126 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
795b609c
BW		 1127 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1128 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
0fb2ed66 1129 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1130 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1131 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1132 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1133 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
96dc3fc5
NO		 1134 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1135 MLX5_CAP_ETH(dev->mdev, swp))
1136 MLX5_SET(sqc, sqc, allow_swp, 1);
0fb2ed66 1137
1138 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1139 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1140 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1141 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1142 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1143 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1144 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1145 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1146 MLX5_SET(wq, wq, page_offset, offset);
1147
1148 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1149 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1150
1151 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1152
1153 kvfree(in);
1154
1155 if (err)
1156 goto err_umem;
1157
b96c9dde
MB		 1158 err = create_flow_rule_vport_sq(dev, sq);
1159 if (err)
1160 goto err_flow;
1161
0fb2ed66 1162 return 0;
1163
b96c9dde
MB		 1164err_flow:
1165 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1166
0fb2ed66 1167err_umem:
1168 ib_umem_release(sq->ubuffer.umem);
1169 sq->ubuffer.umem = NULL;
1170
1171 return err;
1172}
1173
1174static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1175 struct mlx5_ib_sq *sq)
1176{
b96c9dde 1177 destroy_flow_rule_vport_sq(dev, sq);
0fb2ed66 1178 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1179 ib_umem_release(sq->ubuffer.umem);
1180}
1181
2c292dbb 1182static size_t get_rq_pas_size(void *qpc)
0fb2ed66 1183{
1184 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1185 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1186 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1187 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1188 u32 po_quanta = 1 << (log_page_size - 6);
1189 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1190 u32 page_size = 1 << log_page_size;
1191 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1192 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1193
1194 return rq_num_pas * sizeof(u64);
1195}
1196
1197static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2c292dbb
BP		 1198 struct mlx5_ib_rq *rq, void *qpin,
1199 size_t qpinlen)
0fb2ed66 1200{
358e42ea 1201 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
0fb2ed66 1202 __be64 *pas;
1203 __be64 *qp_pas;
1204 void *in;
1205 void *rqc;
1206 void *wq;
1207 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
2c292dbb
BP		 1208 size_t rq_pas_size = get_rq_pas_size(qpc);
1209 size_t inlen;
0fb2ed66 1210 int err;
2c292dbb
BP		 1211
1212 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1213 return -EINVAL;
0fb2ed66 1214
1215 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1b9a07ee 1216 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1217 if (!in)
1218 return -ENOMEM;
1219
1220 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
e4cc4fa7
NO		 1221 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1222 MLX5_SET(rqc, rqc, vsd, 1);
0fb2ed66 1223 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1224 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1225 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1226 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1227 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1228
358e42ea
MD		 1229 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1230 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1231
0fb2ed66 1232 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1233 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 1234 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1235 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
0fb2ed66 1236 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1237 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1238 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1239 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1240 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1241 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1242
1243 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1244 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1245 memcpy(pas, qp_pas, rq_pas_size);
1246
1247 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1248
1249 kvfree(in);
1250
1251 return err;
1252}
1253
1254static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1255 struct mlx5_ib_rq *rq)
1256{
1257 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1258}
1259
f95ef6cb
MG		 1260static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1261{
1262 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1263 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1264 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1265}
1266
0fb2ed66 1267static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
f95ef6cb
MG		 1268 struct mlx5_ib_rq *rq, u32 tdn,
1269 bool tunnel_offload_en)
0fb2ed66 1270{
1271 u32 *in;
1272 void *tirc;
1273 int inlen;
1274 int err;
1275
1276 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1277 in = kvzalloc(inlen, GFP_KERNEL);
0fb2ed66 1278 if (!in)
1279 return -ENOMEM;
1280
1281 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1282 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1283 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1284 MLX5_SET(tirc, tirc, transport_domain, tdn);
f95ef6cb
MG		 1285 if (tunnel_offload_en)
1286 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
0fb2ed66 1287
ec9c2fb8
MB		 1288 if (dev->rep)
1289 MLX5_SET(tirc, tirc, self_lb_block,
1290 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1291
0fb2ed66 1292 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1293
1294 kvfree(in);
1295
1296 return err;
1297}
1298
1299static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1300 struct mlx5_ib_rq *rq)
1301{
1302 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1303}
1304
1305static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2c292dbb 1306 u32 *in, size_t inlen,
0fb2ed66 1307 struct ib_pd *pd)
1308{
1309 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1310 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1311 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1312 struct ib_uobject *uobj = pd->uobject;
1313 struct ib_ucontext *ucontext = uobj->context;
1314 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1315 int err;
1316 u32 tdn = mucontext->tdn;
1317
1318 if (qp->sq.wqe_cnt) {
c2e53b2c 1319 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
0fb2ed66 1320 if (err)
1321 return err;
1322
1323 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1324 if (err)
1325 goto err_destroy_tis;
1326
1327 sq->base.container_mibqp = qp;
1d31e9c0 1328 sq->base.mqp.event = mlx5_ib_qp_event;
0fb2ed66 1329 }
1330
1331 if (qp->rq.wqe_cnt) {
358e42ea
MD		 1332 rq->base.container_mibqp = qp;
1333
e4cc4fa7
NO		 1334 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1335 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
b1383aa6
NO		 1336 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1337 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
2c292dbb 1338 err = create_raw_packet_qp_rq(dev, rq, in, inlen);
0fb2ed66 1339 if (err)
1340 goto err_destroy_sq;
1341
0fb2ed66 1342
f95ef6cb
MG		 1343 err = create_raw_packet_qp_tir(dev, rq, tdn,
1344 qp->tunnel_offload_en);
0fb2ed66 1345 if (err)
1346 goto err_destroy_rq;
1347 }
1348
1349 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1350 rq->base.mqp.qpn;
1351
1352 return 0;
1353
1354err_destroy_rq:
1355 destroy_raw_packet_qp_rq(dev, rq);
1356err_destroy_sq:
1357 if (!qp->sq.wqe_cnt)
1358 return err;
1359 destroy_raw_packet_qp_sq(dev, sq);
1360err_destroy_tis:
1361 destroy_raw_packet_qp_tis(dev, sq);
1362
1363 return err;
1364}
1365
1366static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1367 struct mlx5_ib_qp *qp)
1368{
1369 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1370 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1371 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1372
1373 if (qp->rq.wqe_cnt) {
1374 destroy_raw_packet_qp_tir(dev, rq);
1375 destroy_raw_packet_qp_rq(dev, rq);
1376 }
1377
1378 if (qp->sq.wqe_cnt) {
1379 destroy_raw_packet_qp_sq(dev, sq);
1380 destroy_raw_packet_qp_tis(dev, sq);
1381 }
1382}
1383
1384static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1385 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1386{
1387 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1388 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1389
1390 sq->sq = &qp->sq;
1391 rq->rq = &qp->rq;
1392 sq->doorbell = &qp->db;
1393 rq->doorbell = &qp->db;
1394}
1395
28d61370
YH		 1396static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1397{
1398 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1399}
1400
1401static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1402 struct ib_pd *pd,
1403 struct ib_qp_init_attr *init_attr,
1404 struct ib_udata *udata)
1405{
1406 struct ib_uobject *uobj = pd->uobject;
1407 struct ib_ucontext *ucontext = uobj->context;
1408 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1409 struct mlx5_ib_create_qp_resp resp = {};
1410 int inlen;
1411 int err;
1412 u32 *in;
1413 void *tirc;
1414 void *hfso;
1415 u32 selected_fields = 0;
1416 size_t min_resp_len;
1417 u32 tdn = mucontext->tdn;
1418 struct mlx5_ib_create_qp_rss ucmd = {};
1419 size_t required_cmd_sz;
1420
1421 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1422 return -EOPNOTSUPP;
1423
1424 if (init_attr->create_flags || init_attr->send_cq)
1425 return -EINVAL;
1426
2f5ff264 1427 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
28d61370
YH		 1428 if (udata->outlen < min_resp_len)
1429 return -EINVAL;
1430
f95ef6cb 1431 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
28d61370
YH		 1432 if (udata->inlen < required_cmd_sz) {
1433 mlx5_ib_dbg(dev, "invalid inlen\n");
1434 return -EINVAL;
1435 }
1436
1437 if (udata->inlen > sizeof(ucmd) &&
1438 !ib_is_udata_cleared(udata, sizeof(ucmd),
1439 udata->inlen - sizeof(ucmd))) {
1440 mlx5_ib_dbg(dev, "inlen is not supported\n");
1441 return -EOPNOTSUPP;
1442 }
1443
1444 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1445 mlx5_ib_dbg(dev, "copy failed\n");
1446 return -EFAULT;
1447 }
1448
1449 if (ucmd.comp_mask) {
1450 mlx5_ib_dbg(dev, "invalid comp mask\n");
1451 return -EOPNOTSUPP;
1452 }
1453
f95ef6cb
MG		 1454 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1455 mlx5_ib_dbg(dev, "invalid flags\n");
1456 return -EOPNOTSUPP;
1457 }
1458
1459 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1460 !tunnel_offload_supported(dev->mdev)) {
1461 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
28d61370
YH		 1462 return -EOPNOTSUPP;
1463 }
1464
309fa347
MG		 1465 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1466 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1467 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1468 return -EOPNOTSUPP;
1469 }
1470
28d61370
YH		 1471 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1472 if (err) {
1473 mlx5_ib_dbg(dev, "copy failed\n");
1474 return -EINVAL;
1475 }
1476
1477 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 1478 in = kvzalloc(inlen, GFP_KERNEL);
28d61370
YH		 1479 if (!in)
1480 return -ENOMEM;
1481
1482 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1483 MLX5_SET(tirc, tirc, disp_type,
1484 MLX5_TIRC_DISP_TYPE_INDIRECT);
1485 MLX5_SET(tirc, tirc, indirect_table,
1486 init_attr->rwq_ind_tbl->ind_tbl_num);
1487 MLX5_SET(tirc, tirc, transport_domain, tdn);
1488
1489 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
f95ef6cb
MG		 1490
1491 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1492 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1493
309fa347
MG		 1494 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1495 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1496 else
1497 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1498
28d61370
YH		 1499 switch (ucmd.rx_hash_function) {
1500 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1501 {
1502 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1503 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1504
1505 if (len != ucmd.rx_key_len) {
1506 err = -EINVAL;
1507 goto err;
1508 }
1509
1510 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1511 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1512 memcpy(rss_key, ucmd.rx_hash_key, len);
1513 break;
1514 }
1515 default:
1516 err = -EOPNOTSUPP;
1517 goto err;
1518 }
1519
1520 if (!ucmd.rx_hash_fields_mask) {
1521 /* special case when this TIR serves as steering entry without hashing */
1522 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1523 goto create_tir;
1524 err = -EINVAL;
1525 goto err;
1526 }
1527
1528 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1529 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1530 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1531 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1532 err = -EINVAL;
1533 goto err;
1534 }
1535
1536 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1537 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1538 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1539 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1540 MLX5_L3_PROT_TYPE_IPV4);
1541 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1542 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1543 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1544 MLX5_L3_PROT_TYPE_IPV6);
1545
1546 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1547 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1548 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1549 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1550 err = -EINVAL;
1551 goto err;
1552 }
1553
1554 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1555 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1556 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1557 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1558 MLX5_L4_PROT_TYPE_TCP);
1559 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1560 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1561 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1562 MLX5_L4_PROT_TYPE_UDP);
1563
1564 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1565 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1566 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1567
1568 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1569 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1570 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1571
1572 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1573 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1574 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1575
1576 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1577 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1578 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1579
1580 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1581
1582create_tir:
ec9c2fb8
MB		 1583 if (dev->rep)
1584 MLX5_SET(tirc, tirc, self_lb_block,
1585 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1586
28d61370
YH		 1587 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1588
1589 if (err)
1590 goto err;
1591
1592 kvfree(in);
1593 /* qpn is reserved for that QP */
1594 qp->trans_qp.base.mqp.qpn = 0;
d9f88e5a 1595 qp->flags |= MLX5_IB_QP_RSS;
28d61370
YH		 1596 return 0;
1597
1598err:
1599 kvfree(in);
1600 return err;
1601}
1602
e126ba97
EC		 1603static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1604 struct ib_qp_init_attr *init_attr,
1605 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1606{
1607 struct mlx5_ib_resources *devr = &dev->devr;
09a7d9ec 1608 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
938fe83c 1609 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1610 struct mlx5_ib_create_qp_resp resp;
89ea94a7
MG		 1611 struct mlx5_ib_cq *send_cq;
1612 struct mlx5_ib_cq *recv_cq;
1613 unsigned long flags;
cfb5e088 1614 u32 uidx = MLX5_IB_DEFAULT_UIDX;
09a7d9ec
SM		 1615 struct mlx5_ib_create_qp ucmd;
1616 struct mlx5_ib_qp_base *base;
e7b169f3 1617 int mlx5_st;
cfb5e088 1618 void *qpc;
09a7d9ec
SM		 1619 u32 *in;
1620 int err;
e126ba97
EC		 1621
1622 mutex_init(&qp->mutex);
1623 spin_lock_init(&qp->sq.lock);
1624 spin_lock_init(&qp->rq.lock);
1625
e7b169f3
NO		 1626 mlx5_st = to_mlx5_st(init_attr->qp_type);
1627 if (mlx5_st < 0)
1628 return -EINVAL;
1629
28d61370
YH		 1630 if (init_attr->rwq_ind_tbl) {
1631 if (!udata)
1632 return -ENOSYS;
1633
1634 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1635 return err;
1636 }
1637
f360d88a 1638 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
938fe83c 1639 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
f360d88a
EC		 1640 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1641 return -EINVAL;
1642 } else {
1643 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1644 }
1645 }
1646
051f2630
LR		 1647 if (init_attr->create_flags &
1648 (IB_QP_CREATE_CROSS_CHANNEL |
1649 IB_QP_CREATE_MANAGED_SEND |
1650 IB_QP_CREATE_MANAGED_RECV)) {
1651 if (!MLX5_CAP_GEN(mdev, cd)) {
1652 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1653 return -EINVAL;
1654 }
1655 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1656 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1657 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1658 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1659 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1660 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1661 }
f0313965
ES		 1662
1663 if (init_attr->qp_type == IB_QPT_UD &&
1664 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1665 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1666 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1667 return -EOPNOTSUPP;
1668 }
1669
358e42ea
MD		 1670 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1671 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1672 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1673 return -EOPNOTSUPP;
1674 }
1675 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1676 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1677 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1678 return -EOPNOTSUPP;
1679 }
1680 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1681 }
1682
e126ba97
EC		 1683 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1684 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1685
e4cc4fa7
NO		 1686 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1687 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1688 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1689 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1690 return -EOPNOTSUPP;
1691 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1692 }
1693
e126ba97
EC		 1694 if (pd && pd->uobject) {
1695 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1696 mlx5_ib_dbg(dev, "copy failed\n");
1697 return -EFAULT;
1698 }
1699
cfb5e088
HA		 1700 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1701 &ucmd, udata->inlen, &uidx);
1702 if (err)
1703 return err;
1704
e126ba97
EC		 1705 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1706 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
f95ef6cb
MG		 1707 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1708 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1709 !tunnel_offload_supported(mdev)) {
1710 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1711 return -EOPNOTSUPP;
1712 }
1713 qp->tunnel_offload_en = true;
1714 }
c2e53b2c
YH		 1715
1716 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1717 if (init_attr->qp_type != IB_QPT_UD ||
1718 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1719 MLX5_CAP_PORT_TYPE_IB) ||
1720 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1721 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1722 return -EOPNOTSUPP;
1723 }
1724
1725 qp->flags |= MLX5_IB_QP_UNDERLAY;
1726 qp->underlay_qpn = init_attr->source_qpn;
1727 }
e126ba97
EC		 1728 } else {
1729 qp->wq_sig = !!wq_signature;
1730 }
1731
c2e53b2c
YH		 1732 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1733 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1734 &qp->raw_packet_qp.rq.base :
1735 &qp->trans_qp.base;
1736
e126ba97
EC		 1737 qp->has_rq = qp_has_rq(init_attr);
1738 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1739 qp, (pd && pd->uobject) ? &ucmd : NULL);
1740 if (err) {
1741 mlx5_ib_dbg(dev, "err %d\n", err);
1742 return err;
1743 }
1744
1745 if (pd) {
1746 if (pd->uobject) {
938fe83c
SM		 1747 __u32 max_wqes =
1748 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
e126ba97
EC		 1749 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1750 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1751 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1752 mlx5_ib_dbg(dev, "invalid rq params\n");
1753 return -EINVAL;
1754 }
938fe83c 1755 if (ucmd.sq_wqe_count > max_wqes) {
e126ba97 1756 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
938fe83c 1757 ucmd.sq_wqe_count, max_wqes);
e126ba97
EC		 1758 return -EINVAL;
1759 }
b11a4f9c
HE		 1760 if (init_attr->create_flags &
1761 mlx5_ib_create_qp_sqpn_qp1()) {
1762 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1763 return -EINVAL;
1764 }
0fb2ed66 1765 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1766 &resp, &inlen, base);
e126ba97
EC		 1767 if (err)
1768 mlx5_ib_dbg(dev, "err %d\n", err);
1769 } else {
19098df2 1770 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1771 base);
e126ba97
EC		 1772 if (err)
1773 mlx5_ib_dbg(dev, "err %d\n", err);
e126ba97
EC		 1774 }
1775
1776 if (err)
1777 return err;
1778 } else {
1b9a07ee 1779 in = kvzalloc(inlen, GFP_KERNEL);
e126ba97
EC		 1780 if (!in)
1781 return -ENOMEM;
1782
1783 qp->create_type = MLX5_QP_EMPTY;
1784 }
1785
1786 if (is_sqp(init_attr->qp_type))
1787 qp->port = init_attr->port_num;
1788
09a7d9ec
SM		 1789 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1790
e7b169f3 1791 MLX5_SET(qpc, qpc, st, mlx5_st);
09a7d9ec 1792 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
e126ba97
EC		 1793
1794 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
09a7d9ec 1795 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
e126ba97 1796 else
09a7d9ec
SM		 1797 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1798
e126ba97
EC		 1799
1800 if (qp->wq_sig)
09a7d9ec 1801 MLX5_SET(qpc, qpc, wq_signature, 1);
e126ba97 1802
f360d88a 1803 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
09a7d9ec 1804 MLX5_SET(qpc, qpc, block_lb_mc, 1);
f360d88a 1805
051f2630 1806 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
09a7d9ec 1807 MLX5_SET(qpc, qpc, cd_master, 1);
051f2630 1808 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
09a7d9ec 1809 MLX5_SET(qpc, qpc, cd_slave_send, 1);
051f2630 1810 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
09a7d9ec 1811 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
051f2630 1812
e126ba97
EC		 1813 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1814 int rcqe_sz;
1815 int scqe_sz;
1816
1817 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1818 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1819
1820 if (rcqe_sz == 128)
09a7d9ec 1821 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
e126ba97 1822 else
09a7d9ec 1823 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
e126ba97
EC		 1824
1825 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1826 if (scqe_sz == 128)
09a7d9ec 1827 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
e126ba97 1828 else
09a7d9ec 1829 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
e126ba97
EC		 1830 }
1831 }
1832
1833 if (qp->rq.wqe_cnt) {
09a7d9ec
SM		 1834 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1835 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
e126ba97
EC		 1836 }
1837
09a7d9ec 1838 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
e126ba97 1839
3fd3307e 1840 if (qp->sq.wqe_cnt) {
09a7d9ec 1841 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
3fd3307e 1842 } else {
09a7d9ec 1843 MLX5_SET(qpc, qpc, no_sq, 1);
3fd3307e
AK		 1844 if (init_attr->srq &&
1845 init_attr->srq->srq_type == IB_SRQT_TM)
1846 MLX5_SET(qpc, qpc, offload_type,
1847 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1848 }
e126ba97
EC		 1849
1850 /* Set default resources */
1851 switch (init_attr->qp_type) {
1852 case IB_QPT_XRC_TGT:
09a7d9ec
SM		 1853 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1854 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1855 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1856 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
e126ba97
EC		 1857 break;
1858 case IB_QPT_XRC_INI:
09a7d9ec
SM		 1859 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1860 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1861 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
e126ba97
EC		 1862 break;
1863 default:
1864 if (init_attr->srq) {
09a7d9ec
SM		 1865 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1866 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
e126ba97 1867 } else {
09a7d9ec
SM		 1868 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1869 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
e126ba97
EC		 1870 }
1871 }
1872
1873 if (init_attr->send_cq)
09a7d9ec 1874 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
e126ba97
EC		 1875
1876 if (init_attr->recv_cq)
09a7d9ec 1877 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
e126ba97 1878
09a7d9ec 1879 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
e126ba97 1880
09a7d9ec
SM		 1881 /* 0xffffff means we ask to work with cqe version 0 */
1882 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
cfb5e088 1883 MLX5_SET(qpc, qpc, user_index, uidx);
09a7d9ec 1884
f0313965
ES		 1885 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1886 if (init_attr->qp_type == IB_QPT_UD &&
1887 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
f0313965
ES		 1888 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1889 qp->flags |= MLX5_IB_QP_LSO;
1890 }
cfb5e088 1891
b1383aa6
NO		 1892 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1893 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1894 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1895 err = -EOPNOTSUPP;
1896 goto err;
1897 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1898 MLX5_SET(qpc, qpc, end_padding_mode,
1899 MLX5_WQ_END_PAD_MODE_ALIGN);
1900 } else {
1901 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1902 }
1903 }
1904
2c292dbb
BP		 1905 if (inlen < 0) {
1906 err = -EINVAL;
1907 goto err;
1908 }
1909
c2e53b2c
YH		 1910 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1911 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 1912 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1913 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2c292dbb 1914 err = create_raw_packet_qp(dev, qp, in, inlen, pd);
0fb2ed66 1915 } else {
1916 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1917 }
1918
e126ba97
EC		 1919 if (err) {
1920 mlx5_ib_dbg(dev, "create qp failed\n");
1921 goto err_create;
1922 }
1923
479163f4 1924 kvfree(in);
e126ba97 1925
19098df2 1926 base->container_mibqp = qp;
1927 base->mqp.event = mlx5_ib_qp_event;
e126ba97 1928
89ea94a7
MG		 1929 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1930 &send_cq, &recv_cq);
1931 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1932 mlx5_ib_lock_cqs(send_cq, recv_cq);
1933 /* Maintain device to QPs access, needed for further handling via reset
1934 * flow
1935 */
1936 list_add_tail(&qp->qps_list, &dev->qp_list);
1937 /* Maintain CQ to QPs access, needed for further handling via reset flow
1938 */
1939 if (send_cq)
1940 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1941 if (recv_cq)
1942 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1943 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1944 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1945
e126ba97
EC		 1946 return 0;
1947
1948err_create:
1949 if (qp->create_type == MLX5_QP_USER)
b037c29a 1950 destroy_qp_user(dev, pd, qp, base);
e126ba97
EC		 1951 else if (qp->create_type == MLX5_QP_KERNEL)
1952 destroy_qp_kernel(dev, qp);
1953
b1383aa6 1954err:
479163f4 1955 kvfree(in);
e126ba97
EC		 1956 return err;
1957}
1958
1959static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1960 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1961{
1962 if (send_cq) {
1963 if (recv_cq) {
1964 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
89ea94a7 1965 spin_lock(&send_cq->lock);
e126ba97
EC		 1966 spin_lock_nested(&recv_cq->lock,
1967 SINGLE_DEPTH_NESTING);
1968 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
89ea94a7 1969 spin_lock(&send_cq->lock);
e126ba97
EC		 1970 __acquire(&recv_cq->lock);
1971 } else {
89ea94a7 1972 spin_lock(&recv_cq->lock);
e126ba97
EC		 1973 spin_lock_nested(&send_cq->lock,
1974 SINGLE_DEPTH_NESTING);
1975 }
1976 } else {
89ea94a7 1977 spin_lock(&send_cq->lock);
6a4f139a 1978 __acquire(&recv_cq->lock);
e126ba97
EC		 1979 }
1980 } else if (recv_cq) {
89ea94a7 1981 spin_lock(&recv_cq->lock);
6a4f139a
EC		 1982 __acquire(&send_cq->lock);
1983 } else {
1984 __acquire(&send_cq->lock);
1985 __acquire(&recv_cq->lock);
e126ba97
EC		 1986 }
1987}
1988
1989static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1990 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1991{
1992 if (send_cq) {
1993 if (recv_cq) {
1994 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1995 spin_unlock(&recv_cq->lock);
89ea94a7 1996 spin_unlock(&send_cq->lock);
e126ba97
EC		 1997 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1998 __release(&recv_cq->lock);
89ea94a7 1999 spin_unlock(&send_cq->lock);
e126ba97
EC		 2000 } else {
2001 spin_unlock(&send_cq->lock);
89ea94a7 2002 spin_unlock(&recv_cq->lock);
e126ba97
EC		 2003 }
2004 } else {
6a4f139a 2005 __release(&recv_cq->lock);
89ea94a7 2006 spin_unlock(&send_cq->lock);
e126ba97
EC		 2007 }
2008 } else if (recv_cq) {
6a4f139a 2009 __release(&send_cq->lock);
89ea94a7 2010 spin_unlock(&recv_cq->lock);
6a4f139a
EC		 2011 } else {
2012 __release(&recv_cq->lock);
2013 __release(&send_cq->lock);
e126ba97
EC		 2014 }
2015}
2016
2017static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2018{
2019 return to_mpd(qp->ibqp.pd);
2020}
2021
89ea94a7
MG		 2022static void get_cqs(enum ib_qp_type qp_type,
2023 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
e126ba97
EC		 2024 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2025{
89ea94a7 2026 switch (qp_type) {
e126ba97
EC		 2027 case IB_QPT_XRC_TGT:
2028 *send_cq = NULL;
2029 *recv_cq = NULL;
2030 break;
2031 case MLX5_IB_QPT_REG_UMR:
2032 case IB_QPT_XRC_INI:
89ea94a7 2033 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
e126ba97
EC		 2034 *recv_cq = NULL;
2035 break;
2036
2037 case IB_QPT_SMI:
d16e91da 2038 case MLX5_IB_QPT_HW_GSI:
e126ba97
EC		 2039 case IB_QPT_RC:
2040 case IB_QPT_UC:
2041 case IB_QPT_UD:
2042 case IB_QPT_RAW_IPV6:
2043 case IB_QPT_RAW_ETHERTYPE:
0fb2ed66 2044 case IB_QPT_RAW_PACKET:
89ea94a7
MG		 2045 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2046 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
e126ba97
EC		 2047 break;
2048
e126ba97
EC		 2049 case IB_QPT_MAX:
2050 default:
2051 *send_cq = NULL;
2052 *recv_cq = NULL;
2053 break;
2054 }
2055}
2056
ad5f8e96 2057static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2058 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2059 u8 lag_tx_affinity);
ad5f8e96 2060
e126ba97
EC		 2061static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2062{
2063 struct mlx5_ib_cq *send_cq, *recv_cq;
c2e53b2c 2064 struct mlx5_ib_qp_base *base;
89ea94a7 2065 unsigned long flags;
e126ba97
EC		 2066 int err;
2067
28d61370
YH		 2068 if (qp->ibqp.rwq_ind_tbl) {
2069 destroy_rss_raw_qp_tir(dev, qp);
2070 return;
2071 }
2072
c2e53b2c
YH		 2073 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2074 qp->flags & MLX5_IB_QP_UNDERLAY) ?
0fb2ed66 2075 &qp->raw_packet_qp.rq.base :
2076 &qp->trans_qp.base;
2077
6aec21f6 2078 if (qp->state != IB_QPS_RESET) {
c2e53b2c
YH		 2079 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2080 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
ad5f8e96 2081 err = mlx5_core_qp_modify(dev->mdev,
1a412fb1
SM		 2082 MLX5_CMD_OP_2RST_QP, 0,
2083 NULL, &base->mqp);
ad5f8e96 2084 } else {
0680efa2
AV		 2085 struct mlx5_modify_raw_qp_param raw_qp_param = {
2086 .operation = MLX5_CMD_OP_2RST_QP
2087 };
2088
13eab21f 2089 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
ad5f8e96 2090 }
2091 if (err)
427c1e7b 2092 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
19098df2 2093 base->mqp.qpn);
6aec21f6 2094 }
e126ba97 2095
89ea94a7
MG		 2096 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2097 &send_cq, &recv_cq);
2098
2099 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2100 mlx5_ib_lock_cqs(send_cq, recv_cq);
2101 /* del from lists under both locks above to protect reset flow paths */
2102 list_del(&qp->qps_list);
2103 if (send_cq)
2104 list_del(&qp->cq_send_list);
2105
2106 if (recv_cq)
2107 list_del(&qp->cq_recv_list);
e126ba97
EC		 2108
2109 if (qp->create_type == MLX5_QP_KERNEL) {
19098df2 2110 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 2111 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2112 if (send_cq != recv_cq)
19098df2 2113 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2114 NULL);
e126ba97 2115 }
89ea94a7
MG		 2116 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2117 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
e126ba97 2118
c2e53b2c
YH		 2119 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2120 qp->flags & MLX5_IB_QP_UNDERLAY) {
0fb2ed66 2121 destroy_raw_packet_qp(dev, qp);
2122 } else {
2123 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2124 if (err)
2125 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2126 base->mqp.qpn);
2127 }
e126ba97 2128
e126ba97
EC		 2129 if (qp->create_type == MLX5_QP_KERNEL)
2130 destroy_qp_kernel(dev, qp);
2131 else if (qp->create_type == MLX5_QP_USER)
b037c29a 2132 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
e126ba97
EC		 2133}
2134
2135static const char *ib_qp_type_str(enum ib_qp_type type)
2136{
2137 switch (type) {
2138 case IB_QPT_SMI:
2139 return "IB_QPT_SMI";
2140 case IB_QPT_GSI:
2141 return "IB_QPT_GSI";
2142 case IB_QPT_RC:
2143 return "IB_QPT_RC";
2144 case IB_QPT_UC:
2145 return "IB_QPT_UC";
2146 case IB_QPT_UD:
2147 return "IB_QPT_UD";
2148 case IB_QPT_RAW_IPV6:
2149 return "IB_QPT_RAW_IPV6";
2150 case IB_QPT_RAW_ETHERTYPE:
2151 return "IB_QPT_RAW_ETHERTYPE";
2152 case IB_QPT_XRC_INI:
2153 return "IB_QPT_XRC_INI";
2154 case IB_QPT_XRC_TGT:
2155 return "IB_QPT_XRC_TGT";
2156 case IB_QPT_RAW_PACKET:
2157 return "IB_QPT_RAW_PACKET";
2158 case MLX5_IB_QPT_REG_UMR:
2159 return "MLX5_IB_QPT_REG_UMR";
b4aaa1f0
MS		 2160 case IB_QPT_DRIVER:
2161 return "IB_QPT_DRIVER";
e126ba97
EC		 2162 case IB_QPT_MAX:
2163 default:
2164 return "Invalid QP type";
2165 }
2166}
2167
b4aaa1f0
MS		 2168static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2169 struct ib_qp_init_attr *attr,
2170 struct mlx5_ib_create_qp *ucmd)
2171{
b4aaa1f0
MS		 2172 struct mlx5_ib_qp *qp;
2173 int err = 0;
2174 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2175 void *dctc;
2176
2177 if (!attr->srq || !attr->recv_cq)
2178 return ERR_PTR(-EINVAL);
2179
b4aaa1f0
MS		 2180 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2181 ucmd, sizeof(*ucmd), &uidx);
2182 if (err)
2183 return ERR_PTR(err);
2184
2185 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2186 if (!qp)
2187 return ERR_PTR(-ENOMEM);
2188
2189 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2190 if (!qp->dct.in) {
2191 err = -ENOMEM;
2192 goto err_free;
2193 }
2194
2195 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
776a3906 2196 qp->qp_sub_type = MLX5_IB_QPT_DCT;
b4aaa1f0
MS		 2197 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2198 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2199 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2200 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2201 MLX5_SET(dctc, dctc, user_index, uidx);
2202
2203 qp->state = IB_QPS_RESET;
2204
2205 return &qp->ibqp;
2206err_free:
2207 kfree(qp);
2208 return ERR_PTR(err);
2209}
2210
2211static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2212 struct ib_qp_init_attr *init_attr,
2213 struct mlx5_ib_create_qp *ucmd,
2214 struct ib_udata *udata)
2215{
2216 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2217 int err;
2218
2219 if (!udata)
2220 return -EINVAL;
2221
2222 if (udata->inlen < sizeof(*ucmd)) {
2223 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2224 return -EINVAL;
2225 }
2226 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2227 if (err)
2228 return err;
2229
2230 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2231 init_attr->qp_type = MLX5_IB_QPT_DCI;
2232 } else {
2233 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2234 init_attr->qp_type = MLX5_IB_QPT_DCT;
2235 } else {
2236 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2237 return -EINVAL;
2238 }
2239 }
2240
2241 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2242 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2243 return -EOPNOTSUPP;
2244 }
2245
2246 return 0;
2247}
2248
e126ba97 2249struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
b4aaa1f0 2250 struct ib_qp_init_attr *verbs_init_attr,
e126ba97
EC		 2251 struct ib_udata *udata)
2252{
2253 struct mlx5_ib_dev *dev;
2254 struct mlx5_ib_qp *qp;
2255 u16 xrcdn = 0;
2256 int err;
b4aaa1f0
MS		 2257 struct ib_qp_init_attr mlx_init_attr;
2258 struct ib_qp_init_attr *init_attr = verbs_init_attr;
e126ba97
EC		 2259
2260 if (pd) {
2261 dev = to_mdev(pd->device);
0fb2ed66 2262
2263 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2264 if (!pd->uobject) {
2265 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2266 return ERR_PTR(-EINVAL);
2267 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2268 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2269 return ERR_PTR(-EINVAL);
2270 }
2271 }
09f16cf5
MD		 2272 } else {
2273 /* being cautious here */
2274 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2275 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2276 pr_warn("%s: no PD for transport %s\n", __func__,
2277 ib_qp_type_str(init_attr->qp_type));
2278 return ERR_PTR(-EINVAL);
2279 }
2280 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
e126ba97
EC		 2281 }
2282
b4aaa1f0
MS		 2283 if (init_attr->qp_type == IB_QPT_DRIVER) {
2284 struct mlx5_ib_create_qp ucmd;
2285
2286 init_attr = &mlx_init_attr;
2287 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2288 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2289 if (err)
2290 return ERR_PTR(err);
c32a4f29
MS		 2291
2292 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2293 if (init_attr->cap.max_recv_wr ||
2294 init_attr->cap.max_recv_sge) {
2295 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2296 return ERR_PTR(-EINVAL);
2297 }
776a3906
MS		 2298 } else {
2299 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
c32a4f29 2300 }
b4aaa1f0
MS		 2301 }
2302
e126ba97
EC		 2303 switch (init_attr->qp_type) {
2304 case IB_QPT_XRC_TGT:
2305 case IB_QPT_XRC_INI:
938fe83c 2306 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
e126ba97
EC		 2307 mlx5_ib_dbg(dev, "XRC not supported\n");
2308 return ERR_PTR(-ENOSYS);
2309 }
2310 init_attr->recv_cq = NULL;
2311 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2312 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2313 init_attr->send_cq = NULL;
2314 }
2315
2316 /* fall through */
0fb2ed66 2317 case IB_QPT_RAW_PACKET:
e126ba97
EC		 2318 case IB_QPT_RC:
2319 case IB_QPT_UC:
2320 case IB_QPT_UD:
2321 case IB_QPT_SMI:
d16e91da 2322 case MLX5_IB_QPT_HW_GSI:
e126ba97 2323 case MLX5_IB_QPT_REG_UMR:
c32a4f29 2324 case MLX5_IB_QPT_DCI:
e126ba97
EC		 2325 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2326 if (!qp)
2327 return ERR_PTR(-ENOMEM);
2328
2329 err = create_qp_common(dev, pd, init_attr, udata, qp);
2330 if (err) {
2331 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2332 kfree(qp);
2333 return ERR_PTR(err);
2334 }
2335
2336 if (is_qp0(init_attr->qp_type))
2337 qp->ibqp.qp_num = 0;
2338 else if (is_qp1(init_attr->qp_type))
2339 qp->ibqp.qp_num = 1;
2340 else
19098df2 2341 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
e126ba97
EC		 2342
2343 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
19098df2 2344 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
a1ab8402
EC		 2345 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2346 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
e126ba97 2347
19098df2 2348 qp->trans_qp.xrcdn = xrcdn;
e126ba97
EC		 2349
2350 break;
2351
d16e91da
HE		 2352 case IB_QPT_GSI:
2353 return mlx5_ib_gsi_create_qp(pd, init_attr);
2354
e126ba97
EC		 2355 case IB_QPT_RAW_IPV6:
2356 case IB_QPT_RAW_ETHERTYPE:
e126ba97
EC		 2357 case IB_QPT_MAX:
2358 default:
2359 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2360 init_attr->qp_type);
2361 /* Don't support raw QPs */
2362 return ERR_PTR(-EINVAL);
2363 }
2364
b4aaa1f0
MS		 2365 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2366 qp->qp_sub_type = init_attr->qp_type;
2367
e126ba97
EC		 2368 return &qp->ibqp;
2369}
2370
776a3906
MS		 2371static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2372{
2373 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2374
2375 if (mqp->state == IB_QPS_RTR) {
2376 int err;
2377
2378 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2379 if (err) {
2380 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2381 return err;
2382 }
2383 }
2384
2385 kfree(mqp->dct.in);
2386 kfree(mqp);
2387 return 0;
2388}
2389
e126ba97
EC		 2390int mlx5_ib_destroy_qp(struct ib_qp *qp)
2391{
2392 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2393 struct mlx5_ib_qp *mqp = to_mqp(qp);
2394
d16e91da
HE		 2395 if (unlikely(qp->qp_type == IB_QPT_GSI))
2396 return mlx5_ib_gsi_destroy_qp(qp);
2397
776a3906
MS		 2398 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2399 return mlx5_ib_destroy_dct(mqp);
2400
e126ba97
EC		 2401 destroy_qp_common(dev, mqp);
2402
2403 kfree(mqp);
2404
2405 return 0;
2406}
2407
2408static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2409 int attr_mask)
2410{
2411 u32 hw_access_flags = 0;
2412 u8 dest_rd_atomic;
2413 u32 access_flags;
2414
2415 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2416 dest_rd_atomic = attr->max_dest_rd_atomic;
2417 else
19098df2 2418 dest_rd_atomic = qp->trans_qp.resp_depth;
e126ba97
EC		 2419
2420 if (attr_mask & IB_QP_ACCESS_FLAGS)
2421 access_flags = attr->qp_access_flags;
2422 else
19098df2 2423 access_flags = qp->trans_qp.atomic_rd_en;
e126ba97
EC		 2424
2425 if (!dest_rd_atomic)
2426 access_flags &= IB_ACCESS_REMOTE_WRITE;
2427
2428 if (access_flags & IB_ACCESS_REMOTE_READ)
2429 hw_access_flags |= MLX5_QP_BIT_RRE;
2430 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2431 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2432 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2433 hw_access_flags |= MLX5_QP_BIT_RWE;
2434
2435 return cpu_to_be32(hw_access_flags);
2436}
2437
2438enum {
2439 MLX5_PATH_FLAG_FL = 1 << 0,
2440 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2441 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2442};
2443
2444static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2445{
2446 if (rate == IB_RATE_PORT_CURRENT) {
2447 return 0;
2448 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2449 return -EINVAL;
2450 } else {
2451 while (rate != IB_RATE_2_5_GBPS &&
2452 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
938fe83c 2453 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
e126ba97
EC		 2454 --rate;
2455 }
2456
2457 return rate + MLX5_STAT_RATE_OFFSET;
2458}
2459
75850d0b 2460static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2461 struct mlx5_ib_sq *sq, u8 sl)
2462{
2463 void *in;
2464 void *tisc;
2465 int inlen;
2466 int err;
2467
2468 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2469 in = kvzalloc(inlen, GFP_KERNEL);
75850d0b 2470 if (!in)
2471 return -ENOMEM;
2472
2473 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2474
2475 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2476 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2477
2478 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2479
2480 kvfree(in);
2481
2482 return err;
2483}
2484
13eab21f
AH		 2485static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2486 struct mlx5_ib_sq *sq, u8 tx_affinity)
2487{
2488 void *in;
2489 void *tisc;
2490 int inlen;
2491 int err;
2492
2493 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
1b9a07ee 2494 in = kvzalloc(inlen, GFP_KERNEL);
13eab21f
AH		 2495 if (!in)
2496 return -ENOMEM;
2497
2498 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2499
2500 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2501 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2502
2503 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2504
2505 kvfree(in);
2506
2507 return err;
2508}
2509
75850d0b 2510static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
90898850 2511 const struct rdma_ah_attr *ah,
e126ba97 2512 struct mlx5_qp_path *path, u8 port, int attr_mask,
f879ee8d
AS		 2513 u32 path_flags, const struct ib_qp_attr *attr,
2514 bool alt)
e126ba97 2515{
d8966fcd 2516 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
e126ba97 2517 int err;
ed88451e 2518 enum ib_gid_type gid_type;
d8966fcd
DC		 2519 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2520 u8 sl = rdma_ah_get_sl(ah);
e126ba97 2521
e126ba97 2522 if (attr_mask & IB_QP_PKEY_INDEX)
f879ee8d
AS		 2523 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2524 attr->pkey_index);
e126ba97 2525
d8966fcd
DC		 2526 if (ah_flags & IB_AH_GRH) {
2527 if (grh->sgid_index >=
938fe83c 2528 dev->mdev->port_caps[port - 1].gid_table_len) {
f4f01b54 2529 pr_err("sgid_index (%u) too large. max is %d\n",
d8966fcd 2530 grh->sgid_index,
938fe83c 2531 dev->mdev->port_caps[port - 1].gid_table_len);
f83b4263
EC		 2532 return -EINVAL;
2533 }
2811ba51 2534 }
44c58487
DC		 2535
2536 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 2537 if (!(ah_flags & IB_AH_GRH))
2811ba51 2538 return -EINVAL;
d8966fcd 2539 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
ed88451e
MD		 2540 &gid_type);
2541 if (err)
2542 return err;
44c58487 2543 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2b621851
MD		 2544 if (qp->ibqp.qp_type == IB_QPT_RC ||
2545 qp->ibqp.qp_type == IB_QPT_UC ||
2546 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2547 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2548 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2549 grh->sgid_index);
d8966fcd 2550 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
ed88451e 2551 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
d8966fcd 2552 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2811ba51 2553 } else {
d3ae2bde
NO		 2554 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2555 path->fl_free_ar |=
2556 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
d8966fcd
DC		 2557 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2558 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2559 if (ah_flags & IB_AH_GRH)
2811ba51 2560 path->grh_mlid |= 1 << 7;
d8966fcd 2561 path->dci_cfi_prio_sl = sl & 0xf;
2811ba51
AS		 2562 }
2563
d8966fcd
DC		 2564 if (ah_flags & IB_AH_GRH) {
2565 path->mgid_index = grh->sgid_index;
2566 path->hop_limit = grh->hop_limit;
e126ba97 2567 path->tclass_flowlabel =
d8966fcd
DC		 2568 cpu_to_be32((grh->traffic_class << 20) |
2569 (grh->flow_label));
2570 memcpy(path->rgid, grh->dgid.raw, 16);
e126ba97
EC		 2571 }
2572
d8966fcd 2573 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
e126ba97
EC		 2574 if (err < 0)
2575 return err;
2576 path->static_rate = err;
2577 path->port = port;
2578
e126ba97 2579 if (attr_mask & IB_QP_TIMEOUT)
f879ee8d 2580 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
e126ba97 2581
75850d0b 2582 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2583 return modify_raw_packet_eth_prio(dev->mdev,
2584 &qp->raw_packet_qp.sq,
d8966fcd 2585 sl & 0xf);
75850d0b 2586
e126ba97
EC		 2587 return 0;
2588}
2589
2590static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2591 [MLX5_QP_STATE_INIT] = {
2592 [MLX5_QP_STATE_INIT] = {
2593 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2594 MLX5_QP_OPTPAR_RAE |
2595 MLX5_QP_OPTPAR_RWE |
2596 MLX5_QP_OPTPAR_PKEY_INDEX |
2597 MLX5_QP_OPTPAR_PRI_PORT,
2598 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2599 MLX5_QP_OPTPAR_PKEY_INDEX |
2600 MLX5_QP_OPTPAR_PRI_PORT,
2601 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2602 MLX5_QP_OPTPAR_Q_KEY |
2603 MLX5_QP_OPTPAR_PRI_PORT,
2604 },
2605 [MLX5_QP_STATE_RTR] = {
2606 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2607 MLX5_QP_OPTPAR_RRE |
2608 MLX5_QP_OPTPAR_RAE |
2609 MLX5_QP_OPTPAR_RWE |
2610 MLX5_QP_OPTPAR_PKEY_INDEX,
2611 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2612 MLX5_QP_OPTPAR_RWE |
2613 MLX5_QP_OPTPAR_PKEY_INDEX,
2614 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2615 MLX5_QP_OPTPAR_Q_KEY,
2616 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2617 MLX5_QP_OPTPAR_Q_KEY,
a4774e90
EC		 2618 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2619 MLX5_QP_OPTPAR_RRE |
2620 MLX5_QP_OPTPAR_RAE |
2621 MLX5_QP_OPTPAR_RWE |
2622 MLX5_QP_OPTPAR_PKEY_INDEX,
e126ba97
EC		 2623 },
2624 },
2625 [MLX5_QP_STATE_RTR] = {
2626 [MLX5_QP_STATE_RTS] = {
2627 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2628 MLX5_QP_OPTPAR_RRE |
2629 MLX5_QP_OPTPAR_RAE |
2630 MLX5_QP_OPTPAR_RWE |
2631 MLX5_QP_OPTPAR_PM_STATE |
2632 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2633 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2634 MLX5_QP_OPTPAR_RWE |
2635 MLX5_QP_OPTPAR_PM_STATE,
2636 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2637 },
2638 },
2639 [MLX5_QP_STATE_RTS] = {
2640 [MLX5_QP_STATE_RTS] = {
2641 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2642 MLX5_QP_OPTPAR_RAE |
2643 MLX5_QP_OPTPAR_RWE |
2644 MLX5_QP_OPTPAR_RNR_TIMEOUT |
c2a3431e
EC		 2645 MLX5_QP_OPTPAR_PM_STATE |
2646 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97 2647 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
c2a3431e
EC		 2648 MLX5_QP_OPTPAR_PM_STATE |
2649 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
e126ba97
EC		 2650 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2651 MLX5_QP_OPTPAR_SRQN |
2652 MLX5_QP_OPTPAR_CQN_RCV,
2653 },
2654 },
2655 [MLX5_QP_STATE_SQER] = {
2656 [MLX5_QP_STATE_RTS] = {
2657 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2658 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
75959f56 2659 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
a4774e90
EC		 2660 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2661 MLX5_QP_OPTPAR_RWE |
2662 MLX5_QP_OPTPAR_RAE |
2663 MLX5_QP_OPTPAR_RRE,
e126ba97
EC		 2664 },
2665 },
2666};
2667
2668static int ib_nr_to_mlx5_nr(int ib_mask)
2669{
2670 switch (ib_mask) {
2671 case IB_QP_STATE:
2672 return 0;
2673 case IB_QP_CUR_STATE:
2674 return 0;
2675 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2676 return 0;
2677 case IB_QP_ACCESS_FLAGS:
2678 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2679 MLX5_QP_OPTPAR_RAE;
2680 case IB_QP_PKEY_INDEX:
2681 return MLX5_QP_OPTPAR_PKEY_INDEX;
2682 case IB_QP_PORT:
2683 return MLX5_QP_OPTPAR_PRI_PORT;
2684 case IB_QP_QKEY:
2685 return MLX5_QP_OPTPAR_Q_KEY;
2686 case IB_QP_AV:
2687 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2688 MLX5_QP_OPTPAR_PRI_PORT;
2689 case IB_QP_PATH_MTU:
2690 return 0;
2691 case IB_QP_TIMEOUT:
2692 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2693 case IB_QP_RETRY_CNT:
2694 return MLX5_QP_OPTPAR_RETRY_COUNT;
2695 case IB_QP_RNR_RETRY:
2696 return MLX5_QP_OPTPAR_RNR_RETRY;
2697 case IB_QP_RQ_PSN:
2698 return 0;
2699 case IB_QP_MAX_QP_RD_ATOMIC:
2700 return MLX5_QP_OPTPAR_SRA_MAX;
2701 case IB_QP_ALT_PATH:
2702 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2703 case IB_QP_MIN_RNR_TIMER:
2704 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2705 case IB_QP_SQ_PSN:
2706 return 0;
2707 case IB_QP_MAX_DEST_RD_ATOMIC:
2708 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2709 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2710 case IB_QP_PATH_MIG_STATE:
2711 return MLX5_QP_OPTPAR_PM_STATE;
2712 case IB_QP_CAP:
2713 return 0;
2714 case IB_QP_DEST_QPN:
2715 return 0;
2716 }
2717 return 0;
2718}
2719
2720static int ib_mask_to_mlx5_opt(int ib_mask)
2721{
2722 int result = 0;
2723 int i;
2724
2725 for (i = 0; i < 8 * sizeof(int); i++) {
2726 if ((1 << i) & ib_mask)
2727 result |= ib_nr_to_mlx5_nr(1 << i);
2728 }
2729
2730 return result;
2731}
2732
eb49ab0c
AV		 2733static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2734 struct mlx5_ib_rq *rq, int new_state,
2735 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2736{
2737 void *in;
2738 void *rqc;
2739 int inlen;
2740 int err;
2741
2742 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 2743 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2744 if (!in)
2745 return -ENOMEM;
2746
2747 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2748
2749 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2750 MLX5_SET(rqc, rqc, state, new_state);
2751
eb49ab0c
AV		 2752 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2753 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2754 MLX5_SET64(modify_rq_in, in, modify_bitmask,
23a6964e 2755 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
eb49ab0c
AV		 2756 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2757 } else
2758 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2759 dev->ib_dev.name);
2760 }
2761
2762 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
ad5f8e96 2763 if (err)
2764 goto out;
2765
2766 rq->state = new_state;
2767
2768out:
2769 kvfree(in);
2770 return err;
2771}
2772
2773static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
7d29f349
BW		 2774 struct mlx5_ib_sq *sq,
2775 int new_state,
2776 const struct mlx5_modify_raw_qp_param *raw_qp_param)
ad5f8e96 2777{
7d29f349 2778 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
61147f39
BW		 2779 struct mlx5_rate_limit old_rl = ibqp->rl;
2780 struct mlx5_rate_limit new_rl = old_rl;
2781 bool new_rate_added = false;
7d29f349 2782 u16 rl_index = 0;
ad5f8e96 2783 void *in;
2784 void *sqc;
2785 int inlen;
2786 int err;
2787
2788 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 2789 in = kvzalloc(inlen, GFP_KERNEL);
ad5f8e96 2790 if (!in)
2791 return -ENOMEM;
2792
2793 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2794
2795 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2796 MLX5_SET(sqc, sqc, state, new_state);
2797
7d29f349
BW		 2798 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2799 if (new_state != MLX5_SQC_STATE_RDY)
2800 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2801 __func__);
2802 else
61147f39 2803 new_rl = raw_qp_param->rl;
7d29f349
BW		 2804 }
2805
61147f39
BW		 2806 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
2807 if (new_rl.rate) {
2808 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
7d29f349 2809 if (err) {
61147f39
BW		 2810 pr_err("Failed configuring rate limit(err %d): \
2811 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2812 err, new_rl.rate, new_rl.max_burst_sz,
2813 new_rl.typical_pkt_sz);
2814
7d29f349
BW		 2815 goto out;
2816 }
61147f39 2817 new_rate_added = true;
7d29f349
BW		 2818 }
2819
2820 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
61147f39 2821 /* index 0 means no limit */
7d29f349
BW		 2822 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2823 }
2824
ad5f8e96 2825 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
7d29f349
BW		 2826 if (err) {
2827 /* Remove new rate from table if failed */
61147f39
BW		 2828 if (new_rate_added)
2829 mlx5_rl_remove_rate(dev, &new_rl);
ad5f8e96 2830 goto out;
7d29f349
BW		 2831 }
2832
2833 /* Only remove the old rate after new rate was set */
61147f39
BW		 2834 if ((old_rl.rate &&
2835 !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
7d29f349 2836 (new_state != MLX5_SQC_STATE_RDY))
61147f39 2837 mlx5_rl_remove_rate(dev, &old_rl);
ad5f8e96 2838
61147f39 2839 ibqp->rl = new_rl;
ad5f8e96 2840 sq->state = new_state;
2841
2842out:
2843 kvfree(in);
2844 return err;
2845}
2846
2847static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
13eab21f
AH		 2848 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2849 u8 tx_affinity)
ad5f8e96 2850{
2851 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2852 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2853 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
7d29f349
BW		 2854 int modify_rq = !!qp->rq.wqe_cnt;
2855 int modify_sq = !!qp->sq.wqe_cnt;
ad5f8e96 2856 int rq_state;
2857 int sq_state;
2858 int err;
2859
0680efa2 2860 switch (raw_qp_param->operation) {
ad5f8e96 2861 case MLX5_CMD_OP_RST2INIT_QP:
2862 rq_state = MLX5_RQC_STATE_RDY;
2863 sq_state = MLX5_SQC_STATE_RDY;
2864 break;
2865 case MLX5_CMD_OP_2ERR_QP:
2866 rq_state = MLX5_RQC_STATE_ERR;
2867 sq_state = MLX5_SQC_STATE_ERR;
2868 break;
2869 case MLX5_CMD_OP_2RST_QP:
2870 rq_state = MLX5_RQC_STATE_RST;
2871 sq_state = MLX5_SQC_STATE_RST;
2872 break;
ad5f8e96 2873 case MLX5_CMD_OP_RTR2RTS_QP:
2874 case MLX5_CMD_OP_RTS2RTS_QP:
7d29f349
BW		 2875 if (raw_qp_param->set_mask ==
2876 MLX5_RAW_QP_RATE_LIMIT) {
2877 modify_rq = 0;
2878 sq_state = sq->state;
2879 } else {
2880 return raw_qp_param->set_mask ? -EINVAL : 0;
2881 }
2882 break;
2883 case MLX5_CMD_OP_INIT2INIT_QP:
2884 case MLX5_CMD_OP_INIT2RTR_QP:
eb49ab0c
AV		 2885 if (raw_qp_param->set_mask)
2886 return -EINVAL;
2887 else
2888 return 0;
ad5f8e96 2889 default:
2890 WARN_ON(1);
2891 return -EINVAL;
2892 }
2893
7d29f349
BW		 2894 if (modify_rq) {
2895 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
ad5f8e96 2896 if (err)
2897 return err;
2898 }
2899
7d29f349 2900 if (modify_sq) {
13eab21f
AH		 2901 if (tx_affinity) {
2902 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2903 tx_affinity);
2904 if (err)
2905 return err;
2906 }
2907
7d29f349 2908 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
13eab21f 2909 }
ad5f8e96 2910
2911 return 0;
2912}
2913
e126ba97
EC		 2914static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2915 const struct ib_qp_attr *attr, int attr_mask,
61147f39
BW		 2916 enum ib_qp_state cur_state, enum ib_qp_state new_state,
2917 const struct mlx5_ib_modify_qp *ucmd)
e126ba97 2918{
427c1e7b 2919 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2920 [MLX5_QP_STATE_RST] = {
2921 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2922 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2923 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2924 },
2925 [MLX5_QP_STATE_INIT] = {
2926 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2927 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2928 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2929 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2930 },
2931 [MLX5_QP_STATE_RTR] = {
2932 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2933 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2934 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2935 },
2936 [MLX5_QP_STATE_RTS] = {
2937 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2938 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2939 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2940 },
2941 [MLX5_QP_STATE_SQD] = {
2942 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2943 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2944 },
2945 [MLX5_QP_STATE_SQER] = {
2946 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2947 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2948 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2949 },
2950 [MLX5_QP_STATE_ERR] = {
2951 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2952 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2953 }
2954 };
2955
e126ba97
EC		 2956 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2957 struct mlx5_ib_qp *qp = to_mqp(ibqp);
19098df2 2958 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
e126ba97
EC		 2959 struct mlx5_ib_cq *send_cq, *recv_cq;
2960 struct mlx5_qp_context *context;
e126ba97 2961 struct mlx5_ib_pd *pd;
eb49ab0c 2962 struct mlx5_ib_port *mibport = NULL;
e126ba97
EC		 2963 enum mlx5_qp_state mlx5_cur, mlx5_new;
2964 enum mlx5_qp_optpar optpar;
e126ba97
EC		 2965 int mlx5_st;
2966 int err;
427c1e7b 2967 u16 op;
13eab21f 2968 u8 tx_affinity = 0;
e126ba97 2969
55de9a77
LR		 2970 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
2971 qp->qp_sub_type : ibqp->qp_type);
2972 if (mlx5_st < 0)
2973 return -EINVAL;
2974
1a412fb1
SM		 2975 context = kzalloc(sizeof(*context), GFP_KERNEL);
2976 if (!context)
e126ba97
EC		 2977 return -ENOMEM;
2978
55de9a77 2979 context->flags = cpu_to_be32(mlx5_st << 16);
e126ba97
EC		 2980
2981 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2982 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2983 } else {
2984 switch (attr->path_mig_state) {
2985 case IB_MIG_MIGRATED:
2986 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2987 break;
2988 case IB_MIG_REARM:
2989 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2990 break;
2991 case IB_MIG_ARMED:
2992 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2993 break;
2994 }
2995 }
2996
13eab21f
AH		 2997 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2998 if ((ibqp->qp_type == IB_QPT_RC) ||
2999 (ibqp->qp_type == IB_QPT_UD &&
3000 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3001 (ibqp->qp_type == IB_QPT_UC) ||
3002 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3003 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3004 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3005 if (mlx5_lag_is_active(dev->mdev)) {
7fd8aefb 3006 u8 p = mlx5_core_native_port_num(dev->mdev);
13eab21f 3007 tx_affinity = (unsigned int)atomic_add_return(1,
7fd8aefb 3008 &dev->roce[p].next_port) %
13eab21f
AH		 3009 MLX5_MAX_PORTS + 1;
3010 context->flags |= cpu_to_be32(tx_affinity << 24);
3011 }
3012 }
3013 }
3014
d16e91da 3015 if (is_sqp(ibqp->qp_type)) {
e126ba97 3016 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
c2e53b2c
YH		 3017 } else if ((ibqp->qp_type == IB_QPT_UD &&
3018 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
e126ba97
EC		 3019 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3020 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3021 } else if (attr_mask & IB_QP_PATH_MTU) {
3022 if (attr->path_mtu < IB_MTU_256 ||
3023 attr->path_mtu > IB_MTU_4096) {
3024 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3025 err = -EINVAL;
3026 goto out;
3027 }
938fe83c
SM		 3028 context->mtu_msgmax = (attr->path_mtu << 5) |
3029 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
e126ba97
EC		 3030 }
3031
3032 if (attr_mask & IB_QP_DEST_QPN)
3033 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3034
3035 if (attr_mask & IB_QP_PKEY_INDEX)
d3ae2bde 3036 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
e126ba97
EC		 3037
3038 /* todo implement counter_index functionality */
3039
3040 if (is_sqp(ibqp->qp_type))
3041 context->pri_path.port = qp->port;
3042
3043 if (attr_mask & IB_QP_PORT)
3044 context->pri_path.port = attr->port_num;
3045
3046 if (attr_mask & IB_QP_AV) {
75850d0b 3047 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
e126ba97 3048 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
f879ee8d 3049 attr_mask, 0, attr, false);
e126ba97
EC		 3050 if (err)
3051 goto out;
3052 }
3053
3054 if (attr_mask & IB_QP_TIMEOUT)
3055 context->pri_path.ackto_lt |= attr->timeout << 3;
3056
3057 if (attr_mask & IB_QP_ALT_PATH) {
75850d0b 3058 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3059 &context->alt_path,
f879ee8d
AS		 3060 attr->alt_port_num,
3061 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3062 0, attr, true);
e126ba97
EC		 3063 if (err)
3064 goto out;
3065 }
3066
3067 pd = get_pd(qp);
89ea94a7
MG		 3068 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3069 &send_cq, &recv_cq);
e126ba97
EC		 3070
3071 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3072 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3073 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3074 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3075
3076 if (attr_mask & IB_QP_RNR_RETRY)
3077 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3078
3079 if (attr_mask & IB_QP_RETRY_CNT)
3080 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3081
3082 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3083 if (attr->max_rd_atomic)
3084 context->params1 |=
3085 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3086 }
3087
3088 if (attr_mask & IB_QP_SQ_PSN)
3089 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3090
3091 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3092 if (attr->max_dest_rd_atomic)
3093 context->params2 |=
3094 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3095 }
3096
3097 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3098 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3099
3100 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3101 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3102
3103 if (attr_mask & IB_QP_RQ_PSN)
3104 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3105
3106 if (attr_mask & IB_QP_QKEY)
3107 context->qkey = cpu_to_be32(attr->qkey);
3108
3109 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3110 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3111
0837e86a
MB		 3112 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3113 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3114 qp->port) - 1;
c2e53b2c
YH		 3115
3116 /* Underlay port should be used - index 0 function per port */
3117 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3118 port_num = 0;
3119
eb49ab0c 3120 mibport = &dev->port[port_num];
0837e86a 3121 context->qp_counter_set_usr_page |=
e1f24a79 3122 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
0837e86a
MB		 3123 }
3124
e126ba97
EC		 3125 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3126 context->sq_crq_size |= cpu_to_be16(1 << 4);
3127
b11a4f9c
HE		 3128 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3129 context->deth_sqpn = cpu_to_be32(1);
e126ba97
EC		 3130
3131 mlx5_cur = to_mlx5_state(cur_state);
3132 mlx5_new = to_mlx5_state(new_state);
e126ba97 3133
427c1e7b 3134 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
5d414b17
DC		 3135 !optab[mlx5_cur][mlx5_new]) {
3136 err = -EINVAL;
427c1e7b 3137 goto out;
5d414b17 3138 }
427c1e7b 3139
3140 op = optab[mlx5_cur][mlx5_new];
e126ba97
EC		 3141 optpar = ib_mask_to_mlx5_opt(attr_mask);
3142 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
ad5f8e96 3143
c2e53b2c
YH		 3144 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3145 qp->flags & MLX5_IB_QP_UNDERLAY) {
0680efa2
AV		 3146 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3147
3148 raw_qp_param.operation = op;
eb49ab0c 3149 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
e1f24a79 3150 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
eb49ab0c
AV		 3151 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3152 }
7d29f349
BW		 3153
3154 if (attr_mask & IB_QP_RATE_LIMIT) {
61147f39
BW		 3155 raw_qp_param.rl.rate = attr->rate_limit;
3156
3157 if (ucmd->burst_info.max_burst_sz) {
3158 if (attr->rate_limit &&
3159 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3160 raw_qp_param.rl.max_burst_sz =
3161 ucmd->burst_info.max_burst_sz;
3162 } else {
3163 err = -EINVAL;
3164 goto out;
3165 }
3166 }
3167
3168 if (ucmd->burst_info.typical_pkt_sz) {
3169 if (attr->rate_limit &&
3170 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3171 raw_qp_param.rl.typical_pkt_sz =
3172 ucmd->burst_info.typical_pkt_sz;
3173 } else {
3174 err = -EINVAL;
3175 goto out;
3176 }
3177 }
3178
7d29f349
BW		 3179 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3180 }
3181
13eab21f 3182 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
0680efa2 3183 } else {
1a412fb1 3184 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
ad5f8e96 3185 &base->mqp);
0680efa2
AV		 3186 }
3187
e126ba97
EC		 3188 if (err)
3189 goto out;
3190
3191 qp->state = new_state;
3192
3193 if (attr_mask & IB_QP_ACCESS_FLAGS)
19098df2 3194 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
e126ba97 3195 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
19098df2 3196 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
e126ba97
EC		 3197 if (attr_mask & IB_QP_PORT)
3198 qp->port = attr->port_num;
3199 if (attr_mask & IB_QP_ALT_PATH)
19098df2 3200 qp->trans_qp.alt_port = attr->alt_port_num;
e126ba97
EC		 3201
3202 /*
3203 * If we moved a kernel QP to RESET, clean up all old CQ
3204 * entries and reinitialize the QP.
3205 */
75a45982
LR		 3206 if (new_state == IB_QPS_RESET &&
3207 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
19098df2 3208 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
e126ba97
EC		 3209 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3210 if (send_cq != recv_cq)
19098df2 3211 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
e126ba97
EC		 3212
3213 qp->rq.head = 0;
3214 qp->rq.tail = 0;
3215 qp->sq.head = 0;
3216 qp->sq.tail = 0;
3217 qp->sq.cur_post = 0;
3218 qp->sq.last_poll = 0;
3219 qp->db.db[MLX5_RCV_DBR] = 0;
3220 qp->db.db[MLX5_SND_DBR] = 0;
3221 }
3222
3223out:
1a412fb1 3224 kfree(context);
e126ba97
EC		 3225 return err;
3226}
3227
c32a4f29
MS		 3228static inline bool is_valid_mask(int mask, int req, int opt)
3229{
3230 if ((mask & req) != req)
3231 return false;
3232
3233 if (mask & ~(req | opt))
3234 return false;
3235
3236 return true;
3237}
3238
3239/* check valid transition for driver QP types
3240 * for now the only QP type that this function supports is DCI
3241 */
3242static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3243 enum ib_qp_attr_mask attr_mask)
3244{
3245 int req = IB_QP_STATE;
3246 int opt = 0;
3247
3248 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3249 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3250 return is_valid_mask(attr_mask, req, opt);
3251 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3252 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3253 return is_valid_mask(attr_mask, req, opt);
3254 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3255 req |= IB_QP_PATH_MTU;
3256 opt = IB_QP_PKEY_INDEX;
3257 return is_valid_mask(attr_mask, req, opt);
3258 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3259 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3260 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3261 opt = IB_QP_MIN_RNR_TIMER;
3262 return is_valid_mask(attr_mask, req, opt);
3263 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3264 opt = IB_QP_MIN_RNR_TIMER;
3265 return is_valid_mask(attr_mask, req, opt);
3266 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3267 return is_valid_mask(attr_mask, req, opt);
3268 }
3269 return false;
3270}
3271
776a3906
MS		 3272/* mlx5_ib_modify_dct: modify a DCT QP
3273 * valid transitions are:
3274 * RESET to INIT: must set access_flags, pkey_index and port
3275 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3276 * mtu, gid_index and hop_limit
3277 * Other transitions and attributes are illegal
3278 */
3279static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3280 int attr_mask, struct ib_udata *udata)
3281{
3282 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3283 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3284 enum ib_qp_state cur_state, new_state;
3285 int err = 0;
3286 int required = IB_QP_STATE;
3287 void *dctc;
3288
3289 if (!(attr_mask & IB_QP_STATE))
3290 return -EINVAL;
3291
3292 cur_state = qp->state;
3293 new_state = attr->qp_state;
3294
3295 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3296 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3297 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3298 if (!is_valid_mask(attr_mask, required, 0))
3299 return -EINVAL;
3300
3301 if (attr->port_num == 0 ||
3302 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3303 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3304 attr->port_num, dev->num_ports);
3305 return -EINVAL;
3306 }
3307 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3308 MLX5_SET(dctc, dctc, rre, 1);
3309 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3310 MLX5_SET(dctc, dctc, rwe, 1);
3311 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3312 if (!mlx5_ib_dc_atomic_is_supported(dev))
3313 return -EOPNOTSUPP;
3314 MLX5_SET(dctc, dctc, rae, 1);
3315 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3316 }
3317 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3318 MLX5_SET(dctc, dctc, port, attr->port_num);
3319 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3320
3321 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3322 struct mlx5_ib_modify_qp_resp resp = {};
3323 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3324 sizeof(resp.dctn);
3325
3326 if (udata->outlen < min_resp_len)
3327 return -EINVAL;
3328 resp.response_length = min_resp_len;
3329
3330 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3331 if (!is_valid_mask(attr_mask, required, 0))
3332 return -EINVAL;
3333 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3334 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3335 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3336 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3337 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3338 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3339
3340 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3341 MLX5_ST_SZ_BYTES(create_dct_in));
3342 if (err)
3343 return err;
3344 resp.dctn = qp->dct.mdct.mqp.qpn;
3345 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3346 if (err) {
3347 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3348 return err;
3349 }
3350 } else {
3351 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3352 return -EINVAL;
3353 }
3354 if (err)
3355 qp->state = IB_QPS_ERR;
3356 else
3357 qp->state = new_state;
3358 return err;
3359}
3360
e126ba97
EC		 3361int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3362 int attr_mask, struct ib_udata *udata)
3363{
3364 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3365 struct mlx5_ib_qp *qp = to_mqp(ibqp);
61147f39 3366 struct mlx5_ib_modify_qp ucmd = {};
d16e91da 3367 enum ib_qp_type qp_type;
e126ba97 3368 enum ib_qp_state cur_state, new_state;
61147f39 3369 size_t required_cmd_sz;
e126ba97
EC		 3370 int err = -EINVAL;
3371 int port;
2811ba51 3372 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
e126ba97 3373
28d61370
YH		 3374 if (ibqp->rwq_ind_tbl)
3375 return -ENOSYS;
3376
61147f39
BW		 3377 if (udata && udata->inlen) {
3378 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3379 sizeof(ucmd.reserved);
3380 if (udata->inlen < required_cmd_sz)
3381 return -EINVAL;
3382
3383 if (udata->inlen > sizeof(ucmd) &&
3384 !ib_is_udata_cleared(udata, sizeof(ucmd),
3385 udata->inlen - sizeof(ucmd)))
3386 return -EOPNOTSUPP;
3387
3388 if (ib_copy_from_udata(&ucmd, udata,
3389 min(udata->inlen, sizeof(ucmd))))
3390 return -EFAULT;
3391
3392 if (ucmd.comp_mask ||
3393 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3394 memchr_inv(&ucmd.burst_info.reserved, 0,
3395 sizeof(ucmd.burst_info.reserved)))
3396 return -EOPNOTSUPP;
3397 }
3398
d16e91da
HE		 3399 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3400 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3401
c32a4f29
MS		 3402 if (ibqp->qp_type == IB_QPT_DRIVER)
3403 qp_type = qp->qp_sub_type;
3404 else
3405 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3406 IB_QPT_GSI : ibqp->qp_type;
3407
776a3906
MS		 3408 if (qp_type == MLX5_IB_QPT_DCT)
3409 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
d16e91da 3410
e126ba97
EC		 3411 mutex_lock(&qp->mutex);
3412
3413 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3414 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3415
2811ba51
AS		 3416 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3417 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3418 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3419 }
3420
c2e53b2c
YH		 3421 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3422 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3423 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3424 attr_mask);
3425 goto out;
3426 }
3427 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
c32a4f29
MS		 3428 qp_type != MLX5_IB_QPT_DCI &&
3429 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
158abf86
HE		 3430 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3431 cur_state, new_state, ibqp->qp_type, attr_mask);
e126ba97 3432 goto out;
c32a4f29
MS		 3433 } else if (qp_type == MLX5_IB_QPT_DCI &&
3434 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3435 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3436 cur_state, new_state, qp_type, attr_mask);
3437 goto out;
158abf86 3438 }
e126ba97
EC		 3439
3440 if ((attr_mask & IB_QP_PORT) &&
938fe83c 3441 (attr->port_num == 0 ||
508562d6 3442 attr->port_num > dev->num_ports)) {
158abf86
HE		 3443 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3444 attr->port_num, dev->num_ports);
e126ba97 3445 goto out;
158abf86 3446 }
e126ba97
EC		 3447
3448 if (attr_mask & IB_QP_PKEY_INDEX) {
3449 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
938fe83c 3450 if (attr->pkey_index >=
158abf86
HE		 3451 dev->mdev->port_caps[port - 1].pkey_table_len) {
3452 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3453 attr->pkey_index);
e126ba97 3454 goto out;
158abf86 3455 }
e126ba97
EC		 3456 }
3457
3458 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
938fe83c 3459 attr->max_rd_atomic >
158abf86
HE		 3460 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3461 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3462 attr->max_rd_atomic);
e126ba97 3463 goto out;
158abf86 3464 }
e126ba97
EC		 3465
3466 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
938fe83c 3467 attr->max_dest_rd_atomic >
158abf86
HE		 3468 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3469 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3470 attr->max_dest_rd_atomic);
e126ba97 3471 goto out;
158abf86 3472 }
e126ba97
EC		 3473
3474 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3475 err = 0;
3476 goto out;
3477 }
3478
61147f39
BW		 3479 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3480 new_state, &ucmd);
e126ba97
EC		 3481
3482out:
3483 mutex_unlock(&qp->mutex);
3484 return err;
3485}
3486
3487static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3488{
3489 struct mlx5_ib_cq *cq;
3490 unsigned cur;
3491
3492 cur = wq->head - wq->tail;
3493 if (likely(cur + nreq < wq->max_post))
3494 return 0;
3495
3496 cq = to_mcq(ib_cq);
3497 spin_lock(&cq->lock);
3498 cur = wq->head - wq->tail;
3499 spin_unlock(&cq->lock);
3500
3501 return cur + nreq >= wq->max_post;
3502}
3503
3504static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3505 u64 remote_addr, u32 rkey)
3506{
3507 rseg->raddr = cpu_to_be64(remote_addr);
3508 rseg->rkey = cpu_to_be32(rkey);
3509 rseg->reserved = 0;
3510}
3511
f0313965
ES		 3512static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3513 struct ib_send_wr *wr, void *qend,
3514 struct mlx5_ib_qp *qp, int *size)
3515{
3516 void *seg = eseg;
3517
3518 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3519
3520 if (wr->send_flags & IB_SEND_IP_CSUM)
3521 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3522 MLX5_ETH_WQE_L4_CSUM;
3523
3524 seg += sizeof(struct mlx5_wqe_eth_seg);
3525 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3526
3527 if (wr->opcode == IB_WR_LSO) {
3528 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2b31f7ae 3529 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
f0313965
ES		 3530 u64 left, leftlen, copysz;
3531 void *pdata = ud_wr->header;
3532
3533 left = ud_wr->hlen;
3534 eseg->mss = cpu_to_be16(ud_wr->mss);
2b31f7ae 3535 eseg->inline_hdr.sz = cpu_to_be16(left);
f0313965
ES		 3536
3537 /*
3538 * check if there is space till the end of queue, if yes,
3539 * copy all in one shot, otherwise copy till the end of queue,
3540 * rollback and than the copy the left
3541 */
2b31f7ae 3542 leftlen = qend - (void *)eseg->inline_hdr.start;
f0313965
ES		 3543 copysz = min_t(u64, leftlen, left);
3544
3545 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3546
3547 if (likely(copysz > size_of_inl_hdr_start)) {
3548 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3549 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3550 }
3551
3552 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3553 seg = mlx5_get_send_wqe(qp, 0);
3554 left -= copysz;
3555 pdata += copysz;
3556 memcpy(seg, pdata, left);
3557 seg += ALIGN(left, 16);
3558 *size += ALIGN(left, 16) / 16;
3559 }
3560 }
3561
3562 return seg;
3563}
3564
e126ba97
EC		 3565static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3566 struct ib_send_wr *wr)
3567{
e622f2f4
CH		 3568 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3569 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3570 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
e126ba97
EC		 3571}
3572
3573static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3574{
3575 dseg->byte_count = cpu_to_be32(sg->length);
3576 dseg->lkey = cpu_to_be32(sg->lkey);
3577 dseg->addr = cpu_to_be64(sg->addr);
3578}
3579
31616255 3580static u64 get_xlt_octo(u64 bytes)
e126ba97 3581{
31616255
AK		 3582 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3583 MLX5_IB_UMR_OCTOWORD;
e126ba97
EC		 3584}
3585
3586static __be64 frwr_mkey_mask(void)
3587{
3588 u64 result;
3589
3590 result = MLX5_MKEY_MASK_LEN |
3591 MLX5_MKEY_MASK_PAGE_SIZE |
3592 MLX5_MKEY_MASK_START_ADDR |
3593 MLX5_MKEY_MASK_EN_RINVAL |
3594 MLX5_MKEY_MASK_KEY |
3595 MLX5_MKEY_MASK_LR |
3596 MLX5_MKEY_MASK_LW |
3597 MLX5_MKEY_MASK_RR |
3598 MLX5_MKEY_MASK_RW |
3599 MLX5_MKEY_MASK_A |
3600 MLX5_MKEY_MASK_SMALL_FENCE |
3601 MLX5_MKEY_MASK_FREE;
3602
3603 return cpu_to_be64(result);
3604}
3605
e6631814
SG		 3606static __be64 sig_mkey_mask(void)
3607{
3608 u64 result;
3609
3610 result = MLX5_MKEY_MASK_LEN |
3611 MLX5_MKEY_MASK_PAGE_SIZE |
3612 MLX5_MKEY_MASK_START_ADDR |
d5436ba0 3613 MLX5_MKEY_MASK_EN_SIGERR |
e6631814
SG		 3614 MLX5_MKEY_MASK_EN_RINVAL |
3615 MLX5_MKEY_MASK_KEY |
3616 MLX5_MKEY_MASK_LR |
3617 MLX5_MKEY_MASK_LW |
3618 MLX5_MKEY_MASK_RR |
3619 MLX5_MKEY_MASK_RW |
3620 MLX5_MKEY_MASK_SMALL_FENCE |
3621 MLX5_MKEY_MASK_FREE |
3622 MLX5_MKEY_MASK_BSF_EN;
3623
3624 return cpu_to_be64(result);
3625}
3626
8a187ee5 3627static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 3628 struct mlx5_ib_mr *mr)
8a187ee5 3629{
31616255 3630 int size = mr->ndescs * mr->desc_size;
8a187ee5
SG		 3631
3632 memset(umr, 0, sizeof(*umr));
b005d316 3633
8a187ee5 3634 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
31616255 3635 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
8a187ee5
SG		 3636 umr->mkey_mask = frwr_mkey_mask();
3637}
3638
dd01e66a 3639static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
e126ba97
EC		 3640{
3641 memset(umr, 0, sizeof(*umr));
dd01e66a 3642 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2d221588 3643 umr->flags = MLX5_UMR_INLINE;
e126ba97
EC		 3644}
3645
31616255 3646static __be64 get_umr_enable_mr_mask(void)
968e78dd
HE		 3647{
3648 u64 result;
3649
31616255 3650 result = MLX5_MKEY_MASK_KEY |
968e78dd
HE		 3651 MLX5_MKEY_MASK_FREE;
3652
968e78dd
HE		 3653 return cpu_to_be64(result);
3654}
3655
31616255 3656static __be64 get_umr_disable_mr_mask(void)
968e78dd
HE		 3657{
3658 u64 result;
3659
3660 result = MLX5_MKEY_MASK_FREE;
3661
3662 return cpu_to_be64(result);
3663}
3664
56e11d62
NO		 3665static __be64 get_umr_update_translation_mask(void)
3666{
3667 u64 result;
3668
3669 result = MLX5_MKEY_MASK_LEN |
3670 MLX5_MKEY_MASK_PAGE_SIZE |
31616255 3671 MLX5_MKEY_MASK_START_ADDR;
56e11d62
NO		 3672
3673 return cpu_to_be64(result);
3674}
3675
31616255 3676static __be64 get_umr_update_access_mask(int atomic)
56e11d62
NO		 3677{
3678 u64 result;
3679
31616255
AK		 3680 result = MLX5_MKEY_MASK_LR |
3681 MLX5_MKEY_MASK_LW |
56e11d62 3682 MLX5_MKEY_MASK_RR |
31616255
AK		 3683 MLX5_MKEY_MASK_RW;
3684
3685 if (atomic)
3686 result |= MLX5_MKEY_MASK_A;
56e11d62
NO		 3687
3688 return cpu_to_be64(result);
3689}
3690
3691static __be64 get_umr_update_pd_mask(void)
3692{
3693 u64 result;
3694
31616255 3695 result = MLX5_MKEY_MASK_PD;
56e11d62
NO		 3696
3697 return cpu_to_be64(result);
3698}
3699
e126ba97 3700static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
578e7264 3701 struct ib_send_wr *wr, int atomic)
e126ba97 3702{
e622f2f4 3703 struct mlx5_umr_wr *umrwr = umr_wr(wr);
e126ba97
EC		 3704
3705 memset(umr, 0, sizeof(*umr));
3706
968e78dd
HE		 3707 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3708 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3709 else
3710 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3711
31616255
AK		 3712 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3713 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3714 u64 offset = get_xlt_octo(umrwr->offset);
3715
3716 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3717 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3718 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
e126ba97 3719 }
31616255
AK		 3720 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3721 umr->mkey_mask |= get_umr_update_translation_mask();
3722 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3723 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3724 umr->mkey_mask |= get_umr_update_pd_mask();
3725 }
3726 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3727 umr->mkey_mask |= get_umr_enable_mr_mask();
3728 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3729 umr->mkey_mask |= get_umr_disable_mr_mask();
e126ba97
EC		 3730
3731 if (!wr->num_sge)
968e78dd 3732 umr->flags |= MLX5_UMR_INLINE;
e126ba97
EC		 3733}
3734
3735static u8 get_umr_flags(int acc)
3736{
3737 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3738 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3739 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3740 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2ac45934 3741 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
e126ba97
EC		 3742}
3743
8a187ee5
SG		 3744static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3745 struct mlx5_ib_mr *mr,
3746 u32 key, int access)
3747{
3748 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3749
3750 memset(seg, 0, sizeof(*seg));
b005d316 3751
ec22eb53 3752 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
b005d316 3753 seg->log2_page_size = ilog2(mr->ibmr.page_size);
ec22eb53 3754 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
b005d316
SG		 3755 /* KLMs take twice the size of MTTs */
3756 ndescs *= 2;
3757
3758 seg->flags = get_umr_flags(access) | mr->access_mode;
8a187ee5
SG		 3759 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3760 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3761 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3762 seg->len = cpu_to_be64(mr->ibmr.length);
3763 seg->xlt_oct_size = cpu_to_be32(ndescs);
8a187ee5
SG		 3764}
3765
dd01e66a 3766static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
e126ba97
EC		 3767{
3768 memset(seg, 0, sizeof(*seg));
dd01e66a 3769 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97
EC		 3770}
3771
3772static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3773{
e622f2f4 3774 struct mlx5_umr_wr *umrwr = umr_wr(wr);
968e78dd 3775
e126ba97 3776 memset(seg, 0, sizeof(*seg));
31616255 3777 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
968e78dd 3778 seg->status = MLX5_MKEY_STATUS_FREE;
e126ba97 3779
968e78dd 3780 seg->flags = convert_access(umrwr->access_flags);
31616255
AK		 3781 if (umrwr->pd)
3782 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3783 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3784 !umrwr->length)
3785 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3786
3787 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
968e78dd
HE		 3788 seg->len = cpu_to_be64(umrwr->length);
3789 seg->log2_page_size = umrwr->page_shift;
746b5583 3790 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
968e78dd 3791 mlx5_mkey_variant(umrwr->mkey));
e126ba97
EC		 3792}
3793
8a187ee5
SG		 3794static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3795 struct mlx5_ib_mr *mr,
3796 struct mlx5_ib_pd *pd)
3797{
3798 int bcount = mr->desc_size * mr->ndescs;
3799
3800 dseg->addr = cpu_to_be64(mr->desc_map);
3801 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3802 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3803}
3804
e126ba97
EC		 3805static __be32 send_ieth(struct ib_send_wr *wr)
3806{
3807 switch (wr->opcode) {
3808 case IB_WR_SEND_WITH_IMM:
3809 case IB_WR_RDMA_WRITE_WITH_IMM:
3810 return wr->ex.imm_data;
3811
3812 case IB_WR_SEND_WITH_INV:
3813 return cpu_to_be32(wr->ex.invalidate_rkey);
3814
3815 default:
3816 return 0;
3817 }
3818}
3819
3820static u8 calc_sig(void *wqe, int size)
3821{
3822 u8 *p = wqe;
3823 u8 res = 0;
3824 int i;
3825
3826 for (i = 0; i < size; i++)
3827 res ^= p[i];
3828
3829 return ~res;
3830}
3831
3832static u8 wq_sig(void *wqe)
3833{
3834 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3835}
3836
3837static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3838 void *wqe, int *sz)
3839{
3840 struct mlx5_wqe_inline_seg *seg;
3841 void *qend = qp->sq.qend;
3842 void *addr;
3843 int inl = 0;
3844 int copy;
3845 int len;
3846 int i;
3847
3848 seg = wqe;
3849 wqe += sizeof(*seg);
3850 for (i = 0; i < wr->num_sge; i++) {
3851 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3852 len = wr->sg_list[i].length;
3853 inl += len;
3854
3855 if (unlikely(inl > qp->max_inline_data))
3856 return -ENOMEM;
3857
3858 if (unlikely(wqe + len > qend)) {
3859 copy = qend - wqe;
3860 memcpy(wqe, addr, copy);
3861 addr += copy;
3862 len -= copy;
3863 wqe = mlx5_get_send_wqe(qp, 0);
3864 }
3865 memcpy(wqe, addr, len);
3866 wqe += len;
3867 }
3868
3869 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3870
3871 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3872
3873 return 0;
3874}
3875
e6631814
SG		 3876static u16 prot_field_size(enum ib_signature_type type)
3877{
3878 switch (type) {
3879 case IB_SIG_TYPE_T10_DIF:
3880 return MLX5_DIF_SIZE;
3881 default:
3882 return 0;
3883 }
3884}
3885
3886static u8 bs_selector(int block_size)
3887{
3888 switch (block_size) {
3889 case 512: return 0x1;
3890 case 520: return 0x2;
3891 case 4096: return 0x3;
3892 case 4160: return 0x4;
3893 case 1073741824: return 0x5;
3894 default: return 0;
3895 }
3896}
3897
78eda2bb
SG		 3898static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3899 struct mlx5_bsf_inl *inl)
e6631814 3900{
142537f4
SG		 3901 /* Valid inline section and allow BSF refresh */
3902 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3903 MLX5_BSF_REFRESH_DIF);
3904 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3905 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
78eda2bb
SG		 3906 /* repeating block */
3907 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3908 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3909 MLX5_DIF_CRC : MLX5_DIF_IPCS;
e6631814 3910
78eda2bb
SG		 3911 if (domain->sig.dif.ref_remap)
3912 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
e6631814 3913
78eda2bb
SG		 3914 if (domain->sig.dif.app_escape) {
3915 if (domain->sig.dif.ref_escape)
3916 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3917 else
3918 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
e6631814
SG		 3919 }
3920
78eda2bb
SG		 3921 inl->dif_app_bitmask_check =
3922 cpu_to_be16(domain->sig.dif.apptag_check_mask);
e6631814
SG		 3923}
3924
3925static int mlx5_set_bsf(struct ib_mr *sig_mr,
3926 struct ib_sig_attrs *sig_attrs,
3927 struct mlx5_bsf *bsf, u32 data_size)
3928{
3929 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3930 struct mlx5_bsf_basic *basic = &bsf->basic;
3931 struct ib_sig_domain *mem = &sig_attrs->mem;
3932 struct ib_sig_domain *wire = &sig_attrs->wire;
e6631814 3933
c7f44fbd 3934 memset(bsf, 0, sizeof(*bsf));
78eda2bb
SG		 3935
3936 /* Basic + Extended + Inline */
3937 basic->bsf_size_sbs = 1 << 7;
3938 /* Input domain check byte mask */
3939 basic->check_byte_mask = sig_attrs->check_mask;
3940 basic->raw_data_size = cpu_to_be32(data_size);
3941
3942 /* Memory domain */
e6631814 3943 switch (sig_attrs->mem.sig_type) {
78eda2bb
SG		 3944 case IB_SIG_TYPE_NONE:
3945 break;
e6631814 3946 case IB_SIG_TYPE_T10_DIF:
78eda2bb
SG		 3947 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3948 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3949 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3950 break;
3951 default:
3952 return -EINVAL;
3953 }
e6631814 3954
78eda2bb
SG		 3955 /* Wire domain */
3956 switch (sig_attrs->wire.sig_type) {
3957 case IB_SIG_TYPE_NONE:
3958 break;
3959 case IB_SIG_TYPE_T10_DIF:
e6631814 3960 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
78eda2bb 3961 mem->sig_type == wire->sig_type) {
e6631814 3962 /* Same block structure */
142537f4 3963 basic->bsf_size_sbs |= 1 << 4;
e6631814 3964 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
fd22f78c 3965 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
c7f44fbd 3966 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
fd22f78c 3967 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
c7f44fbd 3968 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
fd22f78c 3969 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
e6631814
SG		 3970 } else
3971 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3972
142537f4 3973 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
78eda2bb 3974 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
e6631814 3975 break;
e6631814
SG		 3976 default:
3977 return -EINVAL;
3978 }
3979
3980 return 0;
3981}
3982
e622f2f4
CH		 3983static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3984 struct mlx5_ib_qp *qp, void **seg, int *size)
e6631814 3985{
e622f2f4
CH		 3986 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3987 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 3988 struct mlx5_bsf *bsf;
e622f2f4
CH		 3989 u32 data_len = wr->wr.sg_list->length;
3990 u32 data_key = wr->wr.sg_list->lkey;
3991 u64 data_va = wr->wr.sg_list->addr;
e6631814
SG		 3992 int ret;
3993 int wqe_size;
3994
e622f2f4
CH		 3995 if (!wr->prot ||
3996 (data_key == wr->prot->lkey &&
3997 data_va == wr->prot->addr &&
3998 data_len == wr->prot->length)) {
e6631814
SG		 3999 /**
4000 * Source domain doesn't contain signature information
5c273b16 4001 * or data and protection are interleaved in memory.
e6631814
SG		 4002 * So need construct:
4003 * ------------------
4004 * | data_klm |
4005 * ------------------
4006 * | BSF |
4007 * ------------------
4008 **/
4009 struct mlx5_klm *data_klm = *seg;
4010
4011 data_klm->bcount = cpu_to_be32(data_len);
4012 data_klm->key = cpu_to_be32(data_key);
4013 data_klm->va = cpu_to_be64(data_va);
4014 wqe_size = ALIGN(sizeof(*data_klm), 64);
4015 } else {
4016 /**
4017 * Source domain contains signature information
4018 * So need construct a strided block format:
4019 * ---------------------------
4020 * | stride_block_ctrl |
4021 * ---------------------------
4022 * | data_klm |
4023 * ---------------------------
4024 * | prot_klm |
4025 * ---------------------------
4026 * | BSF |
4027 * ---------------------------
4028 **/
4029 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4030 struct mlx5_stride_block_entry *data_sentry;
4031 struct mlx5_stride_block_entry *prot_sentry;
e622f2f4
CH		 4032 u32 prot_key = wr->prot->lkey;
4033 u64 prot_va = wr->prot->addr;
e6631814
SG		 4034 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4035 int prot_size;
4036
4037 sblock_ctrl = *seg;
4038 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4039 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4040
4041 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4042 if (!prot_size) {
4043 pr_err("Bad block size given: %u\n", block_size);
4044 return -EINVAL;
4045 }
4046 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4047 prot_size);
4048 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4049 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4050 sblock_ctrl->num_entries = cpu_to_be16(2);
4051
4052 data_sentry->bcount = cpu_to_be16(block_size);
4053 data_sentry->key = cpu_to_be32(data_key);
4054 data_sentry->va = cpu_to_be64(data_va);
5c273b16
SG		 4055 data_sentry->stride = cpu_to_be16(block_size);
4056
e6631814
SG		 4057 prot_sentry->bcount = cpu_to_be16(prot_size);
4058 prot_sentry->key = cpu_to_be32(prot_key);
5c273b16
SG		 4059 prot_sentry->va = cpu_to_be64(prot_va);
4060 prot_sentry->stride = cpu_to_be16(prot_size);
e6631814 4061
e6631814
SG		 4062 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4063 sizeof(*prot_sentry), 64);
4064 }
4065
4066 *seg += wqe_size;
4067 *size += wqe_size / 16;
4068 if (unlikely((*seg == qp->sq.qend)))
4069 *seg = mlx5_get_send_wqe(qp, 0);
4070
4071 bsf = *seg;
4072 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4073 if (ret)
4074 return -EINVAL;
4075
4076 *seg += sizeof(*bsf);
4077 *size += sizeof(*bsf) / 16;
4078 if (unlikely((*seg == qp->sq.qend)))
4079 *seg = mlx5_get_send_wqe(qp, 0);
4080
4081 return 0;
4082}
4083
4084static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
31616255 4085 struct ib_sig_handover_wr *wr, u32 size,
e6631814
SG		 4086 u32 length, u32 pdn)
4087{
e622f2f4 4088 struct ib_mr *sig_mr = wr->sig_mr;
e6631814 4089 u32 sig_key = sig_mr->rkey;
d5436ba0 4090 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
e6631814
SG		 4091
4092 memset(seg, 0, sizeof(*seg));
4093
e622f2f4 4094 seg->flags = get_umr_flags(wr->access_flags) |
ec22eb53 4095 MLX5_MKC_ACCESS_MODE_KLMS;
e6631814 4096 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
d5436ba0 4097 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
e6631814
SG		 4098 MLX5_MKEY_BSF_EN | pdn);
4099 seg->len = cpu_to_be64(length);
31616255 4100 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
e6631814
SG		 4101 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4102}
4103
4104static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
31616255 4105 u32 size)
e6631814
SG		 4106{
4107 memset(umr, 0, sizeof(*umr));
4108
4109 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
31616255 4110 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
e6631814
SG		 4111 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4112 umr->mkey_mask = sig_mkey_mask();
4113}
4114
4115
e622f2f4 4116static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
e6631814
SG		 4117 void **seg, int *size)
4118{
e622f2f4
CH		 4119 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4120 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
e6631814 4121 u32 pdn = get_pd(qp)->pdn;
31616255 4122 u32 xlt_size;
e6631814
SG		 4123 int region_len, ret;
4124
e622f2f4
CH		 4125 if (unlikely(wr->wr.num_sge != 1) ||
4126 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
d5436ba0
SG		 4127 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4128 unlikely(!sig_mr->sig->sig_status_checked))
e6631814
SG		 4129 return -EINVAL;
4130
4131 /* length of the protected region, data + protection */
e622f2f4
CH		 4132 region_len = wr->wr.sg_list->length;
4133 if (wr->prot &&
4134 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4135 wr->prot->addr != wr->wr.sg_list->addr ||
4136 wr->prot->length != wr->wr.sg_list->length))
4137 region_len += wr->prot->length;
e6631814
SG		 4138
4139 /**
4140 * KLM octoword size - if protection was provided
4141 * then we use strided block format (3 octowords),
4142 * else we use single KLM (1 octoword)
4143 **/
31616255 4144 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
e6631814 4145
31616255 4146 set_sig_umr_segment(*seg, xlt_size);
e6631814
SG		 4147 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4148 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4149 if (unlikely((*seg == qp->sq.qend)))
4150 *seg = mlx5_get_send_wqe(qp, 0);
4151
31616255 4152 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
e6631814
SG		 4153 *seg += sizeof(struct mlx5_mkey_seg);
4154 *size += sizeof(struct mlx5_mkey_seg) / 16;
4155 if (unlikely((*seg == qp->sq.qend)))
4156 *seg = mlx5_get_send_wqe(qp, 0);
4157
4158 ret = set_sig_data_segment(wr, qp, seg, size);
4159 if (ret)
4160 return ret;
4161
d5436ba0 4162 sig_mr->sig->sig_status_checked = false;
e6631814
SG		 4163 return 0;
4164}
4165
4166static int set_psv_wr(struct ib_sig_domain *domain,
4167 u32 psv_idx, void **seg, int *size)
4168{
4169 struct mlx5_seg_set_psv *psv_seg = *seg;
4170
4171 memset(psv_seg, 0, sizeof(*psv_seg));
4172 psv_seg->psv_num = cpu_to_be32(psv_idx);
4173 switch (domain->sig_type) {
78eda2bb
SG		 4174 case IB_SIG_TYPE_NONE:
4175 break;
e6631814
SG		 4176 case IB_SIG_TYPE_T10_DIF:
4177 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4178 domain->sig.dif.app_tag);
4179 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
e6631814 4180 break;
e6631814 4181 default:
12bbf1ea
LR		 4182 pr_err("Bad signature type (%d) is given.\n",
4183 domain->sig_type);
4184 return -EINVAL;
e6631814
SG		 4185 }
4186
78eda2bb
SG		 4187 *seg += sizeof(*psv_seg);
4188 *size += sizeof(*psv_seg) / 16;
4189
e6631814
SG		 4190 return 0;
4191}
4192
8a187ee5
SG		 4193static int set_reg_wr(struct mlx5_ib_qp *qp,
4194 struct ib_reg_wr *wr,
4195 void **seg, int *size)
4196{
4197 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4198 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4199
4200 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4201 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4202 "Invalid IB_SEND_INLINE send flag\n");
4203 return -EINVAL;
4204 }
4205
4206 set_reg_umr_seg(*seg, mr);
4207 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4208 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4209 if (unlikely((*seg == qp->sq.qend)))
4210 *seg = mlx5_get_send_wqe(qp, 0);
4211
4212 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4213 *seg += sizeof(struct mlx5_mkey_seg);
4214 *size += sizeof(struct mlx5_mkey_seg) / 16;
4215 if (unlikely((*seg == qp->sq.qend)))
4216 *seg = mlx5_get_send_wqe(qp, 0);
4217
4218 set_reg_data_seg(*seg, mr, pd);
4219 *seg += sizeof(struct mlx5_wqe_data_seg);
4220 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4221
4222 return 0;
4223}
4224
dd01e66a 4225static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
e126ba97 4226{
dd01e66a 4227 set_linv_umr_seg(*seg);
e126ba97
EC		 4228 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4229 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4230 if (unlikely((*seg == qp->sq.qend)))
4231 *seg = mlx5_get_send_wqe(qp, 0);
dd01e66a 4232 set_linv_mkey_seg(*seg);
e126ba97
EC		 4233 *seg += sizeof(struct mlx5_mkey_seg);
4234 *size += sizeof(struct mlx5_mkey_seg) / 16;
4235 if (unlikely((*seg == qp->sq.qend)))
4236 *seg = mlx5_get_send_wqe(qp, 0);
e126ba97
EC		 4237}
4238
4239static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4240{
4241 __be32 *p = NULL;
4242 int tidx = idx;
4243 int i, j;
4244
4245 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4246 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4247 if ((i & 0xf) == 0) {
4248 void *buf = mlx5_get_send_wqe(qp, tidx);
4249 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4250 p = buf;
4251 j = 0;
4252 }
4253 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4254 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4255 be32_to_cpu(p[j + 3]));
4256 }
4257}
4258
6e5eadac
SG		 4259static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4260 struct mlx5_wqe_ctrl_seg **ctrl,
6a4f139a 4261 struct ib_send_wr *wr, unsigned *idx,
6e5eadac
SG		 4262 int *size, int nreq)
4263{
b2a232d2
LR		 4264 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4265 return -ENOMEM;
6e5eadac
SG		 4266
4267 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4268 *seg = mlx5_get_send_wqe(qp, *idx);
4269 *ctrl = *seg;
4270 *(uint32_t *)(*seg + 8) = 0;
4271 (*ctrl)->imm = send_ieth(wr);
4272 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4273 (wr->send_flags & IB_SEND_SIGNALED ?
4274 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4275 (wr->send_flags & IB_SEND_SOLICITED ?
4276 MLX5_WQE_CTRL_SOLICITED : 0);
4277
4278 *seg += sizeof(**ctrl);
4279 *size = sizeof(**ctrl) / 16;
4280
b2a232d2 4281 return 0;
6e5eadac
SG		 4282}
4283
4284static void finish_wqe(struct mlx5_ib_qp *qp,
4285 struct mlx5_wqe_ctrl_seg *ctrl,
4286 u8 size, unsigned idx, u64 wr_id,
6e8484c5 4287 int nreq, u8 fence, u32 mlx5_opcode)
6e5eadac
SG		 4288{
4289 u8 opmod = 0;
4290
4291 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4292 mlx5_opcode | ((u32)opmod << 24));
19098df2 4293 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
6e5eadac 4294 ctrl->fm_ce_se |= fence;
6e5eadac
SG		 4295 if (unlikely(qp->wq_sig))
4296 ctrl->signature = wq_sig(ctrl);
4297
4298 qp->sq.wrid[idx] = wr_id;
4299 qp->sq.w_list[idx].opcode = mlx5_opcode;
4300 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4301 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4302 qp->sq.w_list[idx].next = qp->sq.cur_post;
4303}
4304
4305
e126ba97
EC		 4306int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4307 struct ib_send_wr **bad_wr)
4308{
4309 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4310 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
89ea94a7 4311 struct mlx5_core_dev *mdev = dev->mdev;
d16e91da 4312 struct mlx5_ib_qp *qp;
e6631814 4313 struct mlx5_ib_mr *mr;
e126ba97
EC		 4314 struct mlx5_wqe_data_seg *dpseg;
4315 struct mlx5_wqe_xrc_seg *xrc;
d16e91da 4316 struct mlx5_bf *bf;
e126ba97 4317 int uninitialized_var(size);
d16e91da 4318 void *qend;
e126ba97 4319 unsigned long flags;
e126ba97
EC		 4320 unsigned idx;
4321 int err = 0;
e126ba97
EC		 4322 int num_sge;
4323 void *seg;
4324 int nreq;
4325 int i;
4326 u8 next_fence = 0;
e126ba97
EC		 4327 u8 fence;
4328
d16e91da
HE		 4329 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4330 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4331
4332 qp = to_mqp(ibqp);
5fe9dec0 4333 bf = &qp->bf;
d16e91da
HE		 4334 qend = qp->sq.qend;
4335
e126ba97
EC		 4336 spin_lock_irqsave(&qp->sq.lock, flags);
4337
89ea94a7
MG		 4338 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4339 err = -EIO;
4340 *bad_wr = wr;
4341 nreq = 0;
4342 goto out;
4343 }
4344
e126ba97 4345 for (nreq = 0; wr; nreq++, wr = wr->next) {
a8f731eb 4346 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
e126ba97
EC		 4347 mlx5_ib_warn(dev, "\n");
4348 err = -EINVAL;
4349 *bad_wr = wr;
4350 goto out;
4351 }
4352
6e5eadac
SG		 4353 num_sge = wr->num_sge;
4354 if (unlikely(num_sge > qp->sq.max_gs)) {
e126ba97 4355 mlx5_ib_warn(dev, "\n");
24be409b 4356 err = -EINVAL;
e126ba97
EC		 4357 *bad_wr = wr;
4358 goto out;
4359 }
4360
6e5eadac
SG		 4361 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4362 if (err) {
e126ba97
EC		 4363 mlx5_ib_warn(dev, "\n");
4364 err = -ENOMEM;
4365 *bad_wr = wr;
4366 goto out;
4367 }
4368
6e8484c5
MG		 4369 if (wr->opcode == IB_WR_LOCAL_INV ||
4370 wr->opcode == IB_WR_REG_MR) {
4371 fence = dev->umr_fence;
4372 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4373 } else if (wr->send_flags & IB_SEND_FENCE) {
4374 if (qp->next_fence)
4375 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4376 else
4377 fence = MLX5_FENCE_MODE_FENCE;
4378 } else {
4379 fence = qp->next_fence;
4380 }
4381
e126ba97
EC		 4382 switch (ibqp->qp_type) {
4383 case IB_QPT_XRC_INI:
4384 xrc = seg;
e126ba97
EC		 4385 seg += sizeof(*xrc);
4386 size += sizeof(*xrc) / 16;
4387 /* fall through */
4388 case IB_QPT_RC:
4389 switch (wr->opcode) {
4390 case IB_WR_RDMA_READ:
4391 case IB_WR_RDMA_WRITE:
4392 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4393 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4394 rdma_wr(wr)->rkey);
f241e749 4395 seg += sizeof(struct mlx5_wqe_raddr_seg);
e126ba97
EC		 4396 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4397 break;
4398
4399 case IB_WR_ATOMIC_CMP_AND_SWP:
4400 case IB_WR_ATOMIC_FETCH_AND_ADD:
e126ba97 4401 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
81bea28f
EC		 4402 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4403 err = -ENOSYS;
4404 *bad_wr = wr;
4405 goto out;
e126ba97
EC		 4406
4407 case IB_WR_LOCAL_INV:
e126ba97
EC		 4408 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4409 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
dd01e66a 4410 set_linv_wr(qp, &seg, &size);
e126ba97
EC		 4411 num_sge = 0;
4412 break;
4413
8a187ee5 4414 case IB_WR_REG_MR:
8a187ee5
SG		 4415 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4416 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4417 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4418 if (err) {
4419 *bad_wr = wr;
4420 goto out;
4421 }
4422 num_sge = 0;
4423 break;
4424
e6631814
SG		 4425 case IB_WR_REG_SIG_MR:
4426 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
e622f2f4 4427 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
e6631814
SG		 4428
4429 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4430 err = set_sig_umr_wr(wr, qp, &seg, &size);
4431 if (err) {
4432 mlx5_ib_warn(dev, "\n");
4433 *bad_wr = wr;
4434 goto out;
4435 }
4436
6e8484c5
MG		 4437 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4438 fence, MLX5_OPCODE_UMR);
e6631814
SG		 4439 /*
4440 * SET_PSV WQEs are not signaled and solicited
4441 * on error
4442 */
4443 wr->send_flags &= ~IB_SEND_SIGNALED;
4444 wr->send_flags |= IB_SEND_SOLICITED;
4445 err = begin_wqe(qp, &seg, &ctrl, wr,
4446 &idx, &size, nreq);
4447 if (err) {
4448 mlx5_ib_warn(dev, "\n");
4449 err = -ENOMEM;
4450 *bad_wr = wr;
4451 goto out;
4452 }
4453
e622f2f4 4454 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
e6631814
SG		 4455 mr->sig->psv_memory.psv_idx, &seg,
4456 &size);
4457 if (err) {
4458 mlx5_ib_warn(dev, "\n");
4459 *bad_wr = wr;
4460 goto out;
4461 }
4462
6e8484c5
MG		 4463 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4464 fence, MLX5_OPCODE_SET_PSV);
e6631814
SG		 4465 err = begin_wqe(qp, &seg, &ctrl, wr,
4466 &idx, &size, nreq);
4467 if (err) {
4468 mlx5_ib_warn(dev, "\n");
4469 err = -ENOMEM;
4470 *bad_wr = wr;
4471 goto out;
4472 }
4473
e622f2f4 4474 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
e6631814
SG		 4475 mr->sig->psv_wire.psv_idx, &seg,
4476 &size);
4477 if (err) {
4478 mlx5_ib_warn(dev, "\n");
4479 *bad_wr = wr;
4480 goto out;
4481 }
4482
6e8484c5
MG		 4483 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4484 fence, MLX5_OPCODE_SET_PSV);
4485 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
e6631814
SG		 4486 num_sge = 0;
4487 goto skip_psv;
4488
e126ba97
EC		 4489 default:
4490 break;
4491 }
4492 break;
4493
4494 case IB_QPT_UC:
4495 switch (wr->opcode) {
4496 case IB_WR_RDMA_WRITE:
4497 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 4498 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4499 rdma_wr(wr)->rkey);
e126ba97
EC		 4500 seg += sizeof(struct mlx5_wqe_raddr_seg);
4501 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4502 break;
4503
4504 default:
4505 break;
4506 }
4507 break;
4508
e126ba97 4509 case IB_QPT_SMI:
1e0e50b6
MG		 4510 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4511 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4512 err = -EPERM;
4513 *bad_wr = wr;
4514 goto out;
4515 }
f6b1ee34 4516 /* fall through */
d16e91da 4517 case MLX5_IB_QPT_HW_GSI:
e126ba97 4518 set_datagram_seg(seg, wr);
f241e749 4519 seg += sizeof(struct mlx5_wqe_datagram_seg);
e126ba97
EC		 4520 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4521 if (unlikely((seg == qend)))
4522 seg = mlx5_get_send_wqe(qp, 0);
4523 break;
f0313965
ES		 4524 case IB_QPT_UD:
4525 set_datagram_seg(seg, wr);
4526 seg += sizeof(struct mlx5_wqe_datagram_seg);
4527 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4528
4529 if (unlikely((seg == qend)))
4530 seg = mlx5_get_send_wqe(qp, 0);
4531
4532 /* handle qp that supports ud offload */
4533 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4534 struct mlx5_wqe_eth_pad *pad;
e126ba97 4535
f0313965
ES		 4536 pad = seg;
4537 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4538 seg += sizeof(struct mlx5_wqe_eth_pad);
4539 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4540
4541 seg = set_eth_seg(seg, wr, qend, qp, &size);
4542
4543 if (unlikely((seg == qend)))
4544 seg = mlx5_get_send_wqe(qp, 0);
4545 }
4546 break;
e126ba97
EC		 4547 case MLX5_IB_QPT_REG_UMR:
4548 if (wr->opcode != MLX5_IB_WR_UMR) {
4549 err = -EINVAL;
4550 mlx5_ib_warn(dev, "bad opcode\n");
4551 goto out;
4552 }
4553 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
e622f2f4 4554 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
578e7264 4555 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
e126ba97
EC		 4556 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4557 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4558 if (unlikely((seg == qend)))
4559 seg = mlx5_get_send_wqe(qp, 0);
4560 set_reg_mkey_segment(seg, wr);
4561 seg += sizeof(struct mlx5_mkey_seg);
4562 size += sizeof(struct mlx5_mkey_seg) / 16;
4563 if (unlikely((seg == qend)))
4564 seg = mlx5_get_send_wqe(qp, 0);
4565 break;
4566
4567 default:
4568 break;
4569 }
4570
4571 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4572 int uninitialized_var(sz);
4573
4574 err = set_data_inl_seg(qp, wr, seg, &sz);
4575 if (unlikely(err)) {
4576 mlx5_ib_warn(dev, "\n");
4577 *bad_wr = wr;
4578 goto out;
4579 }
e126ba97
EC		 4580 size += sz;
4581 } else {
4582 dpseg = seg;
4583 for (i = 0; i < num_sge; i++) {
4584 if (unlikely(dpseg == qend)) {
4585 seg = mlx5_get_send_wqe(qp, 0);
4586 dpseg = seg;
4587 }
4588 if (likely(wr->sg_list[i].length)) {
4589 set_data_ptr_seg(dpseg, wr->sg_list + i);
4590 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4591 dpseg++;
4592 }
4593 }
4594 }
4595
6e8484c5
MG		 4596 qp->next_fence = next_fence;
4597 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
6e5eadac 4598 mlx5_ib_opcode[wr->opcode]);
e6631814 4599skip_psv:
e126ba97
EC		 4600 if (0)
4601 dump_wqe(qp, idx, size);
4602 }
4603
4604out:
4605 if (likely(nreq)) {
4606 qp->sq.head += nreq;
4607
4608 /* Make sure that descriptors are written before
4609 * updating doorbell record and ringing the doorbell
4610 */
4611 wmb();
4612
4613 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4614
ada388f7
EC		 4615 /* Make sure doorbell record is visible to the HCA before
4616 * we hit doorbell */
4617 wmb();
4618
5fe9dec0
EC		 4619 /* currently we support only regular doorbells */
4620 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4621 /* Make sure doorbells don't leak out of SQ spinlock
4622 * and reach the HCA out of order.
4623 */
4624 mmiowb();
e126ba97 4625 bf->offset ^= bf->buf_size;
e126ba97
EC		 4626 }
4627
4628 spin_unlock_irqrestore(&qp->sq.lock, flags);
4629
4630 return err;
4631}
4632
4633static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4634{
4635 sig->signature = calc_sig(sig, size);
4636}
4637
4638int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4639 struct ib_recv_wr **bad_wr)
4640{
4641 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4642 struct mlx5_wqe_data_seg *scat;
4643 struct mlx5_rwqe_sig *sig;
89ea94a7
MG		 4644 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4645 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 4646 unsigned long flags;
4647 int err = 0;
4648 int nreq;
4649 int ind;
4650 int i;
4651
d16e91da
HE		 4652 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4653 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4654
e126ba97
EC		 4655 spin_lock_irqsave(&qp->rq.lock, flags);
4656
89ea94a7
MG		 4657 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4658 err = -EIO;
4659 *bad_wr = wr;
4660 nreq = 0;
4661 goto out;
4662 }
4663
e126ba97
EC		 4664 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4665
4666 for (nreq = 0; wr; nreq++, wr = wr->next) {
4667 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4668 err = -ENOMEM;
4669 *bad_wr = wr;
4670 goto out;
4671 }
4672
4673 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4674 err = -EINVAL;
4675 *bad_wr = wr;
4676 goto out;
4677 }
4678
4679 scat = get_recv_wqe(qp, ind);
4680 if (qp->wq_sig)
4681 scat++;
4682
4683 for (i = 0; i < wr->num_sge; i++)
4684 set_data_ptr_seg(scat + i, wr->sg_list + i);
4685
4686 if (i < qp->rq.max_gs) {
4687 scat[i].byte_count = 0;
4688 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4689 scat[i].addr = 0;
4690 }
4691
4692 if (qp->wq_sig) {
4693 sig = (struct mlx5_rwqe_sig *)scat;
4694 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4695 }
4696
4697 qp->rq.wrid[ind] = wr->wr_id;
4698
4699 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4700 }
4701
4702out:
4703 if (likely(nreq)) {
4704 qp->rq.head += nreq;
4705
4706 /* Make sure that descriptors are written before
4707 * doorbell record.
4708 */
4709 wmb();
4710
4711 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4712 }
4713
4714 spin_unlock_irqrestore(&qp->rq.lock, flags);
4715
4716 return err;
4717}
4718
4719static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4720{
4721 switch (mlx5_state) {
4722 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4723 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4724 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4725 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4726 case MLX5_QP_STATE_SQ_DRAINING:
4727 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4728 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4729 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4730 default: return -1;
4731 }
4732}
4733
4734static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4735{
4736 switch (mlx5_mig_state) {
4737 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4738 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4739 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4740 default: return -1;
4741 }
4742}
4743
4744static int to_ib_qp_access_flags(int mlx5_flags)
4745{
4746 int ib_flags = 0;
4747
4748 if (mlx5_flags & MLX5_QP_BIT_RRE)
4749 ib_flags |= IB_ACCESS_REMOTE_READ;
4750 if (mlx5_flags & MLX5_QP_BIT_RWE)
4751 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4752 if (mlx5_flags & MLX5_QP_BIT_RAE)
4753 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4754
4755 return ib_flags;
4756}
4757
38349389 4758static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
d8966fcd 4759 struct rdma_ah_attr *ah_attr,
38349389 4760 struct mlx5_qp_path *path)
e126ba97 4761{
e126ba97 4762
d8966fcd 4763 memset(ah_attr, 0, sizeof(*ah_attr));
e126ba97 4764
e7996a9a 4765 if (!path->port || path->port > ibdev->num_ports)
e126ba97
EC		 4766 return;
4767
ae59c3f0
LR		 4768 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4769
d8966fcd
DC		 4770 rdma_ah_set_port_num(ah_attr, path->port);
4771 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4772
4773 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4774 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4775 rdma_ah_set_static_rate(ah_attr,
4776 path->static_rate ? path->static_rate - 5 : 0);
4777 if (path->grh_mlid & (1 << 7)) {
4778 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4779
4780 rdma_ah_set_grh(ah_attr, NULL,
4781 tc_fl & 0xfffff,
4782 path->mgid_index,
4783 path->hop_limit,
4784 (tc_fl >> 20) & 0xff);
4785 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
e126ba97
EC		 4786 }
4787}
4788
6d2f89df 4789static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4790 struct mlx5_ib_sq *sq,
4791 u8 *sq_state)
4792{
4793 void *out;
4794 void *sqc;
4795 int inlen;
4796 int err;
4797
4798 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
1b9a07ee 4799 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4800 if (!out)
4801 return -ENOMEM;
4802
4803 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4804 if (err)
4805 goto out;
4806
4807 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4808 *sq_state = MLX5_GET(sqc, sqc, state);
4809 sq->state = *sq_state;
4810
4811out:
4812 kvfree(out);
4813 return err;
4814}
4815
4816static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4817 struct mlx5_ib_rq *rq,
4818 u8 *rq_state)
4819{
4820 void *out;
4821 void *rqc;
4822 int inlen;
4823 int err;
4824
4825 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
1b9a07ee 4826 out = kvzalloc(inlen, GFP_KERNEL);
6d2f89df 4827 if (!out)
4828 return -ENOMEM;
4829
4830 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4831 if (err)
4832 goto out;
4833
4834 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4835 *rq_state = MLX5_GET(rqc, rqc, state);
4836 rq->state = *rq_state;
4837
4838out:
4839 kvfree(out);
4840 return err;
4841}
4842
4843static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4844 struct mlx5_ib_qp *qp, u8 *qp_state)
4845{
4846 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4847 [MLX5_RQC_STATE_RST] = {
4848 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4849 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4850 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4851 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4852 },
4853 [MLX5_RQC_STATE_RDY] = {
4854 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4855 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4856 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4857 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4858 },
4859 [MLX5_RQC_STATE_ERR] = {
4860 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4861 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4862 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4863 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4864 },
4865 [MLX5_RQ_STATE_NA] = {
4866 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4867 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4868 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4869 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4870 },
4871 };
4872
4873 *qp_state = sqrq_trans[rq_state][sq_state];
4874
4875 if (*qp_state == MLX5_QP_STATE_BAD) {
4876 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4877 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4878 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4879 return -EINVAL;
4880 }
4881
4882 if (*qp_state == MLX5_QP_STATE)
4883 *qp_state = qp->state;
4884
4885 return 0;
4886}
4887
4888static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4889 struct mlx5_ib_qp *qp,
4890 u8 *raw_packet_qp_state)
4891{
4892 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4893 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4894 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4895 int err;
4896 u8 sq_state = MLX5_SQ_STATE_NA;
4897 u8 rq_state = MLX5_RQ_STATE_NA;
4898
4899 if (qp->sq.wqe_cnt) {
4900 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4901 if (err)
4902 return err;
4903 }
4904
4905 if (qp->rq.wqe_cnt) {
4906 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4907 if (err)
4908 return err;
4909 }
4910
4911 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4912 raw_packet_qp_state);
4913}
4914
4915static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4916 struct ib_qp_attr *qp_attr)
e126ba97 4917{
09a7d9ec 4918 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
e126ba97
EC		 4919 struct mlx5_qp_context *context;
4920 int mlx5_state;
09a7d9ec 4921 u32 *outb;
e126ba97
EC		 4922 int err = 0;
4923
09a7d9ec 4924 outb = kzalloc(outlen, GFP_KERNEL);
6d2f89df 4925 if (!outb)
4926 return -ENOMEM;
4927
19098df2 4928 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
09a7d9ec 4929 outlen);
e126ba97 4930 if (err)
6d2f89df 4931 goto out;
e126ba97 4932
09a7d9ec
SM		 4933 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4934 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4935
e126ba97
EC		 4936 mlx5_state = be32_to_cpu(context->flags) >> 28;
4937
4938 qp->state = to_ib_qp_state(mlx5_state);
e126ba97
EC		 4939 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4940 qp_attr->path_mig_state =
4941 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4942 qp_attr->qkey = be32_to_cpu(context->qkey);
4943 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4944 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4945 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4946 qp_attr->qp_access_flags =
4947 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4948
4949 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
38349389
DC		 4950 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4951 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
d3ae2bde
NO		 4952 qp_attr->alt_pkey_index =
4953 be16_to_cpu(context->alt_path.pkey_index);
d8966fcd
DC		 4954 qp_attr->alt_port_num =
4955 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
e126ba97
EC		 4956 }
4957
d3ae2bde 4958 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
e126ba97
EC		 4959 qp_attr->port_num = context->pri_path.port;
4960
4961 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4962 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4963
4964 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4965
4966 qp_attr->max_dest_rd_atomic =
4967 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4968 qp_attr->min_rnr_timer =
4969 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4970 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4971 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4972 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4973 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
6d2f89df 4974
4975out:
4976 kfree(outb);
4977 return err;
4978}
4979
776a3906
MS		 4980static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
4981 struct ib_qp_attr *qp_attr, int qp_attr_mask,
4982 struct ib_qp_init_attr *qp_init_attr)
4983{
4984 struct mlx5_core_dct *dct = &mqp->dct.mdct;
4985 u32 *out;
4986 u32 access_flags = 0;
4987 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
4988 void *dctc;
4989 int err;
4990 int supported_mask = IB_QP_STATE |
4991 IB_QP_ACCESS_FLAGS |
4992 IB_QP_PORT |
4993 IB_QP_MIN_RNR_TIMER |
4994 IB_QP_AV |
4995 IB_QP_PATH_MTU |
4996 IB_QP_PKEY_INDEX;
4997
4998 if (qp_attr_mask & ~supported_mask)
4999 return -EINVAL;
5000 if (mqp->state != IB_QPS_RTR)
5001 return -EINVAL;
5002
5003 out = kzalloc(outlen, GFP_KERNEL);
5004 if (!out)
5005 return -ENOMEM;
5006
5007 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5008 if (err)
5009 goto out;
5010
5011 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5012
5013 if (qp_attr_mask & IB_QP_STATE)
5014 qp_attr->qp_state = IB_QPS_RTR;
5015
5016 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5017 if (MLX5_GET(dctc, dctc, rre))
5018 access_flags |= IB_ACCESS_REMOTE_READ;
5019 if (MLX5_GET(dctc, dctc, rwe))
5020 access_flags |= IB_ACCESS_REMOTE_WRITE;
5021 if (MLX5_GET(dctc, dctc, rae))
5022 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5023 qp_attr->qp_access_flags = access_flags;
5024 }
5025
5026 if (qp_attr_mask & IB_QP_PORT)
5027 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5028 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5029 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5030 if (qp_attr_mask & IB_QP_AV) {
5031 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5032 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5033 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5034 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5035 }
5036 if (qp_attr_mask & IB_QP_PATH_MTU)
5037 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5038 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5039 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5040out:
5041 kfree(out);
5042 return err;
5043}
5044
6d2f89df 5045int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5046 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5047{
5048 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5049 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5050 int err = 0;
5051 u8 raw_packet_qp_state;
5052
28d61370
YH		 5053 if (ibqp->rwq_ind_tbl)
5054 return -ENOSYS;
5055
d16e91da
HE		 5056 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5057 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5058 qp_init_attr);
5059
c2e53b2c
YH		 5060 /* Not all of output fields are applicable, make sure to zero them */
5061 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5062 memset(qp_attr, 0, sizeof(*qp_attr));
5063
776a3906
MS		 5064 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5065 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5066 qp_attr_mask, qp_init_attr);
5067
6d2f89df 5068 mutex_lock(&qp->mutex);
5069
c2e53b2c
YH		 5070 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5071 qp->flags & MLX5_IB_QP_UNDERLAY) {
6d2f89df 5072 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5073 if (err)
5074 goto out;
5075 qp->state = raw_packet_qp_state;
5076 qp_attr->port_num = 1;
5077 } else {
5078 err = query_qp_attr(dev, qp, qp_attr);
5079 if (err)
5080 goto out;
5081 }
5082
5083 qp_attr->qp_state = qp->state;
e126ba97
EC		 5084 qp_attr->cur_qp_state = qp_attr->qp_state;
5085 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5086 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5087
5088 if (!ibqp->uobject) {
0540d814 5089 qp_attr->cap.max_send_wr = qp->sq.max_post;
e126ba97 5090 qp_attr->cap.max_send_sge = qp->sq.max_gs;
0540d814 5091 qp_init_attr->qp_context = ibqp->qp_context;
e126ba97
EC		 5092 } else {
5093 qp_attr->cap.max_send_wr = 0;
5094 qp_attr->cap.max_send_sge = 0;
5095 }
5096
0540d814
NO		 5097 qp_init_attr->qp_type = ibqp->qp_type;
5098 qp_init_attr->recv_cq = ibqp->recv_cq;
5099 qp_init_attr->send_cq = ibqp->send_cq;
5100 qp_init_attr->srq = ibqp->srq;
5101 qp_attr->cap.max_inline_data = qp->max_inline_data;
e126ba97
EC		 5102
5103 qp_init_attr->cap = qp_attr->cap;
5104
5105 qp_init_attr->create_flags = 0;
5106 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5107 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5108
051f2630
LR		 5109 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5110 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5111 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5112 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5113 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5114 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
b11a4f9c
HE		 5115 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5116 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
051f2630 5117
e126ba97
EC		 5118 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5119 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5120
e126ba97
EC		 5121out:
5122 mutex_unlock(&qp->mutex);
5123 return err;
5124}
5125
5126struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5127 struct ib_ucontext *context,
5128 struct ib_udata *udata)
5129{
5130 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5131 struct mlx5_ib_xrcd *xrcd;
5132 int err;
5133
938fe83c 5134 if (!MLX5_CAP_GEN(dev->mdev, xrc))
e126ba97
EC		 5135 return ERR_PTR(-ENOSYS);
5136
5137 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5138 if (!xrcd)
5139 return ERR_PTR(-ENOMEM);
5140
9603b61d 5141 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
e126ba97
EC		 5142 if (err) {
5143 kfree(xrcd);
5144 return ERR_PTR(-ENOMEM);
5145 }
5146
5147 return &xrcd->ibxrcd;
5148}
5149
5150int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5151{
5152 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5153 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5154 int err;
5155
9603b61d 5156 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
b081808a 5157 if (err)
e126ba97 5158 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
e126ba97
EC		 5159
5160 kfree(xrcd);
e126ba97
EC		 5161 return 0;
5162}
79b20a6c 5163
350d0e4c
YH		 5164static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5165{
5166 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5167 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5168 struct ib_event event;
5169
5170 if (rwq->ibwq.event_handler) {
5171 event.device = rwq->ibwq.device;
5172 event.element.wq = &rwq->ibwq;
5173 switch (type) {
5174 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5175 event.event = IB_EVENT_WQ_FATAL;
5176 break;
5177 default:
5178 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5179 return;
5180 }
5181
5182 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5183 }
5184}
5185
03404e8a
MG		 5186static int set_delay_drop(struct mlx5_ib_dev *dev)
5187{
5188 int err = 0;
5189
5190 mutex_lock(&dev->delay_drop.lock);
5191 if (dev->delay_drop.activate)
5192 goto out;
5193
5194 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5195 if (err)
5196 goto out;
5197
5198 dev->delay_drop.activate = true;
5199out:
5200 mutex_unlock(&dev->delay_drop.lock);
fe248c3a
MG		 5201
5202 if (!err)
5203 atomic_inc(&dev->delay_drop.rqs_cnt);
03404e8a
MG		 5204 return err;
5205}
5206
79b20a6c
YH		 5207static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5208 struct ib_wq_init_attr *init_attr)
5209{
5210 struct mlx5_ib_dev *dev;
4be6da1e 5211 int has_net_offloads;
79b20a6c
YH		 5212 __be64 *rq_pas0;
5213 void *in;
5214 void *rqc;
5215 void *wq;
5216 int inlen;
5217 int err;
5218
5219 dev = to_mdev(pd->device);
5220
5221 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
1b9a07ee 5222 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5223 if (!in)
5224 return -ENOMEM;
5225
5226 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5227 MLX5_SET(rqc, rqc, mem_rq_type,
5228 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5229 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5230 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5231 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5232 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5233 wq = MLX5_ADDR_OF(rqc, rqc, wq);
ccc87087
NO		 5234 MLX5_SET(wq, wq, wq_type,
5235 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5236 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
b1383aa6
NO		 5237 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5238 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5239 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5240 err = -EOPNOTSUPP;
5241 goto out;
5242 } else {
5243 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5244 }
5245 }
79b20a6c 5246 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
ccc87087
NO		 5247 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5248 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5249 MLX5_SET(wq, wq, log_wqe_stride_size,
5250 rwq->single_stride_log_num_of_bytes -
5251 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5252 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5253 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5254 }
79b20a6c
YH		 5255 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5256 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5257 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5258 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5259 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5260 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4be6da1e 5261 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
b1f74a84 5262 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4be6da1e 5263 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
b1f74a84
NO		 5264 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5265 err = -EOPNOTSUPP;
5266 goto out;
5267 }
5268 } else {
5269 MLX5_SET(rqc, rqc, vsd, 1);
5270 }
4be6da1e
NO		 5271 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5272 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5273 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5274 err = -EOPNOTSUPP;
5275 goto out;
5276 }
5277 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5278 }
03404e8a
MG		 5279 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5280 if (!(dev->ib_dev.attrs.raw_packet_caps &
5281 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5282 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5283 err = -EOPNOTSUPP;
5284 goto out;
5285 }
5286 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5287 }
79b20a6c
YH		 5288 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5289 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
350d0e4c 5290 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
03404e8a
MG		 5291 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5292 err = set_delay_drop(dev);
5293 if (err) {
5294 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5295 err);
5296 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5297 } else {
5298 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5299 }
5300 }
b1f74a84 5301out:
79b20a6c
YH		 5302 kvfree(in);
5303 return err;
5304}
5305
5306static int set_user_rq_size(struct mlx5_ib_dev *dev,
5307 struct ib_wq_init_attr *wq_init_attr,
5308 struct mlx5_ib_create_wq *ucmd,
5309 struct mlx5_ib_rwq *rwq)
5310{
5311 /* Sanity check RQ size before proceeding */
5312 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5313 return -EINVAL;
5314
5315 if (!ucmd->rq_wqe_count)
5316 return -EINVAL;
5317
5318 rwq->wqe_count = ucmd->rq_wqe_count;
5319 rwq->wqe_shift = ucmd->rq_wqe_shift;
5320 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
5321 rwq->log_rq_stride = rwq->wqe_shift;
5322 rwq->log_rq_size = ilog2(rwq->wqe_count);
5323 return 0;
5324}
5325
5326static int prepare_user_rq(struct ib_pd *pd,
5327 struct ib_wq_init_attr *init_attr,
5328 struct ib_udata *udata,
5329 struct mlx5_ib_rwq *rwq)
5330{
5331 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5332 struct mlx5_ib_create_wq ucmd = {};
5333 int err;
5334 size_t required_cmd_sz;
5335
ccc87087
NO		 5336 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5337 + sizeof(ucmd.single_stride_log_num_of_bytes);
79b20a6c
YH		 5338 if (udata->inlen < required_cmd_sz) {
5339 mlx5_ib_dbg(dev, "invalid inlen\n");
5340 return -EINVAL;
5341 }
5342
5343 if (udata->inlen > sizeof(ucmd) &&
5344 !ib_is_udata_cleared(udata, sizeof(ucmd),
5345 udata->inlen - sizeof(ucmd))) {
5346 mlx5_ib_dbg(dev, "inlen is not supported\n");
5347 return -EOPNOTSUPP;
5348 }
5349
5350 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5351 mlx5_ib_dbg(dev, "copy failed\n");
5352 return -EFAULT;
5353 }
5354
ccc87087 5355 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
79b20a6c
YH		 5356 mlx5_ib_dbg(dev, "invalid comp mask\n");
5357 return -EOPNOTSUPP;
ccc87087
NO		 5358 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5359 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5360 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5361 return -EOPNOTSUPP;
5362 }
5363 if ((ucmd.single_stride_log_num_of_bytes <
5364 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5365 (ucmd.single_stride_log_num_of_bytes >
5366 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5367 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5368 ucmd.single_stride_log_num_of_bytes,
5369 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5370 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5371 return -EINVAL;
5372 }
5373 if ((ucmd.single_wqe_log_num_of_strides >
5374 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5375 (ucmd.single_wqe_log_num_of_strides <
5376 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5377 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5378 ucmd.single_wqe_log_num_of_strides,
5379 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5380 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5381 return -EINVAL;
5382 }
5383 rwq->single_stride_log_num_of_bytes =
5384 ucmd.single_stride_log_num_of_bytes;
5385 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5386 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5387 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
79b20a6c
YH		 5388 }
5389
5390 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5391 if (err) {
5392 mlx5_ib_dbg(dev, "err %d\n", err);
5393 return err;
5394 }
5395
5396 err = create_user_rq(dev, pd, rwq, &ucmd);
5397 if (err) {
5398 mlx5_ib_dbg(dev, "err %d\n", err);
5399 if (err)
5400 return err;
5401 }
5402
5403 rwq->user_index = ucmd.user_index;
5404 return 0;
5405}
5406
5407struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5408 struct ib_wq_init_attr *init_attr,
5409 struct ib_udata *udata)
5410{
5411 struct mlx5_ib_dev *dev;
5412 struct mlx5_ib_rwq *rwq;
5413 struct mlx5_ib_create_wq_resp resp = {};
5414 size_t min_resp_len;
5415 int err;
5416
5417 if (!udata)
5418 return ERR_PTR(-ENOSYS);
5419
5420 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5421 if (udata->outlen && udata->outlen < min_resp_len)
5422 return ERR_PTR(-EINVAL);
5423
5424 dev = to_mdev(pd->device);
5425 switch (init_attr->wq_type) {
5426 case IB_WQT_RQ:
5427 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5428 if (!rwq)
5429 return ERR_PTR(-ENOMEM);
5430 err = prepare_user_rq(pd, init_attr, udata, rwq);
5431 if (err)
5432 goto err;
5433 err = create_rq(rwq, pd, init_attr);
5434 if (err)
5435 goto err_user_rq;
5436 break;
5437 default:
5438 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5439 init_attr->wq_type);
5440 return ERR_PTR(-EINVAL);
5441 }
5442
350d0e4c 5443 rwq->ibwq.wq_num = rwq->core_qp.qpn;
79b20a6c
YH		 5444 rwq->ibwq.state = IB_WQS_RESET;
5445 if (udata->outlen) {
5446 resp.response_length = offsetof(typeof(resp), response_length) +
5447 sizeof(resp.response_length);
5448 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5449 if (err)
5450 goto err_copy;
5451 }
5452
350d0e4c
YH		 5453 rwq->core_qp.event = mlx5_ib_wq_event;
5454 rwq->ibwq.event_handler = init_attr->event_handler;
79b20a6c
YH		 5455 return &rwq->ibwq;
5456
5457err_copy:
350d0e4c 5458 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
79b20a6c 5459err_user_rq:
fe248c3a 5460 destroy_user_rq(dev, pd, rwq);
79b20a6c
YH		 5461err:
5462 kfree(rwq);
5463 return ERR_PTR(err);
5464}
5465
5466int mlx5_ib_destroy_wq(struct ib_wq *wq)
5467{
5468 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5469 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5470
350d0e4c 5471 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
fe248c3a 5472 destroy_user_rq(dev, wq->pd, rwq);
79b20a6c
YH		 5473 kfree(rwq);
5474
5475 return 0;
5476}
5477
c5f90929
YH		 5478struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5479 struct ib_rwq_ind_table_init_attr *init_attr,
5480 struct ib_udata *udata)
5481{
5482 struct mlx5_ib_dev *dev = to_mdev(device);
5483 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5484 int sz = 1 << init_attr->log_ind_tbl_size;
5485 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5486 size_t min_resp_len;
5487 int inlen;
5488 int err;
5489 int i;
5490 u32 *in;
5491 void *rqtc;
5492
5493 if (udata->inlen > 0 &&
5494 !ib_is_udata_cleared(udata, 0,
5495 udata->inlen))
5496 return ERR_PTR(-EOPNOTSUPP);
5497
efd7f400
MG		 5498 if (init_attr->log_ind_tbl_size >
5499 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5500 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5501 init_attr->log_ind_tbl_size,
5502 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5503 return ERR_PTR(-EINVAL);
5504 }
5505
c5f90929
YH		 5506 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5507 if (udata->outlen && udata->outlen < min_resp_len)
5508 return ERR_PTR(-EINVAL);
5509
5510 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5511 if (!rwq_ind_tbl)
5512 return ERR_PTR(-ENOMEM);
5513
5514 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 5515 in = kvzalloc(inlen, GFP_KERNEL);
c5f90929
YH		 5516 if (!in) {
5517 err = -ENOMEM;
5518 goto err;
5519 }
5520
5521 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5522
5523 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5524 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5525
5526 for (i = 0; i < sz; i++)
5527 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5528
5529 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5530 kvfree(in);
5531
5532 if (err)
5533 goto err;
5534
5535 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5536 if (udata->outlen) {
5537 resp.response_length = offsetof(typeof(resp), response_length) +
5538 sizeof(resp.response_length);
5539 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5540 if (err)
5541 goto err_copy;
5542 }
5543
5544 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5545
5546err_copy:
5547 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5548err:
5549 kfree(rwq_ind_tbl);
5550 return ERR_PTR(err);
5551}
5552
5553int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5554{
5555 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5556 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5557
5558 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5559
5560 kfree(rwq_ind_tbl);
5561 return 0;
5562}
5563
79b20a6c
YH		 5564int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5565 u32 wq_attr_mask, struct ib_udata *udata)
5566{
5567 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5568 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5569 struct mlx5_ib_modify_wq ucmd = {};
5570 size_t required_cmd_sz;
5571 int curr_wq_state;
5572 int wq_state;
5573 int inlen;
5574 int err;
5575 void *rqc;
5576 void *in;
5577
5578 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5579 if (udata->inlen < required_cmd_sz)
5580 return -EINVAL;
5581
5582 if (udata->inlen > sizeof(ucmd) &&
5583 !ib_is_udata_cleared(udata, sizeof(ucmd),
5584 udata->inlen - sizeof(ucmd)))
5585 return -EOPNOTSUPP;
5586
5587 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5588 return -EFAULT;
5589
5590 if (ucmd.comp_mask || ucmd.reserved)
5591 return -EOPNOTSUPP;
5592
5593 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 5594 in = kvzalloc(inlen, GFP_KERNEL);
79b20a6c
YH		 5595 if (!in)
5596 return -ENOMEM;
5597
5598 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5599
5600 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5601 wq_attr->curr_wq_state : wq->state;
5602 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5603 wq_attr->wq_state : curr_wq_state;
5604 if (curr_wq_state == IB_WQS_ERR)
5605 curr_wq_state = MLX5_RQC_STATE_ERR;
5606 if (wq_state == IB_WQS_ERR)
5607 wq_state = MLX5_RQC_STATE_ERR;
5608 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5609 MLX5_SET(rqc, rqc, state, wq_state);
5610
b1f74a84
NO		 5611 if (wq_attr_mask & IB_WQ_FLAGS) {
5612 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5613 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5614 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5615 mlx5_ib_dbg(dev, "VLAN offloads are not "
5616 "supported\n");
5617 err = -EOPNOTSUPP;
5618 goto out;
5619 }
5620 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5621 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5622 MLX5_SET(rqc, rqc, vsd,
5623 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5624 }
b1383aa6
NO		 5625
5626 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5627 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5628 err = -EOPNOTSUPP;
5629 goto out;
5630 }
b1f74a84
NO		 5631 }
5632
23a6964e
MD		 5633 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5634 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5635 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5636 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
e1f24a79
PP		 5637 MLX5_SET(rqc, rqc, counter_set_id,
5638 dev->port->cnts.set_id);
23a6964e
MD		 5639 } else
5640 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5641 dev->ib_dev.name);
5642 }
5643
350d0e4c 5644 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
79b20a6c
YH		 5645 if (!err)
5646 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5647
b1f74a84
NO		 5648out:
5649 kvfree(in);
79b20a6c
YH		 5650 return err;
5651}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git