[people/ms/u-boot.git] / drivers / input / ps2ser.c

/***********************************************************************
 *
 * (C) Copyright 2004-2009
 * DENX Software Engineering
 * Wolfgang Denk, wd@denx.de
 *
 * Simple 16550A serial driver
 *
 * Originally from linux source (drivers/char/ps2ser.c)
 *
 * Used by the PS/2 multiplexer driver (ps2mult.c)
 *
 ***********************************************************************/

#include <common.h>

#include <asm/io.h>
#include <asm/atomic.h>
#include <ps2mult.h>
/* This is needed for ns16550.h */
#ifndef CONFIG_SYS_NS16550_REG_SIZE
#define CONFIG_SYS_NS16550_REG_SIZE 1
#endif
#include <ns16550.h>

DECLARE_GLOBAL_DATA_PTR;

/* #define	DEBUG */

#define PS2SER_BAUD	57600

#ifdef CONFIG_MPC5xxx
#if CONFIG_PS2SERIAL == 1
#define PSC_BASE MPC5XXX_PSC1
#elif CONFIG_PS2SERIAL == 2
#define PSC_BASE MPC5XXX_PSC2
#elif CONFIG_PS2SERIAL == 3
#define PSC_BASE MPC5XXX_PSC3
#elif CONFIG_PS2SERIAL == 4
#define PSC_BASE MPC5XXX_PSC4
#elif CONFIG_PS2SERIAL == 5
#define PSC_BASE MPC5XXX_PSC5
#elif CONFIG_PS2SERIAL == 6
#define PSC_BASE MPC5XXX_PSC6
#else
#error CONFIG_PS2SERIAL must be in 1 ... 6
#endif

#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)

#if CONFIG_PS2SERIAL == 1
#define COM_BASE (CONFIG_SYS_CCSRBAR+0x4500)
#elif CONFIG_PS2SERIAL == 2
#define COM_BASE (CONFIG_SYS_CCSRBAR+0x4600)
#else
#error CONFIG_PS2SERIAL must be in 1 ... 2
#endif

#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */

static int	ps2ser_getc_hw(void);
static void	ps2ser_interrupt(void *dev_id);

extern struct	serial_state rs_table[]; /* in serial.c */
#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && \
    !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8548) && \
    !defined(CONFIG_MPC8555)
static struct	serial_state *state;
#endif

static u_char	ps2buf[PS2BUF_SIZE];
static atomic_t	ps2buf_cnt;
static int	ps2buf_in_idx;
static int	ps2buf_out_idx;

#ifdef CONFIG_MPC5xxx
int ps2ser_init(void)
{
	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
	unsigned long baseclk;
	int div;

	/* reset PSC */
	psc->command = PSC_SEL_MODE_REG_1;

	/* select clock sources */
	psc->psc_clock_select = 0;
	baseclk = (gd->ipb_clk + 16) / 32;

	/* switch to UART mode */
	psc->sicr = 0;

	/* configure parity, bit length and so on */
	psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
	psc->mode = PSC_MODE_ONE_STOP;

	/* set up UART divisor */
	div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
	psc->ctur = (div >> 8) & 0xff;
	psc->ctlr = div & 0xff;

	/* disable all interrupts */
	psc->psc_imr = 0;

	/* reset and enable Rx/Tx */
	psc->command = PSC_RST_RX;
	psc->command = PSC_RST_TX;
	psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;

	return (0);
}

#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
int ps2ser_init(void)
{
	NS16550_t com_port = (NS16550_t)COM_BASE;

	com_port->ier = 0x00;
	com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
	com_port->dll = (CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
	com_port->dlm = ((CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
	com_port->lcr = UART_LCR_8N1;
	com_port->mcr = (UART_MCR_DTR | UART_MCR_RTS);
	com_port->fcr = (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR);

	return (0);
}

#else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */

static inline unsigned int ps2ser_in(int offset)
{
	return readb((unsigned long) state->iomem_base + offset);
}

static inline void ps2ser_out(int offset, int value)
{
	writeb(value, (unsigned long) state->iomem_base + offset);
}

int ps2ser_init(void)
{
	int quot;
	unsigned cval;

	state = rs_table + CONFIG_PS2SERIAL;

	quot = state->baud_base / PS2SER_BAUD;
	cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */

	  /* Set speed, enable interrupts, enable FIFO
	   */
	ps2ser_out(UART_LCR, cval | UART_LCR_DLAB);
	ps2ser_out(UART_DLL, quot & 0xff);
	ps2ser_out(UART_DLM, quot >> 8);
	ps2ser_out(UART_LCR, cval);
	ps2ser_out(UART_IER, UART_IER_RDI);
	ps2ser_out(UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS);
	ps2ser_out(UART_FCR,
	    UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);

	/* If we read 0xff from the LSR, there is no UART here
	 */
	if (ps2ser_in(UART_LSR) == 0xff) {
		printf ("ps2ser.c: no UART found\n");
		return -1;
	}

	irq_install_handler(state->irq, ps2ser_interrupt, NULL);

	return 0;
}
#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */

void ps2ser_putc(int chr)
{
#ifdef CONFIG_MPC5xxx
	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
	NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
#ifdef DEBUG
	printf(">>>> 0x%02x\n", chr);
#endif

#ifdef CONFIG_MPC5xxx
	while (!(psc->psc_status & PSC_SR_TXRDY));

	psc->psc_buffer_8 = chr;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
	while ((com_port->lsr & UART_LSR_THRE) == 0);
	com_port->thr = chr;
#else
	while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));

	ps2ser_out(UART_TX, chr);
#endif
}

static int ps2ser_getc_hw(void)
{
#ifdef CONFIG_MPC5xxx
	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
	NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
	int res = -1;

#ifdef CONFIG_MPC5xxx
	if (psc->psc_status & PSC_SR_RXRDY) {
		res = (psc->psc_buffer_8);
	}
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
	if (com_port->lsr & UART_LSR_DR) {
		res = com_port->rbr;
	}
#else
	if (ps2ser_in(UART_LSR) & UART_LSR_DR) {
		res = (ps2ser_in(UART_RX));
	}
#endif

	return res;
}

int ps2ser_getc(void)
{
	volatile int chr;
	int flags;

#ifdef DEBUG
	printf("<< ");
#endif

	flags = disable_interrupts();

	do {
		if (atomic_read(&ps2buf_cnt) != 0) {
			chr = ps2buf[ps2buf_out_idx++];
			ps2buf_out_idx &= (PS2BUF_SIZE - 1);
			atomic_dec(&ps2buf_cnt);
		} else {
			chr = ps2ser_getc_hw();
		}
	}
	while (chr < 0);

	if (flags) enable_interrupts();

#ifdef DEBUG
	printf("0x%02x\n", chr);
#endif

	return chr;
}

int ps2ser_check(void)
{
	int flags;

	flags = disable_interrupts();
	ps2ser_interrupt(NULL);
	if (flags) enable_interrupts();

	return atomic_read(&ps2buf_cnt);
}

static void ps2ser_interrupt(void *dev_id)
{
#ifdef CONFIG_MPC5xxx
	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
	NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
	int chr;
	int status;

	do {
		chr = ps2ser_getc_hw();
#ifdef CONFIG_MPC5xxx
		status = psc->psc_status;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
		status = com_port->lsr;
#else
		status = ps2ser_in(UART_IIR);
#endif
		if (chr < 0) continue;

		if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
			ps2buf[ps2buf_in_idx++] = chr;
			ps2buf_in_idx &= (PS2BUF_SIZE - 1);
			atomic_inc(&ps2buf_cnt);
		} else {
			printf ("ps2ser.c: buffer overflow\n");
		}
#ifdef CONFIG_MPC5xxx
	} while (status & PSC_SR_RXRDY);
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
      defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
	} while (status & UART_LSR_DR);
#else
	} while (status & UART_IIR_RDI);
#endif

	if (atomic_read(&ps2buf_cnt)) {
		ps2mult_callback(atomic_read(&ps2buf_cnt));
	}
}
Commit	Line	Data
1c43771b WD	1	/***********************************************************************
1c43771b WD	2	*
200779e3	3	* (C) Copyright 2004-2009
1c43771b WD	4	* DENX Software Engineering
1c43771b WD	5	* Wolfgang Denk, wd@denx.de
1c43771b WD	6	*
	7	* Simple 16550A serial driver
	8	*
	9	* Originally from linux source (drivers/char/ps2ser.c)
	10	*
	11	* Used by the PS/2 multiplexer driver (ps2mult.c)
	12	*
	13	***********************************************************************/
	14
	15	#include <common.h>
	16
1c43771b WD	17	#include <asm/io.h>
	18	#include <asm/atomic.h>
	19	#include <ps2mult.h>
200779e3 DZ	20	/* This is needed for ns16550.h */
	21	#ifndef CONFIG_SYS_NS16550_REG_SIZE
	22	#define CONFIG_SYS_NS16550_REG_SIZE 1
bc8bb6d4	23	#endif
200779e3	24	#include <ns16550.h>
1c43771b	25
d87080b7 WD	26	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	27
1c43771b WD	28	/* #define DEBUG */
	29
	30	#define PS2SER_BAUD 57600
	31
7e6bf358 WD	32	#ifdef CONFIG_MPC5xxx
	33	#if CONFIG_PS2SERIAL == 1
	34	#define PSC_BASE MPC5XXX_PSC1
	35	#elif CONFIG_PS2SERIAL == 2
	36	#define PSC_BASE MPC5XXX_PSC2
	37	#elif CONFIG_PS2SERIAL == 3
	38	#define PSC_BASE MPC5XXX_PSC3
7e6bf358 WD	39	#elif CONFIG_PS2SERIAL == 4
	40	#define PSC_BASE MPC5XXX_PSC4
	41	#elif CONFIG_PS2SERIAL == 5
	42	#define PSC_BASE MPC5XXX_PSC5
	43	#elif CONFIG_PS2SERIAL == 6
	44	#define PSC_BASE MPC5XXX_PSC6
	45	#else
	46	#error CONFIG_PS2SERIAL must be in 1 ... 6
	47	#endif
bc8bb6d4	48
1287e0c5 WG	49	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
1287e0c5 WG	50	defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8555)
bc8bb6d4 WD	51
bc8bb6d4 WD	52	#if CONFIG_PS2SERIAL == 1
6d0f6bcf	53	#define COM_BASE (CONFIG_SYS_CCSRBAR+0x4500)
bc8bb6d4	54	#elif CONFIG_PS2SERIAL == 2
6d0f6bcf	55	#define COM_BASE (CONFIG_SYS_CCSRBAR+0x4600)
bc8bb6d4 WD	56	#else
	57	#error CONFIG_PS2SERIAL must be in 1 ... 2
	58	#endif
	59
bd3143f0	60	#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
7e6bf358	61
1c43771b WD	62	static int ps2ser_getc_hw(void);
	63	static void ps2ser_interrupt(void *dev_id);
	64
	65	extern struct serial_state rs_table[]; /* in serial.c */
1287e0c5 WG	66	#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && \
	67	!defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8548) && \
	68	!defined(CONFIG_MPC8555)
ef978730	69	static struct serial_state *state;
7e6bf358	70	#endif
1c43771b WD	71
	72	static u_char ps2buf[PS2BUF_SIZE];
	73	static atomic_t ps2buf_cnt;
	74	static int ps2buf_in_idx;
	75	static int ps2buf_out_idx;
	76
7e6bf358 WD	77	#ifdef CONFIG_MPC5xxx
	78	int ps2ser_init(void)
	79	{
7e6bf358 WD	80	volatile struct mpc5xxx_psc psc = (struct mpc5xxx_psc )PSC_BASE;
	81	unsigned long baseclk;
	82	int div;
	83
	84	/* reset PSC */
	85	psc->command = PSC_SEL_MODE_REG_1;
	86
	87	/* select clock sources */
7e6bf358 WD	88	psc->psc_clock_select = 0;
7e6bf358 WD	89	baseclk = (gd->ipb_clk + 16) / 32;
7e6bf358 WD	90
	91	/* switch to UART mode */
	92	psc->sicr = 0;
	93
	94	/* configure parity, bit length and so on */
7e6bf358	95	psc->mode = PSC_MODE_8_BITS \| PSC_MODE_PARNONE;
7e6bf358 WD	96	psc->mode = PSC_MODE_ONE_STOP;
	97
	98	/* set up UART divisor */
	99	div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
	100	psc->ctur = (div >> 8) & 0xff;
	101	psc->ctlr = div & 0xff;
	102
	103	/* disable all interrupts */
	104	psc->psc_imr = 0;
	105
	106	/* reset and enable Rx/Tx */
	107	psc->command = PSC_RST_RX;
	108	psc->command = PSC_RST_TX;
	109	psc->command = PSC_RX_ENABLE \| PSC_TX_ENABLE;
	110
	111	return (0);
	112	}
	113
1287e0c5 WG	114	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
1287e0c5 WG	115	defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8555)
bc8bb6d4 WD	116	int ps2ser_init(void)
	117	{
	118	NS16550_t com_port = (NS16550_t)COM_BASE;
	119
	120	com_port->ier = 0x00;
200779e3	121	com_port->lcr = UART_LCR_BKSE \| UART_LCR_8N1;
6d0f6bcf JCPV	122	com_port->dll = (CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
6d0f6bcf JCPV	123	com_port->dlm = ((CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
200779e3 DZ	124	com_port->lcr = UART_LCR_8N1;
	125	com_port->mcr = (UART_MCR_DTR \| UART_MCR_RTS);
	126	com_port->fcr = (UART_FCR_FIFO_EN \| UART_FCR_RXSR \| UART_FCR_TXSR);
bc8bb6d4 WD	127
	128	return (0);
	129	}
	130
bd3143f0	131	#else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */
1c43771b WD	132
	133	static inline unsigned int ps2ser_in(int offset)
	134	{
	135	return readb((unsigned long) state->iomem_base + offset);
	136	}
	137
	138	static inline void ps2ser_out(int offset, int value)
	139	{
	140	writeb(value, (unsigned long) state->iomem_base + offset);
	141	}
	142
	143	int ps2ser_init(void)
	144	{
ef978730 WD	145	int quot;
	146	unsigned cval;
	147
	148	state = rs_table + CONFIG_PS2SERIAL;
	149
	150	quot = state->baud_base / PS2SER_BAUD;
	151	cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */
1c43771b WD	152
	153	/* Set speed, enable interrupts, enable FIFO
	154	*/
	155	ps2ser_out(UART_LCR, cval \| UART_LCR_DLAB);
	156	ps2ser_out(UART_DLL, quot & 0xff);
	157	ps2ser_out(UART_DLM, quot >> 8);
	158	ps2ser_out(UART_LCR, cval);
	159	ps2ser_out(UART_IER, UART_IER_RDI);
	160	ps2ser_out(UART_MCR, UART_MCR_OUT2 \| UART_MCR_DTR \| UART_MCR_RTS);
	161	ps2ser_out(UART_FCR,
	162	UART_FCR_ENABLE_FIFO \| UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT);
	163
	164	/* If we read 0xff from the LSR, there is no UART here
	165	*/
	166	if (ps2ser_in(UART_LSR) == 0xff) {
	167	printf ("ps2ser.c: no UART found\n");
	168	return -1;
	169	}
	170
	171	irq_install_handler(state->irq, ps2ser_interrupt, NULL);
	172
	173	return 0;
	174	}
bd3143f0	175	#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
1c43771b WD	176
	177	void ps2ser_putc(int chr)
	178	{
7e6bf358 WD	179	#ifdef CONFIG_MPC5xxx
7e6bf358 WD	180	volatile struct mpc5xxx_psc psc = (struct mpc5xxx_psc )PSC_BASE;
1287e0c5 WG	181	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
1287e0c5 WG	182	defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8555)
bc8bb6d4	183	NS16550_t com_port = (NS16550_t)COM_BASE;
7e6bf358	184	#endif
1c43771b WD	185	#ifdef DEBUG
	186	printf(">>>> 0x%02x\n", chr);
	187	#endif
	188
7e6bf358 WD	189	#ifdef CONFIG_MPC5xxx
7e6bf358 WD	190	while (!(psc->psc_status & PSC_SR_TXRDY));
efe2a4d5	191
7e6bf358	192	psc->psc_buffer_8 = chr;
1287e0c5 WG	193	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
1287e0c5 WG	194	defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8555)
200779e3	195	while ((com_port->lsr & UART_LSR_THRE) == 0);
bc8bb6d4	196	com_port->thr = chr;
7e6bf358	197	#else
1c43771b WD	198	while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
	199
	200	ps2ser_out(UART_TX, chr);
7e6bf358	201	#endif
1c43771b WD	202	}
	203
	204	static int ps2ser_getc_hw(void)
	205	{
7e6bf358 WD	206	#ifdef CONFIG_MPC5xxx
7e6bf358 WD	207	volatile struct mpc5xxx_psc psc = (struct mpc5xxx_psc )PSC_BASE;
1287e0c5 WG	208	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
1287e0c5 WG	209	defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8555)
bc8bb6d4	210	NS16550_t com_port = (NS16550_t)COM_BASE;
7e6bf358	211	#endif
1c43771b WD	212	int res = -1;
1c43771b WD	213
7e6bf358 WD	214	#ifdef CONFIG_MPC5xxx
	215	if (psc->psc_status & PSC_SR_RXRDY) {
	216	res = (psc->psc_buffer_8);
	217	}
1287e0c5 WG	218	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
1287e0c5 WG	219	defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8555)
200779e3	220	if (com_port->lsr & UART_LSR_DR) {
bc8bb6d4 WD	221	res = com_port->rbr;
bc8bb6d4 WD	222	}
7e6bf358	223	#else
1c43771b WD	224	if (ps2ser_in(UART_LSR) & UART_LSR_DR) {
	225	res = (ps2ser_in(UART_RX));
	226	}
7e6bf358	227	#endif
1c43771b WD	228
	229	return res;
	230	}
	231
	232	int ps2ser_getc(void)
	233	{
	234	volatile int chr;
	235	int flags;
	236
	237	#ifdef DEBUG
	238	printf("<< ");
	239	#endif
	240
	241	flags = disable_interrupts();
	242
	243	do {
	244	if (atomic_read(&ps2buf_cnt) != 0) {
	245	chr = ps2buf[ps2buf_out_idx++];
	246	ps2buf_out_idx &= (PS2BUF_SIZE - 1);
	247	atomic_dec(&ps2buf_cnt);
	248	} else {
	249	chr = ps2ser_getc_hw();
	250	}
	251	}
	252	while (chr < 0);
	253
	254	if (flags) enable_interrupts();
	255
	256	#ifdef DEBUG
	257	printf("0x%02x\n", chr);
	258	#endif
	259
	260	return chr;
	261	}
	262
	263	int ps2ser_check(void)
	264	{
	265	int flags;
	266
	267	flags = disable_interrupts();
	268	ps2ser_interrupt(NULL);
	269	if (flags) enable_interrupts();
	270
	271	return atomic_read(&ps2buf_cnt);
	272	}
	273
	274	static void ps2ser_interrupt(void *dev_id)
	275	{
7e6bf358 WD	276	#ifdef CONFIG_MPC5xxx
7e6bf358 WD	277	volatile struct mpc5xxx_psc psc = (struct mpc5xxx_psc )PSC_BASE;
1287e0c5 WG	278	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
1287e0c5 WG	279	defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8555)
bc8bb6d4	280	NS16550_t com_port = (NS16550_t)COM_BASE;
7e6bf358	281	#endif
1c43771b	282	int chr;
7e6bf358	283	int status;
1c43771b WD	284
	285	do {
	286	chr = ps2ser_getc_hw();
7e6bf358 WD	287	#ifdef CONFIG_MPC5xxx
7e6bf358 WD	288	status = psc->psc_status;
1287e0c5 WG	289	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
1287e0c5 WG	290	defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8555)
bc8bb6d4	291	status = com_port->lsr;
7e6bf358 WD	292	#else
	293	status = ps2ser_in(UART_IIR);
	294	#endif
1c43771b WD	295	if (chr < 0) continue;
	296
	297	if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
	298	ps2buf[ps2buf_in_idx++] = chr;
	299	ps2buf_in_idx &= (PS2BUF_SIZE - 1);
	300	atomic_inc(&ps2buf_cnt);
	301	} else {
	302	printf ("ps2ser.c: buffer overflow\n");
	303	}
7e6bf358	304	#ifdef CONFIG_MPC5xxx
efe2a4d5	305	} while (status & PSC_SR_RXRDY);
1287e0c5 WG	306	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
1287e0c5 WG	307	defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8555)
200779e3	308	} while (status & UART_LSR_DR);
7e6bf358 WD	309	#else
	310	} while (status & UART_IIR_RDI);
	311	#endif
1c43771b WD	312
	313	if (atomic_read(&ps2buf_cnt)) {
	314	ps2mult_callback(atomic_read(&ps2buf_cnt));
	315	}
	316	}