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1c43771b WD |
1 | /*********************************************************************** |
2 | * | |
200779e3 | 3 | * (C) Copyright 2004-2009 |
1c43771b WD |
4 | * DENX Software Engineering |
5 | * Wolfgang Denk, wd@denx.de | |
1c43771b WD |
6 | * |
7 | * Simple 16550A serial driver | |
8 | * | |
9 | * Originally from linux source (drivers/char/ps2ser.c) | |
10 | * | |
11 | * Used by the PS/2 multiplexer driver (ps2mult.c) | |
12 | * | |
13 | ***********************************************************************/ | |
14 | ||
15 | #include <common.h> | |
16 | ||
1c43771b WD |
17 | #include <asm/io.h> |
18 | #include <asm/atomic.h> | |
19 | #include <ps2mult.h> | |
200779e3 DZ |
20 | /* This is needed for ns16550.h */ |
21 | #ifndef CONFIG_SYS_NS16550_REG_SIZE | |
22 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
bc8bb6d4 | 23 | #endif |
200779e3 | 24 | #include <ns16550.h> |
1c43771b | 25 | |
d87080b7 WD |
26 | DECLARE_GLOBAL_DATA_PTR; |
27 | ||
1c43771b WD |
28 | /* #define DEBUG */ |
29 | ||
30 | #define PS2SER_BAUD 57600 | |
31 | ||
7e6bf358 WD |
32 | #ifdef CONFIG_MPC5xxx |
33 | #if CONFIG_PS2SERIAL == 1 | |
34 | #define PSC_BASE MPC5XXX_PSC1 | |
35 | #elif CONFIG_PS2SERIAL == 2 | |
36 | #define PSC_BASE MPC5XXX_PSC2 | |
37 | #elif CONFIG_PS2SERIAL == 3 | |
38 | #define PSC_BASE MPC5XXX_PSC3 | |
7e6bf358 WD |
39 | #elif CONFIG_PS2SERIAL == 4 |
40 | #define PSC_BASE MPC5XXX_PSC4 | |
41 | #elif CONFIG_PS2SERIAL == 5 | |
42 | #define PSC_BASE MPC5XXX_PSC5 | |
43 | #elif CONFIG_PS2SERIAL == 6 | |
44 | #define PSC_BASE MPC5XXX_PSC6 | |
45 | #else | |
46 | #error CONFIG_PS2SERIAL must be in 1 ... 6 | |
47 | #endif | |
bc8bb6d4 | 48 | |
77efe35f | 49 | #else |
bc8bb6d4 WD |
50 | |
51 | #if CONFIG_PS2SERIAL == 1 | |
6d0f6bcf | 52 | #define COM_BASE (CONFIG_SYS_CCSRBAR+0x4500) |
bc8bb6d4 | 53 | #elif CONFIG_PS2SERIAL == 2 |
6d0f6bcf | 54 | #define COM_BASE (CONFIG_SYS_CCSRBAR+0x4600) |
bc8bb6d4 WD |
55 | #else |
56 | #error CONFIG_PS2SERIAL must be in 1 ... 2 | |
57 | #endif | |
58 | ||
77efe35f | 59 | #endif /* CONFIG_MPC5xxx / other */ |
7e6bf358 | 60 | |
1c43771b WD |
61 | static int ps2ser_getc_hw(void); |
62 | static void ps2ser_interrupt(void *dev_id); | |
63 | ||
64 | extern struct serial_state rs_table[]; /* in serial.c */ | |
1c43771b WD |
65 | |
66 | static u_char ps2buf[PS2BUF_SIZE]; | |
67 | static atomic_t ps2buf_cnt; | |
68 | static int ps2buf_in_idx; | |
69 | static int ps2buf_out_idx; | |
70 | ||
7e6bf358 WD |
71 | #ifdef CONFIG_MPC5xxx |
72 | int ps2ser_init(void) | |
73 | { | |
7e6bf358 WD |
74 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; |
75 | unsigned long baseclk; | |
76 | int div; | |
77 | ||
78 | /* reset PSC */ | |
79 | psc->command = PSC_SEL_MODE_REG_1; | |
80 | ||
81 | /* select clock sources */ | |
7e6bf358 | 82 | psc->psc_clock_select = 0; |
b2877496 | 83 | baseclk = (gd->arch.ipb_clk + 16) / 32; |
7e6bf358 WD |
84 | |
85 | /* switch to UART mode */ | |
86 | psc->sicr = 0; | |
87 | ||
88 | /* configure parity, bit length and so on */ | |
7e6bf358 | 89 | psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; |
7e6bf358 WD |
90 | psc->mode = PSC_MODE_ONE_STOP; |
91 | ||
92 | /* set up UART divisor */ | |
93 | div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD; | |
94 | psc->ctur = (div >> 8) & 0xff; | |
95 | psc->ctlr = div & 0xff; | |
96 | ||
97 | /* disable all interrupts */ | |
98 | psc->psc_imr = 0; | |
99 | ||
100 | /* reset and enable Rx/Tx */ | |
101 | psc->command = PSC_RST_RX; | |
102 | psc->command = PSC_RST_TX; | |
103 | psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; | |
104 | ||
105 | return (0); | |
106 | } | |
107 | ||
77efe35f WD |
108 | #else |
109 | ||
bc8bb6d4 WD |
110 | int ps2ser_init(void) |
111 | { | |
112 | NS16550_t com_port = (NS16550_t)COM_BASE; | |
113 | ||
114 | com_port->ier = 0x00; | |
200779e3 | 115 | com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; |
6d0f6bcf JCPV |
116 | com_port->dll = (CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff; |
117 | com_port->dlm = ((CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff; | |
200779e3 DZ |
118 | com_port->lcr = UART_LCR_8N1; |
119 | com_port->mcr = (UART_MCR_DTR | UART_MCR_RTS); | |
120 | com_port->fcr = (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR); | |
bc8bb6d4 WD |
121 | |
122 | return (0); | |
123 | } | |
124 | ||
77efe35f | 125 | #endif /* CONFIG_MPC5xxx / other */ |
1c43771b WD |
126 | |
127 | void ps2ser_putc(int chr) | |
128 | { | |
7e6bf358 WD |
129 | #ifdef CONFIG_MPC5xxx |
130 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; | |
77efe35f | 131 | #else |
bc8bb6d4 | 132 | NS16550_t com_port = (NS16550_t)COM_BASE; |
7e6bf358 | 133 | #endif |
77efe35f | 134 | debug(">>>> 0x%02x\n", chr); |
1c43771b | 135 | |
7e6bf358 WD |
136 | #ifdef CONFIG_MPC5xxx |
137 | while (!(psc->psc_status & PSC_SR_TXRDY)); | |
efe2a4d5 | 138 | |
7e6bf358 | 139 | psc->psc_buffer_8 = chr; |
77efe35f | 140 | #else |
200779e3 | 141 | while ((com_port->lsr & UART_LSR_THRE) == 0); |
bc8bb6d4 | 142 | com_port->thr = chr; |
7e6bf358 | 143 | #endif |
1c43771b WD |
144 | } |
145 | ||
146 | static int ps2ser_getc_hw(void) | |
147 | { | |
7e6bf358 WD |
148 | #ifdef CONFIG_MPC5xxx |
149 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; | |
77efe35f | 150 | #else |
bc8bb6d4 | 151 | NS16550_t com_port = (NS16550_t)COM_BASE; |
7e6bf358 | 152 | #endif |
1c43771b WD |
153 | int res = -1; |
154 | ||
7e6bf358 WD |
155 | #ifdef CONFIG_MPC5xxx |
156 | if (psc->psc_status & PSC_SR_RXRDY) { | |
157 | res = (psc->psc_buffer_8); | |
158 | } | |
77efe35f | 159 | #else |
200779e3 | 160 | if (com_port->lsr & UART_LSR_DR) { |
bc8bb6d4 WD |
161 | res = com_port->rbr; |
162 | } | |
7e6bf358 | 163 | #endif |
1c43771b WD |
164 | |
165 | return res; | |
166 | } | |
167 | ||
168 | int ps2ser_getc(void) | |
169 | { | |
170 | volatile int chr; | |
171 | int flags; | |
172 | ||
77efe35f | 173 | debug("<< "); |
1c43771b WD |
174 | |
175 | flags = disable_interrupts(); | |
176 | ||
177 | do { | |
178 | if (atomic_read(&ps2buf_cnt) != 0) { | |
179 | chr = ps2buf[ps2buf_out_idx++]; | |
180 | ps2buf_out_idx &= (PS2BUF_SIZE - 1); | |
181 | atomic_dec(&ps2buf_cnt); | |
182 | } else { | |
183 | chr = ps2ser_getc_hw(); | |
184 | } | |
185 | } | |
186 | while (chr < 0); | |
187 | ||
77efe35f WD |
188 | if (flags) |
189 | enable_interrupts(); | |
1c43771b | 190 | |
77efe35f | 191 | debug("0x%02x\n", chr); |
1c43771b WD |
192 | |
193 | return chr; | |
194 | } | |
195 | ||
196 | int ps2ser_check(void) | |
197 | { | |
198 | int flags; | |
199 | ||
200 | flags = disable_interrupts(); | |
201 | ps2ser_interrupt(NULL); | |
202 | if (flags) enable_interrupts(); | |
203 | ||
204 | return atomic_read(&ps2buf_cnt); | |
205 | } | |
206 | ||
207 | static void ps2ser_interrupt(void *dev_id) | |
208 | { | |
7e6bf358 WD |
209 | #ifdef CONFIG_MPC5xxx |
210 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; | |
77efe35f | 211 | #else |
bc8bb6d4 | 212 | NS16550_t com_port = (NS16550_t)COM_BASE; |
7e6bf358 | 213 | #endif |
1c43771b | 214 | int chr; |
7e6bf358 | 215 | int status; |
1c43771b WD |
216 | |
217 | do { | |
218 | chr = ps2ser_getc_hw(); | |
7e6bf358 WD |
219 | #ifdef CONFIG_MPC5xxx |
220 | status = psc->psc_status; | |
221 | #else | |
77efe35f | 222 | status = com_port->lsr; |
7e6bf358 | 223 | #endif |
1c43771b WD |
224 | if (chr < 0) continue; |
225 | ||
226 | if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) { | |
227 | ps2buf[ps2buf_in_idx++] = chr; | |
228 | ps2buf_in_idx &= (PS2BUF_SIZE - 1); | |
229 | atomic_inc(&ps2buf_cnt); | |
230 | } else { | |
231 | printf ("ps2ser.c: buffer overflow\n"); | |
232 | } | |
7e6bf358 | 233 | #ifdef CONFIG_MPC5xxx |
efe2a4d5 | 234 | } while (status & PSC_SR_RXRDY); |
7e6bf358 | 235 | #else |
77efe35f | 236 | } while (status & UART_LSR_DR); |
7e6bf358 | 237 | #endif |
1c43771b WD |
238 | if (atomic_read(&ps2buf_cnt)) { |
239 | ps2mult_callback(atomic_read(&ps2buf_cnt)); | |
240 | } | |
241 | } |