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b5d2f741 DD |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
aae57773 | 3 | * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. |
b5d2f741 DD |
4 | */ |
5 | ||
b5d2f741 DD |
6 | #include <linux/device.h> |
7 | #include <linux/interconnect.h> | |
8 | #include <linux/interconnect-provider.h> | |
b5d2f741 DD |
9 | #include <linux/module.h> |
10 | #include <linux/of_device.h> | |
b5d2f741 | 11 | |
aae57773 | 12 | #include <dt-bindings/interconnect/qcom,sdm845.h> |
b5d2f741 | 13 | |
aae57773 DD |
14 | #include "bcm-voter.h" |
15 | #include "icc-rpmh.h" | |
78465b0d | 16 | #include "sdm845.h" |
b5d2f741 | 17 | |
aae57773 DD |
18 | DEFINE_QNODE(qhm_a1noc_cfg, SDM845_MASTER_A1NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A1NOC); |
19 | DEFINE_QNODE(qhm_qup1, SDM845_MASTER_BLSP_1, 1, 4, SDM845_SLAVE_A1NOC_SNOC); | |
20 | DEFINE_QNODE(qhm_tsif, SDM845_MASTER_TSIF, 1, 4, SDM845_SLAVE_A1NOC_SNOC); | |
21 | DEFINE_QNODE(xm_sdc2, SDM845_MASTER_SDCC_2, 1, 8, SDM845_SLAVE_A1NOC_SNOC); | |
22 | DEFINE_QNODE(xm_sdc4, SDM845_MASTER_SDCC_4, 1, 8, SDM845_SLAVE_A1NOC_SNOC); | |
23 | DEFINE_QNODE(xm_ufs_card, SDM845_MASTER_UFS_CARD, 1, 8, SDM845_SLAVE_A1NOC_SNOC); | |
24 | DEFINE_QNODE(xm_ufs_mem, SDM845_MASTER_UFS_MEM, 1, 8, SDM845_SLAVE_A1NOC_SNOC); | |
25 | DEFINE_QNODE(xm_pcie_0, SDM845_MASTER_PCIE_0, 1, 8, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC); | |
26 | DEFINE_QNODE(qhm_a2noc_cfg, SDM845_MASTER_A2NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A2NOC); | |
27 | DEFINE_QNODE(qhm_qdss_bam, SDM845_MASTER_QDSS_BAM, 1, 4, SDM845_SLAVE_A2NOC_SNOC); | |
28 | DEFINE_QNODE(qhm_qup2, SDM845_MASTER_BLSP_2, 1, 4, SDM845_SLAVE_A2NOC_SNOC); | |
29 | DEFINE_QNODE(qnm_cnoc, SDM845_MASTER_CNOC_A2NOC, 1, 8, SDM845_SLAVE_A2NOC_SNOC); | |
30 | DEFINE_QNODE(qxm_crypto, SDM845_MASTER_CRYPTO, 1, 8, SDM845_SLAVE_A2NOC_SNOC); | |
31 | DEFINE_QNODE(qxm_ipa, SDM845_MASTER_IPA, 1, 8, SDM845_SLAVE_A2NOC_SNOC); | |
32 | DEFINE_QNODE(xm_pcie3_1, SDM845_MASTER_PCIE_1, 1, 8, SDM845_SLAVE_ANOC_PCIE_SNOC); | |
33 | DEFINE_QNODE(xm_qdss_etr, SDM845_MASTER_QDSS_ETR, 1, 8, SDM845_SLAVE_A2NOC_SNOC); | |
34 | DEFINE_QNODE(xm_usb3_0, SDM845_MASTER_USB3_0, 1, 8, SDM845_SLAVE_A2NOC_SNOC); | |
35 | DEFINE_QNODE(xm_usb3_1, SDM845_MASTER_USB3_1, 1, 8, SDM845_SLAVE_A2NOC_SNOC); | |
36 | DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM845_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP); | |
37 | DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM845_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP); | |
38 | DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM845_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP); | |
39 | DEFINE_QNODE(qhm_spdm, SDM845_MASTER_SPDM, 1, 4, SDM845_SLAVE_CNOC_A2NOC); | |
40 | DEFINE_QNODE(qhm_tic, SDM845_MASTER_TIC, 1, 4, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC); | |
41 | DEFINE_QNODE(qnm_snoc, SDM845_MASTER_SNOC_CNOC, 1, 8, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_SERVICE_CNOC); | |
42 | DEFINE_QNODE(xm_qdss_dap, SDM845_MASTER_QDSS_DAP, 1, 8, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC); | |
43 | DEFINE_QNODE(qhm_cnoc, SDM845_MASTER_CNOC_DC_NOC, 1, 4, SDM845_SLAVE_LLCC_CFG, SDM845_SLAVE_MEM_NOC_CFG); | |
44 | DEFINE_QNODE(acm_l3, SDM845_MASTER_APPSS_PROC, 1, 16, SDM845_SLAVE_GNOC_SNOC, SDM845_SLAVE_GNOC_MEM_NOC, SDM845_SLAVE_SERVICE_GNOC); | |
45 | DEFINE_QNODE(pm_gnoc_cfg, SDM845_MASTER_GNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_GNOC); | |
46 | DEFINE_QNODE(llcc_mc, SDM845_MASTER_LLCC, 4, 4, SDM845_SLAVE_EBI1); | |
47 | DEFINE_QNODE(acm_tcu, SDM845_MASTER_TCU_0, 1, 8, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC); | |
48 | DEFINE_QNODE(qhm_memnoc_cfg, SDM845_MASTER_MEM_NOC_CFG, 1, 4, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, SDM845_SLAVE_SERVICE_MEM_NOC); | |
49 | DEFINE_QNODE(qnm_apps, SDM845_MASTER_GNOC_MEM_NOC, 2, 32, SDM845_SLAVE_LLCC); | |
50 | DEFINE_QNODE(qnm_mnoc_hf, SDM845_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC); | |
51 | DEFINE_QNODE(qnm_mnoc_sf, SDM845_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC); | |
52 | DEFINE_QNODE(qnm_snoc_gc, SDM845_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM845_SLAVE_LLCC); | |
53 | DEFINE_QNODE(qnm_snoc_sf, SDM845_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC); | |
54 | DEFINE_QNODE(qxm_gpu, SDM845_MASTER_GFX3D, 2, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC); | |
55 | DEFINE_QNODE(qhm_mnoc_cfg, SDM845_MASTER_CNOC_MNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_MNOC); | |
56 | DEFINE_QNODE(qxm_camnoc_hf0, SDM845_MASTER_CAMNOC_HF0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC); | |
57 | DEFINE_QNODE(qxm_camnoc_hf1, SDM845_MASTER_CAMNOC_HF1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC); | |
58 | DEFINE_QNODE(qxm_camnoc_sf, SDM845_MASTER_CAMNOC_SF, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC); | |
59 | DEFINE_QNODE(qxm_mdp0, SDM845_MASTER_MDP0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC); | |
60 | DEFINE_QNODE(qxm_mdp1, SDM845_MASTER_MDP1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC); | |
61 | DEFINE_QNODE(qxm_rot, SDM845_MASTER_ROTATOR, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC); | |
62 | DEFINE_QNODE(qxm_venus0, SDM845_MASTER_VIDEO_P0, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC); | |
63 | DEFINE_QNODE(qxm_venus1, SDM845_MASTER_VIDEO_P1, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC); | |
64 | DEFINE_QNODE(qxm_venus_arm9, SDM845_MASTER_VIDEO_PROC, 1, 8, SDM845_SLAVE_MNOC_SF_MEM_NOC); | |
65 | DEFINE_QNODE(qhm_snoc_cfg, SDM845_MASTER_SNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_SNOC); | |
66 | DEFINE_QNODE(qnm_aggre1_noc, SDM845_MASTER_A1NOC_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM); | |
67 | DEFINE_QNODE(qnm_aggre2_noc, SDM845_MASTER_A2NOC_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE_TCU); | |
68 | DEFINE_QNODE(qnm_gladiator_sodv, SDM845_MASTER_GNOC_SNOC, 1, 8, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE_TCU); | |
69 | DEFINE_QNODE(qnm_memnoc, SDM845_MASTER_MEM_NOC_SNOC, 1, 8, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM); | |
70 | DEFINE_QNODE(qnm_pcie_anoc, SDM845_MASTER_ANOC_PCIE_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_QDSS_STM); | |
71 | DEFINE_QNODE(qxm_pimem, SDM845_MASTER_PIMEM, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC, SDM845_SLAVE_IMEM); | |
72 | DEFINE_QNODE(xm_gic, SDM845_MASTER_GIC, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC, SDM845_SLAVE_IMEM); | |
73 | DEFINE_QNODE(qns_a1noc_snoc, SDM845_SLAVE_A1NOC_SNOC, 1, 16, SDM845_MASTER_A1NOC_SNOC); | |
74 | DEFINE_QNODE(srvc_aggre1_noc, SDM845_SLAVE_SERVICE_A1NOC, 1, 4, 0); | |
75 | DEFINE_QNODE(qns_pcie_a1noc_snoc, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, 1, 16, SDM845_MASTER_ANOC_PCIE_SNOC); | |
76 | DEFINE_QNODE(qns_a2noc_snoc, SDM845_SLAVE_A2NOC_SNOC, 1, 16, SDM845_MASTER_A2NOC_SNOC); | |
77 | DEFINE_QNODE(qns_pcie_snoc, SDM845_SLAVE_ANOC_PCIE_SNOC, 1, 16, SDM845_MASTER_ANOC_PCIE_SNOC); | |
78 | DEFINE_QNODE(srvc_aggre2_noc, SDM845_SLAVE_SERVICE_A2NOC, 1, 4); | |
79 | DEFINE_QNODE(qns_camnoc_uncomp, SDM845_SLAVE_CAMNOC_UNCOMP, 1, 32); | |
80 | DEFINE_QNODE(qhs_a1_noc_cfg, SDM845_SLAVE_A1NOC_CFG, 1, 4, SDM845_MASTER_A1NOC_CFG); | |
81 | DEFINE_QNODE(qhs_a2_noc_cfg, SDM845_SLAVE_A2NOC_CFG, 1, 4, SDM845_MASTER_A2NOC_CFG); | |
82 | DEFINE_QNODE(qhs_aop, SDM845_SLAVE_AOP, 1, 4); | |
83 | DEFINE_QNODE(qhs_aoss, SDM845_SLAVE_AOSS, 1, 4); | |
84 | DEFINE_QNODE(qhs_camera_cfg, SDM845_SLAVE_CAMERA_CFG, 1, 4); | |
85 | DEFINE_QNODE(qhs_clk_ctl, SDM845_SLAVE_CLK_CTL, 1, 4); | |
86 | DEFINE_QNODE(qhs_compute_dsp_cfg, SDM845_SLAVE_CDSP_CFG, 1, 4); | |
87 | DEFINE_QNODE(qhs_cpr_cx, SDM845_SLAVE_RBCPR_CX_CFG, 1, 4); | |
88 | DEFINE_QNODE(qhs_crypto0_cfg, SDM845_SLAVE_CRYPTO_0_CFG, 1, 4); | |
89 | DEFINE_QNODE(qhs_dcc_cfg, SDM845_SLAVE_DCC_CFG, 1, 4, SDM845_MASTER_CNOC_DC_NOC); | |
90 | DEFINE_QNODE(qhs_ddrss_cfg, SDM845_SLAVE_CNOC_DDRSS, 1, 4); | |
91 | DEFINE_QNODE(qhs_display_cfg, SDM845_SLAVE_DISPLAY_CFG, 1, 4); | |
92 | DEFINE_QNODE(qhs_glm, SDM845_SLAVE_GLM, 1, 4); | |
93 | DEFINE_QNODE(qhs_gpuss_cfg, SDM845_SLAVE_GFX3D_CFG, 1, 8); | |
94 | DEFINE_QNODE(qhs_imem_cfg, SDM845_SLAVE_IMEM_CFG, 1, 4); | |
95 | DEFINE_QNODE(qhs_ipa, SDM845_SLAVE_IPA_CFG, 1, 4); | |
96 | DEFINE_QNODE(qhs_mnoc_cfg, SDM845_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM845_MASTER_CNOC_MNOC_CFG); | |
97 | DEFINE_QNODE(qhs_pcie0_cfg, SDM845_SLAVE_PCIE_0_CFG, 1, 4); | |
98 | DEFINE_QNODE(qhs_pcie_gen3_cfg, SDM845_SLAVE_PCIE_1_CFG, 1, 4); | |
99 | DEFINE_QNODE(qhs_pdm, SDM845_SLAVE_PDM, 1, 4); | |
100 | DEFINE_QNODE(qhs_phy_refgen_south, SDM845_SLAVE_SOUTH_PHY_CFG, 1, 4); | |
101 | DEFINE_QNODE(qhs_pimem_cfg, SDM845_SLAVE_PIMEM_CFG, 1, 4); | |
102 | DEFINE_QNODE(qhs_prng, SDM845_SLAVE_PRNG, 1, 4); | |
103 | DEFINE_QNODE(qhs_qdss_cfg, SDM845_SLAVE_QDSS_CFG, 1, 4); | |
104 | DEFINE_QNODE(qhs_qupv3_north, SDM845_SLAVE_BLSP_2, 1, 4); | |
105 | DEFINE_QNODE(qhs_qupv3_south, SDM845_SLAVE_BLSP_1, 1, 4); | |
106 | DEFINE_QNODE(qhs_sdc2, SDM845_SLAVE_SDCC_2, 1, 4); | |
107 | DEFINE_QNODE(qhs_sdc4, SDM845_SLAVE_SDCC_4, 1, 4); | |
108 | DEFINE_QNODE(qhs_snoc_cfg, SDM845_SLAVE_SNOC_CFG, 1, 4, SDM845_MASTER_SNOC_CFG); | |
109 | DEFINE_QNODE(qhs_spdm, SDM845_SLAVE_SPDM_WRAPPER, 1, 4); | |
110 | DEFINE_QNODE(qhs_spss_cfg, SDM845_SLAVE_SPSS_CFG, 1, 4); | |
111 | DEFINE_QNODE(qhs_tcsr, SDM845_SLAVE_TCSR, 1, 4); | |
112 | DEFINE_QNODE(qhs_tlmm_north, SDM845_SLAVE_TLMM_NORTH, 1, 4); | |
113 | DEFINE_QNODE(qhs_tlmm_south, SDM845_SLAVE_TLMM_SOUTH, 1, 4); | |
114 | DEFINE_QNODE(qhs_tsif, SDM845_SLAVE_TSIF, 1, 4); | |
115 | DEFINE_QNODE(qhs_ufs_card_cfg, SDM845_SLAVE_UFS_CARD_CFG, 1, 4); | |
116 | DEFINE_QNODE(qhs_ufs_mem_cfg, SDM845_SLAVE_UFS_MEM_CFG, 1, 4); | |
117 | DEFINE_QNODE(qhs_usb3_0, SDM845_SLAVE_USB3_0, 1, 4); | |
118 | DEFINE_QNODE(qhs_usb3_1, SDM845_SLAVE_USB3_1, 1, 4); | |
119 | DEFINE_QNODE(qhs_venus_cfg, SDM845_SLAVE_VENUS_CFG, 1, 4); | |
120 | DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM845_SLAVE_VSENSE_CTRL_CFG, 1, 4); | |
121 | DEFINE_QNODE(qns_cnoc_a2noc, SDM845_SLAVE_CNOC_A2NOC, 1, 8, SDM845_MASTER_CNOC_A2NOC); | |
122 | DEFINE_QNODE(srvc_cnoc, SDM845_SLAVE_SERVICE_CNOC, 1, 4); | |
123 | DEFINE_QNODE(qhs_llcc, SDM845_SLAVE_LLCC_CFG, 1, 4); | |
124 | DEFINE_QNODE(qhs_memnoc, SDM845_SLAVE_MEM_NOC_CFG, 1, 4, SDM845_MASTER_MEM_NOC_CFG); | |
125 | DEFINE_QNODE(qns_gladiator_sodv, SDM845_SLAVE_GNOC_SNOC, 1, 8, SDM845_MASTER_GNOC_SNOC); | |
126 | DEFINE_QNODE(qns_gnoc_memnoc, SDM845_SLAVE_GNOC_MEM_NOC, 2, 32, SDM845_MASTER_GNOC_MEM_NOC); | |
127 | DEFINE_QNODE(srvc_gnoc, SDM845_SLAVE_SERVICE_GNOC, 1, 4); | |
128 | DEFINE_QNODE(ebi, SDM845_SLAVE_EBI1, 4, 4); | |
129 | DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); | |
130 | DEFINE_QNODE(qns_apps_io, SDM845_SLAVE_MEM_NOC_GNOC, 1, 32); | |
131 | DEFINE_QNODE(qns_llcc, SDM845_SLAVE_LLCC, 4, 16, SDM845_MASTER_LLCC); | |
132 | DEFINE_QNODE(qns_memnoc_snoc, SDM845_SLAVE_MEM_NOC_SNOC, 1, 8, SDM845_MASTER_MEM_NOC_SNOC); | |
133 | DEFINE_QNODE(srvc_memnoc, SDM845_SLAVE_SERVICE_MEM_NOC, 1, 4); | |
134 | DEFINE_QNODE(qns2_mem_noc, SDM845_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM845_MASTER_MNOC_SF_MEM_NOC); | |
135 | DEFINE_QNODE(qns_mem_noc_hf, SDM845_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM845_MASTER_MNOC_HF_MEM_NOC); | |
136 | DEFINE_QNODE(srvc_mnoc, SDM845_SLAVE_SERVICE_MNOC, 1, 4); | |
137 | DEFINE_QNODE(qhs_apss, SDM845_SLAVE_APPSS, 1, 8); | |
138 | DEFINE_QNODE(qns_cnoc, SDM845_SLAVE_SNOC_CNOC, 1, 8, SDM845_MASTER_SNOC_CNOC); | |
139 | DEFINE_QNODE(qns_memnoc_gc, SDM845_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM845_MASTER_SNOC_GC_MEM_NOC); | |
140 | DEFINE_QNODE(qns_memnoc_sf, SDM845_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM845_MASTER_SNOC_SF_MEM_NOC); | |
141 | DEFINE_QNODE(qxs_imem, SDM845_SLAVE_IMEM, 1, 8); | |
142 | DEFINE_QNODE(qxs_pcie, SDM845_SLAVE_PCIE_0, 1, 8); | |
143 | DEFINE_QNODE(qxs_pcie_gen3, SDM845_SLAVE_PCIE_1, 1, 8); | |
144 | DEFINE_QNODE(qxs_pimem, SDM845_SLAVE_PIMEM, 1, 8); | |
145 | DEFINE_QNODE(srvc_snoc, SDM845_SLAVE_SERVICE_SNOC, 1, 4); | |
146 | DEFINE_QNODE(xs_qdss_stm, SDM845_SLAVE_QDSS_STM, 1, 4); | |
147 | DEFINE_QNODE(xs_sys_tcu_cfg, SDM845_SLAVE_TCU, 1, 8); | |
148 | ||
149 | DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); | |
150 | DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); | |
151 | DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); | |
152 | DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf); | |
153 | DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io); | |
154 | DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1); | |
155 | DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc); | |
156 | DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc); | |
157 | DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu); | |
158 | DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9); | |
159 | DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps); | |
160 | DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf); | |
161 | DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); | |
162 | DEFINE_QBCM(bcm_cn0, "CN0", false, &qhm_spdm, &qhm_tic, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pcie0_cfg, &qhs_pcie_gen3_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); | |
163 | DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2); | |
164 | DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); | |
165 | DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc); | |
166 | DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc); | |
167 | DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem); | |
168 | DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm); | |
169 | DEFINE_QBCM(bcm_sn6, "SN6", false, &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg); | |
170 | DEFINE_QBCM(bcm_sn7, "SN7", false, &qxs_pcie); | |
171 | DEFINE_QBCM(bcm_sn8, "SN8", false, &qxs_pcie_gen3); | |
172 | DEFINE_QBCM(bcm_sn9, "SN9", false, &srvc_aggre1_noc, &qnm_aggre1_noc); | |
173 | DEFINE_QBCM(bcm_sn11, "SN11", false, &srvc_aggre2_noc, &qnm_aggre2_noc); | |
174 | DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gladiator_sodv, &xm_gic); | |
175 | DEFINE_QBCM(bcm_sn14, "SN14", false, &qnm_pcie_anoc); | |
176 | DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc); | |
177 | ||
178 | static struct qcom_icc_bcm *aggre1_noc_bcms[] = { | |
179 | &bcm_sn9, | |
b5d2f741 DD |
180 | }; |
181 | ||
aae57773 DD |
182 | static struct qcom_icc_node *aggre1_noc_nodes[] = { |
183 | [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, | |
184 | [MASTER_TSIF] = &qhm_tsif, | |
185 | [MASTER_SDCC_2] = &xm_sdc2, | |
186 | [MASTER_SDCC_4] = &xm_sdc4, | |
187 | [MASTER_UFS_CARD] = &xm_ufs_card, | |
188 | [MASTER_UFS_MEM] = &xm_ufs_mem, | |
189 | [MASTER_PCIE_0] = &xm_pcie_0, | |
190 | [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, | |
191 | [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, | |
192 | [SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc, | |
b5d2f741 DD |
193 | }; |
194 | ||
5409e0cc | 195 | static const struct qcom_icc_desc sdm845_aggre1_noc = { |
aae57773 DD |
196 | .nodes = aggre1_noc_nodes, |
197 | .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), | |
198 | .bcms = aggre1_noc_bcms, | |
199 | .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), | |
b5d2f741 DD |
200 | }; |
201 | ||
aae57773 DD |
202 | static struct qcom_icc_bcm *aggre2_noc_bcms[] = { |
203 | &bcm_ce0, | |
204 | &bcm_sn11, | |
205 | &bcm_qup0, | |
206 | }; | |
b5d2f741 | 207 | |
aae57773 | 208 | static struct qcom_icc_node *aggre2_noc_nodes[] = { |
b5d2f741 | 209 | [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, |
b5d2f741 | 210 | [MASTER_QDSS_BAM] = &qhm_qdss_bam, |
b5d2f741 | 211 | [MASTER_CNOC_A2NOC] = &qnm_cnoc, |
b5d2f741 | 212 | [MASTER_CRYPTO] = &qxm_crypto, |
b5d2f741 | 213 | [MASTER_IPA] = &qxm_ipa, |
b5d2f741 | 214 | [MASTER_PCIE_1] = &xm_pcie3_1, |
b5d2f741 | 215 | [MASTER_QDSS_ETR] = &xm_qdss_etr, |
b5d2f741 DD |
216 | [MASTER_USB3_0] = &xm_usb3_0, |
217 | [MASTER_USB3_1] = &xm_usb3_1, | |
aae57773 DD |
218 | [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, |
219 | [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc, | |
220 | [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, | |
221 | }; | |
222 | ||
5409e0cc | 223 | static const struct qcom_icc_desc sdm845_aggre2_noc = { |
aae57773 DD |
224 | .nodes = aggre2_noc_nodes, |
225 | .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), | |
226 | .bcms = aggre2_noc_bcms, | |
227 | .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), | |
228 | }; | |
229 | ||
230 | static struct qcom_icc_bcm *config_noc_bcms[] = { | |
231 | &bcm_cn0, | |
232 | }; | |
233 | ||
234 | static struct qcom_icc_node *config_noc_nodes[] = { | |
235 | [MASTER_SPDM] = &qhm_spdm, | |
236 | [MASTER_TIC] = &qhm_tic, | |
237 | [MASTER_SNOC_CNOC] = &qnm_snoc, | |
238 | [MASTER_QDSS_DAP] = &xm_qdss_dap, | |
b5d2f741 DD |
239 | [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, |
240 | [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, | |
241 | [SLAVE_AOP] = &qhs_aop, | |
242 | [SLAVE_AOSS] = &qhs_aoss, | |
b5d2f741 DD |
243 | [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, |
244 | [SLAVE_CLK_CTL] = &qhs_clk_ctl, | |
245 | [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg, | |
246 | [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, | |
247 | [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, | |
248 | [SLAVE_DCC_CFG] = &qhs_dcc_cfg, | |
249 | [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, | |
250 | [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, | |
251 | [SLAVE_GLM] = &qhs_glm, | |
252 | [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, | |
253 | [SLAVE_IMEM_CFG] = &qhs_imem_cfg, | |
254 | [SLAVE_IPA_CFG] = &qhs_ipa, | |
b5d2f741 DD |
255 | [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, |
256 | [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, | |
257 | [SLAVE_PCIE_1_CFG] = &qhs_pcie_gen3_cfg, | |
258 | [SLAVE_PDM] = &qhs_pdm, | |
259 | [SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south, | |
260 | [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, | |
261 | [SLAVE_PRNG] = &qhs_prng, | |
262 | [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, | |
263 | [SLAVE_BLSP_2] = &qhs_qupv3_north, | |
264 | [SLAVE_BLSP_1] = &qhs_qupv3_south, | |
265 | [SLAVE_SDCC_2] = &qhs_sdc2, | |
266 | [SLAVE_SDCC_4] = &qhs_sdc4, | |
267 | [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, | |
268 | [SLAVE_SPDM_WRAPPER] = &qhs_spdm, | |
269 | [SLAVE_SPSS_CFG] = &qhs_spss_cfg, | |
270 | [SLAVE_TCSR] = &qhs_tcsr, | |
271 | [SLAVE_TLMM_NORTH] = &qhs_tlmm_north, | |
272 | [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, | |
273 | [SLAVE_TSIF] = &qhs_tsif, | |
274 | [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, | |
275 | [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, | |
276 | [SLAVE_USB3_0] = &qhs_usb3_0, | |
277 | [SLAVE_USB3_1] = &qhs_usb3_1, | |
278 | [SLAVE_VENUS_CFG] = &qhs_venus_cfg, | |
279 | [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, | |
b5d2f741 | 280 | [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, |
aae57773 DD |
281 | [SLAVE_SERVICE_CNOC] = &srvc_cnoc, |
282 | }; | |
283 | ||
5409e0cc | 284 | static const struct qcom_icc_desc sdm845_config_noc = { |
aae57773 DD |
285 | .nodes = config_noc_nodes, |
286 | .num_nodes = ARRAY_SIZE(config_noc_nodes), | |
287 | .bcms = config_noc_bcms, | |
288 | .num_bcms = ARRAY_SIZE(config_noc_bcms), | |
289 | }; | |
290 | ||
291 | static struct qcom_icc_bcm *dc_noc_bcms[] = { | |
292 | }; | |
293 | ||
294 | static struct qcom_icc_node *dc_noc_nodes[] = { | |
295 | [MASTER_CNOC_DC_NOC] = &qhm_cnoc, | |
296 | [SLAVE_LLCC_CFG] = &qhs_llcc, | |
297 | [SLAVE_MEM_NOC_CFG] = &qhs_memnoc, | |
298 | }; | |
299 | ||
5409e0cc | 300 | static const struct qcom_icc_desc sdm845_dc_noc = { |
aae57773 DD |
301 | .nodes = dc_noc_nodes, |
302 | .num_nodes = ARRAY_SIZE(dc_noc_nodes), | |
303 | .bcms = dc_noc_bcms, | |
304 | .num_bcms = ARRAY_SIZE(dc_noc_bcms), | |
305 | }; | |
306 | ||
307 | static struct qcom_icc_bcm *gladiator_noc_bcms[] = { | |
308 | }; | |
309 | ||
310 | static struct qcom_icc_node *gladiator_noc_nodes[] = { | |
311 | [MASTER_APPSS_PROC] = &acm_l3, | |
312 | [MASTER_GNOC_CFG] = &pm_gnoc_cfg, | |
b5d2f741 DD |
313 | [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv, |
314 | [SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc, | |
b5d2f741 | 315 | [SLAVE_SERVICE_GNOC] = &srvc_gnoc, |
b5d2f741 DD |
316 | }; |
317 | ||
5409e0cc | 318 | static const struct qcom_icc_desc sdm845_gladiator_noc = { |
aae57773 DD |
319 | .nodes = gladiator_noc_nodes, |
320 | .num_nodes = ARRAY_SIZE(gladiator_noc_nodes), | |
321 | .bcms = gladiator_noc_bcms, | |
322 | .num_bcms = ARRAY_SIZE(gladiator_noc_bcms), | |
323 | }; | |
324 | ||
325 | static struct qcom_icc_bcm *mem_noc_bcms[] = { | |
b5d2f741 | 326 | &bcm_mc0, |
aae57773 | 327 | &bcm_acv, |
b5d2f741 | 328 | &bcm_sh0, |
b5d2f741 | 329 | &bcm_sh1, |
b5d2f741 | 330 | &bcm_sh2, |
b5d2f741 | 331 | &bcm_sh3, |
b5d2f741 | 332 | &bcm_sh5, |
aae57773 DD |
333 | }; |
334 | ||
335 | static struct qcom_icc_node *mem_noc_nodes[] = { | |
336 | [MASTER_TCU_0] = &acm_tcu, | |
337 | [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg, | |
338 | [MASTER_GNOC_MEM_NOC] = &qnm_apps, | |
339 | [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, | |
340 | [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, | |
341 | [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, | |
342 | [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, | |
343 | [MASTER_GFX3D] = &qxm_gpu, | |
344 | [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, | |
345 | [SLAVE_MEM_NOC_GNOC] = &qns_apps_io, | |
346 | [SLAVE_LLCC] = &qns_llcc, | |
347 | [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, | |
348 | [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc, | |
349 | [MASTER_LLCC] = &llcc_mc, | |
350 | [SLAVE_EBI1] = &ebi, | |
351 | }; | |
352 | ||
5409e0cc | 353 | static const struct qcom_icc_desc sdm845_mem_noc = { |
aae57773 DD |
354 | .nodes = mem_noc_nodes, |
355 | .num_nodes = ARRAY_SIZE(mem_noc_nodes), | |
356 | .bcms = mem_noc_bcms, | |
357 | .num_bcms = ARRAY_SIZE(mem_noc_bcms), | |
358 | }; | |
359 | ||
360 | static struct qcom_icc_bcm *mmss_noc_bcms[] = { | |
361 | &bcm_mm0, | |
362 | &bcm_mm1, | |
363 | &bcm_mm2, | |
364 | &bcm_mm3, | |
365 | }; | |
366 | ||
367 | static struct qcom_icc_node *mmss_noc_nodes[] = { | |
368 | [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, | |
369 | [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, | |
370 | [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, | |
371 | [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, | |
372 | [MASTER_MDP0] = &qxm_mdp0, | |
373 | [MASTER_MDP1] = &qxm_mdp1, | |
374 | [MASTER_ROTATOR] = &qxm_rot, | |
375 | [MASTER_VIDEO_P0] = &qxm_venus0, | |
376 | [MASTER_VIDEO_P1] = &qxm_venus1, | |
377 | [MASTER_VIDEO_PROC] = &qxm_venus_arm9, | |
378 | [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, | |
379 | [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, | |
380 | [SLAVE_SERVICE_MNOC] = &srvc_mnoc, | |
381 | [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, | |
382 | [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, | |
383 | [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, | |
384 | [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, | |
385 | }; | |
386 | ||
5409e0cc | 387 | static const struct qcom_icc_desc sdm845_mmss_noc = { |
aae57773 DD |
388 | .nodes = mmss_noc_nodes, |
389 | .num_nodes = ARRAY_SIZE(mmss_noc_nodes), | |
390 | .bcms = mmss_noc_bcms, | |
391 | .num_bcms = ARRAY_SIZE(mmss_noc_bcms), | |
392 | }; | |
393 | ||
394 | static struct qcom_icc_bcm *system_noc_bcms[] = { | |
b5d2f741 | 395 | &bcm_sn0, |
b5d2f741 DD |
396 | &bcm_sn1, |
397 | &bcm_sn2, | |
398 | &bcm_sn3, | |
399 | &bcm_sn4, | |
400 | &bcm_sn5, | |
401 | &bcm_sn6, | |
402 | &bcm_sn7, | |
403 | &bcm_sn8, | |
404 | &bcm_sn9, | |
405 | &bcm_sn11, | |
406 | &bcm_sn12, | |
407 | &bcm_sn14, | |
408 | &bcm_sn15, | |
409 | }; | |
410 | ||
aae57773 DD |
411 | static struct qcom_icc_node *system_noc_nodes[] = { |
412 | [MASTER_SNOC_CFG] = &qhm_snoc_cfg, | |
413 | [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, | |
414 | [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, | |
415 | [MASTER_GNOC_SNOC] = &qnm_gladiator_sodv, | |
416 | [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, | |
417 | [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc, | |
418 | [MASTER_PIMEM] = &qxm_pimem, | |
419 | [MASTER_GIC] = &xm_gic, | |
420 | [SLAVE_APPSS] = &qhs_apss, | |
421 | [SLAVE_SNOC_CNOC] = &qns_cnoc, | |
422 | [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc, | |
423 | [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf, | |
424 | [SLAVE_IMEM] = &qxs_imem, | |
425 | [SLAVE_PCIE_0] = &qxs_pcie, | |
426 | [SLAVE_PCIE_1] = &qxs_pcie_gen3, | |
427 | [SLAVE_PIMEM] = &qxs_pimem, | |
428 | [SLAVE_SERVICE_SNOC] = &srvc_snoc, | |
429 | [SLAVE_QDSS_STM] = &xs_qdss_stm, | |
430 | [SLAVE_TCU] = &xs_sys_tcu_cfg, | |
b5d2f741 DD |
431 | }; |
432 | ||
5409e0cc | 433 | static const struct qcom_icc_desc sdm845_system_noc = { |
aae57773 DD |
434 | .nodes = system_noc_nodes, |
435 | .num_nodes = ARRAY_SIZE(system_noc_nodes), | |
436 | .bcms = system_noc_bcms, | |
437 | .num_bcms = ARRAY_SIZE(system_noc_bcms), | |
438 | }; | |
b5d2f741 DD |
439 | |
440 | static int qnoc_probe(struct platform_device *pdev) | |
441 | { | |
442 | const struct qcom_icc_desc *desc; | |
443 | struct icc_onecell_data *data; | |
444 | struct icc_provider *provider; | |
445 | struct qcom_icc_node **qnodes; | |
446 | struct qcom_icc_provider *qp; | |
447 | struct icc_node *node; | |
448 | size_t num_nodes, i; | |
449 | int ret; | |
450 | ||
aae57773 | 451 | desc = device_get_match_data(&pdev->dev); |
b5d2f741 DD |
452 | if (!desc) |
453 | return -EINVAL; | |
454 | ||
455 | qnodes = desc->nodes; | |
456 | num_nodes = desc->num_nodes; | |
457 | ||
458 | qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL); | |
459 | if (!qp) | |
460 | return -ENOMEM; | |
461 | ||
83c774f0 LC |
462 | data = devm_kzalloc(&pdev->dev, struct_size(data, nodes, num_nodes), |
463 | GFP_KERNEL); | |
b5d2f741 DD |
464 | if (!data) |
465 | return -ENOMEM; | |
466 | ||
467 | provider = &qp->provider; | |
468 | provider->dev = &pdev->dev; | |
469 | provider->set = qcom_icc_set; | |
9e3ce77c | 470 | provider->pre_aggregate = qcom_icc_pre_aggregate; |
b5d2f741 DD |
471 | provider->aggregate = qcom_icc_aggregate; |
472 | provider->xlate = of_icc_xlate_onecell; | |
473 | INIT_LIST_HEAD(&provider->nodes); | |
474 | provider->data = data; | |
475 | ||
476 | qp->dev = &pdev->dev; | |
477 | qp->bcms = desc->bcms; | |
478 | qp->num_bcms = desc->num_bcms; | |
479 | ||
aae57773 DD |
480 | qp->voter = of_bcm_voter_get(qp->dev, NULL); |
481 | if (IS_ERR(qp->voter)) { | |
482 | dev_err(&pdev->dev, "bcm_voter err:%ld\n", PTR_ERR(qp->voter)); | |
483 | return PTR_ERR(qp->voter); | |
484 | } | |
485 | ||
b5d2f741 DD |
486 | ret = icc_provider_add(provider); |
487 | if (ret) { | |
488 | dev_err(&pdev->dev, "error adding interconnect provider\n"); | |
489 | return ret; | |
490 | } | |
491 | ||
492 | for (i = 0; i < num_nodes; i++) { | |
493 | size_t j; | |
494 | ||
aae57773 DD |
495 | if (!qnodes[i]) |
496 | continue; | |
497 | ||
b5d2f741 DD |
498 | node = icc_node_create(qnodes[i]->id); |
499 | if (IS_ERR(node)) { | |
500 | ret = PTR_ERR(node); | |
501 | goto err; | |
502 | } | |
503 | ||
504 | node->name = qnodes[i]->name; | |
505 | node->data = qnodes[i]; | |
506 | icc_node_add(node, provider); | |
507 | ||
b5d2f741 DD |
508 | for (j = 0; j < qnodes[i]->num_links; j++) |
509 | icc_link_create(node, qnodes[i]->links[j]); | |
510 | ||
511 | data->nodes[i] = node; | |
512 | } | |
513 | data->num_nodes = num_nodes; | |
514 | ||
515 | for (i = 0; i < qp->num_bcms; i++) | |
516 | qcom_icc_bcm_init(qp->bcms[i], &pdev->dev); | |
517 | ||
b5d2f741 DD |
518 | platform_set_drvdata(pdev, qp); |
519 | ||
aae57773 | 520 | return 0; |
b5d2f741 | 521 | err: |
ad3703ac | 522 | icc_nodes_remove(provider); |
b5d2f741 DD |
523 | icc_provider_del(provider); |
524 | return ret; | |
525 | } | |
526 | ||
527 | static int qnoc_remove(struct platform_device *pdev) | |
528 | { | |
529 | struct qcom_icc_provider *qp = platform_get_drvdata(pdev); | |
b5d2f741 | 530 | |
ad3703ac GD |
531 | icc_nodes_remove(&qp->provider); |
532 | return icc_provider_del(&qp->provider); | |
b5d2f741 DD |
533 | } |
534 | ||
535 | static const struct of_device_id qnoc_of_match[] = { | |
aae57773 DD |
536 | { .compatible = "qcom,sdm845-aggre1-noc", |
537 | .data = &sdm845_aggre1_noc}, | |
538 | { .compatible = "qcom,sdm845-aggre2-noc", | |
539 | .data = &sdm845_aggre2_noc}, | |
540 | { .compatible = "qcom,sdm845-config-noc", | |
541 | .data = &sdm845_config_noc}, | |
542 | { .compatible = "qcom,sdm845-dc-noc", | |
543 | .data = &sdm845_dc_noc}, | |
544 | { .compatible = "qcom,sdm845-gladiator-noc", | |
545 | .data = &sdm845_gladiator_noc}, | |
546 | { .compatible = "qcom,sdm845-mem-noc", | |
547 | .data = &sdm845_mem_noc}, | |
548 | { .compatible = "qcom,sdm845-mmss-noc", | |
549 | .data = &sdm845_mmss_noc}, | |
550 | { .compatible = "qcom,sdm845-system-noc", | |
551 | .data = &sdm845_system_noc}, | |
552 | { } | |
b5d2f741 DD |
553 | }; |
554 | MODULE_DEVICE_TABLE(of, qnoc_of_match); | |
555 | ||
556 | static struct platform_driver qnoc_driver = { | |
557 | .probe = qnoc_probe, | |
558 | .remove = qnoc_remove, | |
559 | .driver = { | |
560 | .name = "qnoc-sdm845", | |
561 | .of_match_table = qnoc_of_match, | |
562 | }, | |
563 | }; | |
564 | module_platform_driver(qnoc_driver); | |
565 | ||
566 | MODULE_AUTHOR("David Dai <daidavid1@codeaurora.org>"); | |
567 | MODULE_DESCRIPTION("Qualcomm sdm845 NoC driver"); | |
568 | MODULE_LICENSE("GPL v2"); |