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Commit | Line | Data |
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45051539 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b6c02715 | 2 | /* |
5d0d7156 | 3 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 4 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 | 5 | * Leo Duran <leo.duran@amd.com> |
b6c02715 JR |
6 | */ |
7 | ||
101fa037 | 8 | #define pr_fmt(fmt) "AMD-Vi: " fmt |
5f226da1 | 9 | #define dev_fmt(fmt) pr_fmt(fmt) |
101fa037 | 10 | |
72e1dcc4 | 11 | #include <linux/ratelimit.h> |
b6c02715 | 12 | #include <linux/pci.h> |
2bf9a0a1 | 13 | #include <linux/acpi.h> |
9a4d3bf5 | 14 | #include <linux/amba/bus.h> |
0076cd3d | 15 | #include <linux/platform_device.h> |
cb41ed85 | 16 | #include <linux/pci-ats.h> |
a66022c4 | 17 | #include <linux/bitmap.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
7f26508b | 19 | #include <linux/debugfs.h> |
b6c02715 | 20 | #include <linux/scatterlist.h> |
0b1abd1f | 21 | #include <linux/dma-map-ops.h> |
fec777c3 | 22 | #include <linux/dma-direct.h> |
be62dbf5 | 23 | #include <linux/dma-iommu.h> |
b6c02715 | 24 | #include <linux/iommu-helper.h> |
815b33fd | 25 | #include <linux/delay.h> |
403f81d8 | 26 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
27 | #include <linux/notifier.h> |
28 | #include <linux/export.h> | |
2b324506 JR |
29 | #include <linux/irq.h> |
30 | #include <linux/msi.h> | |
7c71d306 | 31 | #include <linux/irqdomain.h> |
5f6bed50 | 32 | #include <linux/percpu.h> |
89c9a09c | 33 | #include <linux/io-pgtable.h> |
e9d1d2bb | 34 | #include <linux/cc_platform.h> |
2b324506 JR |
35 | #include <asm/irq_remapping.h> |
36 | #include <asm/io_apic.h> | |
37 | #include <asm/apic.h> | |
38 | #include <asm/hw_irq.h> | |
b6c02715 | 39 | #include <asm/proto.h> |
46a7fa27 | 40 | #include <asm/iommu.h> |
1d9b16d1 | 41 | #include <asm/gart.h> |
27c2127a | 42 | #include <asm/dma.h> |
403f81d8 | 43 | |
786dfe49 | 44 | #include "amd_iommu.h" |
ad8694ba | 45 | #include "../irq_remapping.h" |
b6c02715 JR |
46 | |
47 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
48 | ||
815b33fd | 49 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 50 | |
307d5851 JR |
51 | /* IO virtual address start page frame number */ |
52 | #define IOVA_START_PFN (1) | |
53 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) | |
307d5851 | 54 | |
81cd07b9 JR |
55 | /* Reserved IOVA ranges */ |
56 | #define MSI_RANGE_START (0xfee00000) | |
57 | #define MSI_RANGE_END (0xfeefffff) | |
58 | #define HT_RANGE_START (0xfd00000000ULL) | |
59 | #define HT_RANGE_END (0xffffffffffULL) | |
60 | ||
a71730e2 JR |
61 | #define DEFAULT_PGTABLE_LEVEL PAGE_MODE_3_LEVEL |
62 | ||
2bc00180 | 63 | static DEFINE_SPINLOCK(pd_bitmap_lock); |
b6c02715 | 64 | |
6efed63b JR |
65 | LIST_HEAD(ioapic_map); |
66 | LIST_HEAD(hpet_map); | |
2a0cb4e2 | 67 | LIST_HEAD(acpihid_map); |
6efed63b | 68 | |
0feae533 JR |
69 | /* |
70 | * Domain for untranslated devices - only allocated | |
71 | * if iommu=pt passed on kernel cmd line. | |
72 | */ | |
b0119e87 | 73 | const struct iommu_ops amd_iommu_ops; |
26961efe | 74 | |
72e1dcc4 | 75 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 76 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 77 | |
431b2a20 JR |
78 | /* |
79 | * general struct to manage commands send to an IOMMU | |
80 | */ | |
d6449536 | 81 | struct iommu_cmd { |
b6c02715 JR |
82 | u32 data[4]; |
83 | }; | |
84 | ||
05152a04 JR |
85 | struct kmem_cache *amd_iommu_irq_cache; |
86 | ||
b6809ee5 | 87 | static void detach_device(struct device *dev); |
81cd07b9 | 88 | |
15898bbc JR |
89 | /**************************************************************************** |
90 | * | |
91 | * Helper functions | |
92 | * | |
93 | ****************************************************************************/ | |
94 | ||
2bf9a0a1 WZ |
95 | static inline int get_acpihid_device_id(struct device *dev, |
96 | struct acpihid_map_entry **entry) | |
97 | { | |
ae5e6c64 | 98 | struct acpi_device *adev = ACPI_COMPANION(dev); |
2bf9a0a1 WZ |
99 | struct acpihid_map_entry *p; |
100 | ||
ae5e6c64 AS |
101 | if (!adev) |
102 | return -ENODEV; | |
103 | ||
2bf9a0a1 | 104 | list_for_each_entry(p, &acpihid_map, list) { |
ea90228c RR |
105 | if (acpi_dev_hid_uid_match(adev, p->hid, |
106 | p->uid[0] ? p->uid : NULL)) { | |
2bf9a0a1 WZ |
107 | if (entry) |
108 | *entry = p; | |
109 | return p->devid; | |
110 | } | |
111 | } | |
112 | return -EINVAL; | |
113 | } | |
114 | ||
bf87972c | 115 | static inline int get_device_sbdf_id(struct device *dev) |
2bf9a0a1 | 116 | { |
bf87972c | 117 | int sbdf; |
2bf9a0a1 WZ |
118 | |
119 | if (dev_is_pci(dev)) | |
bf87972c | 120 | sbdf = get_pci_sbdf_id(to_pci_dev(dev)); |
2bf9a0a1 | 121 | else |
bf87972c | 122 | sbdf = get_acpihid_device_id(dev, NULL); |
2bf9a0a1 | 123 | |
bf87972c | 124 | return sbdf; |
2bf9a0a1 WZ |
125 | } |
126 | ||
04230c11 SS |
127 | struct dev_table_entry *get_dev_table(struct amd_iommu *iommu) |
128 | { | |
129 | struct dev_table_entry *dev_table; | |
130 | struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; | |
131 | ||
132 | BUG_ON(pci_seg == NULL); | |
133 | dev_table = pci_seg->dev_table; | |
134 | BUG_ON(dev_table == NULL); | |
135 | ||
136 | return dev_table; | |
137 | } | |
138 | ||
eda797a2 SS |
139 | static inline u16 get_device_segment(struct device *dev) |
140 | { | |
141 | u16 seg; | |
142 | ||
143 | if (dev_is_pci(dev)) { | |
144 | struct pci_dev *pdev = to_pci_dev(dev); | |
145 | ||
146 | seg = pci_domain_nr(pdev->bus); | |
147 | } else { | |
148 | u32 devid = get_acpihid_device_id(dev, NULL); | |
149 | ||
150 | seg = PCI_SBDF_TO_SEGID(devid); | |
151 | } | |
152 | ||
153 | return seg; | |
154 | } | |
155 | ||
156 | /* Writes the specific IOMMU for a device into the PCI segment rlookup table */ | |
157 | void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid) | |
158 | { | |
159 | struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; | |
160 | ||
161 | pci_seg->rlookup_table[devid] = iommu; | |
162 | } | |
163 | ||
164 | static struct amd_iommu *__rlookup_amd_iommu(u16 seg, u16 devid) | |
165 | { | |
166 | struct amd_iommu_pci_seg *pci_seg; | |
167 | ||
168 | for_each_pci_segment(pci_seg) { | |
169 | if (pci_seg->id == seg) | |
170 | return pci_seg->rlookup_table[devid]; | |
171 | } | |
172 | return NULL; | |
173 | } | |
2bf9a0a1 | 174 | |
eda797a2 SS |
175 | static struct amd_iommu *rlookup_amd_iommu(struct device *dev) |
176 | { | |
177 | u16 seg = get_device_segment(dev); | |
bf87972c | 178 | int devid = get_device_sbdf_id(dev); |
eda797a2 | 179 | |
bf87972c SS |
180 | if (devid < 0) |
181 | return NULL; | |
182 | return __rlookup_amd_iommu(seg, PCI_SBDF_TO_DEVID(devid)); | |
2bf9a0a1 WZ |
183 | } |
184 | ||
3f4b87b9 JR |
185 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
186 | { | |
187 | return container_of(dom, struct protection_domain, domain); | |
188 | } | |
189 | ||
39a303ba | 190 | static struct iommu_dev_data *alloc_dev_data(struct amd_iommu *iommu, u16 devid) |
8fa5f802 JR |
191 | { |
192 | struct iommu_dev_data *dev_data; | |
39a303ba | 193 | struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; |
8fa5f802 JR |
194 | |
195 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
196 | if (!dev_data) | |
197 | return NULL; | |
198 | ||
ab7b2577 | 199 | spin_lock_init(&dev_data->lock); |
f62dda66 | 200 | dev_data->devid = devid; |
30bf2df6 JR |
201 | ratelimit_default_init(&dev_data->rs); |
202 | ||
39a303ba | 203 | llist_add(&dev_data->dev_data_list, &pci_seg->dev_data_list); |
8fa5f802 JR |
204 | return dev_data; |
205 | } | |
206 | ||
39a303ba | 207 | static struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid) |
3b03bb74 JR |
208 | { |
209 | struct iommu_dev_data *dev_data; | |
779da732 | 210 | struct llist_node *node; |
39a303ba | 211 | struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; |
3b03bb74 | 212 | |
39a303ba | 213 | if (llist_empty(&pci_seg->dev_data_list)) |
779da732 | 214 | return NULL; |
3b03bb74 | 215 | |
39a303ba | 216 | node = pci_seg->dev_data_list.first; |
779da732 | 217 | llist_for_each_entry(dev_data, node, dev_data_list) { |
3b03bb74 | 218 | if (dev_data->devid == devid) |
779da732 | 219 | return dev_data; |
3b03bb74 JR |
220 | } |
221 | ||
779da732 | 222 | return NULL; |
3b03bb74 JR |
223 | } |
224 | ||
3332364e | 225 | static int clone_alias(struct pci_dev *pdev, u16 alias, void *data) |
e3156048 | 226 | { |
8b71c9bf | 227 | struct amd_iommu *iommu; |
401360ec | 228 | struct dev_table_entry *dev_table; |
3332364e | 229 | u16 devid = pci_dev_id(pdev); |
5ebb1bc2 | 230 | |
3332364e LG |
231 | if (devid == alias) |
232 | return 0; | |
5ebb1bc2 | 233 | |
8b71c9bf SS |
234 | iommu = rlookup_amd_iommu(&pdev->dev); |
235 | if (!iommu) | |
236 | return 0; | |
237 | ||
238 | amd_iommu_set_rlookup_table(iommu, alias); | |
401360ec SS |
239 | dev_table = get_dev_table(iommu); |
240 | memcpy(dev_table[alias].data, | |
241 | dev_table[devid].data, | |
242 | sizeof(dev_table[alias].data)); | |
5ebb1bc2 | 243 | |
3332364e LG |
244 | return 0; |
245 | } | |
e3156048 | 246 | |
99fc4ac3 | 247 | static void clone_aliases(struct amd_iommu *iommu, struct device *dev) |
3332364e | 248 | { |
d02674d7 VH |
249 | struct pci_dev *pdev; |
250 | ||
251 | if (!dev_is_pci(dev)) | |
3332364e | 252 | return; |
d02674d7 | 253 | pdev = to_pci_dev(dev); |
e3156048 JR |
254 | |
255 | /* | |
3332364e LG |
256 | * The IVRS alias stored in the alias table may not be |
257 | * part of the PCI DMA aliases if it's bus differs | |
258 | * from the original device. | |
e3156048 | 259 | */ |
99fc4ac3 | 260 | clone_alias(pdev, iommu->pci_seg->alias_table[pci_dev_id(pdev)], NULL); |
e3156048 | 261 | |
3332364e LG |
262 | pci_for_each_dma_alias(pdev, clone_alias, NULL); |
263 | } | |
e3156048 | 264 | |
99fc4ac3 | 265 | static void setup_aliases(struct amd_iommu *iommu, struct device *dev) |
3332364e LG |
266 | { |
267 | struct pci_dev *pdev = to_pci_dev(dev); | |
99fc4ac3 | 268 | struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; |
3332364e LG |
269 | u16 ivrs_alias; |
270 | ||
271 | /* For ACPI HID devices, there are no aliases */ | |
272 | if (!dev_is_pci(dev)) | |
d02674d7 | 273 | return; |
e3156048 JR |
274 | |
275 | /* | |
3332364e LG |
276 | * Add the IVRS alias to the pci aliases if it is on the same |
277 | * bus. The IVRS table may know about a quirk that we don't. | |
e3156048 | 278 | */ |
99fc4ac3 | 279 | ivrs_alias = pci_seg->alias_table[pci_dev_id(pdev)]; |
3332364e | 280 | if (ivrs_alias != pci_dev_id(pdev) && |
09298542 JS |
281 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) |
282 | pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1); | |
e3156048 | 283 | |
99fc4ac3 | 284 | clone_aliases(iommu, dev); |
e3156048 JR |
285 | } |
286 | ||
ccacd94f | 287 | static struct iommu_dev_data *find_dev_data(struct amd_iommu *iommu, u16 devid) |
3b03bb74 JR |
288 | { |
289 | struct iommu_dev_data *dev_data; | |
290 | ||
39a303ba | 291 | dev_data = search_dev_data(iommu, devid); |
3b03bb74 | 292 | |
df3f7a6e | 293 | if (dev_data == NULL) { |
39a303ba | 294 | dev_data = alloc_dev_data(iommu, devid); |
39ffe395 SAS |
295 | if (!dev_data) |
296 | return NULL; | |
3b03bb74 | 297 | |
df3f7a6e BH |
298 | if (translation_pre_enabled(iommu)) |
299 | dev_data->defer_attach = true; | |
300 | } | |
301 | ||
3b03bb74 JR |
302 | return dev_data; |
303 | } | |
304 | ||
b097d11a WZ |
305 | /* |
306 | * Find or create an IOMMU group for a acpihid device. | |
307 | */ | |
308 | static struct iommu_group *acpihid_device_group(struct device *dev) | |
657cbb6b | 309 | { |
b097d11a | 310 | struct acpihid_map_entry *p, *entry = NULL; |
2d8e1f03 | 311 | int devid; |
b097d11a WZ |
312 | |
313 | devid = get_acpihid_device_id(dev, &entry); | |
314 | if (devid < 0) | |
315 | return ERR_PTR(devid); | |
316 | ||
317 | list_for_each_entry(p, &acpihid_map, list) { | |
318 | if ((devid == p->devid) && p->group) | |
319 | entry->group = p->group; | |
320 | } | |
321 | ||
322 | if (!entry->group) | |
323 | entry->group = generic_device_group(dev); | |
f2f101f6 RM |
324 | else |
325 | iommu_group_ref_get(entry->group); | |
b097d11a WZ |
326 | |
327 | return entry->group; | |
657cbb6b JR |
328 | } |
329 | ||
5abcdba4 JR |
330 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
331 | { | |
332 | static const int caps[] = { | |
46277b75 JR |
333 | PCI_EXT_CAP_ID_PRI, |
334 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
335 | }; |
336 | int i, pos; | |
337 | ||
7a441b21 | 338 | if (!pci_ats_supported(pdev)) |
cef74409 GK |
339 | return false; |
340 | ||
7a441b21 | 341 | for (i = 0; i < 2; ++i) { |
5abcdba4 JR |
342 | pos = pci_find_ext_capability(pdev, caps[i]); |
343 | if (pos == 0) | |
344 | return false; | |
345 | } | |
346 | ||
347 | return true; | |
348 | } | |
349 | ||
98fc5a69 JR |
350 | /* |
351 | * This function checks if the driver got a valid device from the caller to | |
352 | * avoid dereferencing invalid pointers. | |
353 | */ | |
354 | static bool check_device(struct device *dev) | |
355 | { | |
401360ec SS |
356 | struct amd_iommu_pci_seg *pci_seg; |
357 | struct amd_iommu *iommu; | |
bf87972c | 358 | int devid, sbdf; |
98fc5a69 | 359 | |
c0da9b9f | 360 | if (!dev) |
98fc5a69 JR |
361 | return false; |
362 | ||
bf87972c SS |
363 | sbdf = get_device_sbdf_id(dev); |
364 | if (sbdf < 0) | |
7aba6cb9 | 365 | return false; |
bf87972c | 366 | devid = PCI_SBDF_TO_DEVID(sbdf); |
98fc5a69 | 367 | |
401360ec SS |
368 | iommu = rlookup_amd_iommu(dev); |
369 | if (!iommu) | |
98fc5a69 JR |
370 | return false; |
371 | ||
401360ec SS |
372 | /* Out of our scope? */ |
373 | pci_seg = iommu->pci_seg; | |
bf87972c | 374 | if (devid > pci_seg->last_bdf) |
98fc5a69 JR |
375 | return false; |
376 | ||
377 | return true; | |
378 | } | |
379 | ||
99fc4ac3 | 380 | static int iommu_init_device(struct amd_iommu *iommu, struct device *dev) |
eb9c9527 | 381 | { |
eb9c9527 | 382 | struct iommu_dev_data *dev_data; |
bf87972c | 383 | int devid, sbdf; |
eb9c9527 | 384 | |
05a0542b | 385 | if (dev_iommu_priv_get(dev)) |
eb9c9527 AW |
386 | return 0; |
387 | ||
bf87972c SS |
388 | sbdf = get_device_sbdf_id(dev); |
389 | if (sbdf < 0) | |
390 | return sbdf; | |
7aba6cb9 | 391 | |
bf87972c | 392 | devid = PCI_SBDF_TO_DEVID(sbdf); |
ccacd94f | 393 | dev_data = find_dev_data(iommu, devid); |
eb9c9527 AW |
394 | if (!dev_data) |
395 | return -ENOMEM; | |
396 | ||
d02674d7 | 397 | dev_data->dev = dev; |
99fc4ac3 | 398 | setup_aliases(iommu, dev); |
e3156048 | 399 | |
c12b08eb YZ |
400 | /* |
401 | * By default we use passthrough mode for IOMMUv2 capable device. | |
402 | * But if amd_iommu=force_isolation is set (e.g. to debug DMA to | |
403 | * invalid address), we ignore the capability for the device so | |
404 | * it'll be forced to go into translation mode. | |
405 | */ | |
cc7c8ad9 | 406 | if ((iommu_default_passthrough() || !amd_iommu_force_isolation) && |
c12b08eb | 407 | dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { |
5abcdba4 JR |
408 | dev_data->iommu_v2 = iommu->is_iommu_v2; |
409 | } | |
410 | ||
05a0542b | 411 | dev_iommu_priv_set(dev, dev_data); |
066f2e98 | 412 | |
657cbb6b JR |
413 | return 0; |
414 | } | |
415 | ||
99fc4ac3 | 416 | static void iommu_ignore_device(struct amd_iommu *iommu, struct device *dev) |
26018874 | 417 | { |
ccacd94f | 418 | struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; |
ccbb091f | 419 | struct dev_table_entry *dev_table = get_dev_table(iommu); |
bf87972c | 420 | int devid, sbdf; |
26018874 | 421 | |
bf87972c SS |
422 | sbdf = get_device_sbdf_id(dev); |
423 | if (sbdf < 0) | |
7aba6cb9 WZ |
424 | return; |
425 | ||
bf87972c | 426 | devid = PCI_SBDF_TO_DEVID(sbdf); |
ccacd94f | 427 | pci_seg->rlookup_table[devid] = NULL; |
ccbb091f | 428 | memset(&dev_table[devid], 0, sizeof(struct dev_table_entry)); |
26018874 | 429 | |
99fc4ac3 | 430 | setup_aliases(iommu, dev); |
26018874 JR |
431 | } |
432 | ||
dce8d696 | 433 | static void amd_iommu_uninit_device(struct device *dev) |
657cbb6b | 434 | { |
7aba6cb9 | 435 | struct iommu_dev_data *dev_data; |
c1931090 | 436 | |
736c3333 | 437 | dev_data = dev_iommu_priv_get(dev); |
c1931090 AW |
438 | if (!dev_data) |
439 | return; | |
440 | ||
b6809ee5 JR |
441 | if (dev_data->domain) |
442 | detach_device(dev); | |
443 | ||
05a0542b | 444 | dev_iommu_priv_set(dev, NULL); |
aafd8ba0 | 445 | |
8fa5f802 | 446 | /* |
c1931090 AW |
447 | * We keep dev_data around for unplugged devices and reuse it when the |
448 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 449 | */ |
657cbb6b | 450 | } |
b7cc9554 | 451 | |
a80dc3e0 JR |
452 | /**************************************************************************** |
453 | * | |
454 | * Interrupt handling functions | |
455 | * | |
456 | ****************************************************************************/ | |
457 | ||
4cc053d7 | 458 | static void dump_dte_entry(struct amd_iommu *iommu, u16 devid) |
e3e59876 JR |
459 | { |
460 | int i; | |
4cc053d7 | 461 | struct dev_table_entry *dev_table = get_dev_table(iommu); |
e3e59876 | 462 | |
ee6c2868 | 463 | for (i = 0; i < 4; ++i) |
4cc053d7 | 464 | pr_err("DTE[%d]: %016llx\n", i, dev_table[devid].data[i]); |
e3e59876 JR |
465 | } |
466 | ||
945b4ac4 JR |
467 | static void dump_command(unsigned long phys_addr) |
468 | { | |
2543a786 | 469 | struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr); |
945b4ac4 JR |
470 | int i; |
471 | ||
472 | for (i = 0; i < 4; ++i) | |
101fa037 | 473 | pr_err("CMD[%d]: %08x\n", i, cmd->data[i]); |
945b4ac4 JR |
474 | } |
475 | ||
e5670e18 | 476 | static void amd_iommu_report_rmp_hw_error(struct amd_iommu *iommu, volatile u32 *event) |
2818de6e SS |
477 | { |
478 | struct iommu_dev_data *dev_data = NULL; | |
479 | int devid, vmg_tag, flags; | |
480 | struct pci_dev *pdev; | |
481 | u64 spa; | |
482 | ||
483 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
484 | vmg_tag = (event[1]) & 0xFFFF; | |
485 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
486 | spa = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8); | |
487 | ||
e5670e18 | 488 | pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid), |
2818de6e SS |
489 | devid & 0xff); |
490 | if (pdev) | |
491 | dev_data = dev_iommu_priv_get(&pdev->dev); | |
492 | ||
ee974d96 LB |
493 | if (dev_data) { |
494 | if (__ratelimit(&dev_data->rs)) { | |
495 | pci_err(pdev, "Event logged [RMP_HW_ERROR vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n", | |
496 | vmg_tag, spa, flags); | |
497 | } | |
2818de6e | 498 | } else { |
b36a5b0f VH |
499 | pr_err_ratelimited("Event logged [RMP_HW_ERROR device=%04x:%02x:%02x.%x, vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n", |
500 | iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
2818de6e SS |
501 | vmg_tag, spa, flags); |
502 | } | |
503 | ||
504 | if (pdev) | |
505 | pci_dev_put(pdev); | |
506 | } | |
507 | ||
e5670e18 | 508 | static void amd_iommu_report_rmp_fault(struct amd_iommu *iommu, volatile u32 *event) |
2818de6e SS |
509 | { |
510 | struct iommu_dev_data *dev_data = NULL; | |
511 | int devid, flags_rmp, vmg_tag, flags; | |
512 | struct pci_dev *pdev; | |
513 | u64 gpa; | |
514 | ||
515 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
516 | flags_rmp = (event[0] >> EVENT_FLAGS_SHIFT) & 0xFF; | |
517 | vmg_tag = (event[1]) & 0xFFFF; | |
518 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
519 | gpa = ((u64)event[3] << 32) | event[2]; | |
520 | ||
e5670e18 | 521 | pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid), |
2818de6e SS |
522 | devid & 0xff); |
523 | if (pdev) | |
524 | dev_data = dev_iommu_priv_get(&pdev->dev); | |
525 | ||
ee974d96 LB |
526 | if (dev_data) { |
527 | if (__ratelimit(&dev_data->rs)) { | |
528 | pci_err(pdev, "Event logged [RMP_PAGE_FAULT vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n", | |
529 | vmg_tag, gpa, flags_rmp, flags); | |
530 | } | |
2818de6e | 531 | } else { |
b36a5b0f VH |
532 | pr_err_ratelimited("Event logged [RMP_PAGE_FAULT device=%04x:%02x:%02x.%x, vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n", |
533 | iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
2818de6e SS |
534 | vmg_tag, gpa, flags_rmp, flags); |
535 | } | |
536 | ||
537 | if (pdev) | |
538 | pci_dev_put(pdev); | |
539 | } | |
540 | ||
9f78e446 LB |
541 | #define IS_IOMMU_MEM_TRANSACTION(flags) \ |
542 | (((flags) & EVENT_FLAG_I) == 0) | |
543 | ||
544 | #define IS_WRITE_REQUEST(flags) \ | |
545 | ((flags) & EVENT_FLAG_RW) | |
546 | ||
e5670e18 SS |
547 | static void amd_iommu_report_page_fault(struct amd_iommu *iommu, |
548 | u16 devid, u16 domain_id, | |
30bf2df6 JR |
549 | u64 address, int flags) |
550 | { | |
551 | struct iommu_dev_data *dev_data = NULL; | |
552 | struct pci_dev *pdev; | |
553 | ||
e5670e18 | 554 | pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid), |
d5bf0f4f | 555 | devid & 0xff); |
30bf2df6 | 556 | if (pdev) |
05a0542b | 557 | dev_data = dev_iommu_priv_get(&pdev->dev); |
30bf2df6 | 558 | |
ee974d96 | 559 | if (dev_data) { |
9f78e446 LB |
560 | /* |
561 | * If this is a DMA fault (for which the I(nterrupt) | |
562 | * bit will be unset), allow report_iommu_fault() to | |
563 | * prevent logging it. | |
564 | */ | |
565 | if (IS_IOMMU_MEM_TRANSACTION(flags)) { | |
566 | if (!report_iommu_fault(&dev_data->domain->domain, | |
567 | &pdev->dev, address, | |
568 | IS_WRITE_REQUEST(flags) ? | |
569 | IOMMU_FAULT_WRITE : | |
570 | IOMMU_FAULT_READ)) | |
571 | goto out; | |
572 | } | |
573 | ||
ee974d96 LB |
574 | if (__ratelimit(&dev_data->rs)) { |
575 | pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n", | |
576 | domain_id, address, flags); | |
577 | } | |
578 | } else { | |
b36a5b0f VH |
579 | pr_err_ratelimited("Event logged [IO_PAGE_FAULT device=%04x:%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n", |
580 | iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
30bf2df6 JR |
581 | domain_id, address, flags); |
582 | } | |
583 | ||
9f78e446 | 584 | out: |
30bf2df6 JR |
585 | if (pdev) |
586 | pci_dev_put(pdev); | |
587 | } | |
588 | ||
a345b23b | 589 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 590 | { |
90ca3859 | 591 | struct device *dev = iommu->iommu.dev; |
c7b6bac9 | 592 | int type, devid, flags, tag; |
3d06fca8 JR |
593 | volatile u32 *event = __evt; |
594 | int count = 0; | |
595 | u64 address; | |
c7b6bac9 | 596 | u32 pasid; |
3d06fca8 JR |
597 | |
598 | retry: | |
599 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
600 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
ec21f17a SS |
601 | pasid = (event[0] & EVENT_DOMID_MASK_HI) | |
602 | (event[1] & EVENT_DOMID_MASK_LO); | |
3d06fca8 JR |
603 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; |
604 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
605 | ||
606 | if (type == 0) { | |
607 | /* Did we hit the erratum? */ | |
608 | if (++count == LOOP_TIMEOUT) { | |
101fa037 | 609 | pr_err("No event written to event log\n"); |
3d06fca8 JR |
610 | return; |
611 | } | |
612 | udelay(1); | |
613 | goto retry; | |
614 | } | |
90008ee4 | 615 | |
30bf2df6 | 616 | if (type == EVENT_TYPE_IO_FAULT) { |
e5670e18 | 617 | amd_iommu_report_page_fault(iommu, devid, pasid, address, flags); |
30bf2df6 | 618 | return; |
30bf2df6 | 619 | } |
90008ee4 JR |
620 | |
621 | switch (type) { | |
622 | case EVENT_TYPE_ILL_DEV: | |
b36a5b0f VH |
623 | dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", |
624 | iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
d64c0486 | 625 | pasid, address, flags); |
4cc053d7 | 626 | dump_dte_entry(iommu, devid); |
90008ee4 | 627 | break; |
90008ee4 | 628 | case EVENT_TYPE_DEV_TAB_ERR: |
b36a5b0f | 629 | dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%04x:%02x:%02x.%x " |
6f5086a6 | 630 | "address=0x%llx flags=0x%04x]\n", |
b36a5b0f | 631 | iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90ca3859 | 632 | address, flags); |
90008ee4 JR |
633 | break; |
634 | case EVENT_TYPE_PAGE_TAB_ERR: | |
b36a5b0f VH |
635 | dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%04x:%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n", |
636 | iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
d64c0486 | 637 | pasid, address, flags); |
90008ee4 JR |
638 | break; |
639 | case EVENT_TYPE_ILL_CMD: | |
6f5086a6 | 640 | dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address); |
945b4ac4 | 641 | dump_command(address); |
90008ee4 JR |
642 | break; |
643 | case EVENT_TYPE_CMD_HARD_ERR: | |
6f5086a6 | 644 | dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n", |
d64c0486 | 645 | address, flags); |
90008ee4 JR |
646 | break; |
647 | case EVENT_TYPE_IOTLB_INV_TO: | |
b36a5b0f VH |
648 | dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%04x:%02x:%02x.%x address=0x%llx]\n", |
649 | iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
90ca3859 | 650 | address); |
90008ee4 JR |
651 | break; |
652 | case EVENT_TYPE_INV_DEV_REQ: | |
b36a5b0f VH |
653 | dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", |
654 | iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
d64c0486 | 655 | pasid, address, flags); |
90008ee4 | 656 | break; |
2818de6e | 657 | case EVENT_TYPE_RMP_FAULT: |
e5670e18 | 658 | amd_iommu_report_rmp_fault(iommu, event); |
2818de6e SS |
659 | break; |
660 | case EVENT_TYPE_RMP_HW_ERR: | |
e5670e18 | 661 | amd_iommu_report_rmp_hw_error(iommu, event); |
2818de6e | 662 | break; |
e7f63ffc | 663 | case EVENT_TYPE_INV_PPR_REQ: |
470eb3b3 | 664 | pasid = PPR_PASID(*((u64 *)__evt)); |
e7f63ffc | 665 | tag = event[1] & 0x03FF; |
b36a5b0f VH |
666 | dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n", |
667 | iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
c1ddcf1c | 668 | pasid, address, flags, tag); |
90008ee4 JR |
669 | break; |
670 | default: | |
1a21ee1a | 671 | dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n", |
90ca3859 | 672 | event[0], event[1], event[2], event[3]); |
90008ee4 | 673 | } |
3d06fca8 JR |
674 | |
675 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
676 | } |
677 | ||
678 | static void iommu_poll_events(struct amd_iommu *iommu) | |
679 | { | |
680 | u32 head, tail; | |
90008ee4 JR |
681 | |
682 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
683 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
684 | ||
685 | while (head != tail) { | |
a345b23b | 686 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 687 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
688 | } |
689 | ||
690 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
691 | } |
692 | ||
eee53537 | 693 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
694 | { |
695 | struct amd_iommu_fault fault; | |
72e1dcc4 | 696 | |
72e1dcc4 | 697 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
101fa037 | 698 | pr_err_ratelimited("Unknown PPR request received\n"); |
72e1dcc4 JR |
699 | return; |
700 | } | |
701 | ||
702 | fault.address = raw[1]; | |
703 | fault.pasid = PPR_PASID(raw[0]); | |
214a05c1 | 704 | fault.sbdf = PCI_SEG_DEVID_TO_SBDF(iommu->pci_seg->id, PPR_DEVID(raw[0])); |
72e1dcc4 JR |
705 | fault.tag = PPR_TAG(raw[0]); |
706 | fault.flags = PPR_FLAGS(raw[0]); | |
707 | ||
72e1dcc4 JR |
708 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
709 | } | |
710 | ||
711 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
712 | { | |
72e1dcc4 JR |
713 | u32 head, tail; |
714 | ||
715 | if (iommu->ppr_log == NULL) | |
716 | return; | |
717 | ||
72e1dcc4 JR |
718 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
719 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
720 | ||
721 | while (head != tail) { | |
eee53537 JR |
722 | volatile u64 *raw; |
723 | u64 entry[2]; | |
724 | int i; | |
725 | ||
726 | raw = (u64 *)(iommu->ppr_log + head); | |
727 | ||
728 | /* | |
729 | * Hardware bug: Interrupt may arrive before the entry is | |
730 | * written to memory. If this happens we need to wait for the | |
731 | * entry to arrive. | |
732 | */ | |
733 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
734 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
735 | break; | |
736 | udelay(1); | |
737 | } | |
72e1dcc4 | 738 | |
eee53537 JR |
739 | /* Avoid memcpy function-call overhead */ |
740 | entry[0] = raw[0]; | |
741 | entry[1] = raw[1]; | |
72e1dcc4 | 742 | |
eee53537 JR |
743 | /* |
744 | * To detect the hardware bug we need to clear the entry | |
745 | * back to zero. | |
746 | */ | |
747 | raw[0] = raw[1] = 0UL; | |
748 | ||
749 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
750 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
751 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 752 | |
eee53537 JR |
753 | /* Handle PPR entry */ |
754 | iommu_handle_ppr_entry(iommu, entry); | |
755 | ||
eee53537 JR |
756 | /* Refresh ring-buffer information */ |
757 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
758 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
759 | } | |
72e1dcc4 JR |
760 | } |
761 | ||
bd6fcefc SS |
762 | #ifdef CONFIG_IRQ_REMAP |
763 | static int (*iommu_ga_log_notifier)(u32); | |
764 | ||
765 | int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) | |
766 | { | |
767 | iommu_ga_log_notifier = notifier; | |
768 | ||
769 | return 0; | |
770 | } | |
771 | EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier); | |
772 | ||
773 | static void iommu_poll_ga_log(struct amd_iommu *iommu) | |
774 | { | |
775 | u32 head, tail, cnt = 0; | |
776 | ||
777 | if (iommu->ga_log == NULL) | |
778 | return; | |
779 | ||
780 | head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
781 | tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); | |
782 | ||
783 | while (head != tail) { | |
784 | volatile u64 *raw; | |
785 | u64 log_entry; | |
786 | ||
787 | raw = (u64 *)(iommu->ga_log + head); | |
788 | cnt++; | |
789 | ||
790 | /* Avoid memcpy function-call overhead */ | |
791 | log_entry = *raw; | |
792 | ||
793 | /* Update head pointer of hardware ring-buffer */ | |
794 | head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE; | |
795 | writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
796 | ||
797 | /* Handle GA entry */ | |
798 | switch (GA_REQ_TYPE(log_entry)) { | |
799 | case GA_GUEST_NR: | |
800 | if (!iommu_ga_log_notifier) | |
801 | break; | |
802 | ||
101fa037 | 803 | pr_debug("%s: devid=%#x, ga_tag=%#x\n", |
bd6fcefc SS |
804 | __func__, GA_DEVID(log_entry), |
805 | GA_TAG(log_entry)); | |
806 | ||
807 | if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0) | |
101fa037 | 808 | pr_err("GA log notifier failed.\n"); |
bd6fcefc SS |
809 | break; |
810 | default: | |
811 | break; | |
812 | } | |
813 | } | |
814 | } | |
2b2c6aa6 TG |
815 | |
816 | static void | |
817 | amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) | |
818 | { | |
819 | if (!irq_remapping_enabled || !dev_is_pci(dev) || | |
820 | pci_dev_has_special_msi_domain(to_pci_dev(dev))) | |
821 | return; | |
822 | ||
823 | dev_set_msi_domain(dev, iommu->msi_domain); | |
824 | } | |
825 | ||
826 | #else /* CONFIG_IRQ_REMAP */ | |
827 | static inline void | |
828 | amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { } | |
829 | #endif /* !CONFIG_IRQ_REMAP */ | |
bd6fcefc SS |
830 | |
831 | #define AMD_IOMMU_INT_MASK \ | |
5ce97f4e LB |
832 | (MMIO_STATUS_EVT_OVERFLOW_INT_MASK | \ |
833 | MMIO_STATUS_EVT_INT_MASK | \ | |
bd6fcefc SS |
834 | MMIO_STATUS_PPR_INT_MASK | \ |
835 | MMIO_STATUS_GALOG_INT_MASK) | |
836 | ||
72fe00f0 | 837 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 838 | { |
3f398bc7 SS |
839 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
840 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 841 | |
bd6fcefc | 842 | while (status & AMD_IOMMU_INT_MASK) { |
5ce97f4e | 843 | /* Enable interrupt sources again */ |
bd6fcefc | 844 | writel(AMD_IOMMU_INT_MASK, |
3f398bc7 | 845 | iommu->mmio_base + MMIO_STATUS_OFFSET); |
90008ee4 | 846 | |
3f398bc7 | 847 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
101fa037 | 848 | pr_devel("Processing IOMMU Event Log\n"); |
3f398bc7 SS |
849 | iommu_poll_events(iommu); |
850 | } | |
90008ee4 | 851 | |
3f398bc7 | 852 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
101fa037 | 853 | pr_devel("Processing IOMMU PPR Log\n"); |
3f398bc7 SS |
854 | iommu_poll_ppr_log(iommu); |
855 | } | |
90008ee4 | 856 | |
bd6fcefc SS |
857 | #ifdef CONFIG_IRQ_REMAP |
858 | if (status & MMIO_STATUS_GALOG_INT_MASK) { | |
101fa037 | 859 | pr_devel("Processing IOMMU GA Log\n"); |
bd6fcefc SS |
860 | iommu_poll_ga_log(iommu); |
861 | } | |
862 | #endif | |
863 | ||
5ce97f4e LB |
864 | if (status & MMIO_STATUS_EVT_OVERFLOW_INT_MASK) { |
865 | pr_info_ratelimited("IOMMU event log overflow\n"); | |
866 | amd_iommu_restart_event_logging(iommu); | |
867 | } | |
868 | ||
3f398bc7 SS |
869 | /* |
870 | * Hardware bug: ERBT1312 | |
871 | * When re-enabling interrupt (by writing 1 | |
872 | * to clear the bit), the hardware might also try to set | |
873 | * the interrupt bit in the event status register. | |
874 | * In this scenario, the bit will be set, and disable | |
875 | * subsequent interrupts. | |
876 | * | |
877 | * Workaround: The IOMMU driver should read back the | |
878 | * status register and check if the interrupt bits are cleared. | |
879 | * If not, driver will need to go through the interrupt handler | |
880 | * again and re-clear the bits | |
881 | */ | |
882 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
883 | } | |
90008ee4 | 884 | return IRQ_HANDLED; |
a80dc3e0 JR |
885 | } |
886 | ||
72fe00f0 JR |
887 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
888 | { | |
889 | return IRQ_WAKE_THREAD; | |
890 | } | |
891 | ||
431b2a20 JR |
892 | /**************************************************************************** |
893 | * | |
894 | * IOMMU command queuing functions | |
895 | * | |
896 | ****************************************************************************/ | |
897 | ||
c69d89af | 898 | static int wait_on_sem(struct amd_iommu *iommu, u64 data) |
ac0ea6e9 JR |
899 | { |
900 | int i = 0; | |
901 | ||
c69d89af | 902 | while (*iommu->cmd_sem != data && i < LOOP_TIMEOUT) { |
ac0ea6e9 JR |
903 | udelay(1); |
904 | i += 1; | |
905 | } | |
906 | ||
907 | if (i == LOOP_TIMEOUT) { | |
101fa037 | 908 | pr_alert("Completion-Wait loop timed out\n"); |
ac0ea6e9 JR |
909 | return -EIO; |
910 | } | |
911 | ||
912 | return 0; | |
913 | } | |
914 | ||
915 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
d334a563 | 916 | struct iommu_cmd *cmd) |
a19ae1ec | 917 | { |
a19ae1ec | 918 | u8 *target; |
a5bbbf37 | 919 | u32 tail; |
ac0ea6e9 JR |
920 | |
921 | /* Copy command to buffer */ | |
a5bbbf37 DV |
922 | tail = iommu->cmd_buf_tail; |
923 | target = iommu->cmd_buf + tail; | |
ac0ea6e9 JR |
924 | memcpy(target, cmd, sizeof(*cmd)); |
925 | ||
a5bbbf37 DV |
926 | tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
927 | iommu->cmd_buf_tail = tail; | |
928 | ||
ac0ea6e9 | 929 | /* Tell the IOMMU about it */ |
a5bbbf37 | 930 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 931 | } |
a19ae1ec | 932 | |
c69d89af SS |
933 | static void build_completion_wait(struct iommu_cmd *cmd, |
934 | struct amd_iommu *iommu, | |
935 | u64 data) | |
ded46737 | 936 | { |
c69d89af | 937 | u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem); |
815b33fd | 938 | |
ded46737 | 939 | memset(cmd, 0, sizeof(*cmd)); |
2543a786 TL |
940 | cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; |
941 | cmd->data[1] = upper_32_bits(paddr); | |
94a568ce JS |
942 | cmd->data[2] = lower_32_bits(data); |
943 | cmd->data[3] = upper_32_bits(data); | |
ded46737 JR |
944 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
945 | } | |
946 | ||
94fe79e2 JR |
947 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
948 | { | |
949 | memset(cmd, 0, sizeof(*cmd)); | |
950 | cmd->data[0] = devid; | |
951 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
952 | } | |
953 | ||
268aa454 NA |
954 | /* |
955 | * Builds an invalidation address which is suitable for one page or multiple | |
956 | * pages. Sets the size bit (S) as needed is more than one page is flushed. | |
957 | */ | |
958 | static inline u64 build_inv_address(u64 address, size_t size) | |
11b6402c | 959 | { |
268aa454 | 960 | u64 pages, end, msb_diff; |
11b6402c JR |
961 | |
962 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
11b6402c | 963 | |
268aa454 NA |
964 | if (pages == 1) |
965 | return address & PAGE_MASK; | |
966 | ||
967 | end = address + size - 1; | |
968 | ||
969 | /* | |
970 | * msb_diff would hold the index of the most significant bit that | |
971 | * flipped between the start and end. | |
972 | */ | |
973 | msb_diff = fls64(end ^ address) - 1; | |
974 | ||
975 | /* | |
976 | * Bits 63:52 are sign extended. If for some reason bit 51 is different | |
977 | * between the start and the end, invalidate everything. | |
978 | */ | |
979 | if (unlikely(msb_diff > 51)) { | |
980 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
981 | } else { | |
11b6402c | 982 | /* |
268aa454 NA |
983 | * The msb-bit must be clear on the address. Just set all the |
984 | * lower bits. | |
11b6402c | 985 | */ |
a017c567 | 986 | address |= (1ull << msb_diff) - 1; |
11b6402c JR |
987 | } |
988 | ||
268aa454 | 989 | /* Clear bits 11:0 */ |
11b6402c JR |
990 | address &= PAGE_MASK; |
991 | ||
268aa454 NA |
992 | /* Set the size bit - we flush more than one 4kb page */ |
993 | return address | CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
994 | } | |
995 | ||
996 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, | |
997 | size_t size, u16 domid, int pde) | |
998 | { | |
999 | u64 inv_address = build_inv_address(address, size); | |
1000 | ||
11b6402c JR |
1001 | memset(cmd, 0, sizeof(*cmd)); |
1002 | cmd->data[1] |= domid; | |
268aa454 NA |
1003 | cmd->data[2] = lower_32_bits(inv_address); |
1004 | cmd->data[3] = upper_32_bits(inv_address); | |
11b6402c | 1005 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); |
df805abb | 1006 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
1007 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
1008 | } | |
1009 | ||
cb41ed85 JR |
1010 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
1011 | u64 address, size_t size) | |
1012 | { | |
268aa454 | 1013 | u64 inv_address = build_inv_address(address, size); |
cb41ed85 JR |
1014 | |
1015 | memset(cmd, 0, sizeof(*cmd)); | |
1016 | cmd->data[0] = devid; | |
1017 | cmd->data[0] |= (qdep & 0xff) << 24; | |
1018 | cmd->data[1] = devid; | |
268aa454 NA |
1019 | cmd->data[2] = lower_32_bits(inv_address); |
1020 | cmd->data[3] = upper_32_bits(inv_address); | |
cb41ed85 | 1021 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); |
cb41ed85 JR |
1022 | } |
1023 | ||
c7b6bac9 | 1024 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid, |
22e266c7 JR |
1025 | u64 address, bool size) |
1026 | { | |
1027 | memset(cmd, 0, sizeof(*cmd)); | |
1028 | ||
1029 | address &= ~(0xfffULL); | |
1030 | ||
a919a018 | 1031 | cmd->data[0] = pasid; |
22e266c7 JR |
1032 | cmd->data[1] = domid; |
1033 | cmd->data[2] = lower_32_bits(address); | |
1034 | cmd->data[3] = upper_32_bits(address); | |
1035 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
1036 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
1037 | if (size) | |
1038 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
1039 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
1040 | } | |
1041 | ||
c7b6bac9 | 1042 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid, |
22e266c7 JR |
1043 | int qdep, u64 address, bool size) |
1044 | { | |
1045 | memset(cmd, 0, sizeof(*cmd)); | |
1046 | ||
1047 | address &= ~(0xfffULL); | |
1048 | ||
1049 | cmd->data[0] = devid; | |
e8d2d82d | 1050 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
1051 | cmd->data[0] |= (qdep & 0xff) << 24; |
1052 | cmd->data[1] = devid; | |
e8d2d82d | 1053 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
1054 | cmd->data[2] = lower_32_bits(address); |
1055 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
1056 | cmd->data[3] = upper_32_bits(address); | |
1057 | if (size) | |
1058 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
1059 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
1060 | } | |
1061 | ||
c7b6bac9 | 1062 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid, |
c99afa25 JR |
1063 | int status, int tag, bool gn) |
1064 | { | |
1065 | memset(cmd, 0, sizeof(*cmd)); | |
1066 | ||
1067 | cmd->data[0] = devid; | |
1068 | if (gn) { | |
a919a018 | 1069 | cmd->data[1] = pasid; |
c99afa25 JR |
1070 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
1071 | } | |
1072 | cmd->data[3] = tag & 0x1ff; | |
1073 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
1074 | ||
1075 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
1076 | } | |
1077 | ||
58fc7f14 JR |
1078 | static void build_inv_all(struct iommu_cmd *cmd) |
1079 | { | |
1080 | memset(cmd, 0, sizeof(*cmd)); | |
1081 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
1082 | } |
1083 | ||
7ef2798d JR |
1084 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
1085 | { | |
1086 | memset(cmd, 0, sizeof(*cmd)); | |
1087 | cmd->data[0] = devid; | |
1088 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
1089 | } | |
1090 | ||
431b2a20 | 1091 | /* |
431b2a20 | 1092 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 1093 | * hardware about the new command. |
431b2a20 | 1094 | */ |
4bf5beef JR |
1095 | static int __iommu_queue_command_sync(struct amd_iommu *iommu, |
1096 | struct iommu_cmd *cmd, | |
1097 | bool sync) | |
a19ae1ec | 1098 | { |
23e967e1 | 1099 | unsigned int count = 0; |
d334a563 | 1100 | u32 left, next_tail; |
a19ae1ec | 1101 | |
d334a563 | 1102 | next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 | 1103 | again: |
d334a563 | 1104 | left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE; |
a19ae1ec | 1105 | |
432abf68 | 1106 | if (left <= 0x20) { |
23e967e1 TL |
1107 | /* Skip udelay() the first time around */ |
1108 | if (count++) { | |
1109 | if (count == LOOP_TIMEOUT) { | |
101fa037 | 1110 | pr_err("Command buffer timeout\n"); |
23e967e1 TL |
1111 | return -EIO; |
1112 | } | |
da49f6df | 1113 | |
23e967e1 TL |
1114 | udelay(1); |
1115 | } | |
ac0ea6e9 | 1116 | |
23e967e1 TL |
1117 | /* Update head and recheck remaining space */ |
1118 | iommu->cmd_buf_head = readl(iommu->mmio_base + | |
1119 | MMIO_CMD_HEAD_OFFSET); | |
ac0ea6e9 JR |
1120 | |
1121 | goto again; | |
8d201968 JR |
1122 | } |
1123 | ||
d334a563 | 1124 | copy_cmd_to_buffer(iommu, cmd); |
ac0ea6e9 | 1125 | |
23e967e1 | 1126 | /* Do we need to make sure all commands are processed? */ |
f1ca1512 | 1127 | iommu->need_sync = sync; |
ac0ea6e9 | 1128 | |
4bf5beef JR |
1129 | return 0; |
1130 | } | |
1131 | ||
1132 | static int iommu_queue_command_sync(struct amd_iommu *iommu, | |
1133 | struct iommu_cmd *cmd, | |
1134 | bool sync) | |
1135 | { | |
1136 | unsigned long flags; | |
1137 | int ret; | |
1138 | ||
27790398 | 1139 | raw_spin_lock_irqsave(&iommu->lock, flags); |
4bf5beef | 1140 | ret = __iommu_queue_command_sync(iommu, cmd, sync); |
27790398 | 1141 | raw_spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1142 | |
4bf5beef | 1143 | return ret; |
8d201968 JR |
1144 | } |
1145 | ||
f1ca1512 JR |
1146 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1147 | { | |
1148 | return iommu_queue_command_sync(iommu, cmd, true); | |
1149 | } | |
1150 | ||
8d201968 JR |
1151 | /* |
1152 | * This function queues a completion wait command into the command | |
1153 | * buffer of an IOMMU | |
1154 | */ | |
a19ae1ec | 1155 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1156 | { |
1157 | struct iommu_cmd cmd; | |
4bf5beef | 1158 | unsigned long flags; |
ac0ea6e9 | 1159 | int ret; |
c69d89af | 1160 | u64 data; |
8d201968 | 1161 | |
09ee17eb | 1162 | if (!iommu->need_sync) |
815b33fd | 1163 | return 0; |
09ee17eb | 1164 | |
27790398 | 1165 | raw_spin_lock_irqsave(&iommu->lock, flags); |
4bf5beef | 1166 | |
c69d89af SS |
1167 | data = ++iommu->cmd_sem_val; |
1168 | build_completion_wait(&cmd, iommu, data); | |
4bf5beef JR |
1169 | |
1170 | ret = __iommu_queue_command_sync(iommu, &cmd, false); | |
a19ae1ec | 1171 | if (ret) |
4bf5beef JR |
1172 | goto out_unlock; |
1173 | ||
c69d89af | 1174 | ret = wait_on_sem(iommu, data); |
4bf5beef JR |
1175 | |
1176 | out_unlock: | |
27790398 | 1177 | raw_spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1178 | |
4bf5beef | 1179 | return ret; |
8d201968 JR |
1180 | } |
1181 | ||
d8c13085 | 1182 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1183 | { |
d8c13085 | 1184 | struct iommu_cmd cmd; |
a19ae1ec | 1185 | |
d8c13085 | 1186 | build_inv_dte(&cmd, devid); |
7e4f88da | 1187 | |
d8c13085 JR |
1188 | return iommu_queue_command(iommu, &cmd); |
1189 | } | |
09ee17eb | 1190 | |
0688a099 | 1191 | static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) |
7d0c5cc5 JR |
1192 | { |
1193 | u32 devid; | |
a3cf6ab3 | 1194 | u16 last_bdf = iommu->pci_seg->last_bdf; |
09ee17eb | 1195 | |
a3cf6ab3 | 1196 | for (devid = 0; devid <= last_bdf; ++devid) |
7d0c5cc5 | 1197 | iommu_flush_dte(iommu, devid); |
a19ae1ec | 1198 | |
7d0c5cc5 JR |
1199 | iommu_completion_wait(iommu); |
1200 | } | |
84df8175 | 1201 | |
7d0c5cc5 JR |
1202 | /* |
1203 | * This function uses heavy locking and may disable irqs for some time. But | |
1204 | * this is no issue because it is only called during resume. | |
1205 | */ | |
0688a099 | 1206 | static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu) |
7d0c5cc5 JR |
1207 | { |
1208 | u32 dom_id; | |
a3cf6ab3 | 1209 | u16 last_bdf = iommu->pci_seg->last_bdf; |
a19ae1ec | 1210 | |
a3cf6ab3 | 1211 | for (dom_id = 0; dom_id <= last_bdf; ++dom_id) { |
7d0c5cc5 JR |
1212 | struct iommu_cmd cmd; |
1213 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1214 | dom_id, 1); | |
1215 | iommu_queue_command(iommu, &cmd); | |
1216 | } | |
8eed9833 | 1217 | |
7d0c5cc5 | 1218 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1219 | } |
1220 | ||
36b7200f SH |
1221 | static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id) |
1222 | { | |
1223 | struct iommu_cmd cmd; | |
1224 | ||
1225 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1226 | dom_id, 1); | |
1227 | iommu_queue_command(iommu, &cmd); | |
1228 | ||
1229 | iommu_completion_wait(iommu); | |
1230 | } | |
1231 | ||
0688a099 | 1232 | static void amd_iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1233 | { |
58fc7f14 | 1234 | struct iommu_cmd cmd; |
0518a3a4 | 1235 | |
58fc7f14 | 1236 | build_inv_all(&cmd); |
0518a3a4 | 1237 | |
58fc7f14 JR |
1238 | iommu_queue_command(iommu, &cmd); |
1239 | iommu_completion_wait(iommu); | |
1240 | } | |
1241 | ||
7ef2798d JR |
1242 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1243 | { | |
1244 | struct iommu_cmd cmd; | |
1245 | ||
1246 | build_inv_irt(&cmd, devid); | |
1247 | ||
1248 | iommu_queue_command(iommu, &cmd); | |
1249 | } | |
1250 | ||
0688a099 | 1251 | static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) |
7ef2798d JR |
1252 | { |
1253 | u32 devid; | |
a3cf6ab3 | 1254 | u16 last_bdf = iommu->pci_seg->last_bdf; |
7ef2798d | 1255 | |
a3cf6ab3 | 1256 | for (devid = 0; devid <= last_bdf; devid++) |
7ef2798d JR |
1257 | iommu_flush_irt(iommu, devid); |
1258 | ||
1259 | iommu_completion_wait(iommu); | |
1260 | } | |
1261 | ||
7d0c5cc5 JR |
1262 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1263 | { | |
58fc7f14 | 1264 | if (iommu_feature(iommu, FEATURE_IA)) { |
0688a099 | 1265 | amd_iommu_flush_all(iommu); |
58fc7f14 | 1266 | } else { |
0688a099 JR |
1267 | amd_iommu_flush_dte_all(iommu); |
1268 | amd_iommu_flush_irt_all(iommu); | |
1269 | amd_iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
1270 | } |
1271 | } | |
1272 | ||
431b2a20 | 1273 | /* |
cb41ed85 | 1274 | * Command send function for flushing on-device TLB |
431b2a20 | 1275 | */ |
6c542047 JR |
1276 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1277 | u64 address, size_t size) | |
3fa43655 JR |
1278 | { |
1279 | struct amd_iommu *iommu; | |
b00d3bcf | 1280 | struct iommu_cmd cmd; |
cb41ed85 | 1281 | int qdep; |
3fa43655 | 1282 | |
ea61cddb | 1283 | qdep = dev_data->ats.qdep; |
8b71c9bf SS |
1284 | iommu = rlookup_amd_iommu(dev_data->dev); |
1285 | if (!iommu) | |
1286 | return -EINVAL; | |
3fa43655 | 1287 | |
ea61cddb | 1288 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1289 | |
1290 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1291 | } |
1292 | ||
3332364e LG |
1293 | static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data) |
1294 | { | |
1295 | struct amd_iommu *iommu = data; | |
1296 | ||
1297 | return iommu_flush_dte(iommu, alias); | |
1298 | } | |
1299 | ||
431b2a20 | 1300 | /* |
431b2a20 | 1301 | * Command send function for invalidating a device table entry |
431b2a20 | 1302 | */ |
6c542047 | 1303 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1304 | { |
3fa43655 | 1305 | struct amd_iommu *iommu; |
d02674d7 | 1306 | struct pci_dev *pdev = NULL; |
99fc4ac3 | 1307 | struct amd_iommu_pci_seg *pci_seg; |
e25bfb56 | 1308 | u16 alias; |
ee2fa743 | 1309 | int ret; |
a19ae1ec | 1310 | |
8b71c9bf SS |
1311 | iommu = rlookup_amd_iommu(dev_data->dev); |
1312 | if (!iommu) | |
1313 | return -EINVAL; | |
a19ae1ec | 1314 | |
d02674d7 VH |
1315 | if (dev_is_pci(dev_data->dev)) |
1316 | pdev = to_pci_dev(dev_data->dev); | |
1317 | ||
1318 | if (pdev) | |
1319 | ret = pci_for_each_dma_alias(pdev, | |
3332364e LG |
1320 | device_flush_dte_alias, iommu); |
1321 | else | |
1322 | ret = iommu_flush_dte(iommu, dev_data->devid); | |
cb41ed85 JR |
1323 | if (ret) |
1324 | return ret; | |
1325 | ||
99fc4ac3 SS |
1326 | pci_seg = iommu->pci_seg; |
1327 | alias = pci_seg->alias_table[dev_data->devid]; | |
3332364e LG |
1328 | if (alias != dev_data->devid) { |
1329 | ret = iommu_flush_dte(iommu, alias); | |
1330 | if (ret) | |
1331 | return ret; | |
1332 | } | |
1333 | ||
ea61cddb | 1334 | if (dev_data->ats.enabled) |
6c542047 | 1335 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1336 | |
ee2fa743 | 1337 | return ret; |
a19ae1ec JR |
1338 | } |
1339 | ||
431b2a20 JR |
1340 | /* |
1341 | * TLB invalidation function which is called from the mapping functions. | |
1342 | * It invalidates a single PTE if the range to flush is within a single | |
1343 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1344 | */ | |
17b124bf JR |
1345 | static void __domain_flush_pages(struct protection_domain *domain, |
1346 | u64 address, size_t size, int pde) | |
a19ae1ec | 1347 | { |
cb41ed85 | 1348 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1349 | struct iommu_cmd cmd; |
1350 | int ret = 0, i; | |
a19ae1ec | 1351 | |
11b6402c | 1352 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1353 | |
6b9376e3 | 1354 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
6de8ad9b JR |
1355 | if (!domain->dev_iommu[i]) |
1356 | continue; | |
1357 | ||
1358 | /* | |
1359 | * Devices of this domain are behind this IOMMU | |
1360 | * We need a TLB flush | |
1361 | */ | |
11b6402c | 1362 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1363 | } |
1364 | ||
cb41ed85 | 1365 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1366 | |
ea61cddb | 1367 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1368 | continue; |
1369 | ||
6c542047 | 1370 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1371 | } |
1372 | ||
11b6402c | 1373 | WARN_ON(ret); |
6de8ad9b JR |
1374 | } |
1375 | ||
17b124bf | 1376 | static void domain_flush_pages(struct protection_domain *domain, |
a270be1b | 1377 | u64 address, size_t size, int pde) |
6de8ad9b | 1378 | { |
a270be1b NA |
1379 | if (likely(!amd_iommu_np_cache)) { |
1380 | __domain_flush_pages(domain, address, size, pde); | |
1381 | return; | |
1382 | } | |
1383 | ||
1384 | /* | |
1385 | * When NpCache is on, we infer that we run in a VM and use a vIOMMU. | |
1386 | * In such setups it is best to avoid flushes of ranges which are not | |
1387 | * naturally aligned, since it would lead to flushes of unmodified | |
1388 | * PTEs. Such flushes would require the hypervisor to do more work than | |
1389 | * necessary. Therefore, perform repeated flushes of aligned ranges | |
1390 | * until you cover the range. Each iteration flushes the smaller | |
1391 | * between the natural alignment of the address that we flush and the | |
1392 | * greatest naturally aligned region that fits in the range. | |
1393 | */ | |
1394 | while (size != 0) { | |
1395 | int addr_alignment = __ffs(address); | |
1396 | int size_alignment = __fls(size); | |
1397 | int min_alignment; | |
1398 | size_t flush_size; | |
1399 | ||
1400 | /* | |
1401 | * size is always non-zero, but address might be zero, causing | |
1402 | * addr_alignment to be negative. As the casting of the | |
1403 | * argument in __ffs(address) to long might trim the high bits | |
1404 | * of the address on x86-32, cast to long when doing the check. | |
1405 | */ | |
1406 | if (likely((unsigned long)address != 0)) | |
1407 | min_alignment = min(addr_alignment, size_alignment); | |
1408 | else | |
1409 | min_alignment = size_alignment; | |
1410 | ||
1411 | flush_size = 1ul << min_alignment; | |
1412 | ||
1413 | __domain_flush_pages(domain, address, flush_size, pde); | |
1414 | address += flush_size; | |
1415 | size -= flush_size; | |
1416 | } | |
a19ae1ec | 1417 | } |
b6c02715 | 1418 | |
42a49f96 | 1419 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
f9b4df79 | 1420 | void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1421 | { |
a270be1b | 1422 | domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1423 | } |
1424 | ||
f9b4df79 | 1425 | void amd_iommu_domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1426 | { |
17b124bf | 1427 | int i; |
18811f55 | 1428 | |
6b9376e3 | 1429 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
f1eae7c5 | 1430 | if (domain && !domain->dev_iommu[i]) |
17b124bf | 1431 | continue; |
bfd1be18 | 1432 | |
17b124bf JR |
1433 | /* |
1434 | * Devices of this domain are behind this IOMMU | |
1435 | * We need to wait for completion of all commands. | |
1436 | */ | |
1437 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1438 | } |
e394d72a JR |
1439 | } |
1440 | ||
5cd3f2e9 TM |
1441 | /* Flush the not present cache if it exists */ |
1442 | static void domain_flush_np_cache(struct protection_domain *domain, | |
1443 | dma_addr_t iova, size_t size) | |
1444 | { | |
1445 | if (unlikely(amd_iommu_np_cache)) { | |
2a78f996 JR |
1446 | unsigned long flags; |
1447 | ||
1448 | spin_lock_irqsave(&domain->lock, flags); | |
a270be1b | 1449 | domain_flush_pages(domain, iova, size, 1); |
f9b4df79 | 1450 | amd_iommu_domain_flush_complete(domain); |
2a78f996 | 1451 | spin_unlock_irqrestore(&domain->lock, flags); |
5cd3f2e9 TM |
1452 | } |
1453 | } | |
1454 | ||
b00d3bcf | 1455 | |
09b42804 | 1456 | /* |
b00d3bcf | 1457 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1458 | */ |
17b124bf | 1459 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1460 | { |
b00d3bcf | 1461 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1462 | |
b00d3bcf | 1463 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1464 | device_flush_dte(dev_data); |
a345b23b JR |
1465 | } |
1466 | ||
431b2a20 JR |
1467 | /**************************************************************************** |
1468 | * | |
1469 | * The next functions belong to the domain allocation. A domain is | |
1470 | * allocated for every IOMMU as the default domain. If device isolation | |
1471 | * is enabled, every device get its own domain. The most important thing | |
1472 | * about domains is the page table mapping the DMA address space they | |
1473 | * contain. | |
1474 | * | |
1475 | ****************************************************************************/ | |
1476 | ||
ec487d1a JR |
1477 | static u16 domain_id_alloc(void) |
1478 | { | |
ec487d1a JR |
1479 | int id; |
1480 | ||
2bc00180 | 1481 | spin_lock(&pd_bitmap_lock); |
ec487d1a JR |
1482 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); |
1483 | BUG_ON(id == 0); | |
1484 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1485 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1486 | else | |
1487 | id = 0; | |
2bc00180 | 1488 | spin_unlock(&pd_bitmap_lock); |
ec487d1a JR |
1489 | |
1490 | return id; | |
1491 | } | |
1492 | ||
a2acfb75 JR |
1493 | static void domain_id_free(int id) |
1494 | { | |
2bc00180 | 1495 | spin_lock(&pd_bitmap_lock); |
a2acfb75 JR |
1496 | if (id > 0 && id < MAX_DOMAIN_ID) |
1497 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
2bc00180 | 1498 | spin_unlock(&pd_bitmap_lock); |
a2acfb75 | 1499 | } |
a2acfb75 | 1500 | |
b16137b1 JR |
1501 | static void free_gcr3_tbl_level1(u64 *tbl) |
1502 | { | |
1503 | u64 *ptr; | |
1504 | int i; | |
1505 | ||
1506 | for (i = 0; i < 512; ++i) { | |
1507 | if (!(tbl[i] & GCR3_VALID)) | |
1508 | continue; | |
1509 | ||
2543a786 | 1510 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
b16137b1 JR |
1511 | |
1512 | free_page((unsigned long)ptr); | |
1513 | } | |
1514 | } | |
1515 | ||
1516 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1517 | { | |
1518 | u64 *ptr; | |
1519 | int i; | |
1520 | ||
1521 | for (i = 0; i < 512; ++i) { | |
1522 | if (!(tbl[i] & GCR3_VALID)) | |
1523 | continue; | |
1524 | ||
2543a786 | 1525 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
b16137b1 JR |
1526 | |
1527 | free_gcr3_tbl_level1(ptr); | |
1528 | } | |
1529 | } | |
1530 | ||
52815b75 JR |
1531 | static void free_gcr3_table(struct protection_domain *domain) |
1532 | { | |
b16137b1 JR |
1533 | if (domain->glx == 2) |
1534 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1535 | else if (domain->glx == 1) | |
1536 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1537 | else |
1538 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1539 | |
52815b75 JR |
1540 | free_page((unsigned long)domain->gcr3_tbl); |
1541 | } | |
1542 | ||
8b71c9bf SS |
1543 | static void set_dte_entry(struct amd_iommu *iommu, u16 devid, |
1544 | struct protection_domain *domain, bool ats, bool ppr) | |
b20ac0d4 | 1545 | { |
132bd68f | 1546 | u64 pte_root = 0; |
ee6c2868 | 1547 | u64 flags = 0; |
36b7200f | 1548 | u32 old_domid; |
54625ef1 | 1549 | struct dev_table_entry *dev_table = get_dev_table(iommu); |
863c74eb | 1550 | |
1f585530 SS |
1551 | if (domain->iop.mode != PAGE_MODE_NONE) |
1552 | pte_root = iommu_virt_to_phys(domain->iop.root); | |
eb791aa7 | 1553 | |
1f585530 | 1554 | pte_root |= (domain->iop.mode & DEV_ENTRY_MODE_MASK) |
38ddf41b | 1555 | << DEV_ENTRY_MODE_SHIFT; |
b20ac0d4 | 1556 | |
b9f0043e SS |
1557 | pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V; |
1558 | ||
1559 | /* | |
1560 | * When SNP is enabled, Only set TV bit when IOMMU | |
1561 | * page translation is in use. | |
1562 | */ | |
1563 | if (!amd_iommu_snp_en || (domain->id != 0)) | |
1564 | pte_root |= DTE_FLAG_TV; | |
b20ac0d4 | 1565 | |
54625ef1 | 1566 | flags = dev_table[devid].data[1]; |
ee6c2868 | 1567 | |
fd7b5535 JR |
1568 | if (ats) |
1569 | flags |= DTE_FLAG_IOTLB; | |
1570 | ||
ff18c4e5 | 1571 | if (ppr) { |
ff18c4e5 GH |
1572 | if (iommu_feature(iommu, FEATURE_EPHSUP)) |
1573 | pte_root |= 1ULL << DEV_ENTRY_PPR; | |
1574 | } | |
1575 | ||
52815b75 | 1576 | if (domain->flags & PD_IOMMUV2_MASK) { |
2543a786 | 1577 | u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); |
52815b75 JR |
1578 | u64 glx = domain->glx; |
1579 | u64 tmp; | |
1580 | ||
1581 | pte_root |= DTE_FLAG_GV; | |
1582 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1583 | ||
1584 | /* First mask out possible old values for GCR3 table */ | |
1585 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1586 | flags &= ~tmp; | |
1587 | ||
1588 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1589 | flags &= ~tmp; | |
1590 | ||
1591 | /* Encode GCR3 table into DTE */ | |
1592 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1593 | pte_root |= tmp; | |
1594 | ||
1595 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1596 | flags |= tmp; | |
1597 | ||
1598 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1599 | flags |= tmp; | |
1600 | } | |
1601 | ||
45a01c42 | 1602 | flags &= ~DEV_DOMID_MASK; |
ee6c2868 JR |
1603 | flags |= domain->id; |
1604 | ||
54625ef1 SS |
1605 | old_domid = dev_table[devid].data[1] & DEV_DOMID_MASK; |
1606 | dev_table[devid].data[1] = flags; | |
1607 | dev_table[devid].data[0] = pte_root; | |
36b7200f SH |
1608 | |
1609 | /* | |
1610 | * A kdump kernel might be replacing a domain ID that was copied from | |
1611 | * the previous kernel--if so, it needs to flush the translation cache | |
1612 | * entries for the old domain ID that is being overwritten | |
1613 | */ | |
1614 | if (old_domid) { | |
36b7200f SH |
1615 | amd_iommu_flush_tlb_domid(iommu, old_domid); |
1616 | } | |
15898bbc JR |
1617 | } |
1618 | ||
54625ef1 | 1619 | static void clear_dte_entry(struct amd_iommu *iommu, u16 devid) |
15898bbc | 1620 | { |
54625ef1 SS |
1621 | struct dev_table_entry *dev_table = get_dev_table(iommu); |
1622 | ||
15898bbc | 1623 | /* remove entry from the device table seen by the hardware */ |
b9f0043e SS |
1624 | dev_table[devid].data[0] = DTE_FLAG_V; |
1625 | ||
1626 | if (!amd_iommu_snp_en) | |
1627 | dev_table[devid].data[0] |= DTE_FLAG_TV; | |
1628 | ||
54625ef1 | 1629 | dev_table[devid].data[1] &= DTE_FLAG_MASK; |
15898bbc | 1630 | |
56fb7951 | 1631 | amd_iommu_apply_erratum_63(iommu, devid); |
7f760ddd JR |
1632 | } |
1633 | ||
ec9e79ef JR |
1634 | static void do_attach(struct iommu_dev_data *dev_data, |
1635 | struct protection_domain *domain) | |
7f760ddd | 1636 | { |
7f760ddd | 1637 | struct amd_iommu *iommu; |
ec9e79ef | 1638 | bool ats; |
fd7b5535 | 1639 | |
8b71c9bf SS |
1640 | iommu = rlookup_amd_iommu(dev_data->dev); |
1641 | if (!iommu) | |
1642 | return; | |
ec9e79ef | 1643 | ats = dev_data->ats.enabled; |
7f760ddd JR |
1644 | |
1645 | /* Update data structures */ | |
1646 | dev_data->domain = domain; | |
1647 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
1648 | |
1649 | /* Do reference counting */ | |
1650 | domain->dev_iommu[iommu->index] += 1; | |
1651 | domain->dev_cnt += 1; | |
1652 | ||
e25bfb56 | 1653 | /* Update device table */ |
8b71c9bf | 1654 | set_dte_entry(iommu, dev_data->devid, domain, |
19c6978f | 1655 | ats, dev_data->iommu_v2); |
99fc4ac3 | 1656 | clone_aliases(iommu, dev_data->dev); |
e25bfb56 | 1657 | |
6c542047 | 1658 | device_flush_dte(dev_data); |
7f760ddd JR |
1659 | } |
1660 | ||
ec9e79ef | 1661 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1662 | { |
9825bd94 | 1663 | struct protection_domain *domain = dev_data->domain; |
7f760ddd | 1664 | struct amd_iommu *iommu; |
7f760ddd | 1665 | |
8b71c9bf SS |
1666 | iommu = rlookup_amd_iommu(dev_data->dev); |
1667 | if (!iommu) | |
1668 | return; | |
15898bbc | 1669 | |
7f760ddd JR |
1670 | /* Update data structures */ |
1671 | dev_data->domain = NULL; | |
1672 | list_del(&dev_data->list); | |
54625ef1 | 1673 | clear_dte_entry(iommu, dev_data->devid); |
99fc4ac3 | 1674 | clone_aliases(iommu, dev_data->dev); |
15898bbc | 1675 | |
7f760ddd | 1676 | /* Flush the DTE entry */ |
6c542047 | 1677 | device_flush_dte(dev_data); |
9825bd94 SS |
1678 | |
1679 | /* Flush IOTLB */ | |
f9b4df79 | 1680 | amd_iommu_domain_flush_tlb_pde(domain); |
9825bd94 SS |
1681 | |
1682 | /* Wait for the flushes to finish */ | |
f9b4df79 | 1683 | amd_iommu_domain_flush_complete(domain); |
9825bd94 SS |
1684 | |
1685 | /* decrease reference counters - needs to happen after the flushes */ | |
1686 | domain->dev_iommu[iommu->index] -= 1; | |
1687 | domain->dev_cnt -= 1; | |
2b681faf JR |
1688 | } |
1689 | ||
52815b75 JR |
1690 | static void pdev_iommuv2_disable(struct pci_dev *pdev) |
1691 | { | |
1692 | pci_disable_ats(pdev); | |
1693 | pci_disable_pri(pdev); | |
1694 | pci_disable_pasid(pdev); | |
1695 | } | |
1696 | ||
1697 | static int pdev_iommuv2_enable(struct pci_dev *pdev) | |
1698 | { | |
d151c85c | 1699 | int ret; |
52815b75 JR |
1700 | |
1701 | /* Only allow access to user-accessible pages */ | |
1702 | ret = pci_enable_pasid(pdev, 0); | |
1703 | if (ret) | |
1704 | goto out_err; | |
1705 | ||
1706 | /* First reset the PRI state of the device */ | |
1707 | ret = pci_reset_pri(pdev); | |
1708 | if (ret) | |
1709 | goto out_err; | |
1710 | ||
6a113ddc | 1711 | /* Enable PRI */ |
d151c85c CH |
1712 | /* FIXME: Hardcode number of outstanding requests for now */ |
1713 | ret = pci_enable_pri(pdev, 32); | |
52815b75 JR |
1714 | if (ret) |
1715 | goto out_err; | |
1716 | ||
1717 | ret = pci_enable_ats(pdev, PAGE_SHIFT); | |
1718 | if (ret) | |
1719 | goto out_err; | |
1720 | ||
1721 | return 0; | |
1722 | ||
1723 | out_err: | |
1724 | pci_disable_pri(pdev); | |
1725 | pci_disable_pasid(pdev); | |
1726 | ||
1727 | return ret; | |
1728 | } | |
1729 | ||
407d733e | 1730 | /* |
29a0c415 AMG |
1731 | * If a device is not yet associated with a domain, this function makes the |
1732 | * device visible in the domain | |
407d733e | 1733 | */ |
15898bbc JR |
1734 | static int attach_device(struct device *dev, |
1735 | struct protection_domain *domain) | |
0feae533 | 1736 | { |
ea61cddb | 1737 | struct iommu_dev_data *dev_data; |
57f9842e | 1738 | struct pci_dev *pdev; |
eba6ac60 | 1739 | unsigned long flags; |
15898bbc | 1740 | int ret; |
eba6ac60 | 1741 | |
f6c0bfce JR |
1742 | spin_lock_irqsave(&domain->lock, flags); |
1743 | ||
05a0542b | 1744 | dev_data = dev_iommu_priv_get(dev); |
ea61cddb | 1745 | |
ab7b2577 JR |
1746 | spin_lock(&dev_data->lock); |
1747 | ||
45e528d9 JR |
1748 | ret = -EBUSY; |
1749 | if (dev_data->domain != NULL) | |
1750 | goto out; | |
1751 | ||
2bf9a0a1 WZ |
1752 | if (!dev_is_pci(dev)) |
1753 | goto skip_ats_check; | |
1754 | ||
1755 | pdev = to_pci_dev(dev); | |
52815b75 | 1756 | if (domain->flags & PD_IOMMUV2_MASK) { |
57f9842e JR |
1757 | struct iommu_domain *def_domain = iommu_get_dma_domain(dev); |
1758 | ||
f6c0bfce | 1759 | ret = -EINVAL; |
57f9842e | 1760 | if (def_domain->type != IOMMU_DOMAIN_IDENTITY) |
f6c0bfce | 1761 | goto out; |
52815b75 | 1762 | |
02ca2021 JR |
1763 | if (dev_data->iommu_v2) { |
1764 | if (pdev_iommuv2_enable(pdev) != 0) | |
f6c0bfce | 1765 | goto out; |
52815b75 | 1766 | |
02ca2021 JR |
1767 | dev_data->ats.enabled = true; |
1768 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
83d18bdf | 1769 | dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev); |
02ca2021 | 1770 | } |
52815b75 JR |
1771 | } else if (amd_iommu_iotlb_sup && |
1772 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
1773 | dev_data->ats.enabled = true; |
1774 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
1775 | } | |
fd7b5535 | 1776 | |
2bf9a0a1 | 1777 | skip_ats_check: |
45e528d9 JR |
1778 | ret = 0; |
1779 | ||
1780 | do_attach(dev_data, domain); | |
b20ac0d4 | 1781 | |
0feae533 JR |
1782 | /* |
1783 | * We might boot into a crash-kernel here. The crashed kernel | |
1784 | * left the caches in the IOMMU dirty. So we have to flush | |
1785 | * here to evict all dirty stuff. | |
1786 | */ | |
f9b4df79 | 1787 | amd_iommu_domain_flush_tlb_pde(domain); |
15898bbc | 1788 | |
f9b4df79 | 1789 | amd_iommu_domain_flush_complete(domain); |
71f77580 | 1790 | |
f6c0bfce | 1791 | out: |
ab7b2577 | 1792 | spin_unlock(&dev_data->lock); |
24100055 | 1793 | |
3a11905b | 1794 | spin_unlock_irqrestore(&domain->lock, flags); |
7f760ddd | 1795 | |
f6c0bfce | 1796 | return ret; |
355bf553 JR |
1797 | } |
1798 | ||
1799 | /* | |
1800 | * Removes a device from a protection domain (with devtable_lock held) | |
1801 | */ | |
15898bbc | 1802 | static void detach_device(struct device *dev) |
355bf553 | 1803 | { |
52815b75 | 1804 | struct protection_domain *domain; |
ea61cddb | 1805 | struct iommu_dev_data *dev_data; |
355bf553 JR |
1806 | unsigned long flags; |
1807 | ||
05a0542b | 1808 | dev_data = dev_iommu_priv_get(dev); |
52815b75 | 1809 | domain = dev_data->domain; |
ec9e79ef | 1810 | |
f6c0bfce JR |
1811 | spin_lock_irqsave(&domain->lock, flags); |
1812 | ||
ab7b2577 JR |
1813 | spin_lock(&dev_data->lock); |
1814 | ||
ea3fd040 AMG |
1815 | /* |
1816 | * First check if the device is still attached. It might already | |
1817 | * be detached from its domain because the generic | |
1818 | * iommu_detach_group code detached it and we try again here in | |
1819 | * our alias handling. | |
1820 | */ | |
1821 | if (WARN_ON(!dev_data->domain)) | |
f6c0bfce | 1822 | goto out; |
ea3fd040 | 1823 | |
f6c0bfce | 1824 | do_detach(dev_data); |
fd7b5535 | 1825 | |
2bf9a0a1 | 1826 | if (!dev_is_pci(dev)) |
f6c0bfce | 1827 | goto out; |
2bf9a0a1 | 1828 | |
02ca2021 | 1829 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
1830 | pdev_iommuv2_disable(to_pci_dev(dev)); |
1831 | else if (dev_data->ats.enabled) | |
ea61cddb | 1832 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
1833 | |
1834 | dev_data->ats.enabled = false; | |
f6c0bfce JR |
1835 | |
1836 | out: | |
ab7b2577 JR |
1837 | spin_unlock(&dev_data->lock); |
1838 | ||
f6c0bfce | 1839 | spin_unlock_irqrestore(&domain->lock, flags); |
355bf553 | 1840 | } |
e275a2a0 | 1841 | |
dce8d696 | 1842 | static struct iommu_device *amd_iommu_probe_device(struct device *dev) |
e275a2a0 | 1843 | { |
dce8d696 | 1844 | struct iommu_device *iommu_dev; |
e275a2a0 | 1845 | struct amd_iommu *iommu; |
8b71c9bf | 1846 | int ret; |
e275a2a0 | 1847 | |
57bd2c24 | 1848 | if (!check_device(dev)) |
dce8d696 | 1849 | return ERR_PTR(-ENODEV); |
e275a2a0 | 1850 | |
8b71c9bf SS |
1851 | iommu = rlookup_amd_iommu(dev); |
1852 | if (!iommu) | |
1853 | return ERR_PTR(-ENODEV); | |
657cbb6b | 1854 | |
05a0542b | 1855 | if (dev_iommu_priv_get(dev)) |
dce8d696 JR |
1856 | return &iommu->iommu; |
1857 | ||
99fc4ac3 | 1858 | ret = iommu_init_device(iommu, dev); |
4d58b8a6 JR |
1859 | if (ret) { |
1860 | if (ret != -ENOTSUPP) | |
5f226da1 | 1861 | dev_err(dev, "Failed to initialize - trying to proceed anyway\n"); |
dce8d696 | 1862 | iommu_dev = ERR_PTR(ret); |
99fc4ac3 | 1863 | iommu_ignore_device(iommu, dev); |
dce8d696 | 1864 | } else { |
2b2c6aa6 | 1865 | amd_iommu_set_pci_msi_domain(dev, iommu); |
dce8d696 | 1866 | iommu_dev = &iommu->iommu; |
aafd8ba0 | 1867 | } |
2c9195e9 | 1868 | |
dce8d696 | 1869 | iommu_completion_wait(iommu); |
2c9195e9 | 1870 | |
dce8d696 JR |
1871 | return iommu_dev; |
1872 | } | |
657cbb6b | 1873 | |
dce8d696 JR |
1874 | static void amd_iommu_probe_finalize(struct device *dev) |
1875 | { | |
07ee8694 | 1876 | /* Domains are initialized for this device - have a look what we ended up with */ |
6d596039 RM |
1877 | set_dma_ops(dev, NULL); |
1878 | iommu_setup_dma_ops(dev, 0, U64_MAX); | |
e275a2a0 JR |
1879 | } |
1880 | ||
dce8d696 | 1881 | static void amd_iommu_release_device(struct device *dev) |
8638c491 | 1882 | { |
aafd8ba0 | 1883 | struct amd_iommu *iommu; |
aafd8ba0 JR |
1884 | |
1885 | if (!check_device(dev)) | |
1886 | return; | |
1887 | ||
8b71c9bf SS |
1888 | iommu = rlookup_amd_iommu(dev); |
1889 | if (!iommu) | |
1890 | return; | |
aafd8ba0 | 1891 | |
dce8d696 | 1892 | amd_iommu_uninit_device(dev); |
aafd8ba0 | 1893 | iommu_completion_wait(iommu); |
8638c491 JR |
1894 | } |
1895 | ||
b097d11a WZ |
1896 | static struct iommu_group *amd_iommu_device_group(struct device *dev) |
1897 | { | |
1898 | if (dev_is_pci(dev)) | |
1899 | return pci_device_group(dev); | |
1900 | ||
1901 | return acpihid_device_group(dev); | |
1902 | } | |
1903 | ||
431b2a20 JR |
1904 | /***************************************************************************** |
1905 | * | |
1906 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1907 | * | |
1908 | *****************************************************************************/ | |
1909 | ||
1f585530 | 1910 | static void update_device_table(struct protection_domain *domain) |
04bfdd84 | 1911 | { |
492667da | 1912 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1913 | |
3254de6b | 1914 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
99fc4ac3 SS |
1915 | struct amd_iommu *iommu = rlookup_amd_iommu(dev_data->dev); |
1916 | ||
1917 | if (!iommu) | |
1918 | continue; | |
8b71c9bf | 1919 | set_dte_entry(iommu, dev_data->devid, domain, |
19c6978f | 1920 | dev_data->ats.enabled, dev_data->iommu_v2); |
99fc4ac3 | 1921 | clone_aliases(iommu, dev_data->dev); |
3254de6b | 1922 | } |
04bfdd84 JR |
1923 | } |
1924 | ||
1f585530 | 1925 | void amd_iommu_update_and_flush_device_table(struct protection_domain *domain) |
19c6978f | 1926 | { |
1f585530 | 1927 | update_device_table(domain); |
19c6978f JR |
1928 | domain_flush_devices(domain); |
1929 | } | |
1930 | ||
f9b4df79 | 1931 | void amd_iommu_domain_update(struct protection_domain *domain) |
04bfdd84 | 1932 | { |
19c6978f | 1933 | /* Update device table */ |
1f585530 | 1934 | amd_iommu_update_and_flush_device_table(domain); |
19c6978f JR |
1935 | |
1936 | /* Flush domain TLB(s) and wait for completion */ | |
f9b4df79 SS |
1937 | amd_iommu_domain_flush_tlb_pde(domain); |
1938 | amd_iommu_domain_flush_complete(domain); | |
04bfdd84 JR |
1939 | } |
1940 | ||
3a18404c | 1941 | int __init amd_iommu_init_api(void) |
27c2127a | 1942 | { |
340ec061 | 1943 | int err; |
307d5851 | 1944 | |
9a4d3bf5 WZ |
1945 | err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
1946 | if (err) | |
1947 | return err; | |
1948 | #ifdef CONFIG_ARM_AMBA | |
1949 | err = bus_set_iommu(&amba_bustype, &amd_iommu_ops); | |
1950 | if (err) | |
1951 | return err; | |
1952 | #endif | |
0076cd3d WZ |
1953 | err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops); |
1954 | if (err) | |
1955 | return err; | |
c5b5da9c | 1956 | |
460c26d0 | 1957 | return 0; |
f5325094 JR |
1958 | } |
1959 | ||
6d98cd80 JR |
1960 | /***************************************************************************** |
1961 | * | |
1962 | * The following functions belong to the exported interface of AMD IOMMU | |
1963 | * | |
1964 | * This interface allows access to lower level functions of the IOMMU | |
1965 | * like protection domain handling and assignement of devices to domains | |
1966 | * which is not possible with the dma_ops interface. | |
1967 | * | |
1968 | *****************************************************************************/ | |
1969 | ||
6d98cd80 JR |
1970 | static void cleanup_domain(struct protection_domain *domain) |
1971 | { | |
9b29d3c6 | 1972 | struct iommu_dev_data *entry; |
6d98cd80 | 1973 | unsigned long flags; |
6d98cd80 | 1974 | |
f6c0bfce | 1975 | spin_lock_irqsave(&domain->lock, flags); |
6d98cd80 | 1976 | |
9b29d3c6 JR |
1977 | while (!list_empty(&domain->dev_list)) { |
1978 | entry = list_first_entry(&domain->dev_list, | |
1979 | struct iommu_dev_data, list); | |
ea3fd040 | 1980 | BUG_ON(!entry->domain); |
f6c0bfce | 1981 | do_detach(entry); |
492667da | 1982 | } |
6d98cd80 | 1983 | |
f6c0bfce | 1984 | spin_unlock_irqrestore(&domain->lock, flags); |
6d98cd80 JR |
1985 | } |
1986 | ||
2650815f JR |
1987 | static void protection_domain_free(struct protection_domain *domain) |
1988 | { | |
1989 | if (!domain) | |
1990 | return; | |
1991 | ||
1992 | if (domain->id) | |
1993 | domain_id_free(domain->id); | |
1994 | ||
e42ba063 SS |
1995 | if (domain->iop.pgtbl_cfg.tlb) |
1996 | free_io_pgtable_ops(&domain->iop.iop.ops); | |
75b27745 | 1997 | |
2650815f JR |
1998 | kfree(domain); |
1999 | } | |
2000 | ||
89c9a09c | 2001 | static int protection_domain_init_v1(struct protection_domain *domain, int mode) |
7a5a566e | 2002 | { |
70fcd359 | 2003 | u64 *pt_root = NULL; |
a71730e2 JR |
2004 | |
2005 | BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL); | |
2006 | ||
7a5a566e | 2007 | spin_lock_init(&domain->lock); |
7a5a566e JR |
2008 | domain->id = domain_id_alloc(); |
2009 | if (!domain->id) | |
2010 | return -ENOMEM; | |
2011 | INIT_LIST_HEAD(&domain->dev_list); | |
2012 | ||
a71730e2 JR |
2013 | if (mode != PAGE_MODE_NONE) { |
2014 | pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2015 | if (!pt_root) | |
2016 | return -ENOMEM; | |
2017 | } | |
2018 | ||
70fcd359 | 2019 | amd_iommu_domain_set_pgtable(domain, pt_root, mode); |
a71730e2 | 2020 | |
7a5a566e JR |
2021 | return 0; |
2022 | } | |
2023 | ||
89c9a09c | 2024 | static struct protection_domain *protection_domain_alloc(unsigned int type) |
c156e347 | 2025 | { |
89c9a09c | 2026 | struct io_pgtable_ops *pgtbl_ops; |
c156e347 | 2027 | struct protection_domain *domain; |
89c9a09c SS |
2028 | int pgtable = amd_iommu_pgtable; |
2029 | int mode = DEFAULT_PGTABLE_LEVEL; | |
2030 | int ret; | |
c156e347 JR |
2031 | |
2032 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2033 | if (!domain) | |
2650815f | 2034 | return NULL; |
c156e347 | 2035 | |
89c9a09c SS |
2036 | /* |
2037 | * Force IOMMU v1 page table when iommu=pt and | |
2038 | * when allocating domain for pass-through devices. | |
2039 | */ | |
2040 | if (type == IOMMU_DOMAIN_IDENTITY) { | |
2041 | pgtable = AMD_IOMMU_V1; | |
2042 | mode = PAGE_MODE_NONE; | |
2043 | } else if (type == IOMMU_DOMAIN_UNMANAGED) { | |
2044 | pgtable = AMD_IOMMU_V1; | |
2045 | } | |
2046 | ||
2047 | switch (pgtable) { | |
2048 | case AMD_IOMMU_V1: | |
2049 | ret = protection_domain_init_v1(domain, mode); | |
2050 | break; | |
2051 | default: | |
2052 | ret = -EINVAL; | |
2053 | } | |
2054 | ||
2055 | if (ret) | |
2650815f JR |
2056 | goto out_err; |
2057 | ||
89c9a09c SS |
2058 | pgtbl_ops = alloc_io_pgtable_ops(pgtable, &domain->iop.pgtbl_cfg, domain); |
2059 | if (!pgtbl_ops) | |
2060 | goto out_err; | |
2650815f | 2061 | |
89c9a09c | 2062 | return domain; |
2650815f JR |
2063 | out_err: |
2064 | kfree(domain); | |
2650815f JR |
2065 | return NULL; |
2066 | } | |
2067 | ||
3f4b87b9 | 2068 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 2069 | { |
301441a0 | 2070 | struct protection_domain *domain; |
c156e347 | 2071 | |
8388f7df SS |
2072 | /* |
2073 | * Since DTE[Mode]=0 is prohibited on SNP-enabled system, | |
2074 | * default to use IOMMU_DOMAIN_DMA[_FQ]. | |
2075 | */ | |
2076 | if (amd_iommu_snp_en && (type == IOMMU_DOMAIN_IDENTITY)) | |
2077 | return NULL; | |
2078 | ||
89c9a09c | 2079 | domain = protection_domain_alloc(type); |
301441a0 | 2080 | if (!domain) |
0bb6e243 | 2081 | return NULL; |
c156e347 | 2082 | |
301441a0 JR |
2083 | domain->domain.geometry.aperture_start = 0; |
2084 | domain->domain.geometry.aperture_end = ~0ULL; | |
2085 | domain->domain.geometry.force_aperture = true; | |
eb791aa7 | 2086 | |
301441a0 | 2087 | return &domain->domain; |
c156e347 JR |
2088 | } |
2089 | ||
3f4b87b9 | 2090 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 2091 | { |
3f4b87b9 | 2092 | struct protection_domain *domain; |
98383fc3 | 2093 | |
3f4b87b9 JR |
2094 | domain = to_pdomain(dom); |
2095 | ||
98383fc3 JR |
2096 | if (domain->dev_cnt > 0) |
2097 | cleanup_domain(domain); | |
2098 | ||
2099 | BUG_ON(domain->dev_cnt != 0); | |
2100 | ||
cda7005b JR |
2101 | if (!dom) |
2102 | return; | |
98383fc3 | 2103 | |
301441a0 JR |
2104 | if (domain->flags & PD_IOMMUV2_MASK) |
2105 | free_gcr3_table(domain); | |
cda7005b | 2106 | |
301441a0 | 2107 | protection_domain_free(domain); |
98383fc3 JR |
2108 | } |
2109 | ||
684f2888 JR |
2110 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2111 | struct device *dev) | |
2112 | { | |
05a0542b | 2113 | struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); |
684f2888 | 2114 | struct amd_iommu *iommu; |
684f2888 | 2115 | |
98fc5a69 | 2116 | if (!check_device(dev)) |
684f2888 JR |
2117 | return; |
2118 | ||
657cbb6b | 2119 | if (dev_data->domain != NULL) |
15898bbc | 2120 | detach_device(dev); |
684f2888 | 2121 | |
8b71c9bf | 2122 | iommu = rlookup_amd_iommu(dev); |
684f2888 JR |
2123 | if (!iommu) |
2124 | return; | |
2125 | ||
d98de49a SS |
2126 | #ifdef CONFIG_IRQ_REMAP |
2127 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && | |
2128 | (dom->type == IOMMU_DOMAIN_UNMANAGED)) | |
2129 | dev_data->use_vapic = 0; | |
2130 | #endif | |
2131 | ||
684f2888 JR |
2132 | iommu_completion_wait(iommu); |
2133 | } | |
2134 | ||
01106066 JR |
2135 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2136 | struct device *dev) | |
2137 | { | |
3f4b87b9 | 2138 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 2139 | struct iommu_dev_data *dev_data; |
01106066 | 2140 | struct amd_iommu *iommu; |
15898bbc | 2141 | int ret; |
01106066 | 2142 | |
98fc5a69 | 2143 | if (!check_device(dev)) |
01106066 JR |
2144 | return -EINVAL; |
2145 | ||
05a0542b | 2146 | dev_data = dev_iommu_priv_get(dev); |
be62dbf5 | 2147 | dev_data->defer_attach = false; |
657cbb6b | 2148 | |
8b71c9bf | 2149 | iommu = rlookup_amd_iommu(dev); |
01106066 JR |
2150 | if (!iommu) |
2151 | return -EINVAL; | |
2152 | ||
657cbb6b | 2153 | if (dev_data->domain) |
15898bbc | 2154 | detach_device(dev); |
01106066 | 2155 | |
15898bbc | 2156 | ret = attach_device(dev, domain); |
01106066 | 2157 | |
d98de49a SS |
2158 | #ifdef CONFIG_IRQ_REMAP |
2159 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
2160 | if (dom->type == IOMMU_DOMAIN_UNMANAGED) | |
2161 | dev_data->use_vapic = 1; | |
2162 | else | |
2163 | dev_data->use_vapic = 0; | |
2164 | } | |
2165 | #endif | |
2166 | ||
01106066 JR |
2167 | iommu_completion_wait(iommu); |
2168 | ||
15898bbc | 2169 | return ret; |
01106066 JR |
2170 | } |
2171 | ||
3b122a56 NA |
2172 | static void amd_iommu_iotlb_sync_map(struct iommu_domain *dom, |
2173 | unsigned long iova, size_t size) | |
2174 | { | |
2175 | struct protection_domain *domain = to_pdomain(dom); | |
2176 | struct io_pgtable_ops *ops = &domain->iop.iop.ops; | |
2177 | ||
2178 | if (ops->map) | |
2179 | domain_flush_np_cache(domain, iova, size); | |
2180 | } | |
2181 | ||
468e2366 | 2182 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
781ca2de TM |
2183 | phys_addr_t paddr, size_t page_size, int iommu_prot, |
2184 | gfp_t gfp) | |
c6229ca6 | 2185 | { |
3f4b87b9 | 2186 | struct protection_domain *domain = to_pdomain(dom); |
fd86c950 | 2187 | struct io_pgtable_ops *ops = &domain->iop.iop.ops; |
c6229ca6 | 2188 | int prot = 0; |
fd86c950 | 2189 | int ret = -EINVAL; |
c6229ca6 | 2190 | |
89c9a09c SS |
2191 | if ((amd_iommu_pgtable == AMD_IOMMU_V1) && |
2192 | (domain->iop.mode == PAGE_MODE_NONE)) | |
132bd68f JR |
2193 | return -EINVAL; |
2194 | ||
c6229ca6 JR |
2195 | if (iommu_prot & IOMMU_READ) |
2196 | prot |= IOMMU_PROT_IR; | |
2197 | if (iommu_prot & IOMMU_WRITE) | |
2198 | prot |= IOMMU_PROT_IW; | |
2199 | ||
3b122a56 | 2200 | if (ops->map) |
fd86c950 | 2201 | ret = ops->map(ops, iova, paddr, page_size, prot, gfp); |
5cd3f2e9 | 2202 | |
795e74f7 | 2203 | return ret; |
c6229ca6 JR |
2204 | } |
2205 | ||
fe6d269d NA |
2206 | static void amd_iommu_iotlb_gather_add_page(struct iommu_domain *domain, |
2207 | struct iommu_iotlb_gather *gather, | |
2208 | unsigned long iova, size_t size) | |
2209 | { | |
2210 | /* | |
2211 | * AMD's IOMMU can flush as many pages as necessary in a single flush. | |
2212 | * Unless we run in a virtual machine, which can be inferred according | |
2213 | * to whether "non-present cache" is on, it is probably best to prefer | |
2214 | * (potentially) too extensive TLB flushing (i.e., more misses) over | |
2215 | * mutliple TLB flushes (i.e., more flushes). For virtual machines the | |
2216 | * hypervisor needs to synchronize the host IOMMU PTEs with those of | |
2217 | * the guest, and the trade-off is different: unnecessary TLB flushes | |
2218 | * should be avoided. | |
2219 | */ | |
2220 | if (amd_iommu_np_cache && | |
2221 | iommu_iotlb_gather_is_disjoint(gather, iova, size)) | |
2222 | iommu_iotlb_sync(domain, gather); | |
2223 | ||
2224 | iommu_iotlb_gather_add_range(gather, iova, size); | |
2225 | } | |
2226 | ||
5009065d | 2227 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
56f8af5e WD |
2228 | size_t page_size, |
2229 | struct iommu_iotlb_gather *gather) | |
eb74ff6c | 2230 | { |
3f4b87b9 | 2231 | struct protection_domain *domain = to_pdomain(dom); |
fd86c950 | 2232 | struct io_pgtable_ops *ops = &domain->iop.iop.ops; |
fc65d0ac | 2233 | size_t r; |
eb74ff6c | 2234 | |
89c9a09c SS |
2235 | if ((amd_iommu_pgtable == AMD_IOMMU_V1) && |
2236 | (domain->iop.mode == PAGE_MODE_NONE)) | |
c5611a87 | 2237 | return 0; |
132bd68f | 2238 | |
fc65d0ac NA |
2239 | r = (ops->unmap) ? ops->unmap(ops, iova, page_size, gather) : 0; |
2240 | ||
fe6d269d | 2241 | amd_iommu_iotlb_gather_add_page(dom, gather, iova, page_size); |
fc65d0ac NA |
2242 | |
2243 | return r; | |
eb74ff6c JR |
2244 | } |
2245 | ||
645c4c8d | 2246 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 2247 | dma_addr_t iova) |
645c4c8d | 2248 | { |
3f4b87b9 | 2249 | struct protection_domain *domain = to_pdomain(dom); |
0633bbcc | 2250 | struct io_pgtable_ops *ops = &domain->iop.iop.ops; |
645c4c8d | 2251 | |
441555c6 | 2252 | return ops->iova_to_phys(ops, iova); |
645c4c8d JR |
2253 | } |
2254 | ||
ab636481 | 2255 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 2256 | { |
80a506b8 JR |
2257 | switch (cap) { |
2258 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 2259 | return true; |
bdddadcb | 2260 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 2261 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
2262 | case IOMMU_CAP_NOEXEC: |
2263 | return false; | |
f1ca7071 ML |
2264 | case IOMMU_CAP_PRE_BOOT_PROTECTION: |
2265 | return amdr_ivrs_remap_support; | |
e84b7cc4 LB |
2266 | default: |
2267 | break; | |
80a506b8 JR |
2268 | } |
2269 | ||
ab636481 | 2270 | return false; |
dbb9fd86 SY |
2271 | } |
2272 | ||
e5b5234a EA |
2273 | static void amd_iommu_get_resv_regions(struct device *dev, |
2274 | struct list_head *head) | |
35cf248f | 2275 | { |
4397f32c | 2276 | struct iommu_resv_region *region; |
35cf248f | 2277 | struct unity_map_entry *entry; |
b618ae62 VH |
2278 | struct amd_iommu *iommu; |
2279 | struct amd_iommu_pci_seg *pci_seg; | |
bf87972c | 2280 | int devid, sbdf; |
35cf248f | 2281 | |
bf87972c SS |
2282 | sbdf = get_device_sbdf_id(dev); |
2283 | if (sbdf < 0) | |
7aba6cb9 | 2284 | return; |
bf87972c SS |
2285 | |
2286 | devid = PCI_SBDF_TO_DEVID(sbdf); | |
b618ae62 VH |
2287 | iommu = rlookup_amd_iommu(dev); |
2288 | if (!iommu) | |
7aba6cb9 | 2289 | return; |
b618ae62 | 2290 | pci_seg = iommu->pci_seg; |
35cf248f | 2291 | |
b618ae62 | 2292 | list_for_each_entry(entry, &pci_seg->unity_map, list) { |
8aafaaf2 | 2293 | int type, prot = 0; |
4397f32c | 2294 | size_t length; |
35cf248f JR |
2295 | |
2296 | if (devid < entry->devid_start || devid > entry->devid_end) | |
2297 | continue; | |
2298 | ||
8aafaaf2 | 2299 | type = IOMMU_RESV_DIRECT; |
4397f32c EA |
2300 | length = entry->address_end - entry->address_start; |
2301 | if (entry->prot & IOMMU_PROT_IR) | |
2302 | prot |= IOMMU_READ; | |
2303 | if (entry->prot & IOMMU_PROT_IW) | |
2304 | prot |= IOMMU_WRITE; | |
8aafaaf2 JR |
2305 | if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE) |
2306 | /* Exclusion range */ | |
2307 | type = IOMMU_RESV_RESERVED; | |
4397f32c EA |
2308 | |
2309 | region = iommu_alloc_resv_region(entry->address_start, | |
8aafaaf2 | 2310 | length, prot, type); |
35cf248f | 2311 | if (!region) { |
5f226da1 | 2312 | dev_err(dev, "Out of memory allocating dm-regions\n"); |
35cf248f JR |
2313 | return; |
2314 | } | |
35cf248f JR |
2315 | list_add_tail(®ion->list, head); |
2316 | } | |
4397f32c EA |
2317 | |
2318 | region = iommu_alloc_resv_region(MSI_RANGE_START, | |
2319 | MSI_RANGE_END - MSI_RANGE_START + 1, | |
9d3a4de4 | 2320 | 0, IOMMU_RESV_MSI); |
4397f32c EA |
2321 | if (!region) |
2322 | return; | |
2323 | list_add_tail(®ion->list, head); | |
2324 | ||
2325 | region = iommu_alloc_resv_region(HT_RANGE_START, | |
2326 | HT_RANGE_END - HT_RANGE_START + 1, | |
2327 | 0, IOMMU_RESV_RESERVED); | |
2328 | if (!region) | |
2329 | return; | |
2330 | list_add_tail(®ion->list, head); | |
35cf248f JR |
2331 | } |
2332 | ||
41bb23e7 | 2333 | bool amd_iommu_is_attach_deferred(struct device *dev) |
df3f7a6e | 2334 | { |
05a0542b | 2335 | struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); |
fb1b6955 | 2336 | |
df3f7a6e BH |
2337 | return dev_data->defer_attach; |
2338 | } | |
fb1b6955 | 2339 | EXPORT_SYMBOL_GPL(amd_iommu_is_attach_deferred); |
df3f7a6e | 2340 | |
eb5ecd1a SS |
2341 | static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain) |
2342 | { | |
2343 | struct protection_domain *dom = to_pdomain(domain); | |
2a78f996 | 2344 | unsigned long flags; |
eb5ecd1a | 2345 | |
2a78f996 | 2346 | spin_lock_irqsave(&dom->lock, flags); |
f9b4df79 SS |
2347 | amd_iommu_domain_flush_tlb_pde(dom); |
2348 | amd_iommu_domain_flush_complete(dom); | |
2a78f996 | 2349 | spin_unlock_irqrestore(&dom->lock, flags); |
eb5ecd1a SS |
2350 | } |
2351 | ||
56f8af5e WD |
2352 | static void amd_iommu_iotlb_sync(struct iommu_domain *domain, |
2353 | struct iommu_iotlb_gather *gather) | |
eb5ecd1a | 2354 | { |
fc65d0ac NA |
2355 | struct protection_domain *dom = to_pdomain(domain); |
2356 | unsigned long flags; | |
2357 | ||
2358 | spin_lock_irqsave(&dom->lock, flags); | |
a270be1b | 2359 | domain_flush_pages(dom, gather->start, gather->end - gather->start, 1); |
fc65d0ac NA |
2360 | amd_iommu_domain_flush_complete(dom); |
2361 | spin_unlock_irqrestore(&dom->lock, flags); | |
eb5ecd1a SS |
2362 | } |
2363 | ||
bdf4a7c4 JR |
2364 | static int amd_iommu_def_domain_type(struct device *dev) |
2365 | { | |
2366 | struct iommu_dev_data *dev_data; | |
2367 | ||
05a0542b | 2368 | dev_data = dev_iommu_priv_get(dev); |
bdf4a7c4 JR |
2369 | if (!dev_data) |
2370 | return 0; | |
2371 | ||
7cad5548 JR |
2372 | /* |
2373 | * Do not identity map IOMMUv2 capable devices when memory encryption is | |
2374 | * active, because some of those devices (AMD GPUs) don't have the | |
2375 | * encryption bit in their DMA-mask and require remapping. | |
2376 | */ | |
e9d1d2bb | 2377 | if (!cc_platform_has(CC_ATTR_MEM_ENCRYPT) && dev_data->iommu_v2) |
bdf4a7c4 JR |
2378 | return IOMMU_DOMAIN_IDENTITY; |
2379 | ||
2380 | return 0; | |
2381 | } | |
2382 | ||
6043257b JG |
2383 | static bool amd_iommu_enforce_cache_coherency(struct iommu_domain *domain) |
2384 | { | |
2385 | /* IOMMU_PTE_FC is always set */ | |
2386 | return true; | |
2387 | } | |
2388 | ||
b0119e87 | 2389 | const struct iommu_ops amd_iommu_ops = { |
ab636481 | 2390 | .capable = amd_iommu_capable, |
3f4b87b9 | 2391 | .domain_alloc = amd_iommu_domain_alloc, |
dce8d696 JR |
2392 | .probe_device = amd_iommu_probe_device, |
2393 | .release_device = amd_iommu_release_device, | |
2394 | .probe_finalize = amd_iommu_probe_finalize, | |
b097d11a | 2395 | .device_group = amd_iommu_device_group, |
e5b5234a | 2396 | .get_resv_regions = amd_iommu_get_resv_regions, |
df3f7a6e | 2397 | .is_attach_deferred = amd_iommu_is_attach_deferred, |
aa3de9c0 | 2398 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
bdf4a7c4 | 2399 | .def_domain_type = amd_iommu_def_domain_type, |
9a630a4b LB |
2400 | .default_domain_ops = &(const struct iommu_domain_ops) { |
2401 | .attach_dev = amd_iommu_attach_device, | |
2402 | .detach_dev = amd_iommu_detach_device, | |
2403 | .map = amd_iommu_map, | |
2404 | .unmap = amd_iommu_unmap, | |
2405 | .iotlb_sync_map = amd_iommu_iotlb_sync_map, | |
2406 | .iova_to_phys = amd_iommu_iova_to_phys, | |
2407 | .flush_iotlb_all = amd_iommu_flush_iotlb_all, | |
2408 | .iotlb_sync = amd_iommu_iotlb_sync, | |
2409 | .free = amd_iommu_domain_free, | |
6043257b | 2410 | .enforce_cache_coherency = amd_iommu_enforce_cache_coherency, |
9a630a4b | 2411 | } |
26961efe JR |
2412 | }; |
2413 | ||
0feae533 JR |
2414 | /***************************************************************************** |
2415 | * | |
2416 | * The next functions do a basic initialization of IOMMU for pass through | |
2417 | * mode | |
2418 | * | |
2419 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2420 | * DMA-API translation. | |
2421 | * | |
2422 | *****************************************************************************/ | |
2423 | ||
72e1dcc4 JR |
2424 | /* IOMMUv2 specific functions */ |
2425 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
2426 | { | |
2427 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
2428 | } | |
2429 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
2430 | ||
2431 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
2432 | { | |
2433 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
2434 | } | |
2435 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
2436 | |
2437 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
2438 | { | |
3f4b87b9 | 2439 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
2440 | unsigned long flags; |
2441 | ||
2442 | spin_lock_irqsave(&domain->lock, flags); | |
2443 | ||
e42ba063 SS |
2444 | if (domain->iop.pgtbl_cfg.tlb) |
2445 | free_io_pgtable_ops(&domain->iop.iop.ops); | |
132bd68f JR |
2446 | |
2447 | spin_unlock_irqrestore(&domain->lock, flags); | |
2448 | } | |
2449 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
2450 | |
2451 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
2452 | { | |
3f4b87b9 | 2453 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
2454 | unsigned long flags; |
2455 | int levels, ret; | |
2456 | ||
52815b75 JR |
2457 | /* Number of GCR3 table levels required */ |
2458 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
2459 | levels += 1; | |
2460 | ||
2461 | if (levels > amd_iommu_max_glx_val) | |
2462 | return -EINVAL; | |
2463 | ||
2464 | spin_lock_irqsave(&domain->lock, flags); | |
2465 | ||
2466 | /* | |
2467 | * Save us all sanity checks whether devices already in the | |
2468 | * domain support IOMMUv2. Just force that the domain has no | |
2469 | * devices attached when it is switched into IOMMUv2 mode. | |
2470 | */ | |
2471 | ret = -EBUSY; | |
2472 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
2473 | goto out; | |
2474 | ||
2475 | ret = -ENOMEM; | |
2476 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
2477 | if (domain->gcr3_tbl == NULL) | |
2478 | goto out; | |
2479 | ||
2480 | domain->glx = levels; | |
2481 | domain->flags |= PD_IOMMUV2_MASK; | |
52815b75 | 2482 | |
f9b4df79 | 2483 | amd_iommu_domain_update(domain); |
52815b75 JR |
2484 | |
2485 | ret = 0; | |
2486 | ||
2487 | out: | |
2488 | spin_unlock_irqrestore(&domain->lock, flags); | |
2489 | ||
2490 | return ret; | |
2491 | } | |
2492 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 | 2493 | |
c7b6bac9 | 2494 | static int __flush_pasid(struct protection_domain *domain, u32 pasid, |
22e266c7 JR |
2495 | u64 address, bool size) |
2496 | { | |
2497 | struct iommu_dev_data *dev_data; | |
2498 | struct iommu_cmd cmd; | |
2499 | int i, ret; | |
2500 | ||
2501 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
2502 | return -EINVAL; | |
2503 | ||
2504 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
2505 | ||
2506 | /* | |
2507 | * IOMMU TLB needs to be flushed before Device TLB to | |
2508 | * prevent device TLB refill from IOMMU TLB | |
2509 | */ | |
6b9376e3 | 2510 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
22e266c7 JR |
2511 | if (domain->dev_iommu[i] == 0) |
2512 | continue; | |
2513 | ||
2514 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
2515 | if (ret != 0) | |
2516 | goto out; | |
2517 | } | |
2518 | ||
2519 | /* Wait until IOMMU TLB flushes are complete */ | |
f9b4df79 | 2520 | amd_iommu_domain_flush_complete(domain); |
22e266c7 JR |
2521 | |
2522 | /* Now flush device TLBs */ | |
2523 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
2524 | struct amd_iommu *iommu; | |
2525 | int qdep; | |
2526 | ||
1c1cc454 JR |
2527 | /* |
2528 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
2529 | * domain. | |
2530 | */ | |
2531 | if (!dev_data->ats.enabled) | |
2532 | continue; | |
22e266c7 JR |
2533 | |
2534 | qdep = dev_data->ats.qdep; | |
8b71c9bf SS |
2535 | iommu = rlookup_amd_iommu(dev_data->dev); |
2536 | if (!iommu) | |
2537 | continue; | |
22e266c7 JR |
2538 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, |
2539 | qdep, address, size); | |
2540 | ||
2541 | ret = iommu_queue_command(iommu, &cmd); | |
2542 | if (ret != 0) | |
2543 | goto out; | |
2544 | } | |
2545 | ||
2546 | /* Wait until all device TLBs are flushed */ | |
f9b4df79 | 2547 | amd_iommu_domain_flush_complete(domain); |
22e266c7 JR |
2548 | |
2549 | ret = 0; | |
2550 | ||
2551 | out: | |
2552 | ||
2553 | return ret; | |
2554 | } | |
2555 | ||
c7b6bac9 | 2556 | static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid, |
22e266c7 JR |
2557 | u64 address) |
2558 | { | |
2559 | return __flush_pasid(domain, pasid, address, false); | |
2560 | } | |
2561 | ||
c7b6bac9 | 2562 | int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, |
22e266c7 JR |
2563 | u64 address) |
2564 | { | |
3f4b87b9 | 2565 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
2566 | unsigned long flags; |
2567 | int ret; | |
2568 | ||
2569 | spin_lock_irqsave(&domain->lock, flags); | |
2570 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
2571 | spin_unlock_irqrestore(&domain->lock, flags); | |
2572 | ||
2573 | return ret; | |
2574 | } | |
2575 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
2576 | ||
c7b6bac9 | 2577 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid) |
22e266c7 JR |
2578 | { |
2579 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
2580 | true); | |
2581 | } | |
2582 | ||
c7b6bac9 | 2583 | int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid) |
22e266c7 | 2584 | { |
3f4b87b9 | 2585 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
2586 | unsigned long flags; |
2587 | int ret; | |
2588 | ||
2589 | spin_lock_irqsave(&domain->lock, flags); | |
2590 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
2591 | spin_unlock_irqrestore(&domain->lock, flags); | |
2592 | ||
2593 | return ret; | |
2594 | } | |
2595 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
2596 | ||
c7b6bac9 | 2597 | static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc) |
b16137b1 JR |
2598 | { |
2599 | int index; | |
2600 | u64 *pte; | |
2601 | ||
2602 | while (true) { | |
2603 | ||
2604 | index = (pasid >> (9 * level)) & 0x1ff; | |
2605 | pte = &root[index]; | |
2606 | ||
2607 | if (level == 0) | |
2608 | break; | |
2609 | ||
2610 | if (!(*pte & GCR3_VALID)) { | |
2611 | if (!alloc) | |
2612 | return NULL; | |
2613 | ||
2614 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
2615 | if (root == NULL) | |
2616 | return NULL; | |
2617 | ||
2543a786 | 2618 | *pte = iommu_virt_to_phys(root) | GCR3_VALID; |
b16137b1 JR |
2619 | } |
2620 | ||
2543a786 | 2621 | root = iommu_phys_to_virt(*pte & PAGE_MASK); |
b16137b1 JR |
2622 | |
2623 | level -= 1; | |
2624 | } | |
2625 | ||
2626 | return pte; | |
2627 | } | |
2628 | ||
c7b6bac9 | 2629 | static int __set_gcr3(struct protection_domain *domain, u32 pasid, |
b16137b1 JR |
2630 | unsigned long cr3) |
2631 | { | |
2632 | u64 *pte; | |
2633 | ||
6eedb59c | 2634 | if (domain->iop.mode != PAGE_MODE_NONE) |
b16137b1 JR |
2635 | return -EINVAL; |
2636 | ||
2637 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
2638 | if (pte == NULL) | |
2639 | return -ENOMEM; | |
2640 | ||
2641 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
2642 | ||
2643 | return __amd_iommu_flush_tlb(domain, pasid); | |
2644 | } | |
2645 | ||
c7b6bac9 | 2646 | static int __clear_gcr3(struct protection_domain *domain, u32 pasid) |
b16137b1 JR |
2647 | { |
2648 | u64 *pte; | |
2649 | ||
6eedb59c | 2650 | if (domain->iop.mode != PAGE_MODE_NONE) |
b16137b1 JR |
2651 | return -EINVAL; |
2652 | ||
2653 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
2654 | if (pte == NULL) | |
2655 | return 0; | |
2656 | ||
2657 | *pte = 0; | |
2658 | ||
2659 | return __amd_iommu_flush_tlb(domain, pasid); | |
2660 | } | |
2661 | ||
c7b6bac9 | 2662 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid, |
b16137b1 JR |
2663 | unsigned long cr3) |
2664 | { | |
3f4b87b9 | 2665 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
2666 | unsigned long flags; |
2667 | int ret; | |
2668 | ||
2669 | spin_lock_irqsave(&domain->lock, flags); | |
2670 | ret = __set_gcr3(domain, pasid, cr3); | |
2671 | spin_unlock_irqrestore(&domain->lock, flags); | |
2672 | ||
2673 | return ret; | |
2674 | } | |
2675 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
2676 | ||
c7b6bac9 | 2677 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid) |
b16137b1 | 2678 | { |
3f4b87b9 | 2679 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
2680 | unsigned long flags; |
2681 | int ret; | |
2682 | ||
2683 | spin_lock_irqsave(&domain->lock, flags); | |
2684 | ret = __clear_gcr3(domain, pasid); | |
2685 | spin_unlock_irqrestore(&domain->lock, flags); | |
2686 | ||
2687 | return ret; | |
2688 | } | |
2689 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 | 2690 | |
c7b6bac9 | 2691 | int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid, |
c99afa25 JR |
2692 | int status, int tag) |
2693 | { | |
2694 | struct iommu_dev_data *dev_data; | |
2695 | struct amd_iommu *iommu; | |
2696 | struct iommu_cmd cmd; | |
2697 | ||
05a0542b | 2698 | dev_data = dev_iommu_priv_get(&pdev->dev); |
8b71c9bf SS |
2699 | iommu = rlookup_amd_iommu(&pdev->dev); |
2700 | if (!iommu) | |
2701 | return -ENODEV; | |
c99afa25 JR |
2702 | |
2703 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
2704 | tag, dev_data->pri_tlp); | |
2705 | ||
2706 | return iommu_queue_command(iommu, &cmd); | |
2707 | } | |
2708 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 | 2709 | |
52efdb89 JR |
2710 | int amd_iommu_device_info(struct pci_dev *pdev, |
2711 | struct amd_iommu_device_info *info) | |
2712 | { | |
2713 | int max_pasids; | |
2714 | int pos; | |
2715 | ||
2716 | if (pdev == NULL || info == NULL) | |
2717 | return -EINVAL; | |
2718 | ||
2719 | if (!amd_iommu_v2_supported()) | |
2720 | return -EINVAL; | |
2721 | ||
2722 | memset(info, 0, sizeof(*info)); | |
2723 | ||
7a441b21 JPB |
2724 | if (pci_ats_supported(pdev)) |
2725 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
52efdb89 JR |
2726 | |
2727 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
2728 | if (pos) | |
2729 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
2730 | ||
2731 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
2732 | if (pos) { | |
2733 | int features; | |
2734 | ||
2735 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
2736 | max_pasids = min(max_pasids, (1 << 20)); | |
2737 | ||
2738 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
2739 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
2740 | ||
2741 | features = pci_pasid_features(pdev); | |
2742 | if (features & PCI_PASID_CAP_EXEC) | |
2743 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
2744 | if (features & PCI_PASID_CAP_PRIV) | |
2745 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
2746 | } | |
2747 | ||
2748 | return 0; | |
2749 | } | |
2750 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
2751 | |
2752 | #ifdef CONFIG_IRQ_REMAP | |
2753 | ||
2754 | /***************************************************************************** | |
2755 | * | |
2756 | * Interrupt Remapping Implementation | |
2757 | * | |
2758 | *****************************************************************************/ | |
2759 | ||
7c71d306 | 2760 | static struct irq_chip amd_ir_chip; |
94c793ac | 2761 | static DEFINE_SPINLOCK(iommu_table_lock); |
7c71d306 | 2762 | |
c7d31124 SS |
2763 | static void set_dte_irq_entry(struct amd_iommu *iommu, u16 devid, |
2764 | struct irq_remap_table *table) | |
2b324506 JR |
2765 | { |
2766 | u64 dte; | |
c7d31124 | 2767 | struct dev_table_entry *dev_table = get_dev_table(iommu); |
2b324506 | 2768 | |
c7d31124 | 2769 | dte = dev_table[devid].data[2]; |
2b324506 | 2770 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; |
2543a786 | 2771 | dte |= iommu_virt_to_phys(table->table); |
2b324506 | 2772 | dte |= DTE_IRQ_REMAP_INTCTL; |
5ae9a046 | 2773 | dte |= DTE_INTTABLEN; |
2b324506 JR |
2774 | dte |= DTE_IRQ_REMAP_ENABLE; |
2775 | ||
c7d31124 | 2776 | dev_table[devid].data[2] = dte; |
2b324506 JR |
2777 | } |
2778 | ||
0217ed5a | 2779 | static struct irq_remap_table *get_irq_table(struct amd_iommu *iommu, u16 devid) |
df42a04b SW |
2780 | { |
2781 | struct irq_remap_table *table; | |
0217ed5a | 2782 | struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; |
df42a04b | 2783 | |
ccacd94f VH |
2784 | if (WARN_ONCE(!pci_seg->rlookup_table[devid], |
2785 | "%s: no iommu for devid %x:%x\n", | |
2786 | __func__, pci_seg->id, devid)) | |
df42a04b SW |
2787 | return NULL; |
2788 | ||
0217ed5a VH |
2789 | table = pci_seg->irq_lookup_table[devid]; |
2790 | if (WARN_ONCE(!table, "%s: no table for devid %x:%x\n", | |
2791 | __func__, pci_seg->id, devid)) | |
df42a04b SW |
2792 | return NULL; |
2793 | ||
2794 | return table; | |
2795 | } | |
2796 | ||
993ca6e0 SAS |
2797 | static struct irq_remap_table *__alloc_irq_table(void) |
2798 | { | |
2799 | struct irq_remap_table *table; | |
2800 | ||
2801 | table = kzalloc(sizeof(*table), GFP_KERNEL); | |
2802 | if (!table) | |
2803 | return NULL; | |
2804 | ||
2805 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL); | |
2806 | if (!table->table) { | |
2807 | kfree(table); | |
2808 | return NULL; | |
2809 | } | |
2810 | raw_spin_lock_init(&table->lock); | |
2811 | ||
2812 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) | |
2813 | memset(table->table, 0, | |
2814 | MAX_IRQS_PER_TABLE * sizeof(u32)); | |
2815 | else | |
2816 | memset(table->table, 0, | |
2817 | (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2))); | |
2818 | return table; | |
2819 | } | |
2820 | ||
2fcc1e8a SAS |
2821 | static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid, |
2822 | struct irq_remap_table *table) | |
2823 | { | |
0217ed5a VH |
2824 | struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; |
2825 | ||
2826 | pci_seg->irq_lookup_table[devid] = table; | |
c7d31124 | 2827 | set_dte_irq_entry(iommu, devid, table); |
2fcc1e8a SAS |
2828 | iommu_flush_dte(iommu, devid); |
2829 | } | |
2830 | ||
3c124435 LG |
2831 | static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias, |
2832 | void *data) | |
2833 | { | |
2834 | struct irq_remap_table *table = data; | |
0217ed5a VH |
2835 | struct amd_iommu_pci_seg *pci_seg; |
2836 | struct amd_iommu *iommu = rlookup_amd_iommu(&pdev->dev); | |
3c124435 | 2837 | |
0217ed5a VH |
2838 | if (!iommu) |
2839 | return -EINVAL; | |
3c124435 | 2840 | |
0217ed5a VH |
2841 | pci_seg = iommu->pci_seg; |
2842 | pci_seg->irq_lookup_table[alias] = table; | |
c7d31124 | 2843 | set_dte_irq_entry(iommu, alias, table); |
ccacd94f | 2844 | iommu_flush_dte(pci_seg->rlookup_table[alias], alias); |
3c124435 LG |
2845 | |
2846 | return 0; | |
2847 | } | |
2848 | ||
e6457d7c SS |
2849 | static struct irq_remap_table *alloc_irq_table(struct amd_iommu *iommu, |
2850 | u16 devid, struct pci_dev *pdev) | |
2b324506 JR |
2851 | { |
2852 | struct irq_remap_table *table = NULL; | |
993ca6e0 | 2853 | struct irq_remap_table *new_table = NULL; |
99fc4ac3 | 2854 | struct amd_iommu_pci_seg *pci_seg; |
2b324506 JR |
2855 | unsigned long flags; |
2856 | u16 alias; | |
2857 | ||
ea6166f4 | 2858 | spin_lock_irqsave(&iommu_table_lock, flags); |
2b324506 | 2859 | |
99fc4ac3 | 2860 | pci_seg = iommu->pci_seg; |
0217ed5a | 2861 | table = pci_seg->irq_lookup_table[devid]; |
2b324506 | 2862 | if (table) |
09284b9c | 2863 | goto out_unlock; |
2b324506 | 2864 | |
99fc4ac3 | 2865 | alias = pci_seg->alias_table[devid]; |
0217ed5a | 2866 | table = pci_seg->irq_lookup_table[alias]; |
2b324506 | 2867 | if (table) { |
2fcc1e8a | 2868 | set_remap_table_entry(iommu, devid, table); |
993ca6e0 | 2869 | goto out_wait; |
2b324506 | 2870 | } |
993ca6e0 | 2871 | spin_unlock_irqrestore(&iommu_table_lock, flags); |
2b324506 JR |
2872 | |
2873 | /* Nothing there yet, allocate new irq remapping table */ | |
993ca6e0 SAS |
2874 | new_table = __alloc_irq_table(); |
2875 | if (!new_table) | |
2876 | return NULL; | |
197887f0 | 2877 | |
993ca6e0 | 2878 | spin_lock_irqsave(&iommu_table_lock, flags); |
2b324506 | 2879 | |
0217ed5a | 2880 | table = pci_seg->irq_lookup_table[devid]; |
993ca6e0 | 2881 | if (table) |
09284b9c | 2882 | goto out_unlock; |
2b324506 | 2883 | |
0217ed5a | 2884 | table = pci_seg->irq_lookup_table[alias]; |
993ca6e0 SAS |
2885 | if (table) { |
2886 | set_remap_table_entry(iommu, devid, table); | |
2887 | goto out_wait; | |
2b324506 JR |
2888 | } |
2889 | ||
993ca6e0 SAS |
2890 | table = new_table; |
2891 | new_table = NULL; | |
2b324506 | 2892 | |
3c124435 LG |
2893 | if (pdev) |
2894 | pci_for_each_dma_alias(pdev, set_remap_table_entry_alias, | |
2895 | table); | |
2896 | else | |
2897 | set_remap_table_entry(iommu, devid, table); | |
2898 | ||
2fcc1e8a SAS |
2899 | if (devid != alias) |
2900 | set_remap_table_entry(iommu, alias, table); | |
2b324506 | 2901 | |
993ca6e0 | 2902 | out_wait: |
2b324506 JR |
2903 | iommu_completion_wait(iommu); |
2904 | ||
2905 | out_unlock: | |
ea6166f4 | 2906 | spin_unlock_irqrestore(&iommu_table_lock, flags); |
2b324506 | 2907 | |
993ca6e0 SAS |
2908 | if (new_table) { |
2909 | kmem_cache_free(amd_iommu_irq_cache, new_table->table); | |
2910 | kfree(new_table); | |
2911 | } | |
2b324506 JR |
2912 | return table; |
2913 | } | |
2914 | ||
e6457d7c SS |
2915 | static int alloc_irq_index(struct amd_iommu *iommu, u16 devid, int count, |
2916 | bool align, struct pci_dev *pdev) | |
2b324506 JR |
2917 | { |
2918 | struct irq_remap_table *table; | |
37946d95 | 2919 | int index, c, alignment = 1; |
2b324506 | 2920 | unsigned long flags; |
77bdab46 | 2921 | |
e6457d7c | 2922 | table = alloc_irq_table(iommu, devid, pdev); |
2b324506 JR |
2923 | if (!table) |
2924 | return -ENODEV; | |
2925 | ||
37946d95 JR |
2926 | if (align) |
2927 | alignment = roundup_pow_of_two(count); | |
2928 | ||
27790398 | 2929 | raw_spin_lock_irqsave(&table->lock, flags); |
2b324506 JR |
2930 | |
2931 | /* Scan table for free entries */ | |
37946d95 | 2932 | for (index = ALIGN(table->min_index, alignment), c = 0; |
07d1c91b | 2933 | index < MAX_IRQS_PER_TABLE;) { |
37946d95 | 2934 | if (!iommu->irte_ops->is_allocated(table, index)) { |
2b324506 | 2935 | c += 1; |
37946d95 JR |
2936 | } else { |
2937 | c = 0; | |
07d1c91b | 2938 | index = ALIGN(index + 1, alignment); |
37946d95 JR |
2939 | continue; |
2940 | } | |
2b324506 JR |
2941 | |
2942 | if (c == count) { | |
2b324506 | 2943 | for (; c != 0; --c) |
77bdab46 | 2944 | iommu->irte_ops->set_allocated(table, index - c + 1); |
2b324506 JR |
2945 | |
2946 | index -= count - 1; | |
2b324506 JR |
2947 | goto out; |
2948 | } | |
07d1c91b AW |
2949 | |
2950 | index++; | |
2b324506 JR |
2951 | } |
2952 | ||
2953 | index = -ENOSPC; | |
2954 | ||
2955 | out: | |
27790398 | 2956 | raw_spin_unlock_irqrestore(&table->lock, flags); |
2b324506 JR |
2957 | |
2958 | return index; | |
2959 | } | |
2960 | ||
c4649a45 SS |
2961 | static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index, |
2962 | struct irte_ga *irte, struct amd_ir_data *data) | |
2b324506 | 2963 | { |
e52d58d5 | 2964 | bool ret; |
2b324506 | 2965 | struct irq_remap_table *table; |
2b324506 | 2966 | unsigned long flags; |
880ac60e | 2967 | struct irte_ga *entry; |
2b324506 | 2968 | |
0217ed5a | 2969 | table = get_irq_table(iommu, devid); |
2b324506 JR |
2970 | if (!table) |
2971 | return -ENOMEM; | |
2972 | ||
27790398 | 2973 | raw_spin_lock_irqsave(&table->lock, flags); |
880ac60e SS |
2974 | |
2975 | entry = (struct irte_ga *)table->table; | |
2976 | entry = &entry[index]; | |
e52d58d5 SS |
2977 | |
2978 | ret = cmpxchg_double(&entry->lo.val, &entry->hi.val, | |
2979 | entry->lo.val, entry->hi.val, | |
2980 | irte->lo.val, irte->hi.val); | |
2981 | /* | |
2982 | * We use cmpxchg16 to atomically update the 128-bit IRTE, | |
2983 | * and it cannot be updated by the hardware or other processors | |
2984 | * behind us, so the return value of cmpxchg16 should be the | |
2985 | * same as the old value. | |
2986 | */ | |
2987 | WARN_ON(!ret); | |
2988 | ||
b9fc6b56 SS |
2989 | if (data) |
2990 | data->ref = entry; | |
880ac60e | 2991 | |
27790398 | 2992 | raw_spin_unlock_irqrestore(&table->lock, flags); |
880ac60e SS |
2993 | |
2994 | iommu_flush_irt(iommu, devid); | |
2995 | iommu_completion_wait(iommu); | |
2996 | ||
2997 | return 0; | |
2998 | } | |
2999 | ||
c4649a45 SS |
3000 | static int modify_irte(struct amd_iommu *iommu, |
3001 | u16 devid, int index, union irte *irte) | |
2b324506 JR |
3002 | { |
3003 | struct irq_remap_table *table; | |
2b324506 JR |
3004 | unsigned long flags; |
3005 | ||
0217ed5a | 3006 | table = get_irq_table(iommu, devid); |
2b324506 JR |
3007 | if (!table) |
3008 | return -ENOMEM; | |
3009 | ||
27790398 | 3010 | raw_spin_lock_irqsave(&table->lock, flags); |
880ac60e | 3011 | table->table[index] = irte->val; |
27790398 | 3012 | raw_spin_unlock_irqrestore(&table->lock, flags); |
2b324506 JR |
3013 | |
3014 | iommu_flush_irt(iommu, devid); | |
3015 | iommu_completion_wait(iommu); | |
3016 | ||
3017 | return 0; | |
3018 | } | |
3019 | ||
9457d75c | 3020 | static void free_irte(struct amd_iommu *iommu, u16 devid, int index) |
2b324506 JR |
3021 | { |
3022 | struct irq_remap_table *table; | |
2b324506 JR |
3023 | unsigned long flags; |
3024 | ||
0217ed5a | 3025 | table = get_irq_table(iommu, devid); |
2b324506 JR |
3026 | if (!table) |
3027 | return; | |
3028 | ||
27790398 | 3029 | raw_spin_lock_irqsave(&table->lock, flags); |
77bdab46 | 3030 | iommu->irte_ops->clear_allocated(table, index); |
27790398 | 3031 | raw_spin_unlock_irqrestore(&table->lock, flags); |
2b324506 JR |
3032 | |
3033 | iommu_flush_irt(iommu, devid); | |
3034 | iommu_completion_wait(iommu); | |
3035 | } | |
3036 | ||
880ac60e | 3037 | static void irte_prepare(void *entry, |
8c44963b | 3038 | u32 delivery_mode, bool dest_mode, |
d98de49a | 3039 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3040 | { |
3041 | union irte *irte = (union irte *) entry; | |
3042 | ||
3043 | irte->val = 0; | |
3044 | irte->fields.vector = vector; | |
3045 | irte->fields.int_type = delivery_mode; | |
3046 | irte->fields.destination = dest_apicid; | |
3047 | irte->fields.dm = dest_mode; | |
3048 | irte->fields.valid = 1; | |
3049 | } | |
3050 | ||
3051 | static void irte_ga_prepare(void *entry, | |
8c44963b | 3052 | u32 delivery_mode, bool dest_mode, |
d98de49a | 3053 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3054 | { |
3055 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3056 | ||
3057 | irte->lo.val = 0; | |
3058 | irte->hi.val = 0; | |
880ac60e SS |
3059 | irte->lo.fields_remap.int_type = delivery_mode; |
3060 | irte->lo.fields_remap.dm = dest_mode; | |
3061 | irte->hi.fields.vector = vector; | |
90fcffd9 SS |
3062 | irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid); |
3063 | irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid); | |
880ac60e SS |
3064 | irte->lo.fields_remap.valid = 1; |
3065 | } | |
3066 | ||
c4649a45 | 3067 | static void irte_activate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index) |
880ac60e SS |
3068 | { |
3069 | union irte *irte = (union irte *) entry; | |
3070 | ||
3071 | irte->fields.valid = 1; | |
c4649a45 | 3072 | modify_irte(iommu, devid, index, irte); |
880ac60e SS |
3073 | } |
3074 | ||
c4649a45 | 3075 | static void irte_ga_activate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index) |
880ac60e SS |
3076 | { |
3077 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3078 | ||
3079 | irte->lo.fields_remap.valid = 1; | |
c4649a45 | 3080 | modify_irte_ga(iommu, devid, index, irte, NULL); |
880ac60e SS |
3081 | } |
3082 | ||
c4649a45 | 3083 | static void irte_deactivate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index) |
880ac60e SS |
3084 | { |
3085 | union irte *irte = (union irte *) entry; | |
3086 | ||
3087 | irte->fields.valid = 0; | |
c4649a45 | 3088 | modify_irte(iommu, devid, index, irte); |
880ac60e SS |
3089 | } |
3090 | ||
c4649a45 | 3091 | static void irte_ga_deactivate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index) |
880ac60e SS |
3092 | { |
3093 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3094 | ||
3095 | irte->lo.fields_remap.valid = 0; | |
c4649a45 | 3096 | modify_irte_ga(iommu, devid, index, irte, NULL); |
880ac60e SS |
3097 | } |
3098 | ||
c4649a45 | 3099 | static void irte_set_affinity(struct amd_iommu *iommu, void *entry, u16 devid, u16 index, |
880ac60e SS |
3100 | u8 vector, u32 dest_apicid) |
3101 | { | |
3102 | union irte *irte = (union irte *) entry; | |
3103 | ||
3104 | irte->fields.vector = vector; | |
3105 | irte->fields.destination = dest_apicid; | |
c4649a45 | 3106 | modify_irte(iommu, devid, index, irte); |
880ac60e SS |
3107 | } |
3108 | ||
c4649a45 | 3109 | static void irte_ga_set_affinity(struct amd_iommu *iommu, void *entry, u16 devid, u16 index, |
880ac60e SS |
3110 | u8 vector, u32 dest_apicid) |
3111 | { | |
3112 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3113 | ||
01ee04ba | 3114 | if (!irte->lo.fields_remap.guest_mode) { |
d98de49a | 3115 | irte->hi.fields.vector = vector; |
90fcffd9 SS |
3116 | irte->lo.fields_remap.destination = |
3117 | APICID_TO_IRTE_DEST_LO(dest_apicid); | |
3118 | irte->hi.fields.destination = | |
3119 | APICID_TO_IRTE_DEST_HI(dest_apicid); | |
c4649a45 | 3120 | modify_irte_ga(iommu, devid, index, irte, NULL); |
d98de49a | 3121 | } |
880ac60e SS |
3122 | } |
3123 | ||
77bdab46 | 3124 | #define IRTE_ALLOCATED (~1U) |
880ac60e SS |
3125 | static void irte_set_allocated(struct irq_remap_table *table, int index) |
3126 | { | |
3127 | table->table[index] = IRTE_ALLOCATED; | |
3128 | } | |
3129 | ||
3130 | static void irte_ga_set_allocated(struct irq_remap_table *table, int index) | |
3131 | { | |
3132 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3133 | struct irte_ga *irte = &ptr[index]; | |
3134 | ||
3135 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3136 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3137 | irte->hi.fields.vector = 0xff; | |
3138 | } | |
3139 | ||
3140 | static bool irte_is_allocated(struct irq_remap_table *table, int index) | |
3141 | { | |
3142 | union irte *ptr = (union irte *)table->table; | |
3143 | union irte *irte = &ptr[index]; | |
3144 | ||
3145 | return irte->val != 0; | |
3146 | } | |
3147 | ||
3148 | static bool irte_ga_is_allocated(struct irq_remap_table *table, int index) | |
3149 | { | |
3150 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3151 | struct irte_ga *irte = &ptr[index]; | |
3152 | ||
3153 | return irte->hi.fields.vector != 0; | |
3154 | } | |
3155 | ||
3156 | static void irte_clear_allocated(struct irq_remap_table *table, int index) | |
3157 | { | |
3158 | table->table[index] = 0; | |
3159 | } | |
3160 | ||
3161 | static void irte_ga_clear_allocated(struct irq_remap_table *table, int index) | |
3162 | { | |
3163 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3164 | struct irte_ga *irte = &ptr[index]; | |
3165 | ||
3166 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3167 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3168 | } | |
3169 | ||
7c71d306 | 3170 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 3171 | { |
7c71d306 JL |
3172 | switch (info->type) { |
3173 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
33a65ba4 | 3174 | return get_ioapic_devid(info->devid); |
7c71d306 | 3175 | case X86_IRQ_ALLOC_TYPE_HPET: |
2bf1e7bc | 3176 | return get_hpet_devid(info->devid); |
801b5e4c TG |
3177 | case X86_IRQ_ALLOC_TYPE_PCI_MSI: |
3178 | case X86_IRQ_ALLOC_TYPE_PCI_MSIX: | |
bf87972c | 3179 | return get_device_sbdf_id(msi_desc_to_dev(info->desc)); |
7c71d306 | 3180 | default: |
192a99f4 TG |
3181 | WARN_ON_ONCE(1); |
3182 | return -1; | |
7c71d306 | 3183 | } |
7c71d306 | 3184 | } |
5527de74 | 3185 | |
6b474b82 | 3186 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
3187 | .prepare = amd_iommu_prepare, |
3188 | .enable = amd_iommu_enable, | |
3189 | .disable = amd_iommu_disable, | |
3190 | .reenable = amd_iommu_reenable, | |
3191 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 | 3192 | }; |
5527de74 | 3193 | |
b5c3786e TG |
3194 | static void fill_msi_msg(struct msi_msg *msg, u32 index) |
3195 | { | |
3196 | msg->data = index; | |
3197 | msg->address_lo = 0; | |
3198 | msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; | |
3199 | msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; | |
3200 | } | |
3201 | ||
7c71d306 JL |
3202 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
3203 | struct irq_cfg *irq_cfg, | |
3204 | struct irq_alloc_info *info, | |
3205 | int devid, int index, int sub_handle) | |
3206 | { | |
3207 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
9457d75c | 3208 | struct amd_iommu *iommu = data->iommu; |
77bdab46 SS |
3209 | |
3210 | if (!iommu) | |
3211 | return; | |
5527de74 | 3212 | |
7c71d306 JL |
3213 | data->irq_2_irte.devid = devid; |
3214 | data->irq_2_irte.index = index + sub_handle; | |
72161299 | 3215 | iommu->irte_ops->prepare(data->entry, apic->delivery_mode, |
8c44963b | 3216 | apic->dest_mode_logical, irq_cfg->vector, |
d98de49a | 3217 | irq_cfg->dest_apicid, devid); |
7c71d306 JL |
3218 | |
3219 | switch (info->type) { | |
3220 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
7c71d306 | 3221 | case X86_IRQ_ALLOC_TYPE_HPET: |
801b5e4c TG |
3222 | case X86_IRQ_ALLOC_TYPE_PCI_MSI: |
3223 | case X86_IRQ_ALLOC_TYPE_PCI_MSIX: | |
b5c3786e | 3224 | fill_msi_msg(&data->msi_entry, irte_info->index); |
7c71d306 | 3225 | break; |
5527de74 | 3226 | |
7c71d306 JL |
3227 | default: |
3228 | BUG_ON(1); | |
3229 | break; | |
3230 | } | |
5527de74 JR |
3231 | } |
3232 | ||
880ac60e SS |
3233 | struct amd_irte_ops irte_32_ops = { |
3234 | .prepare = irte_prepare, | |
3235 | .activate = irte_activate, | |
3236 | .deactivate = irte_deactivate, | |
3237 | .set_affinity = irte_set_affinity, | |
3238 | .set_allocated = irte_set_allocated, | |
3239 | .is_allocated = irte_is_allocated, | |
3240 | .clear_allocated = irte_clear_allocated, | |
3241 | }; | |
3242 | ||
3243 | struct amd_irte_ops irte_128_ops = { | |
3244 | .prepare = irte_ga_prepare, | |
3245 | .activate = irte_ga_activate, | |
3246 | .deactivate = irte_ga_deactivate, | |
3247 | .set_affinity = irte_ga_set_affinity, | |
3248 | .set_allocated = irte_ga_set_allocated, | |
3249 | .is_allocated = irte_ga_is_allocated, | |
3250 | .clear_allocated = irte_ga_clear_allocated, | |
3251 | }; | |
3252 | ||
7c71d306 JL |
3253 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
3254 | unsigned int nr_irqs, void *arg) | |
5527de74 | 3255 | { |
7c71d306 JL |
3256 | struct irq_alloc_info *info = arg; |
3257 | struct irq_data *irq_data; | |
77bdab46 | 3258 | struct amd_ir_data *data = NULL; |
9873ae6e | 3259 | struct amd_iommu *iommu; |
5527de74 | 3260 | struct irq_cfg *cfg; |
9873ae6e | 3261 | int i, ret, devid, seg, sbdf; |
29d049be | 3262 | int index; |
5527de74 | 3263 | |
7c71d306 JL |
3264 | if (!info) |
3265 | return -EINVAL; | |
801b5e4c TG |
3266 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI && |
3267 | info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX) | |
5527de74 JR |
3268 | return -EINVAL; |
3269 | ||
7c71d306 JL |
3270 | /* |
3271 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
3272 | * to support multiple MSI interrupts. | |
3273 | */ | |
801b5e4c | 3274 | if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI) |
7c71d306 | 3275 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; |
5527de74 | 3276 | |
9873ae6e SS |
3277 | sbdf = get_devid(info); |
3278 | if (sbdf < 0) | |
3279 | return -EINVAL; | |
3280 | ||
3281 | seg = PCI_SBDF_TO_SEGID(sbdf); | |
3282 | devid = PCI_SBDF_TO_DEVID(sbdf); | |
3283 | iommu = __rlookup_amd_iommu(seg, devid); | |
3284 | if (!iommu) | |
7c71d306 | 3285 | return -EINVAL; |
5527de74 | 3286 | |
7c71d306 JL |
3287 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
3288 | if (ret < 0) | |
3289 | return ret; | |
0b4d48cb | 3290 | |
7c71d306 | 3291 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
fde65dd3 | 3292 | struct irq_remap_table *table; |
fde65dd3 | 3293 | |
e6457d7c | 3294 | table = alloc_irq_table(iommu, devid, NULL); |
fde65dd3 SAS |
3295 | if (table) { |
3296 | if (!table->min_index) { | |
3297 | /* | |
3298 | * Keep the first 32 indexes free for IOAPIC | |
3299 | * interrupts. | |
3300 | */ | |
3301 | table->min_index = 32; | |
fde65dd3 SAS |
3302 | for (i = 0; i < 32; ++i) |
3303 | iommu->irte_ops->set_allocated(table, i); | |
3304 | } | |
3305 | WARN_ON(table->min_index != 32); | |
33a65ba4 | 3306 | index = info->ioapic.pin; |
fde65dd3 | 3307 | } else { |
29d049be | 3308 | index = -ENOMEM; |
fde65dd3 | 3309 | } |
801b5e4c TG |
3310 | } else if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI || |
3311 | info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX) { | |
3312 | bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI); | |
53b9ec3f | 3313 | |
e6457d7c | 3314 | index = alloc_irq_index(iommu, devid, nr_irqs, align, |
3b9c1d37 | 3315 | msi_desc_to_pci_dev(info->desc)); |
3c124435 | 3316 | } else { |
e6457d7c | 3317 | index = alloc_irq_index(iommu, devid, nr_irqs, false, NULL); |
7c71d306 | 3318 | } |
3c124435 | 3319 | |
7c71d306 JL |
3320 | if (index < 0) { |
3321 | pr_warn("Failed to allocate IRTE\n"); | |
517abe49 | 3322 | ret = index; |
7c71d306 JL |
3323 | goto out_free_parent; |
3324 | } | |
0b4d48cb | 3325 | |
7c71d306 JL |
3326 | for (i = 0; i < nr_irqs; i++) { |
3327 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
23357b61 TG |
3328 | cfg = irq_data ? irqd_cfg(irq_data) : NULL; |
3329 | if (!cfg) { | |
7c71d306 JL |
3330 | ret = -EINVAL; |
3331 | goto out_free_data; | |
3332 | } | |
0b4d48cb | 3333 | |
a130e69f JR |
3334 | ret = -ENOMEM; |
3335 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
3336 | if (!data) | |
3337 | goto out_free_data; | |
3338 | ||
77bdab46 SS |
3339 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
3340 | data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); | |
3341 | else | |
3342 | data->entry = kzalloc(sizeof(struct irte_ga), | |
3343 | GFP_KERNEL); | |
3344 | if (!data->entry) { | |
3345 | kfree(data); | |
3346 | goto out_free_data; | |
3347 | } | |
3348 | ||
9457d75c | 3349 | data->iommu = iommu; |
7c71d306 JL |
3350 | irq_data->hwirq = (devid << 16) + i; |
3351 | irq_data->chip_data = data; | |
3352 | irq_data->chip = &amd_ir_chip; | |
3353 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
3354 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
3355 | } | |
a130e69f | 3356 | |
7c71d306 | 3357 | return 0; |
0b4d48cb | 3358 | |
7c71d306 JL |
3359 | out_free_data: |
3360 | for (i--; i >= 0; i--) { | |
3361 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
3362 | if (irq_data) | |
3363 | kfree(irq_data->chip_data); | |
3364 | } | |
3365 | for (i = 0; i < nr_irqs; i++) | |
9457d75c | 3366 | free_irte(iommu, devid, index + i); |
7c71d306 JL |
3367 | out_free_parent: |
3368 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
3369 | return ret; | |
0b4d48cb JR |
3370 | } |
3371 | ||
7c71d306 JL |
3372 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
3373 | unsigned int nr_irqs) | |
0b4d48cb | 3374 | { |
7c71d306 JL |
3375 | struct irq_2_irte *irte_info; |
3376 | struct irq_data *irq_data; | |
3377 | struct amd_ir_data *data; | |
3378 | int i; | |
0b4d48cb | 3379 | |
7c71d306 JL |
3380 | for (i = 0; i < nr_irqs; i++) { |
3381 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
3382 | if (irq_data && irq_data->chip_data) { | |
3383 | data = irq_data->chip_data; | |
3384 | irte_info = &data->irq_2_irte; | |
9457d75c | 3385 | free_irte(data->iommu, irte_info->devid, irte_info->index); |
77bdab46 | 3386 | kfree(data->entry); |
7c71d306 JL |
3387 | kfree(data); |
3388 | } | |
3389 | } | |
3390 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
3391 | } | |
0b4d48cb | 3392 | |
5ba204a1 TG |
3393 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, |
3394 | struct amd_ir_data *ir_data, | |
3395 | struct irq_2_irte *irte_info, | |
3396 | struct irq_cfg *cfg); | |
3397 | ||
72491643 | 3398 | static int irq_remapping_activate(struct irq_domain *domain, |
702cb0a0 | 3399 | struct irq_data *irq_data, bool reserve) |
7c71d306 JL |
3400 | { |
3401 | struct amd_ir_data *data = irq_data->chip_data; | |
3402 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
9457d75c | 3403 | struct amd_iommu *iommu = data->iommu; |
5ba204a1 | 3404 | struct irq_cfg *cfg = irqd_cfg(irq_data); |
0b4d48cb | 3405 | |
5ba204a1 TG |
3406 | if (!iommu) |
3407 | return 0; | |
3408 | ||
c4649a45 | 3409 | iommu->irte_ops->activate(iommu, data->entry, irte_info->devid, |
5ba204a1 TG |
3410 | irte_info->index); |
3411 | amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg); | |
72491643 | 3412 | return 0; |
0b4d48cb JR |
3413 | } |
3414 | ||
7c71d306 JL |
3415 | static void irq_remapping_deactivate(struct irq_domain *domain, |
3416 | struct irq_data *irq_data) | |
0b4d48cb | 3417 | { |
7c71d306 JL |
3418 | struct amd_ir_data *data = irq_data->chip_data; |
3419 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
9457d75c | 3420 | struct amd_iommu *iommu = data->iommu; |
0b4d48cb | 3421 | |
77bdab46 | 3422 | if (iommu) |
c4649a45 | 3423 | iommu->irte_ops->deactivate(iommu, data->entry, irte_info->devid, |
77bdab46 | 3424 | irte_info->index); |
7c71d306 | 3425 | } |
0b4d48cb | 3426 | |
a1a785b5 DW |
3427 | static int irq_remapping_select(struct irq_domain *d, struct irq_fwspec *fwspec, |
3428 | enum irq_domain_bus_token bus_token) | |
3429 | { | |
3430 | struct amd_iommu *iommu; | |
3431 | int devid = -1; | |
3432 | ||
b34f10c2 DW |
3433 | if (!amd_iommu_irq_remap) |
3434 | return 0; | |
3435 | ||
a1a785b5 DW |
3436 | if (x86_fwspec_is_ioapic(fwspec)) |
3437 | devid = get_ioapic_devid(fwspec->param[0]); | |
3438 | else if (x86_fwspec_is_hpet(fwspec)) | |
3439 | devid = get_hpet_devid(fwspec->param[0]); | |
3440 | ||
3441 | if (devid < 0) | |
3442 | return 0; | |
e6457d7c | 3443 | iommu = __rlookup_amd_iommu((devid >> 16), (devid & 0xffff)); |
a1a785b5 | 3444 | |
a1a785b5 DW |
3445 | return iommu && iommu->ir_domain == d; |
3446 | } | |
3447 | ||
e2f9d45f | 3448 | static const struct irq_domain_ops amd_ir_domain_ops = { |
a1a785b5 | 3449 | .select = irq_remapping_select, |
7c71d306 JL |
3450 | .alloc = irq_remapping_alloc, |
3451 | .free = irq_remapping_free, | |
3452 | .activate = irq_remapping_activate, | |
3453 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 3454 | }; |
0b4d48cb | 3455 | |
b9c6ff94 SS |
3456 | int amd_iommu_activate_guest_mode(void *data) |
3457 | { | |
3458 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; | |
3459 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
e97685ab | 3460 | u64 valid; |
b9c6ff94 SS |
3461 | |
3462 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
3463 | !entry || entry->lo.fields_vapic.guest_mode) | |
3464 | return 0; | |
3465 | ||
e97685ab SS |
3466 | valid = entry->lo.fields_vapic.valid; |
3467 | ||
b9c6ff94 SS |
3468 | entry->lo.val = 0; |
3469 | entry->hi.val = 0; | |
3470 | ||
e97685ab | 3471 | entry->lo.fields_vapic.valid = valid; |
b9c6ff94 SS |
3472 | entry->lo.fields_vapic.guest_mode = 1; |
3473 | entry->lo.fields_vapic.ga_log_intr = 1; | |
3474 | entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr; | |
3475 | entry->hi.fields.vector = ir_data->ga_vector; | |
3476 | entry->lo.fields_vapic.ga_tag = ir_data->ga_tag; | |
3477 | ||
c4649a45 | 3478 | return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, |
730ad0ed | 3479 | ir_data->irq_2_irte.index, entry, ir_data); |
b9c6ff94 SS |
3480 | } |
3481 | EXPORT_SYMBOL(amd_iommu_activate_guest_mode); | |
3482 | ||
3483 | int amd_iommu_deactivate_guest_mode(void *data) | |
3484 | { | |
3485 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; | |
3486 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
3487 | struct irq_cfg *cfg = ir_data->cfg; | |
14c4acc5 | 3488 | u64 valid; |
b9c6ff94 SS |
3489 | |
3490 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
3491 | !entry || !entry->lo.fields_vapic.guest_mode) | |
3492 | return 0; | |
3493 | ||
14c4acc5 JM |
3494 | valid = entry->lo.fields_remap.valid; |
3495 | ||
b9c6ff94 SS |
3496 | entry->lo.val = 0; |
3497 | entry->hi.val = 0; | |
3498 | ||
26e495f3 | 3499 | entry->lo.fields_remap.valid = valid; |
8c44963b | 3500 | entry->lo.fields_remap.dm = apic->dest_mode_logical; |
72161299 | 3501 | entry->lo.fields_remap.int_type = apic->delivery_mode; |
b9c6ff94 SS |
3502 | entry->hi.fields.vector = cfg->vector; |
3503 | entry->lo.fields_remap.destination = | |
3504 | APICID_TO_IRTE_DEST_LO(cfg->dest_apicid); | |
3505 | entry->hi.fields.destination = | |
3506 | APICID_TO_IRTE_DEST_HI(cfg->dest_apicid); | |
3507 | ||
c4649a45 | 3508 | return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, |
730ad0ed | 3509 | ir_data->irq_2_irte.index, entry, ir_data); |
b9c6ff94 SS |
3510 | } |
3511 | EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode); | |
3512 | ||
b9fc6b56 SS |
3513 | static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) |
3514 | { | |
b9c6ff94 | 3515 | int ret; |
b9fc6b56 SS |
3516 | struct amd_iommu_pi_data *pi_data = vcpu_info; |
3517 | struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; | |
3518 | struct amd_ir_data *ir_data = data->chip_data; | |
b9fc6b56 | 3519 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; |
9457d75c SS |
3520 | struct iommu_dev_data *dev_data; |
3521 | ||
3522 | if (ir_data->iommu == NULL) | |
3523 | return -EINVAL; | |
3524 | ||
3525 | dev_data = search_dev_data(ir_data->iommu, irte_info->devid); | |
d98de49a SS |
3526 | |
3527 | /* Note: | |
3528 | * This device has never been set up for guest mode. | |
3529 | * we should not modify the IRTE | |
3530 | */ | |
3531 | if (!dev_data || !dev_data->use_vapic) | |
3532 | return 0; | |
b9fc6b56 | 3533 | |
b9c6ff94 | 3534 | ir_data->cfg = irqd_cfg(data); |
b9fc6b56 SS |
3535 | pi_data->ir_data = ir_data; |
3536 | ||
3537 | /* Note: | |
3538 | * SVM tries to set up for VAPIC mode, but we are in | |
3539 | * legacy mode. So, we force legacy mode instead. | |
3540 | */ | |
3541 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
101fa037 | 3542 | pr_debug("%s: Fall back to using intr legacy remap\n", |
b9fc6b56 SS |
3543 | __func__); |
3544 | pi_data->is_guest_mode = false; | |
3545 | } | |
3546 | ||
b9fc6b56 SS |
3547 | pi_data->prev_ga_tag = ir_data->cached_ga_tag; |
3548 | if (pi_data->is_guest_mode) { | |
b9c6ff94 SS |
3549 | ir_data->ga_root_ptr = (pi_data->base >> 12); |
3550 | ir_data->ga_vector = vcpu_pi_info->vector; | |
3551 | ir_data->ga_tag = pi_data->ga_tag; | |
3552 | ret = amd_iommu_activate_guest_mode(ir_data); | |
3553 | if (!ret) | |
3554 | ir_data->cached_ga_tag = pi_data->ga_tag; | |
b9fc6b56 | 3555 | } else { |
b9c6ff94 | 3556 | ret = amd_iommu_deactivate_guest_mode(ir_data); |
b9fc6b56 SS |
3557 | |
3558 | /* | |
3559 | * This communicates the ga_tag back to the caller | |
3560 | * so that it can do all the necessary clean up. | |
3561 | */ | |
b9c6ff94 SS |
3562 | if (!ret) |
3563 | ir_data->cached_ga_tag = 0; | |
b9fc6b56 SS |
3564 | } |
3565 | ||
b9c6ff94 | 3566 | return ret; |
b9fc6b56 SS |
3567 | } |
3568 | ||
5ba204a1 TG |
3569 | |
3570 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, | |
3571 | struct amd_ir_data *ir_data, | |
3572 | struct irq_2_irte *irte_info, | |
3573 | struct irq_cfg *cfg) | |
3574 | { | |
3575 | ||
3576 | /* | |
3577 | * Atomically updates the IRTE with the new destination, vector | |
3578 | * and flushes the interrupt entry cache. | |
3579 | */ | |
c4649a45 | 3580 | iommu->irte_ops->set_affinity(iommu, ir_data->entry, irte_info->devid, |
5ba204a1 TG |
3581 | irte_info->index, cfg->vector, |
3582 | cfg->dest_apicid); | |
3583 | } | |
3584 | ||
7c71d306 JL |
3585 | static int amd_ir_set_affinity(struct irq_data *data, |
3586 | const struct cpumask *mask, bool force) | |
3587 | { | |
3588 | struct amd_ir_data *ir_data = data->chip_data; | |
3589 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
3590 | struct irq_cfg *cfg = irqd_cfg(data); | |
3591 | struct irq_data *parent = data->parent_data; | |
9457d75c | 3592 | struct amd_iommu *iommu = ir_data->iommu; |
7c71d306 | 3593 | int ret; |
0b4d48cb | 3594 | |
77bdab46 SS |
3595 | if (!iommu) |
3596 | return -ENODEV; | |
3597 | ||
7c71d306 JL |
3598 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
3599 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
3600 | return ret; | |
0b4d48cb | 3601 | |
5ba204a1 | 3602 | amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg); |
7c71d306 JL |
3603 | /* |
3604 | * After this point, all the interrupts will start arriving | |
3605 | * at the new destination. So, time to cleanup the previous | |
3606 | * vector allocation. | |
3607 | */ | |
c6c2002b | 3608 | send_cleanup_vector(cfg); |
7c71d306 JL |
3609 | |
3610 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
3611 | } |
3612 | ||
7c71d306 | 3613 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 3614 | { |
7c71d306 | 3615 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 3616 | |
7c71d306 JL |
3617 | *msg = ir_data->msi_entry; |
3618 | } | |
d976195c | 3619 | |
7c71d306 | 3620 | static struct irq_chip amd_ir_chip = { |
290be194 | 3621 | .name = "AMD-IR", |
8a2b7d14 | 3622 | .irq_ack = apic_ack_irq, |
290be194 TG |
3623 | .irq_set_affinity = amd_ir_set_affinity, |
3624 | .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, | |
3625 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
7c71d306 | 3626 | }; |
d976195c | 3627 | |
7c71d306 JL |
3628 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
3629 | { | |
3e49a818 TG |
3630 | struct fwnode_handle *fn; |
3631 | ||
3632 | fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index); | |
3633 | if (!fn) | |
3634 | return -ENOMEM; | |
3635 | iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu); | |
e3beca48 TG |
3636 | if (!iommu->ir_domain) { |
3637 | irq_domain_free_fwnode(fn); | |
7c71d306 | 3638 | return -ENOMEM; |
e3beca48 | 3639 | } |
d976195c | 3640 | |
7c71d306 | 3641 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
3e49a818 TG |
3642 | iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain, |
3643 | "AMD-IR-MSI", | |
3644 | iommu->index); | |
d976195c JR |
3645 | return 0; |
3646 | } | |
8dbea3fd SS |
3647 | |
3648 | int amd_iommu_update_ga(int cpu, bool is_run, void *data) | |
3649 | { | |
3650 | unsigned long flags; | |
3651 | struct amd_iommu *iommu; | |
4fde541c | 3652 | struct irq_remap_table *table; |
8dbea3fd SS |
3653 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; |
3654 | int devid = ir_data->irq_2_irte.devid; | |
3655 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
3656 | struct irte_ga *ref = (struct irte_ga *) ir_data->ref; | |
3657 | ||
3658 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
3659 | !ref || !entry || !entry->lo.fields_vapic.guest_mode) | |
3660 | return 0; | |
3661 | ||
9457d75c | 3662 | iommu = ir_data->iommu; |
8dbea3fd SS |
3663 | if (!iommu) |
3664 | return -ENODEV; | |
3665 | ||
0217ed5a | 3666 | table = get_irq_table(iommu, devid); |
4fde541c | 3667 | if (!table) |
8dbea3fd SS |
3668 | return -ENODEV; |
3669 | ||
4fde541c | 3670 | raw_spin_lock_irqsave(&table->lock, flags); |
8dbea3fd SS |
3671 | |
3672 | if (ref->lo.fields_vapic.guest_mode) { | |
90fcffd9 SS |
3673 | if (cpu >= 0) { |
3674 | ref->lo.fields_vapic.destination = | |
3675 | APICID_TO_IRTE_DEST_LO(cpu); | |
3676 | ref->hi.fields.destination = | |
3677 | APICID_TO_IRTE_DEST_HI(cpu); | |
3678 | } | |
8dbea3fd SS |
3679 | ref->lo.fields_vapic.is_run = is_run; |
3680 | barrier(); | |
3681 | } | |
3682 | ||
4fde541c | 3683 | raw_spin_unlock_irqrestore(&table->lock, flags); |
8dbea3fd SS |
3684 | |
3685 | iommu_flush_irt(iommu, devid); | |
3686 | iommu_completion_wait(iommu); | |
3687 | return 0; | |
3688 | } | |
3689 | EXPORT_SYMBOL(amd_iommu_update_ga); | |
2b324506 | 3690 | #endif |