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3b20eb23 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
10e5247f KA |
2 | /* |
3 | * Copyright (c) 2006, Intel Corporation. | |
4 | * | |
98bcef56 | 5 | * Copyright (C) 2006-2008 Intel Corporation |
6 | * Author: Ashok Raj <ashok.raj@intel.com> | |
7 | * Author: Shaohua Li <shaohua.li@intel.com> | |
8 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
10e5247f | 9 | * |
e61d98d8 | 10 | * This file implements early detection/parsing of Remapping Devices |
10e5247f KA |
11 | * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI |
12 | * tables. | |
e61d98d8 SS |
13 | * |
14 | * These routines are used by both DMA-remapping and Interrupt-remapping | |
10e5247f KA |
15 | */ |
16 | ||
9f10e5bf | 17 | #define pr_fmt(fmt) "DMAR: " fmt |
e9071b0b | 18 | |
10e5247f KA |
19 | #include <linux/pci.h> |
20 | #include <linux/dmar.h> | |
38717946 | 21 | #include <linux/iova.h> |
fe962e90 | 22 | #include <linux/timer.h> |
0ac2491f SS |
23 | #include <linux/irq.h> |
24 | #include <linux/interrupt.h> | |
69575d38 | 25 | #include <linux/tboot.h> |
eb27cae8 | 26 | #include <linux/dmi.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
a5459cfe | 28 | #include <linux/iommu.h> |
98fa15f3 | 29 | #include <linux/numa.h> |
da72a379 | 30 | #include <linux/limits.h> |
8a8f422d | 31 | #include <asm/irq_remapping.h> |
10e5247f | 32 | |
2585a279 | 33 | #include "iommu.h" |
672cf6df | 34 | #include "../irq_remapping.h" |
74eb87a0 | 35 | #include "perf.h" |
933ab6d3 | 36 | #include "trace.h" |
078e1ee2 | 37 | |
c2a0b538 JL |
38 | typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *); |
39 | struct dmar_res_callback { | |
40 | dmar_res_handler_t cb[ACPI_DMAR_TYPE_RESERVED]; | |
41 | void *arg[ACPI_DMAR_TYPE_RESERVED]; | |
42 | bool ignore_unhandled; | |
43 | bool print_entry; | |
44 | }; | |
45 | ||
3a5670e8 JL |
46 | /* |
47 | * Assumptions: | |
48 | * 1) The hotplug framework guarentees that DMAR unit will be hot-added | |
49 | * before IO devices managed by that unit. | |
50 | * 2) The hotplug framework guarantees that DMAR unit will be hot-removed | |
51 | * after IO devices managed by that unit. | |
52 | * 3) Hotplug events are rare. | |
53 | * | |
54 | * Locking rules for DMA and interrupt remapping related global data structures: | |
55 | * 1) Use dmar_global_lock in process context | |
56 | * 2) Use RCU in interrupt context | |
10e5247f | 57 | */ |
3a5670e8 | 58 | DECLARE_RWSEM(dmar_global_lock); |
10e5247f | 59 | LIST_HEAD(dmar_drhd_units); |
10e5247f | 60 | |
41750d31 | 61 | struct acpi_table_header * __initdata dmar_tbl; |
2e455289 | 62 | static int dmar_dev_scope_status = 1; |
913432f2 | 63 | static DEFINE_IDA(dmar_seq_ids); |
10e5247f | 64 | |
694835dc | 65 | static int alloc_iommu(struct dmar_drhd_unit *drhd); |
a868e6b7 | 66 | static void free_iommu(struct intel_iommu *iommu); |
694835dc | 67 | |
6b197249 | 68 | static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd) |
10e5247f KA |
69 | { |
70 | /* | |
71 | * add INCLUDE_ALL at the tail, so scan the list will find it at | |
72 | * the very end. | |
73 | */ | |
74 | if (drhd->include_all) | |
0e242612 | 75 | list_add_tail_rcu(&drhd->list, &dmar_drhd_units); |
10e5247f | 76 | else |
0e242612 | 77 | list_add_rcu(&drhd->list, &dmar_drhd_units); |
10e5247f KA |
78 | } |
79 | ||
bb3a6b78 | 80 | void *dmar_alloc_dev_scope(void *start, void *end, int *cnt) |
10e5247f KA |
81 | { |
82 | struct acpi_dmar_device_scope *scope; | |
10e5247f KA |
83 | |
84 | *cnt = 0; | |
85 | while (start < end) { | |
86 | scope = start; | |
83118b0d | 87 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE || |
07cb52ff | 88 | scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || |
10e5247f KA |
89 | scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) |
90 | (*cnt)++; | |
ae3e7f3a LC |
91 | else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC && |
92 | scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) { | |
e9071b0b | 93 | pr_warn("Unsupported device scope\n"); |
5715f0f9 | 94 | } |
10e5247f KA |
95 | start += scope->length; |
96 | } | |
97 | if (*cnt == 0) | |
bb3a6b78 JL |
98 | return NULL; |
99 | ||
832bd858 | 100 | return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL); |
bb3a6b78 JL |
101 | } |
102 | ||
832bd858 | 103 | void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt) |
ada4d4b2 | 104 | { |
b683b230 | 105 | int i; |
832bd858 | 106 | struct device *tmp_dev; |
b683b230 | 107 | |
ada4d4b2 | 108 | if (*devices && *cnt) { |
b683b230 | 109 | for_each_active_dev_scope(*devices, *cnt, i, tmp_dev) |
832bd858 | 110 | put_device(tmp_dev); |
ada4d4b2 | 111 | kfree(*devices); |
ada4d4b2 | 112 | } |
0e242612 JL |
113 | |
114 | *devices = NULL; | |
115 | *cnt = 0; | |
ada4d4b2 JL |
116 | } |
117 | ||
59ce0515 JL |
118 | /* Optimize out kzalloc()/kfree() for normal cases */ |
119 | static char dmar_pci_notify_info_buf[64]; | |
120 | ||
121 | static struct dmar_pci_notify_info * | |
122 | dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event) | |
123 | { | |
124 | int level = 0; | |
125 | size_t size; | |
126 | struct pci_dev *tmp; | |
127 | struct dmar_pci_notify_info *info; | |
128 | ||
129 | BUG_ON(dev->is_virtfn); | |
130 | ||
da72a379 DD |
131 | /* |
132 | * Ignore devices that have a domain number higher than what can | |
133 | * be looked up in DMAR, e.g. VMD subdevices with domain 0x10000 | |
134 | */ | |
135 | if (pci_domain_nr(dev->bus) > U16_MAX) | |
136 | return NULL; | |
137 | ||
59ce0515 JL |
138 | /* Only generate path[] for device addition event */ |
139 | if (event == BUS_NOTIFY_ADD_DEVICE) | |
140 | for (tmp = dev; tmp; tmp = tmp->bus->self) | |
141 | level++; | |
142 | ||
553d66cb | 143 | size = struct_size(info, path, level); |
59ce0515 JL |
144 | if (size <= sizeof(dmar_pci_notify_info_buf)) { |
145 | info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf; | |
146 | } else { | |
147 | info = kzalloc(size, GFP_KERNEL); | |
148 | if (!info) { | |
2e455289 JL |
149 | if (dmar_dev_scope_status == 0) |
150 | dmar_dev_scope_status = -ENOMEM; | |
59ce0515 JL |
151 | return NULL; |
152 | } | |
153 | } | |
154 | ||
155 | info->event = event; | |
156 | info->dev = dev; | |
157 | info->seg = pci_domain_nr(dev->bus); | |
158 | info->level = level; | |
159 | if (event == BUS_NOTIFY_ADD_DEVICE) { | |
5ae0566a JL |
160 | for (tmp = dev; tmp; tmp = tmp->bus->self) { |
161 | level--; | |
57384592 | 162 | info->path[level].bus = tmp->bus->number; |
59ce0515 JL |
163 | info->path[level].device = PCI_SLOT(tmp->devfn); |
164 | info->path[level].function = PCI_FUNC(tmp->devfn); | |
165 | if (pci_is_root_bus(tmp->bus)) | |
166 | info->bus = tmp->bus->number; | |
167 | } | |
168 | } | |
169 | ||
170 | return info; | |
171 | } | |
172 | ||
173 | static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info) | |
174 | { | |
175 | if ((void *)info != dmar_pci_notify_info_buf) | |
176 | kfree(info); | |
177 | } | |
178 | ||
179 | static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus, | |
180 | struct acpi_dmar_pci_path *path, int count) | |
181 | { | |
182 | int i; | |
183 | ||
184 | if (info->bus != bus) | |
80f7b3d1 | 185 | goto fallback; |
59ce0515 | 186 | if (info->level != count) |
80f7b3d1 | 187 | goto fallback; |
59ce0515 JL |
188 | |
189 | for (i = 0; i < count; i++) { | |
190 | if (path[i].device != info->path[i].device || | |
191 | path[i].function != info->path[i].function) | |
80f7b3d1 | 192 | goto fallback; |
59ce0515 JL |
193 | } |
194 | ||
195 | return true; | |
80f7b3d1 JR |
196 | |
197 | fallback: | |
198 | ||
199 | if (count != 1) | |
200 | return false; | |
201 | ||
202 | i = info->level - 1; | |
203 | if (bus == info->path[i].bus && | |
204 | path[0].device == info->path[i].device && | |
205 | path[0].function == info->path[i].function) { | |
206 | pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n", | |
207 | bus, path[0].device, path[0].function); | |
208 | return true; | |
209 | } | |
210 | ||
211 | return false; | |
59ce0515 JL |
212 | } |
213 | ||
214 | /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */ | |
215 | int dmar_insert_dev_scope(struct dmar_pci_notify_info *info, | |
216 | void *start, void*end, u16 segment, | |
832bd858 DW |
217 | struct dmar_dev_scope *devices, |
218 | int devices_cnt) | |
59ce0515 JL |
219 | { |
220 | int i, level; | |
832bd858 | 221 | struct device *tmp, *dev = &info->dev->dev; |
59ce0515 JL |
222 | struct acpi_dmar_device_scope *scope; |
223 | struct acpi_dmar_pci_path *path; | |
224 | ||
225 | if (segment != info->seg) | |
226 | return 0; | |
227 | ||
228 | for (; start < end; start += scope->length) { | |
229 | scope = start; | |
230 | if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && | |
231 | scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE) | |
232 | continue; | |
233 | ||
234 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
235 | level = (scope->length - sizeof(*scope)) / sizeof(*path); | |
236 | if (!dmar_match_pci_path(info, scope->bus, path, level)) | |
237 | continue; | |
238 | ||
ffb2d1eb RD |
239 | /* |
240 | * We expect devices with endpoint scope to have normal PCI | |
241 | * headers, and devices with bridge scope to have bridge PCI | |
242 | * headers. However PCI NTB devices may be listed in the | |
243 | * DMAR table with bridge scope, even though they have a | |
244 | * normal PCI header. NTB devices are identified by class | |
245 | * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch | |
246 | * for this special case. | |
247 | */ | |
248 | if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && | |
249 | info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) || | |
250 | (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE && | |
251 | (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
53291622 | 252 | info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) { |
59ce0515 | 253 | pr_warn("Device scope type does not match for %s\n", |
832bd858 | 254 | pci_name(info->dev)); |
59ce0515 JL |
255 | return -EINVAL; |
256 | } | |
257 | ||
258 | for_each_dev_scope(devices, devices_cnt, i, tmp) | |
259 | if (tmp == NULL) { | |
832bd858 DW |
260 | devices[i].bus = info->dev->bus->number; |
261 | devices[i].devfn = info->dev->devfn; | |
262 | rcu_assign_pointer(devices[i].dev, | |
263 | get_device(dev)); | |
59ce0515 JL |
264 | return 1; |
265 | } | |
266 | BUG_ON(i >= devices_cnt); | |
267 | } | |
268 | ||
269 | return 0; | |
270 | } | |
271 | ||
272 | int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment, | |
832bd858 | 273 | struct dmar_dev_scope *devices, int count) |
59ce0515 JL |
274 | { |
275 | int index; | |
832bd858 | 276 | struct device *tmp; |
59ce0515 JL |
277 | |
278 | if (info->seg != segment) | |
279 | return 0; | |
280 | ||
281 | for_each_active_dev_scope(devices, count, index, tmp) | |
832bd858 | 282 | if (tmp == &info->dev->dev) { |
eecbad7d | 283 | RCU_INIT_POINTER(devices[index].dev, NULL); |
59ce0515 | 284 | synchronize_rcu(); |
832bd858 | 285 | put_device(tmp); |
59ce0515 JL |
286 | return 1; |
287 | } | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info) | |
293 | { | |
294 | int ret = 0; | |
295 | struct dmar_drhd_unit *dmaru; | |
296 | struct acpi_dmar_hardware_unit *drhd; | |
297 | ||
298 | for_each_drhd_unit(dmaru) { | |
299 | if (dmaru->include_all) | |
300 | continue; | |
301 | ||
302 | drhd = container_of(dmaru->hdr, | |
303 | struct acpi_dmar_hardware_unit, header); | |
304 | ret = dmar_insert_dev_scope(info, (void *)(drhd + 1), | |
305 | ((void *)drhd) + drhd->header.length, | |
306 | dmaru->segment, | |
307 | dmaru->devices, dmaru->devices_cnt); | |
f9808079 | 308 | if (ret) |
59ce0515 JL |
309 | break; |
310 | } | |
311 | if (ret >= 0) | |
312 | ret = dmar_iommu_notify_scope_dev(info); | |
2e455289 JL |
313 | if (ret < 0 && dmar_dev_scope_status == 0) |
314 | dmar_dev_scope_status = ret; | |
59ce0515 | 315 | |
85a8dfc5 TG |
316 | if (ret >= 0) |
317 | intel_irq_remap_add_device(info); | |
318 | ||
59ce0515 JL |
319 | return ret; |
320 | } | |
321 | ||
322 | static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info) | |
323 | { | |
324 | struct dmar_drhd_unit *dmaru; | |
325 | ||
326 | for_each_drhd_unit(dmaru) | |
327 | if (dmar_remove_dev_scope(info, dmaru->segment, | |
328 | dmaru->devices, dmaru->devices_cnt)) | |
329 | break; | |
330 | dmar_iommu_notify_scope_dev(info); | |
331 | } | |
332 | ||
ff828729 TG |
333 | static inline void vf_inherit_msi_domain(struct pci_dev *pdev) |
334 | { | |
3645a34f LB |
335 | struct pci_dev *physfn = pci_physfn(pdev); |
336 | ||
337 | dev_set_msi_domain(&pdev->dev, dev_get_msi_domain(&physfn->dev)); | |
ff828729 TG |
338 | } |
339 | ||
59ce0515 JL |
340 | static int dmar_pci_bus_notifier(struct notifier_block *nb, |
341 | unsigned long action, void *data) | |
342 | { | |
343 | struct pci_dev *pdev = to_pci_dev(data); | |
344 | struct dmar_pci_notify_info *info; | |
345 | ||
1c387188 AR |
346 | /* Only care about add/remove events for physical functions. |
347 | * For VFs we actually do the lookup based on the corresponding | |
348 | * PF in device_to_iommu() anyway. */ | |
ff828729 TG |
349 | if (pdev->is_virtfn) { |
350 | /* | |
351 | * Ensure that the VF device inherits the irq domain of the | |
352 | * PF device. Ideally the device would inherit the domain | |
353 | * from the bus, but DMAR can have multiple units per bus | |
354 | * which makes this impossible. The VF 'bus' could inherit | |
355 | * from the PF device, but that's yet another x86'sism to | |
356 | * inflict on everybody else. | |
357 | */ | |
358 | if (action == BUS_NOTIFY_ADD_DEVICE) | |
359 | vf_inherit_msi_domain(pdev); | |
59ce0515 | 360 | return NOTIFY_DONE; |
ff828729 TG |
361 | } |
362 | ||
e6a8c9b3 JR |
363 | if (action != BUS_NOTIFY_ADD_DEVICE && |
364 | action != BUS_NOTIFY_REMOVED_DEVICE) | |
59ce0515 JL |
365 | return NOTIFY_DONE; |
366 | ||
367 | info = dmar_alloc_pci_notify_info(pdev, action); | |
368 | if (!info) | |
369 | return NOTIFY_DONE; | |
370 | ||
371 | down_write(&dmar_global_lock); | |
372 | if (action == BUS_NOTIFY_ADD_DEVICE) | |
373 | dmar_pci_bus_add_dev(info); | |
e6a8c9b3 | 374 | else if (action == BUS_NOTIFY_REMOVED_DEVICE) |
59ce0515 JL |
375 | dmar_pci_bus_del_dev(info); |
376 | up_write(&dmar_global_lock); | |
377 | ||
378 | dmar_free_pci_notify_info(info); | |
379 | ||
380 | return NOTIFY_OK; | |
381 | } | |
382 | ||
383 | static struct notifier_block dmar_pci_bus_nb = { | |
384 | .notifier_call = dmar_pci_bus_notifier, | |
316f92a7 | 385 | .priority = 1, |
59ce0515 JL |
386 | }; |
387 | ||
6b197249 JL |
388 | static struct dmar_drhd_unit * |
389 | dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd) | |
390 | { | |
391 | struct dmar_drhd_unit *dmaru; | |
392 | ||
f5152416 QC |
393 | list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list, |
394 | dmar_rcu_check()) | |
6b197249 JL |
395 | if (dmaru->segment == drhd->segment && |
396 | dmaru->reg_base_addr == drhd->address) | |
397 | return dmaru; | |
398 | ||
399 | return NULL; | |
400 | } | |
401 | ||
3207fa32 | 402 | /* |
10e5247f KA |
403 | * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition |
404 | * structure which uniquely represent one DMA remapping hardware unit | |
405 | * present in the platform | |
406 | */ | |
6b197249 | 407 | static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg) |
10e5247f KA |
408 | { |
409 | struct acpi_dmar_hardware_unit *drhd; | |
410 | struct dmar_drhd_unit *dmaru; | |
3f6db659 | 411 | int ret; |
10e5247f | 412 | |
e523b38e | 413 | drhd = (struct acpi_dmar_hardware_unit *)header; |
6b197249 JL |
414 | dmaru = dmar_find_dmaru(drhd); |
415 | if (dmaru) | |
416 | goto out; | |
417 | ||
418 | dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL); | |
10e5247f KA |
419 | if (!dmaru) |
420 | return -ENOMEM; | |
421 | ||
6b197249 JL |
422 | /* |
423 | * If header is allocated from slab by ACPI _DSM method, we need to | |
424 | * copy the content because the memory buffer will be freed on return. | |
425 | */ | |
426 | dmaru->hdr = (void *)(dmaru + 1); | |
427 | memcpy(dmaru->hdr, header, header->length); | |
10e5247f | 428 | dmaru->reg_base_addr = drhd->address; |
276dbf99 | 429 | dmaru->segment = drhd->segment; |
10e5247f | 430 | dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */ |
07cb52ff DW |
431 | dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1), |
432 | ((void *)drhd) + drhd->header.length, | |
433 | &dmaru->devices_cnt); | |
434 | if (dmaru->devices_cnt && dmaru->devices == NULL) { | |
435 | kfree(dmaru); | |
436 | return -ENOMEM; | |
2e455289 | 437 | } |
10e5247f | 438 | |
1886e8a9 SS |
439 | ret = alloc_iommu(dmaru); |
440 | if (ret) { | |
07cb52ff DW |
441 | dmar_free_dev_scope(&dmaru->devices, |
442 | &dmaru->devices_cnt); | |
1886e8a9 SS |
443 | kfree(dmaru); |
444 | return ret; | |
445 | } | |
446 | dmar_register_drhd_unit(dmaru); | |
c2a0b538 | 447 | |
6b197249 | 448 | out: |
c2a0b538 JL |
449 | if (arg) |
450 | (*(int *)arg)++; | |
451 | ||
1886e8a9 SS |
452 | return 0; |
453 | } | |
454 | ||
a868e6b7 JL |
455 | static void dmar_free_drhd(struct dmar_drhd_unit *dmaru) |
456 | { | |
457 | if (dmaru->devices && dmaru->devices_cnt) | |
458 | dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt); | |
459 | if (dmaru->iommu) | |
460 | free_iommu(dmaru->iommu); | |
461 | kfree(dmaru); | |
462 | } | |
463 | ||
c2a0b538 JL |
464 | static int __init dmar_parse_one_andd(struct acpi_dmar_header *header, |
465 | void *arg) | |
e625b4a9 DW |
466 | { |
467 | struct acpi_dmar_andd *andd = (void *)header; | |
468 | ||
469 | /* Check for NUL termination within the designated length */ | |
83118b0d | 470 | if (strnlen(andd->device_name, header->length - 8) == header->length - 8) { |
59833696 | 471 | pr_warn(FW_BUG |
e625b4a9 DW |
472 | "Your BIOS is broken; ANDD object name is not NUL-terminated\n" |
473 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
474 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
475 | dmi_get_system_info(DMI_BIOS_VERSION), | |
476 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
59833696 | 477 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); |
e625b4a9 DW |
478 | return -EINVAL; |
479 | } | |
480 | pr_info("ANDD device: %x name: %s\n", andd->device_number, | |
83118b0d | 481 | andd->device_name); |
e625b4a9 DW |
482 | |
483 | return 0; | |
484 | } | |
485 | ||
aa697079 | 486 | #ifdef CONFIG_ACPI_NUMA |
6b197249 | 487 | static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg) |
ee34b32d SS |
488 | { |
489 | struct acpi_dmar_rhsa *rhsa; | |
490 | struct dmar_drhd_unit *drhd; | |
491 | ||
492 | rhsa = (struct acpi_dmar_rhsa *)header; | |
aa697079 | 493 | for_each_drhd_unit(drhd) { |
ee34b32d | 494 | if (drhd->reg_base_addr == rhsa->base_address) { |
01feba59 | 495 | int node = pxm_to_node(rhsa->proximity_domain); |
ee34b32d | 496 | |
b0b0b77e | 497 | if (node != NUMA_NO_NODE && !node_online(node)) |
98fa15f3 | 498 | node = NUMA_NO_NODE; |
ee34b32d | 499 | drhd->iommu->node = node; |
aa697079 DW |
500 | return 0; |
501 | } | |
ee34b32d | 502 | } |
59833696 | 503 | pr_warn(FW_BUG |
fd0c8894 BH |
504 | "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n" |
505 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
b0bb0c22 | 506 | rhsa->base_address, |
fd0c8894 BH |
507 | dmi_get_system_info(DMI_BIOS_VENDOR), |
508 | dmi_get_system_info(DMI_BIOS_VERSION), | |
509 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
59833696 | 510 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); |
ee34b32d | 511 | |
aa697079 | 512 | return 0; |
ee34b32d | 513 | } |
c2a0b538 JL |
514 | #else |
515 | #define dmar_parse_one_rhsa dmar_res_noop | |
aa697079 | 516 | #endif |
ee34b32d | 517 | |
3bd71e18 | 518 | static void |
10e5247f KA |
519 | dmar_table_print_dmar_entry(struct acpi_dmar_header *header) |
520 | { | |
521 | struct acpi_dmar_hardware_unit *drhd; | |
522 | struct acpi_dmar_reserved_memory *rmrr; | |
aa5d2b51 | 523 | struct acpi_dmar_atsr *atsr; |
17b60977 | 524 | struct acpi_dmar_rhsa *rhsa; |
31a75cbb | 525 | struct acpi_dmar_satc *satc; |
10e5247f KA |
526 | |
527 | switch (header->type) { | |
528 | case ACPI_DMAR_TYPE_HARDWARE_UNIT: | |
aa5d2b51 YZ |
529 | drhd = container_of(header, struct acpi_dmar_hardware_unit, |
530 | header); | |
e9071b0b | 531 | pr_info("DRHD base: %#016Lx flags: %#x\n", |
aa5d2b51 | 532 | (unsigned long long)drhd->address, drhd->flags); |
10e5247f KA |
533 | break; |
534 | case ACPI_DMAR_TYPE_RESERVED_MEMORY: | |
aa5d2b51 YZ |
535 | rmrr = container_of(header, struct acpi_dmar_reserved_memory, |
536 | header); | |
e9071b0b | 537 | pr_info("RMRR base: %#016Lx end: %#016Lx\n", |
5b6985ce FY |
538 | (unsigned long long)rmrr->base_address, |
539 | (unsigned long long)rmrr->end_address); | |
10e5247f | 540 | break; |
83118b0d | 541 | case ACPI_DMAR_TYPE_ROOT_ATS: |
aa5d2b51 | 542 | atsr = container_of(header, struct acpi_dmar_atsr, header); |
e9071b0b | 543 | pr_info("ATSR flags: %#x\n", atsr->flags); |
aa5d2b51 | 544 | break; |
83118b0d | 545 | case ACPI_DMAR_TYPE_HARDWARE_AFFINITY: |
17b60977 | 546 | rhsa = container_of(header, struct acpi_dmar_rhsa, header); |
e9071b0b | 547 | pr_info("RHSA base: %#016Lx proximity domain: %#x\n", |
17b60977 RD |
548 | (unsigned long long)rhsa->base_address, |
549 | rhsa->proximity_domain); | |
550 | break; | |
83118b0d | 551 | case ACPI_DMAR_TYPE_NAMESPACE: |
e625b4a9 DW |
552 | /* We don't print this here because we need to sanity-check |
553 | it first. So print it in dmar_parse_one_andd() instead. */ | |
554 | break; | |
31a75cbb YC |
555 | case ACPI_DMAR_TYPE_SATC: |
556 | satc = container_of(header, struct acpi_dmar_satc, header); | |
557 | pr_info("SATC flags: 0x%x\n", satc->flags); | |
558 | break; | |
10e5247f KA |
559 | } |
560 | } | |
561 | ||
f6dd5c31 YL |
562 | /** |
563 | * dmar_table_detect - checks to see if the platform supports DMAR devices | |
564 | */ | |
565 | static int __init dmar_table_detect(void) | |
566 | { | |
567 | acpi_status status = AE_OK; | |
568 | ||
569 | /* if we could find DMAR table, then there are DMAR devices */ | |
6b11d1d6 | 570 | status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl); |
f6dd5c31 YL |
571 | |
572 | if (ACPI_SUCCESS(status) && !dmar_tbl) { | |
e9071b0b | 573 | pr_warn("Unable to map DMAR\n"); |
f6dd5c31 YL |
574 | status = AE_NOT_FOUND; |
575 | } | |
576 | ||
8326c5d2 | 577 | return ACPI_SUCCESS(status) ? 0 : -ENOENT; |
f6dd5c31 | 578 | } |
aaa9d1dd | 579 | |
c2a0b538 JL |
580 | static int dmar_walk_remapping_entries(struct acpi_dmar_header *start, |
581 | size_t len, struct dmar_res_callback *cb) | |
582 | { | |
c2a0b538 JL |
583 | struct acpi_dmar_header *iter, *next; |
584 | struct acpi_dmar_header *end = ((void *)start) + len; | |
585 | ||
4a8ed2b8 | 586 | for (iter = start; iter < end; iter = next) { |
c2a0b538 JL |
587 | next = (void *)iter + iter->length; |
588 | if (iter->length == 0) { | |
589 | /* Avoid looping forever on bad ACPI tables */ | |
590 | pr_debug(FW_BUG "Invalid 0-length structure\n"); | |
591 | break; | |
592 | } else if (next > end) { | |
593 | /* Avoid passing table end */ | |
9f10e5bf | 594 | pr_warn(FW_BUG "Record passes table end\n"); |
4a8ed2b8 | 595 | return -EINVAL; |
c2a0b538 JL |
596 | } |
597 | ||
598 | if (cb->print_entry) | |
599 | dmar_table_print_dmar_entry(iter); | |
600 | ||
601 | if (iter->type >= ACPI_DMAR_TYPE_RESERVED) { | |
602 | /* continue for forward compatibility */ | |
603 | pr_debug("Unknown DMAR structure type %d\n", | |
604 | iter->type); | |
605 | } else if (cb->cb[iter->type]) { | |
4a8ed2b8 AS |
606 | int ret; |
607 | ||
c2a0b538 | 608 | ret = cb->cb[iter->type](iter, cb->arg[iter->type]); |
4a8ed2b8 AS |
609 | if (ret) |
610 | return ret; | |
c2a0b538 JL |
611 | } else if (!cb->ignore_unhandled) { |
612 | pr_warn("No handler for DMAR structure type %d\n", | |
613 | iter->type); | |
4a8ed2b8 | 614 | return -EINVAL; |
c2a0b538 JL |
615 | } |
616 | } | |
617 | ||
4a8ed2b8 | 618 | return 0; |
c2a0b538 JL |
619 | } |
620 | ||
621 | static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar, | |
622 | struct dmar_res_callback *cb) | |
623 | { | |
624 | return dmar_walk_remapping_entries((void *)(dmar + 1), | |
625 | dmar->header.length - sizeof(*dmar), cb); | |
626 | } | |
627 | ||
10e5247f KA |
628 | /** |
629 | * parse_dmar_table - parses the DMA reporting table | |
630 | */ | |
631 | static int __init | |
632 | parse_dmar_table(void) | |
633 | { | |
634 | struct acpi_table_dmar *dmar; | |
7cef3347 | 635 | int drhd_count = 0; |
3f6db659 | 636 | int ret; |
c2a0b538 JL |
637 | struct dmar_res_callback cb = { |
638 | .print_entry = true, | |
639 | .ignore_unhandled = true, | |
640 | .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count, | |
641 | .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd, | |
642 | .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr, | |
643 | .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr, | |
644 | .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa, | |
645 | .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd, | |
31a75cbb | 646 | .cb[ACPI_DMAR_TYPE_SATC] = &dmar_parse_one_satc, |
c2a0b538 | 647 | }; |
10e5247f | 648 | |
f6dd5c31 YL |
649 | /* |
650 | * Do it again, earlier dmar_tbl mapping could be mapped with | |
651 | * fixed map. | |
652 | */ | |
653 | dmar_table_detect(); | |
654 | ||
a59b50e9 JC |
655 | /* |
656 | * ACPI tables may not be DMA protected by tboot, so use DMAR copy | |
657 | * SINIT saved in SinitMleData in TXT heap (which is DMA protected) | |
658 | */ | |
659 | dmar_tbl = tboot_get_dmar_table(dmar_tbl); | |
660 | ||
10e5247f KA |
661 | dmar = (struct acpi_table_dmar *)dmar_tbl; |
662 | if (!dmar) | |
663 | return -ENODEV; | |
664 | ||
5b6985ce | 665 | if (dmar->width < PAGE_SHIFT - 1) { |
e9071b0b | 666 | pr_warn("Invalid DMAR haw\n"); |
10e5247f KA |
667 | return -EINVAL; |
668 | } | |
669 | ||
e9071b0b | 670 | pr_info("Host address width %d\n", dmar->width + 1); |
c2a0b538 JL |
671 | ret = dmar_walk_dmar_table(dmar, &cb); |
672 | if (ret == 0 && drhd_count == 0) | |
7cef3347 | 673 | pr_warn(FW_BUG "No DRHD structure found in DMAR table\n"); |
c2a0b538 | 674 | |
10e5247f KA |
675 | return ret; |
676 | } | |
677 | ||
832bd858 DW |
678 | static int dmar_pci_device_match(struct dmar_dev_scope devices[], |
679 | int cnt, struct pci_dev *dev) | |
e61d98d8 SS |
680 | { |
681 | int index; | |
832bd858 | 682 | struct device *tmp; |
e61d98d8 SS |
683 | |
684 | while (dev) { | |
b683b230 | 685 | for_each_active_dev_scope(devices, cnt, index, tmp) |
832bd858 | 686 | if (dev_is_pci(tmp) && dev == to_pci_dev(tmp)) |
e61d98d8 SS |
687 | return 1; |
688 | ||
689 | /* Check our parent */ | |
690 | dev = dev->bus->self; | |
691 | } | |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
696 | struct dmar_drhd_unit * | |
697 | dmar_find_matched_drhd_unit(struct pci_dev *dev) | |
698 | { | |
0e242612 | 699 | struct dmar_drhd_unit *dmaru; |
2e824f79 YZ |
700 | struct acpi_dmar_hardware_unit *drhd; |
701 | ||
dda56549 Y |
702 | dev = pci_physfn(dev); |
703 | ||
0e242612 | 704 | rcu_read_lock(); |
8b161f0e | 705 | for_each_drhd_unit(dmaru) { |
2e824f79 YZ |
706 | drhd = container_of(dmaru->hdr, |
707 | struct acpi_dmar_hardware_unit, | |
708 | header); | |
709 | ||
710 | if (dmaru->include_all && | |
711 | drhd->segment == pci_domain_nr(dev->bus)) | |
0e242612 | 712 | goto out; |
e61d98d8 | 713 | |
2e824f79 YZ |
714 | if (dmar_pci_device_match(dmaru->devices, |
715 | dmaru->devices_cnt, dev)) | |
0e242612 | 716 | goto out; |
e61d98d8 | 717 | } |
0e242612 JL |
718 | dmaru = NULL; |
719 | out: | |
720 | rcu_read_unlock(); | |
e61d98d8 | 721 | |
0e242612 | 722 | return dmaru; |
e61d98d8 SS |
723 | } |
724 | ||
ed40356b DW |
725 | static void __init dmar_acpi_insert_dev_scope(u8 device_number, |
726 | struct acpi_device *adev) | |
727 | { | |
728 | struct dmar_drhd_unit *dmaru; | |
729 | struct acpi_dmar_hardware_unit *drhd; | |
730 | struct acpi_dmar_device_scope *scope; | |
731 | struct device *tmp; | |
732 | int i; | |
733 | struct acpi_dmar_pci_path *path; | |
734 | ||
735 | for_each_drhd_unit(dmaru) { | |
736 | drhd = container_of(dmaru->hdr, | |
737 | struct acpi_dmar_hardware_unit, | |
738 | header); | |
739 | ||
740 | for (scope = (void *)(drhd + 1); | |
741 | (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length; | |
742 | scope = ((void *)scope) + scope->length) { | |
83118b0d | 743 | if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE) |
ed40356b DW |
744 | continue; |
745 | if (scope->enumeration_id != device_number) | |
746 | continue; | |
747 | ||
748 | path = (void *)(scope + 1); | |
749 | pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n", | |
750 | dev_name(&adev->dev), dmaru->reg_base_addr, | |
751 | scope->bus, path->device, path->function); | |
752 | for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp) | |
753 | if (tmp == NULL) { | |
754 | dmaru->devices[i].bus = scope->bus; | |
755 | dmaru->devices[i].devfn = PCI_DEVFN(path->device, | |
756 | path->function); | |
757 | rcu_assign_pointer(dmaru->devices[i].dev, | |
758 | get_device(&adev->dev)); | |
759 | return; | |
760 | } | |
761 | BUG_ON(i >= dmaru->devices_cnt); | |
762 | } | |
763 | } | |
764 | pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", | |
765 | device_number, dev_name(&adev->dev)); | |
766 | } | |
767 | ||
768 | static int __init dmar_acpi_dev_scope_init(void) | |
769 | { | |
11f1a776 JR |
770 | struct acpi_dmar_andd *andd; |
771 | ||
772 | if (dmar_tbl == NULL) | |
773 | return -ENODEV; | |
774 | ||
7713ec06 DW |
775 | for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar); |
776 | ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length; | |
777 | andd = ((void *)andd) + andd->header.length) { | |
83118b0d | 778 | if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) { |
ed40356b DW |
779 | acpi_handle h; |
780 | struct acpi_device *adev; | |
781 | ||
782 | if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT, | |
83118b0d | 783 | andd->device_name, |
ed40356b DW |
784 | &h))) { |
785 | pr_err("Failed to find handle for ACPI object %s\n", | |
83118b0d | 786 | andd->device_name); |
ed40356b DW |
787 | continue; |
788 | } | |
f266c11b RW |
789 | adev = acpi_fetch_acpi_dev(h); |
790 | if (!adev) { | |
ed40356b | 791 | pr_err("Failed to get device for ACPI object %s\n", |
83118b0d | 792 | andd->device_name); |
ed40356b DW |
793 | continue; |
794 | } | |
795 | dmar_acpi_insert_dev_scope(andd->device_number, adev); | |
796 | } | |
ed40356b DW |
797 | } |
798 | return 0; | |
799 | } | |
800 | ||
1886e8a9 SS |
801 | int __init dmar_dev_scope_init(void) |
802 | { | |
2e455289 JL |
803 | struct pci_dev *dev = NULL; |
804 | struct dmar_pci_notify_info *info; | |
1886e8a9 | 805 | |
2e455289 JL |
806 | if (dmar_dev_scope_status != 1) |
807 | return dmar_dev_scope_status; | |
c2c7286a | 808 | |
2e455289 JL |
809 | if (list_empty(&dmar_drhd_units)) { |
810 | dmar_dev_scope_status = -ENODEV; | |
811 | } else { | |
812 | dmar_dev_scope_status = 0; | |
813 | ||
63b42624 DW |
814 | dmar_acpi_dev_scope_init(); |
815 | ||
2e455289 JL |
816 | for_each_pci_dev(dev) { |
817 | if (dev->is_virtfn) | |
818 | continue; | |
819 | ||
820 | info = dmar_alloc_pci_notify_info(dev, | |
821 | BUS_NOTIFY_ADD_DEVICE); | |
822 | if (!info) { | |
823 | return dmar_dev_scope_status; | |
824 | } else { | |
825 | dmar_pci_bus_add_dev(info); | |
826 | dmar_free_pci_notify_info(info); | |
827 | } | |
828 | } | |
1886e8a9 SS |
829 | } |
830 | ||
2e455289 | 831 | return dmar_dev_scope_status; |
1886e8a9 SS |
832 | } |
833 | ||
d15a339e | 834 | void __init dmar_register_bus_notifier(void) |
ec154bf5 JR |
835 | { |
836 | bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb); | |
837 | } | |
838 | ||
10e5247f KA |
839 | |
840 | int __init dmar_table_init(void) | |
841 | { | |
1886e8a9 | 842 | static int dmar_table_initialized; |
093f87d2 FY |
843 | int ret; |
844 | ||
cc05301f JL |
845 | if (dmar_table_initialized == 0) { |
846 | ret = parse_dmar_table(); | |
847 | if (ret < 0) { | |
848 | if (ret != -ENODEV) | |
9f10e5bf | 849 | pr_info("Parse DMAR table failure.\n"); |
cc05301f JL |
850 | } else if (list_empty(&dmar_drhd_units)) { |
851 | pr_info("No DMAR devices found\n"); | |
852 | ret = -ENODEV; | |
853 | } | |
093f87d2 | 854 | |
cc05301f JL |
855 | if (ret < 0) |
856 | dmar_table_initialized = ret; | |
857 | else | |
858 | dmar_table_initialized = 1; | |
10e5247f | 859 | } |
093f87d2 | 860 | |
cc05301f | 861 | return dmar_table_initialized < 0 ? dmar_table_initialized : 0; |
10e5247f KA |
862 | } |
863 | ||
3a8663ee BH |
864 | static void warn_invalid_dmar(u64 addr, const char *message) |
865 | { | |
59833696 | 866 | pr_warn_once(FW_BUG |
fd0c8894 BH |
867 | "Your BIOS is broken; DMAR reported at address %llx%s!\n" |
868 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
869 | addr, message, | |
870 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
871 | dmi_get_system_info(DMI_BIOS_VERSION), | |
872 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
59833696 | 873 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); |
3a8663ee | 874 | } |
6ecbf01c | 875 | |
c2a0b538 JL |
876 | static int __ref |
877 | dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg) | |
86cf898e | 878 | { |
86cf898e | 879 | struct acpi_dmar_hardware_unit *drhd; |
c2a0b538 JL |
880 | void __iomem *addr; |
881 | u64 cap, ecap; | |
86cf898e | 882 | |
c2a0b538 JL |
883 | drhd = (void *)entry; |
884 | if (!drhd->address) { | |
885 | warn_invalid_dmar(0, ""); | |
886 | return -EINVAL; | |
887 | } | |
2c992208 | 888 | |
6b197249 JL |
889 | if (arg) |
890 | addr = ioremap(drhd->address, VTD_PAGE_SIZE); | |
891 | else | |
892 | addr = early_ioremap(drhd->address, VTD_PAGE_SIZE); | |
c2a0b538 | 893 | if (!addr) { |
9f10e5bf | 894 | pr_warn("Can't validate DRHD address: %llx\n", drhd->address); |
c2a0b538 JL |
895 | return -EINVAL; |
896 | } | |
6b197249 | 897 | |
c2a0b538 JL |
898 | cap = dmar_readq(addr + DMAR_CAP_REG); |
899 | ecap = dmar_readq(addr + DMAR_ECAP_REG); | |
6b197249 JL |
900 | |
901 | if (arg) | |
902 | iounmap(addr); | |
903 | else | |
904 | early_iounmap(addr, VTD_PAGE_SIZE); | |
86cf898e | 905 | |
c2a0b538 JL |
906 | if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) { |
907 | warn_invalid_dmar(drhd->address, " returns all ones"); | |
908 | return -EINVAL; | |
86cf898e | 909 | } |
2c992208 | 910 | |
2c992208 | 911 | return 0; |
86cf898e DW |
912 | } |
913 | ||
78013eaa | 914 | void __init detect_intel_iommu(void) |
2ae21010 SS |
915 | { |
916 | int ret; | |
c2a0b538 JL |
917 | struct dmar_res_callback validate_drhd_cb = { |
918 | .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd, | |
919 | .ignore_unhandled = true, | |
920 | }; | |
2ae21010 | 921 | |
3a5670e8 | 922 | down_write(&dmar_global_lock); |
f6dd5c31 | 923 | ret = dmar_table_detect(); |
8326c5d2 AS |
924 | if (!ret) |
925 | ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl, | |
926 | &validate_drhd_cb); | |
50310600 LB |
927 | if (!ret && !no_iommu && !iommu_detected && |
928 | (!dmar_disabled || dmar_platform_optin())) { | |
c2a0b538 JL |
929 | iommu_detected = 1; |
930 | /* Make sure ACS will be enabled */ | |
931 | pci_request_acs(); | |
932 | } | |
f5d1b97b | 933 | |
9d5ce73a | 934 | #ifdef CONFIG_X86 |
6c3a44ed | 935 | if (!ret) { |
c2a0b538 | 936 | x86_init.iommu.iommu_init = intel_iommu_init; |
6c3a44ed DD |
937 | x86_platform.iommu_shutdown = intel_iommu_shutdown; |
938 | } | |
939 | ||
2ae21010 | 940 | #endif |
c2a0b538 | 941 | |
696c7f8e RW |
942 | if (dmar_tbl) { |
943 | acpi_put_table(dmar_tbl); | |
944 | dmar_tbl = NULL; | |
945 | } | |
3a5670e8 | 946 | up_write(&dmar_global_lock); |
2ae21010 SS |
947 | } |
948 | ||
6f5cf521 DD |
949 | static void unmap_iommu(struct intel_iommu *iommu) |
950 | { | |
951 | iounmap(iommu->reg); | |
952 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
953 | } | |
954 | ||
955 | /** | |
956 | * map_iommu: map the iommu's registers | |
957 | * @iommu: the iommu to map | |
958 | * @phys_addr: the physical address of the base resgister | |
e9071b0b | 959 | * |
6f5cf521 | 960 | * Memory map the iommu's registers. Start w/ a single page, and |
e9071b0b | 961 | * possibly expand if that turns out to be insufficent. |
6f5cf521 DD |
962 | */ |
963 | static int map_iommu(struct intel_iommu *iommu, u64 phys_addr) | |
964 | { | |
965 | int map_size, err=0; | |
966 | ||
967 | iommu->reg_phys = phys_addr; | |
968 | iommu->reg_size = VTD_PAGE_SIZE; | |
969 | ||
970 | if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) { | |
9f10e5bf | 971 | pr_err("Can't reserve memory\n"); |
6f5cf521 DD |
972 | err = -EBUSY; |
973 | goto out; | |
974 | } | |
975 | ||
976 | iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); | |
977 | if (!iommu->reg) { | |
9f10e5bf | 978 | pr_err("Can't map the region\n"); |
6f5cf521 DD |
979 | err = -ENOMEM; |
980 | goto release; | |
981 | } | |
982 | ||
983 | iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); | |
984 | iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); | |
985 | ||
986 | if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { | |
987 | err = -EINVAL; | |
988 | warn_invalid_dmar(phys_addr, " returns all ones"); | |
989 | goto unmap; | |
990 | } | |
d76b42e9 DW |
991 | if (ecap_vcs(iommu->ecap)) |
992 | iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG); | |
6f5cf521 DD |
993 | |
994 | /* the registers might be more than one page */ | |
995 | map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), | |
996 | cap_max_fault_reg_offset(iommu->cap)); | |
997 | map_size = VTD_PAGE_ALIGN(map_size); | |
998 | if (map_size > iommu->reg_size) { | |
999 | iounmap(iommu->reg); | |
1000 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
1001 | iommu->reg_size = map_size; | |
1002 | if (!request_mem_region(iommu->reg_phys, iommu->reg_size, | |
1003 | iommu->name)) { | |
9f10e5bf | 1004 | pr_err("Can't reserve memory\n"); |
6f5cf521 DD |
1005 | err = -EBUSY; |
1006 | goto out; | |
1007 | } | |
1008 | iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); | |
1009 | if (!iommu->reg) { | |
9f10e5bf | 1010 | pr_err("Can't map the region\n"); |
6f5cf521 DD |
1011 | err = -ENOMEM; |
1012 | goto release; | |
1013 | } | |
1014 | } | |
1015 | err = 0; | |
1016 | goto out; | |
1017 | ||
1018 | unmap: | |
1019 | iounmap(iommu->reg); | |
1020 | release: | |
1021 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
1022 | out: | |
1023 | return err; | |
1024 | } | |
1025 | ||
694835dc | 1026 | static int alloc_iommu(struct dmar_drhd_unit *drhd) |
e61d98d8 | 1027 | { |
c42d9f32 | 1028 | struct intel_iommu *iommu; |
3a93c841 | 1029 | u32 ver, sts; |
c40aaaac DW |
1030 | int agaw = -1; |
1031 | int msagaw = -1; | |
6f5cf521 | 1032 | int err; |
c42d9f32 | 1033 | |
6ecbf01c | 1034 | if (!drhd->reg_base_addr) { |
3a8663ee | 1035 | warn_invalid_dmar(0, ""); |
6ecbf01c DW |
1036 | return -EINVAL; |
1037 | } | |
1038 | ||
c42d9f32 SS |
1039 | iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); |
1040 | if (!iommu) | |
1886e8a9 | 1041 | return -ENOMEM; |
c42d9f32 | 1042 | |
913432f2 LB |
1043 | iommu->seq_id = ida_alloc_range(&dmar_seq_ids, 0, |
1044 | DMAR_UNITS_SUPPORTED - 1, GFP_KERNEL); | |
1045 | if (iommu->seq_id < 0) { | |
9f10e5bf | 1046 | pr_err("Failed to allocate seq_id\n"); |
913432f2 | 1047 | err = iommu->seq_id; |
78d8e704 JL |
1048 | goto error; |
1049 | } | |
913432f2 | 1050 | sprintf(iommu->name, "dmar%d", iommu->seq_id); |
e61d98d8 | 1051 | |
6f5cf521 DD |
1052 | err = map_iommu(iommu, drhd->reg_base_addr); |
1053 | if (err) { | |
9f10e5bf | 1054 | pr_err("Failed to map %s\n", iommu->name); |
78d8e704 | 1055 | goto error_free_seq_id; |
e61d98d8 | 1056 | } |
0815565a | 1057 | |
6f5cf521 | 1058 | err = -EINVAL; |
c40aaaac DW |
1059 | if (cap_sagaw(iommu->cap) == 0) { |
1060 | pr_info("%s: No supported address widths. Not attempting DMA translation.\n", | |
1061 | iommu->name); | |
1062 | drhd->ignored = 1; | |
4ed0d3e6 | 1063 | } |
c40aaaac DW |
1064 | |
1065 | if (!drhd->ignored) { | |
1066 | agaw = iommu_calculate_agaw(iommu); | |
1067 | if (agaw < 0) { | |
1068 | pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n", | |
1069 | iommu->seq_id); | |
1070 | drhd->ignored = 1; | |
1071 | } | |
4ed0d3e6 | 1072 | } |
c40aaaac DW |
1073 | if (!drhd->ignored) { |
1074 | msagaw = iommu_calculate_max_sagaw(iommu); | |
1075 | if (msagaw < 0) { | |
1076 | pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n", | |
1077 | iommu->seq_id); | |
1078 | drhd->ignored = 1; | |
1079 | agaw = -1; | |
1080 | } | |
1b573683 WH |
1081 | } |
1082 | iommu->agaw = agaw; | |
4ed0d3e6 | 1083 | iommu->msagaw = msagaw; |
67ccac41 | 1084 | iommu->segment = drhd->segment; |
1b573683 | 1085 | |
98fa15f3 | 1086 | iommu->node = NUMA_NO_NODE; |
ee34b32d | 1087 | |
e61d98d8 | 1088 | ver = readl(iommu->reg + DMAR_VER_REG); |
9f10e5bf JR |
1089 | pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n", |
1090 | iommu->name, | |
5b6985ce FY |
1091 | (unsigned long long)drhd->reg_base_addr, |
1092 | DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver), | |
1093 | (unsigned long long)iommu->cap, | |
1094 | (unsigned long long)iommu->ecap); | |
e61d98d8 | 1095 | |
3a93c841 TI |
1096 | /* Reflect status in gcmd */ |
1097 | sts = readl(iommu->reg + DMAR_GSTS_REG); | |
1098 | if (sts & DMA_GSTS_IRES) | |
1099 | iommu->gcmd |= DMA_GCMD_IRE; | |
1100 | if (sts & DMA_GSTS_TES) | |
1101 | iommu->gcmd |= DMA_GCMD_TE; | |
1102 | if (sts & DMA_GSTS_QIES) | |
1103 | iommu->gcmd |= DMA_GCMD_QIE; | |
1104 | ||
1f5b3c3f | 1105 | raw_spin_lock_init(&iommu->register_lock); |
e61d98d8 | 1106 | |
c40aaaac DW |
1107 | /* |
1108 | * This is only for hotplug; at boot time intel_iommu_enabled won't | |
1109 | * be set yet. When intel_iommu_init() runs, it registers the units | |
1110 | * present at boot time, then sets intel_iommu_enabled. | |
1111 | */ | |
1112 | if (intel_iommu_enabled && !drhd->ignored) { | |
39ab9555 JR |
1113 | err = iommu_device_sysfs_add(&iommu->iommu, NULL, |
1114 | intel_iommu_groups, | |
1115 | "%s", iommu->name); | |
1116 | if (err) | |
bc847454 | 1117 | goto err_unmap; |
a5459cfe | 1118 | |
2d471b20 | 1119 | err = iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL); |
b0119e87 | 1120 | if (err) |
0ee74d5a | 1121 | goto err_sysfs; |
59203379 NK |
1122 | } |
1123 | ||
bc847454 | 1124 | drhd->iommu = iommu; |
b1012ca8 | 1125 | iommu->drhd = drhd; |
bc847454 | 1126 | |
1886e8a9 | 1127 | return 0; |
0815565a | 1128 | |
0ee74d5a REB |
1129 | err_sysfs: |
1130 | iommu_device_sysfs_remove(&iommu->iommu); | |
78d8e704 | 1131 | err_unmap: |
6f5cf521 | 1132 | unmap_iommu(iommu); |
78d8e704 | 1133 | error_free_seq_id: |
913432f2 | 1134 | ida_free(&dmar_seq_ids, iommu->seq_id); |
78d8e704 | 1135 | error: |
e61d98d8 | 1136 | kfree(iommu); |
6f5cf521 | 1137 | return err; |
e61d98d8 SS |
1138 | } |
1139 | ||
a868e6b7 | 1140 | static void free_iommu(struct intel_iommu *iommu) |
e61d98d8 | 1141 | { |
9def3b1a | 1142 | if (intel_iommu_enabled && !iommu->drhd->ignored) { |
c37a0177 AS |
1143 | iommu_device_unregister(&iommu->iommu); |
1144 | iommu_device_sysfs_remove(&iommu->iommu); | |
1145 | } | |
a5459cfe | 1146 | |
a868e6b7 | 1147 | if (iommu->irq) { |
1208225c DW |
1148 | if (iommu->pr_irq) { |
1149 | free_irq(iommu->pr_irq, iommu); | |
1150 | dmar_free_hwirq(iommu->pr_irq); | |
1151 | iommu->pr_irq = 0; | |
1152 | } | |
a868e6b7 | 1153 | free_irq(iommu->irq, iommu); |
a553b142 | 1154 | dmar_free_hwirq(iommu->irq); |
34742db8 | 1155 | iommu->irq = 0; |
a868e6b7 | 1156 | } |
e61d98d8 | 1157 | |
a84da70b JL |
1158 | if (iommu->qi) { |
1159 | free_page((unsigned long)iommu->qi->desc); | |
1160 | kfree(iommu->qi->desc_status); | |
1161 | kfree(iommu->qi); | |
1162 | } | |
1163 | ||
e61d98d8 | 1164 | if (iommu->reg) |
6f5cf521 DD |
1165 | unmap_iommu(iommu); |
1166 | ||
913432f2 | 1167 | ida_free(&dmar_seq_ids, iommu->seq_id); |
e61d98d8 SS |
1168 | kfree(iommu); |
1169 | } | |
fe962e90 SS |
1170 | |
1171 | /* | |
1172 | * Reclaim all the submitted descriptors which have completed its work. | |
1173 | */ | |
1174 | static inline void reclaim_free_desc(struct q_inval *qi) | |
1175 | { | |
6ba6c3a4 YZ |
1176 | while (qi->desc_status[qi->free_tail] == QI_DONE || |
1177 | qi->desc_status[qi->free_tail] == QI_ABORT) { | |
fe962e90 SS |
1178 | qi->desc_status[qi->free_tail] = QI_FREE; |
1179 | qi->free_tail = (qi->free_tail + 1) % QI_LENGTH; | |
1180 | qi->free_cnt++; | |
1181 | } | |
1182 | } | |
1183 | ||
6ca69e58 LB |
1184 | static const char *qi_type_string(u8 type) |
1185 | { | |
1186 | switch (type) { | |
1187 | case QI_CC_TYPE: | |
1188 | return "Context-cache Invalidation"; | |
1189 | case QI_IOTLB_TYPE: | |
1190 | return "IOTLB Invalidation"; | |
1191 | case QI_DIOTLB_TYPE: | |
1192 | return "Device-TLB Invalidation"; | |
1193 | case QI_IEC_TYPE: | |
1194 | return "Interrupt Entry Cache Invalidation"; | |
1195 | case QI_IWD_TYPE: | |
1196 | return "Invalidation Wait"; | |
1197 | case QI_EIOTLB_TYPE: | |
1198 | return "PASID-based IOTLB Invalidation"; | |
1199 | case QI_PC_TYPE: | |
1200 | return "PASID-cache Invalidation"; | |
1201 | case QI_DEIOTLB_TYPE: | |
1202 | return "PASID-based Device-TLB Invalidation"; | |
1203 | case QI_PGRP_RESP_TYPE: | |
1204 | return "Page Group Response"; | |
1205 | default: | |
1206 | return "UNKNOWN"; | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | static void qi_dump_fault(struct intel_iommu *iommu, u32 fault) | |
1211 | { | |
1212 | unsigned int head = dmar_readl(iommu->reg + DMAR_IQH_REG); | |
1213 | u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG); | |
1214 | struct qi_desc *desc = iommu->qi->desc + head; | |
1215 | ||
1216 | if (fault & DMA_FSTS_IQE) | |
1217 | pr_err("VT-d detected Invalidation Queue Error: Reason %llx", | |
1218 | DMAR_IQER_REG_IQEI(iqe_err)); | |
1219 | if (fault & DMA_FSTS_ITE) | |
1220 | pr_err("VT-d detected Invalidation Time-out Error: SID %llx", | |
1221 | DMAR_IQER_REG_ITESID(iqe_err)); | |
1222 | if (fault & DMA_FSTS_ICE) | |
1223 | pr_err("VT-d detected Invalidation Completion Error: SID %llx", | |
1224 | DMAR_IQER_REG_ICESID(iqe_err)); | |
1225 | ||
1226 | pr_err("QI HEAD: %s qw0 = 0x%llx, qw1 = 0x%llx\n", | |
1227 | qi_type_string(desc->qw0 & 0xf), | |
1228 | (unsigned long long)desc->qw0, | |
1229 | (unsigned long long)desc->qw1); | |
1230 | ||
1231 | head = ((head >> qi_shift(iommu)) + QI_LENGTH - 1) % QI_LENGTH; | |
1232 | head <<= qi_shift(iommu); | |
1233 | desc = iommu->qi->desc + head; | |
1234 | ||
1235 | pr_err("QI PRIOR: %s qw0 = 0x%llx, qw1 = 0x%llx\n", | |
1236 | qi_type_string(desc->qw0 & 0xf), | |
1237 | (unsigned long long)desc->qw0, | |
1238 | (unsigned long long)desc->qw1); | |
1239 | } | |
1240 | ||
8a1d8246 | 1241 | static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index) |
704126ad YZ |
1242 | { |
1243 | u32 fault; | |
6ba6c3a4 | 1244 | int head, tail; |
704126ad | 1245 | struct q_inval *qi = iommu->qi; |
5d308fc1 | 1246 | int shift = qi_shift(iommu); |
704126ad | 1247 | |
6ba6c3a4 YZ |
1248 | if (qi->desc_status[wait_index] == QI_ABORT) |
1249 | return -EAGAIN; | |
1250 | ||
704126ad | 1251 | fault = readl(iommu->reg + DMAR_FSTS_REG); |
6ca69e58 LB |
1252 | if (fault & (DMA_FSTS_IQE | DMA_FSTS_ITE | DMA_FSTS_ICE)) |
1253 | qi_dump_fault(iommu, fault); | |
704126ad YZ |
1254 | |
1255 | /* | |
1256 | * If IQE happens, the head points to the descriptor associated | |
1257 | * with the error. No new descriptors are fetched until the IQE | |
1258 | * is cleared. | |
1259 | */ | |
1260 | if (fault & DMA_FSTS_IQE) { | |
1261 | head = readl(iommu->reg + DMAR_IQH_REG); | |
5d308fc1 LB |
1262 | if ((head >> shift) == index) { |
1263 | struct qi_desc *desc = qi->desc + head; | |
1264 | ||
1265 | /* | |
1266 | * desc->qw2 and desc->qw3 are either reserved or | |
1267 | * used by software as private data. We won't print | |
1268 | * out these two qw's for security consideration. | |
1269 | */ | |
5d308fc1 LB |
1270 | memcpy(desc, qi->desc + (wait_index << shift), |
1271 | 1 << shift); | |
704126ad | 1272 | writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); |
6ca69e58 | 1273 | pr_info("Invalidation Queue Error (IQE) cleared\n"); |
704126ad YZ |
1274 | return -EINVAL; |
1275 | } | |
1276 | } | |
1277 | ||
6ba6c3a4 YZ |
1278 | /* |
1279 | * If ITE happens, all pending wait_desc commands are aborted. | |
1280 | * No new descriptors are fetched until the ITE is cleared. | |
1281 | */ | |
1282 | if (fault & DMA_FSTS_ITE) { | |
1283 | head = readl(iommu->reg + DMAR_IQH_REG); | |
5d308fc1 | 1284 | head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH; |
6ba6c3a4 YZ |
1285 | head |= 1; |
1286 | tail = readl(iommu->reg + DMAR_IQT_REG); | |
5d308fc1 | 1287 | tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH; |
6ba6c3a4 YZ |
1288 | |
1289 | writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); | |
6ca69e58 | 1290 | pr_info("Invalidation Time-out Error (ITE) cleared\n"); |
6ba6c3a4 YZ |
1291 | |
1292 | do { | |
1293 | if (qi->desc_status[head] == QI_IN_USE) | |
1294 | qi->desc_status[head] = QI_ABORT; | |
1295 | head = (head - 2 + QI_LENGTH) % QI_LENGTH; | |
1296 | } while (head != tail); | |
1297 | ||
1298 | if (qi->desc_status[wait_index] == QI_ABORT) | |
1299 | return -EAGAIN; | |
1300 | } | |
1301 | ||
6ca69e58 | 1302 | if (fault & DMA_FSTS_ICE) { |
6ba6c3a4 | 1303 | writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); |
6ca69e58 LB |
1304 | pr_info("Invalidation Completion Error (ICE) cleared\n"); |
1305 | } | |
6ba6c3a4 | 1306 | |
704126ad YZ |
1307 | return 0; |
1308 | } | |
1309 | ||
fe962e90 | 1310 | /* |
8a1d8246 LB |
1311 | * Function to submit invalidation descriptors of all types to the queued |
1312 | * invalidation interface(QI). Multiple descriptors can be submitted at a | |
1313 | * time, a wait descriptor will be appended to each submission to ensure | |
1314 | * hardware has completed the invalidation before return. Wait descriptors | |
1315 | * can be part of the submission but it will not be polled for completion. | |
fe962e90 | 1316 | */ |
8a1d8246 LB |
1317 | int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc, |
1318 | unsigned int count, unsigned long options) | |
fe962e90 SS |
1319 | { |
1320 | struct q_inval *qi = iommu->qi; | |
74eb87a0 LB |
1321 | s64 devtlb_start_ktime = 0; |
1322 | s64 iotlb_start_ktime = 0; | |
1323 | s64 iec_start_ktime = 0; | |
5d308fc1 | 1324 | struct qi_desc wait_desc; |
fe962e90 SS |
1325 | int wait_index, index; |
1326 | unsigned long flags; | |
8a1d8246 LB |
1327 | int offset, shift; |
1328 | int rc, i; | |
74eb87a0 | 1329 | u64 type; |
fe962e90 SS |
1330 | |
1331 | if (!qi) | |
704126ad | 1332 | return 0; |
fe962e90 | 1333 | |
74eb87a0 LB |
1334 | type = desc->qw0 & GENMASK_ULL(3, 0); |
1335 | ||
1336 | if ((type == QI_IOTLB_TYPE || type == QI_EIOTLB_TYPE) && | |
1337 | dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IOTLB)) | |
1338 | iotlb_start_ktime = ktime_to_ns(ktime_get()); | |
1339 | ||
1340 | if ((type == QI_DIOTLB_TYPE || type == QI_DEIOTLB_TYPE) && | |
1341 | dmar_latency_enabled(iommu, DMAR_LATENCY_INV_DEVTLB)) | |
1342 | devtlb_start_ktime = ktime_to_ns(ktime_get()); | |
1343 | ||
1344 | if (type == QI_IEC_TYPE && | |
1345 | dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IEC)) | |
1346 | iec_start_ktime = ktime_to_ns(ktime_get()); | |
1347 | ||
6ba6c3a4 YZ |
1348 | restart: |
1349 | rc = 0; | |
1350 | ||
3b8f4048 | 1351 | raw_spin_lock_irqsave(&qi->q_lock, flags); |
8a1d8246 LB |
1352 | /* |
1353 | * Check if we have enough empty slots in the queue to submit, | |
1354 | * the calculation is based on: | |
1355 | * # of desc + 1 wait desc + 1 space between head and tail | |
1356 | */ | |
1357 | while (qi->free_cnt < count + 2) { | |
3b8f4048 | 1358 | raw_spin_unlock_irqrestore(&qi->q_lock, flags); |
fe962e90 | 1359 | cpu_relax(); |
3b8f4048 | 1360 | raw_spin_lock_irqsave(&qi->q_lock, flags); |
fe962e90 SS |
1361 | } |
1362 | ||
1363 | index = qi->free_head; | |
8a1d8246 | 1364 | wait_index = (index + count) % QI_LENGTH; |
5d308fc1 | 1365 | shift = qi_shift(iommu); |
fe962e90 | 1366 | |
8a1d8246 LB |
1367 | for (i = 0; i < count; i++) { |
1368 | offset = ((index + i) % QI_LENGTH) << shift; | |
1369 | memcpy(qi->desc + offset, &desc[i], 1 << shift); | |
1370 | qi->desc_status[(index + i) % QI_LENGTH] = QI_IN_USE; | |
f2dd8717 LB |
1371 | trace_qi_submit(iommu, desc[i].qw0, desc[i].qw1, |
1372 | desc[i].qw2, desc[i].qw3); | |
8a1d8246 LB |
1373 | } |
1374 | qi->desc_status[wait_index] = QI_IN_USE; | |
fe962e90 | 1375 | |
5d308fc1 | 1376 | wait_desc.qw0 = QI_IWD_STATUS_DATA(QI_DONE) | |
704126ad | 1377 | QI_IWD_STATUS_WRITE | QI_IWD_TYPE; |
8a1d8246 LB |
1378 | if (options & QI_OPT_WAIT_DRAIN) |
1379 | wait_desc.qw0 |= QI_IWD_PRQ_DRAIN; | |
5d308fc1 LB |
1380 | wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]); |
1381 | wait_desc.qw2 = 0; | |
1382 | wait_desc.qw3 = 0; | |
fe962e90 | 1383 | |
5d308fc1 | 1384 | offset = wait_index << shift; |
8a1d8246 | 1385 | memcpy(qi->desc + offset, &wait_desc, 1 << shift); |
fe962e90 | 1386 | |
8a1d8246 LB |
1387 | qi->free_head = (qi->free_head + count + 1) % QI_LENGTH; |
1388 | qi->free_cnt -= count + 1; | |
fe962e90 | 1389 | |
fe962e90 SS |
1390 | /* |
1391 | * update the HW tail register indicating the presence of | |
1392 | * new descriptors. | |
1393 | */ | |
5d308fc1 | 1394 | writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); |
fe962e90 SS |
1395 | |
1396 | while (qi->desc_status[wait_index] != QI_DONE) { | |
f05810c9 SS |
1397 | /* |
1398 | * We will leave the interrupts disabled, to prevent interrupt | |
1399 | * context to queue another cmd while a cmd is already submitted | |
1400 | * and waiting for completion on this cpu. This is to avoid | |
1401 | * a deadlock where the interrupt context can wait indefinitely | |
1402 | * for free slots in the queue. | |
1403 | */ | |
8a1d8246 | 1404 | rc = qi_check_fault(iommu, index, wait_index); |
704126ad | 1405 | if (rc) |
6ba6c3a4 | 1406 | break; |
704126ad | 1407 | |
3b8f4048 | 1408 | raw_spin_unlock(&qi->q_lock); |
fe962e90 | 1409 | cpu_relax(); |
3b8f4048 | 1410 | raw_spin_lock(&qi->q_lock); |
fe962e90 | 1411 | } |
6ba6c3a4 | 1412 | |
8a1d8246 LB |
1413 | for (i = 0; i < count; i++) |
1414 | qi->desc_status[(index + i) % QI_LENGTH] = QI_DONE; | |
fe962e90 SS |
1415 | |
1416 | reclaim_free_desc(qi); | |
3b8f4048 | 1417 | raw_spin_unlock_irqrestore(&qi->q_lock, flags); |
704126ad | 1418 | |
6ba6c3a4 YZ |
1419 | if (rc == -EAGAIN) |
1420 | goto restart; | |
1421 | ||
74eb87a0 LB |
1422 | if (iotlb_start_ktime) |
1423 | dmar_latency_update(iommu, DMAR_LATENCY_INV_IOTLB, | |
1424 | ktime_to_ns(ktime_get()) - iotlb_start_ktime); | |
1425 | ||
1426 | if (devtlb_start_ktime) | |
1427 | dmar_latency_update(iommu, DMAR_LATENCY_INV_DEVTLB, | |
1428 | ktime_to_ns(ktime_get()) - devtlb_start_ktime); | |
1429 | ||
1430 | if (iec_start_ktime) | |
1431 | dmar_latency_update(iommu, DMAR_LATENCY_INV_IEC, | |
1432 | ktime_to_ns(ktime_get()) - iec_start_ktime); | |
1433 | ||
704126ad | 1434 | return rc; |
fe962e90 SS |
1435 | } |
1436 | ||
1437 | /* | |
1438 | * Flush the global interrupt entry cache. | |
1439 | */ | |
1440 | void qi_global_iec(struct intel_iommu *iommu) | |
1441 | { | |
1442 | struct qi_desc desc; | |
1443 | ||
5d308fc1 LB |
1444 | desc.qw0 = QI_IEC_TYPE; |
1445 | desc.qw1 = 0; | |
1446 | desc.qw2 = 0; | |
1447 | desc.qw3 = 0; | |
fe962e90 | 1448 | |
704126ad | 1449 | /* should never fail */ |
8a1d8246 | 1450 | qi_submit_sync(iommu, &desc, 1, 0); |
fe962e90 SS |
1451 | } |
1452 | ||
4c25a2c1 DW |
1453 | void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm, |
1454 | u64 type) | |
3481f210 | 1455 | { |
3481f210 YS |
1456 | struct qi_desc desc; |
1457 | ||
5d308fc1 | 1458 | desc.qw0 = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did) |
3481f210 | 1459 | | QI_CC_GRAN(type) | QI_CC_TYPE; |
5d308fc1 LB |
1460 | desc.qw1 = 0; |
1461 | desc.qw2 = 0; | |
1462 | desc.qw3 = 0; | |
3481f210 | 1463 | |
8a1d8246 | 1464 | qi_submit_sync(iommu, &desc, 1, 0); |
3481f210 YS |
1465 | } |
1466 | ||
1f0ef2aa DW |
1467 | void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, |
1468 | unsigned int size_order, u64 type) | |
3481f210 YS |
1469 | { |
1470 | u8 dw = 0, dr = 0; | |
1471 | ||
1472 | struct qi_desc desc; | |
1473 | int ih = 0; | |
1474 | ||
3481f210 YS |
1475 | if (cap_write_drain(iommu->cap)) |
1476 | dw = 1; | |
1477 | ||
1478 | if (cap_read_drain(iommu->cap)) | |
1479 | dr = 1; | |
1480 | ||
5d308fc1 | 1481 | desc.qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw) |
3481f210 | 1482 | | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE; |
5d308fc1 | 1483 | desc.qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih) |
3481f210 | 1484 | | QI_IOTLB_AM(size_order); |
5d308fc1 LB |
1485 | desc.qw2 = 0; |
1486 | desc.qw3 = 0; | |
3481f210 | 1487 | |
8a1d8246 | 1488 | qi_submit_sync(iommu, &desc, 1, 0); |
3481f210 YS |
1489 | } |
1490 | ||
1c48db44 JP |
1491 | void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, |
1492 | u16 qdep, u64 addr, unsigned mask) | |
6ba6c3a4 YZ |
1493 | { |
1494 | struct qi_desc desc; | |
1495 | ||
1496 | if (mask) { | |
c8acb28b | 1497 | addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1; |
5d308fc1 | 1498 | desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE; |
6ba6c3a4 | 1499 | } else |
5d308fc1 | 1500 | desc.qw1 = QI_DEV_IOTLB_ADDR(addr); |
6ba6c3a4 YZ |
1501 | |
1502 | if (qdep >= QI_DEV_IOTLB_MAX_INVS) | |
1503 | qdep = 0; | |
1504 | ||
5d308fc1 | 1505 | desc.qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) | |
1c48db44 | 1506 | QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid); |
5d308fc1 LB |
1507 | desc.qw2 = 0; |
1508 | desc.qw3 = 0; | |
6ba6c3a4 | 1509 | |
8a1d8246 | 1510 | qi_submit_sync(iommu, &desc, 1, 0); |
6ba6c3a4 YZ |
1511 | } |
1512 | ||
33cd6e64 LB |
1513 | /* PASID-based IOTLB invalidation */ |
1514 | void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, | |
1515 | unsigned long npages, bool ih) | |
1516 | { | |
1517 | struct qi_desc desc = {.qw2 = 0, .qw3 = 0}; | |
1518 | ||
1519 | /* | |
1520 | * npages == -1 means a PASID-selective invalidation, otherwise, | |
1521 | * a positive value for Page-selective-within-PASID invalidation. | |
1522 | * 0 is not a valid input. | |
1523 | */ | |
1524 | if (WARN_ON(!npages)) { | |
1525 | pr_err("Invalid input npages = %ld\n", npages); | |
1526 | return; | |
1527 | } | |
1528 | ||
1529 | if (npages == -1) { | |
1530 | desc.qw0 = QI_EIOTLB_PASID(pasid) | | |
1531 | QI_EIOTLB_DID(did) | | |
1532 | QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | | |
1533 | QI_EIOTLB_TYPE; | |
1534 | desc.qw1 = 0; | |
1535 | } else { | |
1536 | int mask = ilog2(__roundup_pow_of_two(npages)); | |
1537 | unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask)); | |
1538 | ||
1efd17e7 LB |
1539 | if (WARN_ON_ONCE(!IS_ALIGNED(addr, align))) |
1540 | addr = ALIGN_DOWN(addr, align); | |
33cd6e64 LB |
1541 | |
1542 | desc.qw0 = QI_EIOTLB_PASID(pasid) | | |
1543 | QI_EIOTLB_DID(did) | | |
1544 | QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | | |
1545 | QI_EIOTLB_TYPE; | |
1546 | desc.qw1 = QI_EIOTLB_ADDR(addr) | | |
1547 | QI_EIOTLB_IH(ih) | | |
1548 | QI_EIOTLB_AM(mask); | |
1549 | } | |
1550 | ||
8a1d8246 | 1551 | qi_submit_sync(iommu, &desc, 1, 0); |
33cd6e64 LB |
1552 | } |
1553 | ||
61a06a16 JP |
1554 | /* PASID-based device IOTLB Invalidate */ |
1555 | void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, | |
78df6c86 | 1556 | u32 pasid, u16 qdep, u64 addr, unsigned int size_order) |
61a06a16 JP |
1557 | { |
1558 | unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1); | |
1559 | struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0}; | |
1560 | ||
1561 | desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) | | |
1562 | QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE | | |
1563 | QI_DEV_IOTLB_PFSID(pfsid); | |
61a06a16 JP |
1564 | |
1565 | /* | |
1566 | * If S bit is 0, we only flush a single page. If S bit is set, | |
1567 | * The least significant zero bit indicates the invalidation address | |
1568 | * range. VT-d spec 6.5.2.6. | |
1569 | * e.g. address bit 12[0] indicates 8KB, 13[0] indicates 16KB. | |
1570 | * size order = 0 is PAGE_SIZE 4KB | |
1571 | * Max Invs Pending (MIP) is set to 0 for now until we have DIT in | |
1572 | * ECAP. | |
1573 | */ | |
494b3688 | 1574 | if (!IS_ALIGNED(addr, VTD_PAGE_SIZE << size_order)) |
288d08e7 LY |
1575 | pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n", |
1576 | addr, size_order); | |
1577 | ||
1578 | /* Take page address */ | |
1579 | desc.qw1 = QI_DEV_EIOTLB_ADDR(addr); | |
1580 | ||
1581 | if (size_order) { | |
1582 | /* | |
1583 | * Existing 0s in address below size_order may be the least | |
1584 | * significant bit, we must set them to 1s to avoid having | |
1585 | * smaller size than desired. | |
1586 | */ | |
1587 | desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1, | |
1588 | VTD_PAGE_SHIFT); | |
1589 | /* Clear size_order bit to indicate size */ | |
1590 | desc.qw1 &= ~mask; | |
1591 | /* Set the S bit to indicate flushing more than 1 page */ | |
61a06a16 | 1592 | desc.qw1 |= QI_DEV_EIOTLB_SIZE; |
288d08e7 | 1593 | } |
61a06a16 | 1594 | |
8a1d8246 | 1595 | qi_submit_sync(iommu, &desc, 1, 0); |
61a06a16 JP |
1596 | } |
1597 | ||
1598 | void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, | |
c7b6bac9 | 1599 | u64 granu, u32 pasid) |
61a06a16 JP |
1600 | { |
1601 | struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0}; | |
1602 | ||
1603 | desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) | | |
1604 | QI_PC_GRAN(granu) | QI_PC_TYPE; | |
8a1d8246 | 1605 | qi_submit_sync(iommu, &desc, 1, 0); |
61a06a16 JP |
1606 | } |
1607 | ||
eba67e5d SS |
1608 | /* |
1609 | * Disable Queued Invalidation interface. | |
1610 | */ | |
1611 | void dmar_disable_qi(struct intel_iommu *iommu) | |
1612 | { | |
1613 | unsigned long flags; | |
1614 | u32 sts; | |
1615 | cycles_t start_time = get_cycles(); | |
1616 | ||
1617 | if (!ecap_qis(iommu->ecap)) | |
1618 | return; | |
1619 | ||
1f5b3c3f | 1620 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d | 1621 | |
fda3bec1 | 1622 | sts = readl(iommu->reg + DMAR_GSTS_REG); |
eba67e5d SS |
1623 | if (!(sts & DMA_GSTS_QIES)) |
1624 | goto end; | |
1625 | ||
1626 | /* | |
1627 | * Give a chance to HW to complete the pending invalidation requests. | |
1628 | */ | |
1629 | while ((readl(iommu->reg + DMAR_IQT_REG) != | |
1630 | readl(iommu->reg + DMAR_IQH_REG)) && | |
1631 | (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time))) | |
1632 | cpu_relax(); | |
1633 | ||
1634 | iommu->gcmd &= ~DMA_GCMD_QIE; | |
eba67e5d SS |
1635 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
1636 | ||
1637 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, | |
1638 | !(sts & DMA_GSTS_QIES), sts); | |
1639 | end: | |
1f5b3c3f | 1640 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
1641 | } |
1642 | ||
eb4a52bc FY |
1643 | /* |
1644 | * Enable queued invalidation. | |
1645 | */ | |
1646 | static void __dmar_enable_qi(struct intel_iommu *iommu) | |
1647 | { | |
c416daa9 | 1648 | u32 sts; |
eb4a52bc FY |
1649 | unsigned long flags; |
1650 | struct q_inval *qi = iommu->qi; | |
5d308fc1 | 1651 | u64 val = virt_to_phys(qi->desc); |
eb4a52bc FY |
1652 | |
1653 | qi->free_head = qi->free_tail = 0; | |
1654 | qi->free_cnt = QI_LENGTH; | |
1655 | ||
5d308fc1 LB |
1656 | /* |
1657 | * Set DW=1 and QS=1 in IQA_REG when Scalable Mode capability | |
1658 | * is present. | |
1659 | */ | |
1660 | if (ecap_smts(iommu->ecap)) | |
1661 | val |= (1 << 11) | 1; | |
1662 | ||
1f5b3c3f | 1663 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eb4a52bc FY |
1664 | |
1665 | /* write zero to the tail reg */ | |
1666 | writel(0, iommu->reg + DMAR_IQT_REG); | |
1667 | ||
5d308fc1 | 1668 | dmar_writeq(iommu->reg + DMAR_IQA_REG, val); |
eb4a52bc | 1669 | |
eb4a52bc | 1670 | iommu->gcmd |= DMA_GCMD_QIE; |
c416daa9 | 1671 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
eb4a52bc FY |
1672 | |
1673 | /* Make sure hardware complete it */ | |
1674 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); | |
1675 | ||
1f5b3c3f | 1676 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eb4a52bc FY |
1677 | } |
1678 | ||
fe962e90 SS |
1679 | /* |
1680 | * Enable Queued Invalidation interface. This is a must to support | |
1681 | * interrupt-remapping. Also used by DMA-remapping, which replaces | |
1682 | * register based IOTLB invalidation. | |
1683 | */ | |
1684 | int dmar_enable_qi(struct intel_iommu *iommu) | |
1685 | { | |
fe962e90 | 1686 | struct q_inval *qi; |
751cafe3 | 1687 | struct page *desc_page; |
fe962e90 SS |
1688 | |
1689 | if (!ecap_qis(iommu->ecap)) | |
1690 | return -ENOENT; | |
1691 | ||
1692 | /* | |
1693 | * queued invalidation is already setup and enabled. | |
1694 | */ | |
1695 | if (iommu->qi) | |
1696 | return 0; | |
1697 | ||
fa4b57cc | 1698 | iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC); |
fe962e90 SS |
1699 | if (!iommu->qi) |
1700 | return -ENOMEM; | |
1701 | ||
1702 | qi = iommu->qi; | |
1703 | ||
5d308fc1 LB |
1704 | /* |
1705 | * Need two pages to accommodate 256 descriptors of 256 bits each | |
1706 | * if the remapping hardware supports scalable mode translation. | |
1707 | */ | |
1708 | desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, | |
1709 | !!ecap_smts(iommu->ecap)); | |
751cafe3 | 1710 | if (!desc_page) { |
fe962e90 | 1711 | kfree(qi); |
b707cb02 | 1712 | iommu->qi = NULL; |
fe962e90 SS |
1713 | return -ENOMEM; |
1714 | } | |
1715 | ||
751cafe3 SS |
1716 | qi->desc = page_address(desc_page); |
1717 | ||
6396bb22 | 1718 | qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC); |
fe962e90 SS |
1719 | if (!qi->desc_status) { |
1720 | free_page((unsigned long) qi->desc); | |
1721 | kfree(qi); | |
b707cb02 | 1722 | iommu->qi = NULL; |
fe962e90 SS |
1723 | return -ENOMEM; |
1724 | } | |
1725 | ||
3b8f4048 | 1726 | raw_spin_lock_init(&qi->q_lock); |
fe962e90 | 1727 | |
eb4a52bc | 1728 | __dmar_enable_qi(iommu); |
fe962e90 SS |
1729 | |
1730 | return 0; | |
1731 | } | |
0ac2491f SS |
1732 | |
1733 | /* iommu interrupt handling. Most stuff are MSI-like. */ | |
1734 | ||
9d783ba0 SS |
1735 | enum faulttype { |
1736 | DMA_REMAP, | |
1737 | INTR_REMAP, | |
1738 | UNKNOWN, | |
1739 | }; | |
1740 | ||
1741 | static const char *dma_remap_fault_reasons[] = | |
0ac2491f SS |
1742 | { |
1743 | "Software", | |
1744 | "Present bit in root entry is clear", | |
1745 | "Present bit in context entry is clear", | |
1746 | "Invalid context entry", | |
1747 | "Access beyond MGAW", | |
1748 | "PTE Write access is not set", | |
1749 | "PTE Read access is not set", | |
1750 | "Next page table ptr is invalid", | |
1751 | "Root table address invalid", | |
1752 | "Context table ptr is invalid", | |
1753 | "non-zero reserved fields in RTP", | |
1754 | "non-zero reserved fields in CTP", | |
1755 | "non-zero reserved fields in PTE", | |
4ecccd9e | 1756 | "PCE for translation request specifies blocking", |
0ac2491f | 1757 | }; |
9d783ba0 | 1758 | |
fd730007 KMP |
1759 | static const char * const dma_remap_sm_fault_reasons[] = { |
1760 | "SM: Invalid Root Table Address", | |
1761 | "SM: TTM 0 for request with PASID", | |
1762 | "SM: TTM 0 for page group request", | |
1763 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */ | |
1764 | "SM: Error attempting to access Root Entry", | |
1765 | "SM: Present bit in Root Entry is clear", | |
1766 | "SM: Non-zero reserved field set in Root Entry", | |
1767 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */ | |
1768 | "SM: Error attempting to access Context Entry", | |
1769 | "SM: Present bit in Context Entry is clear", | |
1770 | "SM: Non-zero reserved field set in the Context Entry", | |
1771 | "SM: Invalid Context Entry", | |
1772 | "SM: DTE field in Context Entry is clear", | |
1773 | "SM: PASID Enable field in Context Entry is clear", | |
1774 | "SM: PASID is larger than the max in Context Entry", | |
1775 | "SM: PRE field in Context-Entry is clear", | |
1776 | "SM: RID_PASID field error in Context-Entry", | |
1777 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */ | |
1778 | "SM: Error attempting to access the PASID Directory Entry", | |
1779 | "SM: Present bit in Directory Entry is clear", | |
1780 | "SM: Non-zero reserved field set in PASID Directory Entry", | |
1781 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */ | |
1782 | "SM: Error attempting to access PASID Table Entry", | |
1783 | "SM: Present bit in PASID Table Entry is clear", | |
1784 | "SM: Non-zero reserved field set in PASID Table Entry", | |
1785 | "SM: Invalid Scalable-Mode PASID Table Entry", | |
1786 | "SM: ERE field is clear in PASID Table Entry", | |
1787 | "SM: SRE field is clear in PASID Table Entry", | |
1788 | "Unknown", "Unknown",/* 0x5E-0x5F */ | |
1789 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x67 */ | |
1790 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x6F */ | |
1791 | "SM: Error attempting to access first-level paging entry", | |
1792 | "SM: Present bit in first-level paging entry is clear", | |
1793 | "SM: Non-zero reserved field set in first-level paging entry", | |
1794 | "SM: Error attempting to access FL-PML4 entry", | |
1795 | "SM: First-level entry address beyond MGAW in Nested translation", | |
1796 | "SM: Read permission error in FL-PML4 entry in Nested translation", | |
1797 | "SM: Read permission error in first-level paging entry in Nested translation", | |
1798 | "SM: Write permission error in first-level paging entry in Nested translation", | |
1799 | "SM: Error attempting to access second-level paging entry", | |
1800 | "SM: Read/Write permission error in second-level paging entry", | |
1801 | "SM: Non-zero reserved field set in second-level paging entry", | |
1802 | "SM: Invalid second-level page table pointer", | |
1803 | "SM: A/D bit update needed in second-level entry when set up in no snoop", | |
1804 | "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */ | |
1805 | "SM: Address in first-level translation is not canonical", | |
1806 | "SM: U/S set 0 for first-level translation with user privilege", | |
1807 | "SM: No execute permission for request with PASID and ER=1", | |
1808 | "SM: Address beyond the DMA hardware max", | |
1809 | "SM: Second-level entry address beyond the max", | |
1810 | "SM: No write permission for Write/AtomicOp request", | |
1811 | "SM: No read permission for Read/AtomicOp request", | |
1812 | "SM: Invalid address-interrupt address", | |
1813 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x8F */ | |
1814 | "SM: A/D bit update needed in first-level entry when set up in no snoop", | |
1815 | }; | |
1816 | ||
95a02e97 | 1817 | static const char *irq_remap_fault_reasons[] = |
9d783ba0 SS |
1818 | { |
1819 | "Detected reserved fields in the decoded interrupt-remapped request", | |
1820 | "Interrupt index exceeded the interrupt-remapping table size", | |
1821 | "Present field in the IRTE entry is clear", | |
1822 | "Error accessing interrupt-remapping table pointed by IRTA_REG", | |
1823 | "Detected reserved fields in the IRTE entry", | |
1824 | "Blocked a compatibility format interrupt request", | |
1825 | "Blocked an interrupt request due to source-id verification failure", | |
1826 | }; | |
1827 | ||
21004dcd | 1828 | static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type) |
0ac2491f | 1829 | { |
fefe1ed1 DC |
1830 | if (fault_reason >= 0x20 && (fault_reason - 0x20 < |
1831 | ARRAY_SIZE(irq_remap_fault_reasons))) { | |
9d783ba0 | 1832 | *fault_type = INTR_REMAP; |
95a02e97 | 1833 | return irq_remap_fault_reasons[fault_reason - 0x20]; |
fd730007 KMP |
1834 | } else if (fault_reason >= 0x30 && (fault_reason - 0x30 < |
1835 | ARRAY_SIZE(dma_remap_sm_fault_reasons))) { | |
1836 | *fault_type = DMA_REMAP; | |
1837 | return dma_remap_sm_fault_reasons[fault_reason - 0x30]; | |
9d783ba0 SS |
1838 | } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) { |
1839 | *fault_type = DMA_REMAP; | |
1840 | return dma_remap_fault_reasons[fault_reason]; | |
1841 | } else { | |
1842 | *fault_type = UNKNOWN; | |
0ac2491f | 1843 | return "Unknown"; |
9d783ba0 | 1844 | } |
0ac2491f SS |
1845 | } |
1846 | ||
1208225c DW |
1847 | |
1848 | static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq) | |
1849 | { | |
1850 | if (iommu->irq == irq) | |
1851 | return DMAR_FECTL_REG; | |
1852 | else if (iommu->pr_irq == irq) | |
1853 | return DMAR_PECTL_REG; | |
1854 | else | |
1855 | BUG(); | |
1856 | } | |
1857 | ||
5c2837fb | 1858 | void dmar_msi_unmask(struct irq_data *data) |
0ac2491f | 1859 | { |
dced35ae | 1860 | struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); |
1208225c | 1861 | int reg = dmar_msi_reg(iommu, data->irq); |
0ac2491f SS |
1862 | unsigned long flag; |
1863 | ||
1864 | /* unmask it */ | |
1f5b3c3f | 1865 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c | 1866 | writel(0, iommu->reg + reg); |
0ac2491f | 1867 | /* Read a reg to force flush the post write */ |
1208225c | 1868 | readl(iommu->reg + reg); |
1f5b3c3f | 1869 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1870 | } |
1871 | ||
5c2837fb | 1872 | void dmar_msi_mask(struct irq_data *data) |
0ac2491f | 1873 | { |
dced35ae | 1874 | struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); |
1208225c DW |
1875 | int reg = dmar_msi_reg(iommu, data->irq); |
1876 | unsigned long flag; | |
0ac2491f SS |
1877 | |
1878 | /* mask it */ | |
1f5b3c3f | 1879 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c | 1880 | writel(DMA_FECTL_IM, iommu->reg + reg); |
0ac2491f | 1881 | /* Read a reg to force flush the post write */ |
1208225c | 1882 | readl(iommu->reg + reg); |
1f5b3c3f | 1883 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1884 | } |
1885 | ||
1886 | void dmar_msi_write(int irq, struct msi_msg *msg) | |
1887 | { | |
dced35ae | 1888 | struct intel_iommu *iommu = irq_get_handler_data(irq); |
1208225c | 1889 | int reg = dmar_msi_reg(iommu, irq); |
0ac2491f SS |
1890 | unsigned long flag; |
1891 | ||
1f5b3c3f | 1892 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c DW |
1893 | writel(msg->data, iommu->reg + reg + 4); |
1894 | writel(msg->address_lo, iommu->reg + reg + 8); | |
1895 | writel(msg->address_hi, iommu->reg + reg + 12); | |
1f5b3c3f | 1896 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1897 | } |
1898 | ||
1899 | void dmar_msi_read(int irq, struct msi_msg *msg) | |
1900 | { | |
dced35ae | 1901 | struct intel_iommu *iommu = irq_get_handler_data(irq); |
1208225c | 1902 | int reg = dmar_msi_reg(iommu, irq); |
0ac2491f SS |
1903 | unsigned long flag; |
1904 | ||
1f5b3c3f | 1905 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c DW |
1906 | msg->data = readl(iommu->reg + reg + 4); |
1907 | msg->address_lo = readl(iommu->reg + reg + 8); | |
1908 | msg->address_hi = readl(iommu->reg + reg + 12); | |
1f5b3c3f | 1909 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1910 | } |
1911 | ||
1912 | static int dmar_fault_do_one(struct intel_iommu *iommu, int type, | |
c7b6bac9 | 1913 | u8 fault_reason, u32 pasid, u16 source_id, |
fd730007 | 1914 | unsigned long long addr) |
0ac2491f SS |
1915 | { |
1916 | const char *reason; | |
9d783ba0 | 1917 | int fault_type; |
0ac2491f | 1918 | |
9d783ba0 | 1919 | reason = dmar_get_fault_reason(fault_reason, &fault_type); |
0ac2491f | 1920 | |
914ff771 | 1921 | if (fault_type == INTR_REMAP) { |
0b482d0c | 1922 | pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index 0x%llx [fault reason 0x%02x] %s\n", |
719a1933 LB |
1923 | source_id >> 8, PCI_SLOT(source_id & 0xFF), |
1924 | PCI_FUNC(source_id & 0xFF), addr >> 48, | |
1925 | fault_reason, reason); | |
914ff771 KMP |
1926 | |
1927 | return 0; | |
1928 | } | |
1929 | ||
1930 | if (pasid == INVALID_IOASID) | |
0b482d0c | 1931 | pr_err("[%s NO_PASID] Request device [%02x:%02x.%d] fault addr 0x%llx [fault reason 0x%02x] %s\n", |
a0fe14d7 AW |
1932 | type ? "DMA Read" : "DMA Write", |
1933 | source_id >> 8, PCI_SLOT(source_id & 0xFF), | |
719a1933 | 1934 | PCI_FUNC(source_id & 0xFF), addr, |
fd730007 | 1935 | fault_reason, reason); |
719a1933 | 1936 | else |
0b482d0c | 1937 | pr_err("[%s PASID 0x%x] Request device [%02x:%02x.%d] fault addr 0x%llx [fault reason 0x%02x] %s\n", |
719a1933 LB |
1938 | type ? "DMA Read" : "DMA Write", pasid, |
1939 | source_id >> 8, PCI_SLOT(source_id & 0xFF), | |
1940 | PCI_FUNC(source_id & 0xFF), addr, | |
1941 | fault_reason, reason); | |
1942 | ||
914ff771 KMP |
1943 | dmar_fault_dump_ptes(iommu, source_id, addr, pasid); |
1944 | ||
0ac2491f SS |
1945 | return 0; |
1946 | } | |
1947 | ||
1948 | #define PRIMARY_FAULT_REG_LEN (16) | |
1531a6a6 | 1949 | irqreturn_t dmar_fault(int irq, void *dev_id) |
0ac2491f SS |
1950 | { |
1951 | struct intel_iommu *iommu = dev_id; | |
1952 | int reg, fault_index; | |
1953 | u32 fault_status; | |
1954 | unsigned long flag; | |
c43fce4e AW |
1955 | static DEFINE_RATELIMIT_STATE(rs, |
1956 | DEFAULT_RATELIMIT_INTERVAL, | |
1957 | DEFAULT_RATELIMIT_BURST); | |
1958 | ||
1f5b3c3f | 1959 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f | 1960 | fault_status = readl(iommu->reg + DMAR_FSTS_REG); |
6c50d79f | 1961 | if (fault_status && __ratelimit(&rs)) |
bf947fcb | 1962 | pr_err("DRHD: handling fault status reg %x\n", fault_status); |
0ac2491f SS |
1963 | |
1964 | /* TBD: ignore advanced fault log currently */ | |
1965 | if (!(fault_status & DMA_FSTS_PPF)) | |
bd5cdad0 | 1966 | goto unlock_exit; |
0ac2491f SS |
1967 | |
1968 | fault_index = dma_fsts_fault_record_index(fault_status); | |
1969 | reg = cap_fault_reg_offset(iommu->cap); | |
1970 | while (1) { | |
6c50d79f DS |
1971 | /* Disable printing, simply clear the fault when ratelimited */ |
1972 | bool ratelimited = !__ratelimit(&rs); | |
0ac2491f SS |
1973 | u8 fault_reason; |
1974 | u16 source_id; | |
1975 | u64 guest_addr; | |
c7b6bac9 FY |
1976 | u32 pasid; |
1977 | int type; | |
0ac2491f | 1978 | u32 data; |
fd730007 | 1979 | bool pasid_present; |
0ac2491f SS |
1980 | |
1981 | /* highest 32 bits */ | |
1982 | data = readl(iommu->reg + reg + | |
1983 | fault_index * PRIMARY_FAULT_REG_LEN + 12); | |
1984 | if (!(data & DMA_FRCD_F)) | |
1985 | break; | |
1986 | ||
c43fce4e AW |
1987 | if (!ratelimited) { |
1988 | fault_reason = dma_frcd_fault_reason(data); | |
1989 | type = dma_frcd_type(data); | |
0ac2491f | 1990 | |
fd730007 | 1991 | pasid = dma_frcd_pasid_value(data); |
c43fce4e AW |
1992 | data = readl(iommu->reg + reg + |
1993 | fault_index * PRIMARY_FAULT_REG_LEN + 8); | |
1994 | source_id = dma_frcd_source_id(data); | |
1995 | ||
fd730007 | 1996 | pasid_present = dma_frcd_pasid_present(data); |
c43fce4e AW |
1997 | guest_addr = dmar_readq(iommu->reg + reg + |
1998 | fault_index * PRIMARY_FAULT_REG_LEN); | |
1999 | guest_addr = dma_frcd_page_addr(guest_addr); | |
2000 | } | |
0ac2491f | 2001 | |
0ac2491f SS |
2002 | /* clear the fault */ |
2003 | writel(DMA_FRCD_F, iommu->reg + reg + | |
2004 | fault_index * PRIMARY_FAULT_REG_LEN + 12); | |
2005 | ||
1f5b3c3f | 2006 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f | 2007 | |
c43fce4e | 2008 | if (!ratelimited) |
fd730007 | 2009 | /* Using pasid -1 if pasid is not present */ |
c43fce4e | 2010 | dmar_fault_do_one(iommu, type, fault_reason, |
719a1933 | 2011 | pasid_present ? pasid : INVALID_IOASID, |
c43fce4e | 2012 | source_id, guest_addr); |
0ac2491f SS |
2013 | |
2014 | fault_index++; | |
8211a7b5 | 2015 | if (fault_index >= cap_num_fault_regs(iommu->cap)) |
0ac2491f | 2016 | fault_index = 0; |
1f5b3c3f | 2017 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f | 2018 | } |
0ac2491f | 2019 | |
973b5464 LB |
2020 | writel(DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_PRO, |
2021 | iommu->reg + DMAR_FSTS_REG); | |
bd5cdad0 LZH |
2022 | |
2023 | unlock_exit: | |
1f5b3c3f | 2024 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
2025 | return IRQ_HANDLED; |
2026 | } | |
2027 | ||
2028 | int dmar_set_interrupt(struct intel_iommu *iommu) | |
2029 | { | |
2030 | int irq, ret; | |
2031 | ||
9d783ba0 SS |
2032 | /* |
2033 | * Check if the fault interrupt is already initialized. | |
2034 | */ | |
2035 | if (iommu->irq) | |
2036 | return 0; | |
2037 | ||
34742db8 JL |
2038 | irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu); |
2039 | if (irq > 0) { | |
2040 | iommu->irq = irq; | |
2041 | } else { | |
9f10e5bf | 2042 | pr_err("No free IRQ vectors\n"); |
0ac2491f SS |
2043 | return -EINVAL; |
2044 | } | |
2045 | ||
477694e7 | 2046 | ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu); |
0ac2491f | 2047 | if (ret) |
9f10e5bf | 2048 | pr_err("Can't request irq\n"); |
0ac2491f SS |
2049 | return ret; |
2050 | } | |
9d783ba0 SS |
2051 | |
2052 | int __init enable_drhd_fault_handling(void) | |
2053 | { | |
2054 | struct dmar_drhd_unit *drhd; | |
7c919779 | 2055 | struct intel_iommu *iommu; |
9d783ba0 SS |
2056 | |
2057 | /* | |
2058 | * Enable fault control interrupt. | |
2059 | */ | |
7c919779 | 2060 | for_each_iommu(iommu, drhd) { |
bd5cdad0 | 2061 | u32 fault_status; |
7c919779 | 2062 | int ret = dmar_set_interrupt(iommu); |
9d783ba0 SS |
2063 | |
2064 | if (ret) { | |
e9071b0b | 2065 | pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n", |
9d783ba0 SS |
2066 | (unsigned long long)drhd->reg_base_addr, ret); |
2067 | return -1; | |
2068 | } | |
7f99d946 SS |
2069 | |
2070 | /* | |
2071 | * Clear any previous faults. | |
2072 | */ | |
2073 | dmar_fault(iommu->irq, iommu); | |
bd5cdad0 LZH |
2074 | fault_status = readl(iommu->reg + DMAR_FSTS_REG); |
2075 | writel(fault_status, iommu->reg + DMAR_FSTS_REG); | |
9d783ba0 SS |
2076 | } |
2077 | ||
2078 | return 0; | |
2079 | } | |
eb4a52bc FY |
2080 | |
2081 | /* | |
2082 | * Re-enable Queued Invalidation interface. | |
2083 | */ | |
2084 | int dmar_reenable_qi(struct intel_iommu *iommu) | |
2085 | { | |
2086 | if (!ecap_qis(iommu->ecap)) | |
2087 | return -ENOENT; | |
2088 | ||
2089 | if (!iommu->qi) | |
2090 | return -ENOENT; | |
2091 | ||
2092 | /* | |
2093 | * First disable queued invalidation. | |
2094 | */ | |
2095 | dmar_disable_qi(iommu); | |
2096 | /* | |
2097 | * Then enable queued invalidation again. Since there is no pending | |
2098 | * invalidation requests now, it's safe to re-enable queued | |
2099 | * invalidation. | |
2100 | */ | |
2101 | __dmar_enable_qi(iommu); | |
2102 | ||
2103 | return 0; | |
2104 | } | |
074835f0 YS |
2105 | |
2106 | /* | |
2107 | * Check interrupt remapping support in DMAR table description. | |
2108 | */ | |
0b8973a8 | 2109 | int __init dmar_ir_support(void) |
074835f0 YS |
2110 | { |
2111 | struct acpi_table_dmar *dmar; | |
2112 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
4f506e07 AP |
2113 | if (!dmar) |
2114 | return 0; | |
074835f0 YS |
2115 | return dmar->flags & 0x1; |
2116 | } | |
694835dc | 2117 | |
6b197249 JL |
2118 | /* Check whether DMAR units are in use */ |
2119 | static inline bool dmar_in_use(void) | |
2120 | { | |
2121 | return irq_remapping_enabled || intel_iommu_enabled; | |
2122 | } | |
2123 | ||
a868e6b7 JL |
2124 | static int __init dmar_free_unused_resources(void) |
2125 | { | |
2126 | struct dmar_drhd_unit *dmaru, *dmaru_n; | |
2127 | ||
6b197249 | 2128 | if (dmar_in_use()) |
a868e6b7 JL |
2129 | return 0; |
2130 | ||
2e455289 JL |
2131 | if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units)) |
2132 | bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb); | |
59ce0515 | 2133 | |
3a5670e8 | 2134 | down_write(&dmar_global_lock); |
a868e6b7 JL |
2135 | list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) { |
2136 | list_del(&dmaru->list); | |
2137 | dmar_free_drhd(dmaru); | |
2138 | } | |
3a5670e8 | 2139 | up_write(&dmar_global_lock); |
a868e6b7 JL |
2140 | |
2141 | return 0; | |
2142 | } | |
2143 | ||
2144 | late_initcall(dmar_free_unused_resources); | |
6b197249 JL |
2145 | |
2146 | /* | |
2147 | * DMAR Hotplug Support | |
2148 | * For more details, please refer to Intel(R) Virtualization Technology | |
2149 | * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8 | |
2150 | * "Remapping Hardware Unit Hot Plug". | |
2151 | */ | |
94116f81 AS |
2152 | static guid_t dmar_hp_guid = |
2153 | GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B, | |
2154 | 0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF); | |
6b197249 JL |
2155 | |
2156 | /* | |
2157 | * Currently there's only one revision and BIOS will not check the revision id, | |
2158 | * so use 0 for safety. | |
2159 | */ | |
2160 | #define DMAR_DSM_REV_ID 0 | |
2161 | #define DMAR_DSM_FUNC_DRHD 1 | |
2162 | #define DMAR_DSM_FUNC_ATSR 2 | |
2163 | #define DMAR_DSM_FUNC_RHSA 3 | |
31a75cbb | 2164 | #define DMAR_DSM_FUNC_SATC 4 |
6b197249 JL |
2165 | |
2166 | static inline bool dmar_detect_dsm(acpi_handle handle, int func) | |
2167 | { | |
94116f81 | 2168 | return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func); |
6b197249 JL |
2169 | } |
2170 | ||
2171 | static int dmar_walk_dsm_resource(acpi_handle handle, int func, | |
2172 | dmar_res_handler_t handler, void *arg) | |
2173 | { | |
2174 | int ret = -ENODEV; | |
2175 | union acpi_object *obj; | |
2176 | struct acpi_dmar_header *start; | |
2177 | struct dmar_res_callback callback; | |
2178 | static int res_type[] = { | |
2179 | [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT, | |
2180 | [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS, | |
2181 | [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY, | |
31a75cbb | 2182 | [DMAR_DSM_FUNC_SATC] = ACPI_DMAR_TYPE_SATC, |
6b197249 JL |
2183 | }; |
2184 | ||
2185 | if (!dmar_detect_dsm(handle, func)) | |
2186 | return 0; | |
2187 | ||
94116f81 | 2188 | obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, |
6b197249 JL |
2189 | func, NULL, ACPI_TYPE_BUFFER); |
2190 | if (!obj) | |
2191 | return -ENODEV; | |
2192 | ||
2193 | memset(&callback, 0, sizeof(callback)); | |
2194 | callback.cb[res_type[func]] = handler; | |
2195 | callback.arg[res_type[func]] = arg; | |
2196 | start = (struct acpi_dmar_header *)obj->buffer.pointer; | |
2197 | ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback); | |
2198 | ||
2199 | ACPI_FREE(obj); | |
2200 | ||
2201 | return ret; | |
2202 | } | |
2203 | ||
2204 | static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg) | |
2205 | { | |
2206 | int ret; | |
2207 | struct dmar_drhd_unit *dmaru; | |
2208 | ||
2209 | dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); | |
2210 | if (!dmaru) | |
2211 | return -ENODEV; | |
2212 | ||
2213 | ret = dmar_ir_hotplug(dmaru, true); | |
2214 | if (ret == 0) | |
2215 | ret = dmar_iommu_hotplug(dmaru, true); | |
2216 | ||
2217 | return ret; | |
2218 | } | |
2219 | ||
2220 | static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg) | |
2221 | { | |
2222 | int i, ret; | |
2223 | struct device *dev; | |
2224 | struct dmar_drhd_unit *dmaru; | |
2225 | ||
2226 | dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); | |
2227 | if (!dmaru) | |
2228 | return 0; | |
2229 | ||
2230 | /* | |
2231 | * All PCI devices managed by this unit should have been destroyed. | |
2232 | */ | |
194dc870 | 2233 | if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) { |
6b197249 JL |
2234 | for_each_active_dev_scope(dmaru->devices, |
2235 | dmaru->devices_cnt, i, dev) | |
2236 | return -EBUSY; | |
194dc870 | 2237 | } |
6b197249 JL |
2238 | |
2239 | ret = dmar_ir_hotplug(dmaru, false); | |
2240 | if (ret == 0) | |
2241 | ret = dmar_iommu_hotplug(dmaru, false); | |
2242 | ||
2243 | return ret; | |
2244 | } | |
2245 | ||
2246 | static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg) | |
2247 | { | |
2248 | struct dmar_drhd_unit *dmaru; | |
2249 | ||
2250 | dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); | |
2251 | if (dmaru) { | |
2252 | list_del_rcu(&dmaru->list); | |
2253 | synchronize_rcu(); | |
2254 | dmar_free_drhd(dmaru); | |
2255 | } | |
2256 | ||
2257 | return 0; | |
2258 | } | |
2259 | ||
2260 | static int dmar_hotplug_insert(acpi_handle handle) | |
2261 | { | |
2262 | int ret; | |
2263 | int drhd_count = 0; | |
2264 | ||
2265 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2266 | &dmar_validate_one_drhd, (void *)1); | |
2267 | if (ret) | |
2268 | goto out; | |
2269 | ||
2270 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2271 | &dmar_parse_one_drhd, (void *)&drhd_count); | |
2272 | if (ret == 0 && drhd_count == 0) { | |
2273 | pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n"); | |
2274 | goto out; | |
2275 | } else if (ret) { | |
2276 | goto release_drhd; | |
2277 | } | |
2278 | ||
2279 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA, | |
2280 | &dmar_parse_one_rhsa, NULL); | |
2281 | if (ret) | |
2282 | goto release_drhd; | |
2283 | ||
2284 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
2285 | &dmar_parse_one_atsr, NULL); | |
2286 | if (ret) | |
2287 | goto release_atsr; | |
2288 | ||
2289 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2290 | &dmar_hp_add_drhd, NULL); | |
2291 | if (!ret) | |
2292 | return 0; | |
2293 | ||
2294 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2295 | &dmar_hp_remove_drhd, NULL); | |
2296 | release_atsr: | |
2297 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
2298 | &dmar_release_one_atsr, NULL); | |
2299 | release_drhd: | |
2300 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2301 | &dmar_hp_release_drhd, NULL); | |
2302 | out: | |
2303 | return ret; | |
2304 | } | |
2305 | ||
2306 | static int dmar_hotplug_remove(acpi_handle handle) | |
2307 | { | |
2308 | int ret; | |
2309 | ||
2310 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
2311 | &dmar_check_one_atsr, NULL); | |
2312 | if (ret) | |
2313 | return ret; | |
2314 | ||
2315 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2316 | &dmar_hp_remove_drhd, NULL); | |
2317 | if (ret == 0) { | |
2318 | WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
2319 | &dmar_release_one_atsr, NULL)); | |
2320 | WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2321 | &dmar_hp_release_drhd, NULL)); | |
2322 | } else { | |
2323 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2324 | &dmar_hp_add_drhd, NULL); | |
2325 | } | |
2326 | ||
2327 | return ret; | |
2328 | } | |
2329 | ||
d35165a9 JL |
2330 | static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl, |
2331 | void *context, void **retval) | |
2332 | { | |
2333 | acpi_handle *phdl = retval; | |
2334 | ||
2335 | if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) { | |
2336 | *phdl = handle; | |
2337 | return AE_CTRL_TERMINATE; | |
2338 | } | |
2339 | ||
2340 | return AE_OK; | |
2341 | } | |
2342 | ||
6b197249 JL |
2343 | static int dmar_device_hotplug(acpi_handle handle, bool insert) |
2344 | { | |
2345 | int ret; | |
d35165a9 JL |
2346 | acpi_handle tmp = NULL; |
2347 | acpi_status status; | |
6b197249 JL |
2348 | |
2349 | if (!dmar_in_use()) | |
2350 | return 0; | |
2351 | ||
9cd4f143 LB |
2352 | /* |
2353 | * It's unlikely that any I/O board is hot added before the IOMMU | |
2354 | * subsystem is initialized. | |
2355 | */ | |
2356 | if (IS_ENABLED(CONFIG_INTEL_IOMMU) && !intel_iommu_enabled) | |
2357 | return -EOPNOTSUPP; | |
2358 | ||
d35165a9 JL |
2359 | if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) { |
2360 | tmp = handle; | |
2361 | } else { | |
2362 | status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, | |
2363 | ACPI_UINT32_MAX, | |
2364 | dmar_get_dsm_handle, | |
2365 | NULL, NULL, &tmp); | |
2366 | if (ACPI_FAILURE(status)) { | |
2367 | pr_warn("Failed to locate _DSM method.\n"); | |
2368 | return -ENXIO; | |
2369 | } | |
2370 | } | |
2371 | if (tmp == NULL) | |
6b197249 JL |
2372 | return 0; |
2373 | ||
2374 | down_write(&dmar_global_lock); | |
2375 | if (insert) | |
d35165a9 | 2376 | ret = dmar_hotplug_insert(tmp); |
6b197249 | 2377 | else |
d35165a9 | 2378 | ret = dmar_hotplug_remove(tmp); |
6b197249 JL |
2379 | up_write(&dmar_global_lock); |
2380 | ||
2381 | return ret; | |
2382 | } | |
2383 | ||
2384 | int dmar_device_add(acpi_handle handle) | |
2385 | { | |
2386 | return dmar_device_hotplug(handle, true); | |
2387 | } | |
2388 | ||
2389 | int dmar_device_remove(acpi_handle handle) | |
2390 | { | |
2391 | return dmar_device_hotplug(handle, false); | |
2392 | } | |
89a6079d LB |
2393 | |
2394 | /* | |
2395 | * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table | |
2396 | * | |
2397 | * Returns true if the platform has %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in | |
2398 | * the ACPI DMAR table. This means that the platform boot firmware has made | |
2399 | * sure no device can issue DMA outside of RMRR regions. | |
2400 | */ | |
2401 | bool dmar_platform_optin(void) | |
2402 | { | |
2403 | struct acpi_table_dmar *dmar; | |
2404 | acpi_status status; | |
2405 | bool ret; | |
2406 | ||
2407 | status = acpi_get_table(ACPI_SIG_DMAR, 0, | |
2408 | (struct acpi_table_header **)&dmar); | |
2409 | if (ACPI_FAILURE(status)) | |
2410 | return false; | |
2411 | ||
2412 | ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN); | |
2413 | acpi_put_table((struct acpi_table_header *)dmar); | |
2414 | ||
2415 | return ret; | |
2416 | } | |
2417 | EXPORT_SYMBOL_GPL(dmar_platform_optin); |