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3b20eb23 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
ba395927 | 2 | /* |
2f26e0a9 DW |
3 | * Copyright © 2006-2015, Intel Corporation. |
4 | * | |
5 | * Authors: Ashok Raj <ashok.raj@intel.com> | |
6 | * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
7 | * David Woodhouse <David.Woodhouse@intel.com> | |
ba395927 KA |
8 | */ |
9 | ||
10 | #ifndef _INTEL_IOMMU_H_ | |
11 | #define _INTEL_IOMMU_H_ | |
12 | ||
13 | #include <linux/types.h> | |
38717946 | 14 | #include <linux/iova.h> |
ba395927 | 15 | #include <linux/io.h> |
2f26e0a9 | 16 | #include <linux/idr.h> |
2f26e0a9 DW |
17 | #include <linux/mmu_notifier.h> |
18 | #include <linux/list.h> | |
b0119e87 | 19 | #include <linux/iommu.h> |
61012985 | 20 | #include <linux/io-64-nonatomic-lo-hi.h> |
9ddbfb42 | 21 | #include <linux/dmar.h> |
6ca69e58 | 22 | #include <linux/bitfield.h> |
ba949f4c | 23 | #include <linux/xarray.h> |
7232ab8b | 24 | #include <linux/perf_event.h> |
61012985 | 25 | |
fe962e90 | 26 | #include <asm/cacheflush.h> |
5b6985ce | 27 | #include <asm/iommu.h> |
04f261ac | 28 | #include <uapi/linux/iommufd.h> |
f661197e | 29 | |
ba395927 | 30 | /* |
daedaa33 | 31 | * VT-d hardware uses 4KiB page size regardless of host page size. |
ba395927 | 32 | */ |
daedaa33 LB |
33 | #define VTD_PAGE_SHIFT (12) |
34 | #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT) | |
35 | #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT) | |
36 | #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK) | |
37 | ||
38 | #define VTD_STRIDE_SHIFT (9) | |
39 | #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT) | |
40 | ||
ddf09b6d LB |
41 | #define DMA_PTE_READ BIT_ULL(0) |
42 | #define DMA_PTE_WRITE BIT_ULL(1) | |
43 | #define DMA_PTE_LARGE_PAGE BIT_ULL(7) | |
44 | #define DMA_PTE_SNP BIT_ULL(11) | |
45 | ||
46 | #define DMA_FL_PTE_PRESENT BIT_ULL(0) | |
16ecf10e | 47 | #define DMA_FL_PTE_US BIT_ULL(2) |
a8ce9ebb LB |
48 | #define DMA_FL_PTE_ACCESS BIT_ULL(5) |
49 | #define DMA_FL_PTE_DIRTY BIT_ULL(6) | |
ddf09b6d | 50 | #define DMA_FL_PTE_XD BIT_ULL(63) |
daedaa33 | 51 | |
f35f22cc JM |
52 | #define DMA_SL_PTE_DIRTY_BIT 9 |
53 | #define DMA_SL_PTE_DIRTY BIT_ULL(DMA_SL_PTE_DIRTY_BIT) | |
54 | ||
b0d1f874 JP |
55 | #define ADDR_WIDTH_5LEVEL (57) |
56 | #define ADDR_WIDTH_4LEVEL (48) | |
57 | ||
daedaa33 LB |
58 | #define CONTEXT_TT_MULTI_LEVEL 0 |
59 | #define CONTEXT_TT_DEV_IOTLB 1 | |
60 | #define CONTEXT_TT_PASS_THROUGH 2 | |
1c4f88b7 | 61 | #define CONTEXT_PASIDE BIT_ULL(3) |
ba395927 | 62 | |
daedaa33 LB |
63 | /* |
64 | * Intel IOMMU register specification per version 1.0 public spec. | |
65 | */ | |
ba395927 KA |
66 | #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ |
67 | #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ | |
68 | #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ | |
69 | #define DMAR_GCMD_REG 0x18 /* Global command register */ | |
70 | #define DMAR_GSTS_REG 0x1c /* Global status register */ | |
71 | #define DMAR_RTADDR_REG 0x20 /* Root entry table */ | |
72 | #define DMAR_CCMD_REG 0x28 /* Context command reg */ | |
73 | #define DMAR_FSTS_REG 0x34 /* Fault Status register */ | |
74 | #define DMAR_FECTL_REG 0x38 /* Fault control register */ | |
75 | #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ | |
76 | #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ | |
77 | #define DMAR_FEUADDR_REG 0x44 /* Upper address register */ | |
78 | #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ | |
79 | #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ | |
80 | #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ | |
81 | #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ | |
82 | #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ | |
83 | #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ | |
fe962e90 SS |
84 | #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */ |
85 | #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */ | |
6ba6c3a4 | 86 | #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */ |
fe962e90 | 87 | #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */ |
82aeef0b | 88 | #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */ |
6ca69e58 | 89 | #define DMAR_IQER_REG 0xb0 /* Invalidation queue error record register */ |
2ae21010 | 90 | #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */ |
1208225c DW |
91 | #define DMAR_PQH_REG 0xc0 /* Page request queue head register */ |
92 | #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */ | |
93 | #define DMAR_PQA_REG 0xd0 /* Page request queue address register */ | |
94 | #define DMAR_PRS_REG 0xdc /* Page request status register */ | |
95 | #define DMAR_PECTL_REG 0xe0 /* Page request event control register */ | |
96 | #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */ | |
97 | #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */ | |
98 | #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */ | |
4a2d80db SM |
99 | #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */ |
100 | #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */ | |
101 | #define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */ | |
102 | #define DMAR_MTRR_FIX16K_80000_REG 0x128 | |
103 | #define DMAR_MTRR_FIX16K_A0000_REG 0x130 | |
104 | #define DMAR_MTRR_FIX4K_C0000_REG 0x138 | |
105 | #define DMAR_MTRR_FIX4K_C8000_REG 0x140 | |
106 | #define DMAR_MTRR_FIX4K_D0000_REG 0x148 | |
107 | #define DMAR_MTRR_FIX4K_D8000_REG 0x150 | |
108 | #define DMAR_MTRR_FIX4K_E0000_REG 0x158 | |
109 | #define DMAR_MTRR_FIX4K_E8000_REG 0x160 | |
110 | #define DMAR_MTRR_FIX4K_F0000_REG 0x168 | |
111 | #define DMAR_MTRR_FIX4K_F8000_REG 0x170 | |
112 | #define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */ | |
113 | #define DMAR_MTRR_PHYSMASK0_REG 0x188 | |
114 | #define DMAR_MTRR_PHYSBASE1_REG 0x190 | |
115 | #define DMAR_MTRR_PHYSMASK1_REG 0x198 | |
116 | #define DMAR_MTRR_PHYSBASE2_REG 0x1a0 | |
117 | #define DMAR_MTRR_PHYSMASK2_REG 0x1a8 | |
118 | #define DMAR_MTRR_PHYSBASE3_REG 0x1b0 | |
119 | #define DMAR_MTRR_PHYSMASK3_REG 0x1b8 | |
120 | #define DMAR_MTRR_PHYSBASE4_REG 0x1c0 | |
121 | #define DMAR_MTRR_PHYSMASK4_REG 0x1c8 | |
122 | #define DMAR_MTRR_PHYSBASE5_REG 0x1d0 | |
123 | #define DMAR_MTRR_PHYSMASK5_REG 0x1d8 | |
124 | #define DMAR_MTRR_PHYSBASE6_REG 0x1e0 | |
125 | #define DMAR_MTRR_PHYSMASK6_REG 0x1e8 | |
126 | #define DMAR_MTRR_PHYSBASE7_REG 0x1f0 | |
127 | #define DMAR_MTRR_PHYSMASK7_REG 0x1f8 | |
128 | #define DMAR_MTRR_PHYSBASE8_REG 0x200 | |
129 | #define DMAR_MTRR_PHYSMASK8_REG 0x208 | |
130 | #define DMAR_MTRR_PHYSBASE9_REG 0x210 | |
131 | #define DMAR_MTRR_PHYSMASK9_REG 0x218 | |
a6a5006d KL |
132 | #define DMAR_PERFCAP_REG 0x300 |
133 | #define DMAR_PERFCFGOFF_REG 0x310 | |
134 | #define DMAR_PERFOVFOFF_REG 0x318 | |
135 | #define DMAR_PERFCNTROFF_REG 0x31c | |
4a0d4265 KL |
136 | #define DMAR_PERFINTRSTS_REG 0x324 |
137 | #define DMAR_PERFINTRCTL_REG 0x328 | |
a6a5006d | 138 | #define DMAR_PERFEVNTCAP_REG 0x380 |
dc578758 KL |
139 | #define DMAR_ECMD_REG 0x400 |
140 | #define DMAR_ECEO_REG 0x408 | |
141 | #define DMAR_ECRSP_REG 0x410 | |
142 | #define DMAR_ECCAP_REG 0x430 | |
4d99efb2 LB |
143 | #define DMAR_VCCAP_REG 0xe30 /* Virtual command capability register */ |
144 | #define DMAR_VCMD_REG 0xe00 /* Virtual command register */ | |
145 | #define DMAR_VCRSP_REG 0xe10 /* Virtual command response register */ | |
ba395927 | 146 | |
6ca69e58 LB |
147 | #define DMAR_IQER_REG_IQEI(reg) FIELD_GET(GENMASK_ULL(3, 0), reg) |
148 | #define DMAR_IQER_REG_ITESID(reg) FIELD_GET(GENMASK_ULL(47, 32), reg) | |
149 | #define DMAR_IQER_REG_ICESID(reg) FIELD_GET(GENMASK_ULL(63, 48), reg) | |
150 | ||
ba395927 | 151 | #define OFFSET_STRIDE (9) |
50d3fb56 | 152 | |
50d3fb56 DW |
153 | #define dmar_readq(a) readq(a) |
154 | #define dmar_writeq(a,v) writeq(v,a) | |
ba3b01d7 MD |
155 | #define dmar_readl(a) readl(a) |
156 | #define dmar_writel(a, v) writel(v, a) | |
ba395927 KA |
157 | |
158 | #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) | |
159 | #define DMAR_VER_MINOR(v) ((v) & 0x0f) | |
160 | ||
161 | /* | |
162 | * Decoding Capability Register | |
163 | */ | |
6ad931a2 | 164 | #define cap_esrtps(c) (((c) >> 63) & 1) |
eb5b2011 | 165 | #define cap_esirtps(c) (((c) >> 62) & 1) |
a6a5006d | 166 | #define cap_ecmds(c) (((c) >> 61) & 1) |
b722cb32 | 167 | #define cap_fl5lp_support(c) (((c) >> 60) & 1) |
07c09787 | 168 | #define cap_pi_support(c) (((c) >> 59) & 1) |
59103caa | 169 | #define cap_fl1gp_support(c) (((c) >> 56) & 1) |
ba395927 KA |
170 | #define cap_read_drain(c) (((c) >> 55) & 1) |
171 | #define cap_write_drain(c) (((c) >> 54) & 1) | |
172 | #define cap_max_amask_val(c) (((c) >> 48) & 0x3f) | |
173 | #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1) | |
174 | #define cap_pgsel_inv(c) (((c) >> 39) & 1) | |
175 | ||
176 | #define cap_super_page_val(c) (((c) >> 34) & 0xf) | |
177 | #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \ | |
178 | * OFFSET_STRIDE) + 21) | |
179 | ||
180 | #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16) | |
181 | #define cap_max_fault_reg_offset(c) \ | |
182 | (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16) | |
183 | ||
184 | #define cap_zlr(c) (((c) >> 22) & 1) | |
185 | #define cap_isoch(c) (((c) >> 23) & 1) | |
186 | #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1) | |
187 | #define cap_sagaw(c) (((c) >> 8) & 0x1f) | |
188 | #define cap_caching_mode(c) (((c) >> 7) & 1) | |
189 | #define cap_phmr(c) (((c) >> 6) & 1) | |
190 | #define cap_plmr(c) (((c) >> 5) & 1) | |
191 | #define cap_rwbf(c) (((c) >> 4) & 1) | |
192 | #define cap_afl(c) (((c) >> 3) & 1) | |
193 | #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7))) | |
194 | /* | |
195 | * Extended Capability Register | |
196 | */ | |
197 | ||
a6a5006d KL |
198 | #define ecap_pms(e) (((e) >> 51) & 0x1) |
199 | #define ecap_rps(e) (((e) >> 49) & 0x1) | |
6f7db75e | 200 | #define ecap_smpwc(e) (((e) >> 48) & 0x1) |
437f35e1 | 201 | #define ecap_flts(e) (((e) >> 47) & 0x1) |
6f7db75e | 202 | #define ecap_slts(e) (((e) >> 46) & 0x1) |
ad3d1902 | 203 | #define ecap_slads(e) (((e) >> 45) & 0x1) |
765b6a98 | 204 | #define ecap_smts(e) (((e) >> 43) & 0x1) |
ad3d1902 KMP |
205 | #define ecap_dit(e) (((e) >> 41) & 0x1) |
206 | #define ecap_pds(e) (((e) >> 42) & 0x1) | |
207 | #define ecap_pasid(e) (((e) >> 40) & 0x1) | |
208 | #define ecap_pss(e) (((e) >> 35) & 0x1f) | |
209 | #define ecap_eafs(e) (((e) >> 34) & 0x1) | |
210 | #define ecap_nwfs(e) (((e) >> 33) & 0x1) | |
211 | #define ecap_srs(e) (((e) >> 31) & 0x1) | |
212 | #define ecap_ers(e) (((e) >> 30) & 0x1) | |
213 | #define ecap_prs(e) (((e) >> 29) & 0x1) | |
214 | #define ecap_broken_pasid(e) (((e) >> 28) & 0x1) | |
215 | #define ecap_dis(e) (((e) >> 27) & 0x1) | |
216 | #define ecap_nest(e) (((e) >> 26) & 0x1) | |
217 | #define ecap_mts(e) (((e) >> 25) & 0x1) | |
ba395927 | 218 | #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) |
44caf2f3 | 219 | #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16) |
ba395927 | 220 | #define ecap_coherent(e) ((e) & 0x1) |
fe962e90 | 221 | #define ecap_qis(e) ((e) & 0x2) |
ad3d1902 KMP |
222 | #define ecap_pass_through(e) (((e) >> 6) & 0x1) |
223 | #define ecap_eim_support(e) (((e) >> 4) & 0x1) | |
224 | #define ecap_ir_support(e) (((e) >> 3) & 0x1) | |
93a23a72 | 225 | #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1) |
ad3d1902 KMP |
226 | #define ecap_max_handle_mask(e) (((e) >> 20) & 0xf) |
227 | #define ecap_sc_support(e) (((e) >> 7) & 0x1) /* Snooping Control */ | |
ba395927 | 228 | |
a6a5006d KL |
229 | /* |
230 | * Decoding Perf Capability Register | |
231 | */ | |
232 | #define pcap_num_cntr(p) ((p) & 0xffff) | |
233 | #define pcap_cntr_width(p) (((p) >> 16) & 0x7f) | |
234 | #define pcap_num_event_group(p) (((p) >> 24) & 0x1f) | |
235 | #define pcap_filters_mask(p) (((p) >> 32) & 0x1f) | |
236 | #define pcap_interrupt(p) (((p) >> 50) & 0x1) | |
237 | /* The counter stride is calculated as 2 ^ (x+10) bytes */ | |
238 | #define pcap_cntr_stride(p) (1ULL << ((((p) >> 52) & 0x7) + 10)) | |
239 | ||
240 | /* | |
241 | * Decoding Perf Event Capability Register | |
242 | */ | |
243 | #define pecap_es(p) ((p) & 0xfffffff) | |
244 | ||
3375303e JP |
245 | /* Virtual command interface capability */ |
246 | #define vccap_pasid(v) (((v) & DMA_VCS_PAS)) /* PASID allocation */ | |
247 | ||
ba395927 | 248 | /* IOTLB_REG */ |
3481f210 | 249 | #define DMA_TLB_FLUSH_GRANU_OFFSET 60 |
ba395927 KA |
250 | #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) |
251 | #define DMA_TLB_DSI_FLUSH (((u64)2) << 60) | |
252 | #define DMA_TLB_PSI_FLUSH (((u64)3) << 60) | |
aaa59306 CT |
253 | #define DMA_TLB_IIRG(type) ((type >> 60) & 3) |
254 | #define DMA_TLB_IAIG(val) (((val) >> 57) & 3) | |
ba395927 KA |
255 | #define DMA_TLB_READ_DRAIN (((u64)1) << 49) |
256 | #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) | |
257 | #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) | |
258 | #define DMA_TLB_IVT (((u64)1) << 63) | |
259 | #define DMA_TLB_IH_NONLEAF (((u64)1) << 6) | |
260 | #define DMA_TLB_MAX_SIZE (0x3f) | |
261 | ||
fe962e90 | 262 | /* INVALID_DESC */ |
3481f210 | 263 | #define DMA_CCMD_INVL_GRANU_OFFSET 61 |
aaa59306 CT |
264 | #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4) |
265 | #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4) | |
266 | #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4) | |
fe962e90 SS |
267 | #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7) |
268 | #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6) | |
269 | #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16))) | |
270 | #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6) | |
271 | #define DMA_ID_TLB_ADDR(addr) (addr) | |
272 | #define DMA_ID_TLB_ADDR_MASK(mask) (mask) | |
273 | ||
f8bab735 | 274 | /* PMEN_REG */ |
275 | #define DMA_PMEN_EPM (((u32)1)<<31) | |
276 | #define DMA_PMEN_PRS (((u32)1)<<0) | |
277 | ||
ba395927 KA |
278 | /* GCMD_REG */ |
279 | #define DMA_GCMD_TE (((u32)1) << 31) | |
280 | #define DMA_GCMD_SRTP (((u32)1) << 30) | |
281 | #define DMA_GCMD_SFL (((u32)1) << 29) | |
282 | #define DMA_GCMD_EAFL (((u32)1) << 28) | |
283 | #define DMA_GCMD_WBF (((u32)1) << 27) | |
2ae21010 SS |
284 | #define DMA_GCMD_QIE (((u32)1) << 26) |
285 | #define DMA_GCMD_SIRTP (((u32)1) << 24) | |
286 | #define DMA_GCMD_IRE (((u32) 1) << 25) | |
161fde08 | 287 | #define DMA_GCMD_CFI (((u32) 1) << 23) |
ba395927 KA |
288 | |
289 | /* GSTS_REG */ | |
290 | #define DMA_GSTS_TES (((u32)1) << 31) | |
291 | #define DMA_GSTS_RTPS (((u32)1) << 30) | |
292 | #define DMA_GSTS_FLS (((u32)1) << 29) | |
293 | #define DMA_GSTS_AFLS (((u32)1) << 28) | |
294 | #define DMA_GSTS_WBFS (((u32)1) << 27) | |
2ae21010 SS |
295 | #define DMA_GSTS_QIES (((u32)1) << 26) |
296 | #define DMA_GSTS_IRTPS (((u32)1) << 24) | |
297 | #define DMA_GSTS_IRES (((u32)1) << 25) | |
161fde08 | 298 | #define DMA_GSTS_CFIS (((u32)1) << 23) |
ba395927 | 299 | |
4423f5e7 | 300 | /* DMA_RTADDR_REG */ |
7373a8cc | 301 | #define DMA_RTADDR_SMT (((u64)1) << 10) |
4423f5e7 | 302 | |
ba395927 KA |
303 | /* CCMD_REG */ |
304 | #define DMA_CCMD_ICC (((u64)1) << 63) | |
305 | #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61) | |
306 | #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61) | |
307 | #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61) | |
308 | #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32) | |
309 | #define DMA_CCMD_MASK_NOBIT 0 | |
310 | #define DMA_CCMD_MASK_1BIT 1 | |
311 | #define DMA_CCMD_MASK_2BIT 2 | |
312 | #define DMA_CCMD_MASK_3BIT 3 | |
313 | #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16) | |
314 | #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff)) | |
315 | ||
dc578758 KL |
316 | /* ECMD_REG */ |
317 | #define DMA_MAX_NUM_ECMD 256 | |
318 | #define DMA_MAX_NUM_ECMDCAP (DMA_MAX_NUM_ECMD / 64) | |
319 | #define DMA_ECMD_REG_STEP 8 | |
320 | #define DMA_ECMD_ENABLE 0xf0 | |
321 | #define DMA_ECMD_DISABLE 0xf1 | |
322 | #define DMA_ECMD_FREEZE 0xf4 | |
323 | #define DMA_ECMD_UNFREEZE 0xf5 | |
324 | #define DMA_ECMD_OA_SHIFT 16 | |
325 | #define DMA_ECMD_ECRSP_IP 0x1 | |
326 | #define DMA_ECMD_ECCAP3 3 | |
327 | #define DMA_ECMD_ECCAP3_ECNTS BIT_ULL(48) | |
328 | #define DMA_ECMD_ECCAP3_DCNTS BIT_ULL(49) | |
329 | #define DMA_ECMD_ECCAP3_FCNTS BIT_ULL(52) | |
330 | #define DMA_ECMD_ECCAP3_UFCNTS BIT_ULL(53) | |
331 | #define DMA_ECMD_ECCAP3_ESSENTIAL (DMA_ECMD_ECCAP3_ECNTS | \ | |
332 | DMA_ECMD_ECCAP3_DCNTS | \ | |
333 | DMA_ECMD_ECCAP3_FCNTS | \ | |
334 | DMA_ECMD_ECCAP3_UFCNTS) | |
335 | ||
ba395927 KA |
336 | /* FECTL_REG */ |
337 | #define DMA_FECTL_IM (((u32)1) << 31) | |
338 | ||
339 | /* FSTS_REG */ | |
b1d03c1d DS |
340 | #define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */ |
341 | #define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */ | |
342 | #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */ | |
343 | #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */ | |
344 | #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */ | |
345 | #define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */ | |
ba395927 KA |
346 | #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff) |
347 | ||
348 | /* FRCD_REG, 32 bits access */ | |
349 | #define DMA_FRCD_F (((u32)1) << 31) | |
350 | #define dma_frcd_type(d) ((d >> 30) & 1) | |
351 | #define dma_frcd_fault_reason(c) (c & 0xff) | |
352 | #define dma_frcd_source_id(c) (c & 0xffff) | |
fd730007 KMP |
353 | #define dma_frcd_pasid_value(c) (((c) >> 8) & 0xfffff) |
354 | #define dma_frcd_pasid_present(c) (((c) >> 31) & 1) | |
5b6985ce FY |
355 | /* low 64 bit */ |
356 | #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT)) | |
357 | ||
46924008 DW |
358 | /* PRS_REG */ |
359 | #define DMA_PRS_PPR ((u32)1) | |
66ac4db3 LB |
360 | #define DMA_PRS_PRO ((u32)2) |
361 | ||
3375303e | 362 | #define DMA_VCS_PAS ((u64)1) |
46924008 | 363 | |
4a0d4265 KL |
364 | /* PERFINTRSTS_REG */ |
365 | #define DMA_PERFINTRSTS_PIS ((u32)1) | |
366 | ||
5b6985ce FY |
367 | #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ |
368 | do { \ | |
369 | cycles_t start_time = get_cycles(); \ | |
370 | while (1) { \ | |
371 | sts = op(iommu->reg + offset); \ | |
372 | if (cond) \ | |
373 | break; \ | |
cf1337f0 | 374 | if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ |
5b6985ce FY |
375 | panic("DMAR hardware is malfunctioning\n"); \ |
376 | cpu_relax(); \ | |
377 | } \ | |
378 | } while (0) | |
cf1337f0 | 379 | |
fe962e90 SS |
380 | #define QI_LENGTH 256 /* queue length */ |
381 | ||
382 | enum { | |
383 | QI_FREE, | |
384 | QI_IN_USE, | |
6ba6c3a4 YZ |
385 | QI_DONE, |
386 | QI_ABORT | |
fe962e90 SS |
387 | }; |
388 | ||
389 | #define QI_CC_TYPE 0x1 | |
390 | #define QI_IOTLB_TYPE 0x2 | |
391 | #define QI_DIOTLB_TYPE 0x3 | |
392 | #define QI_IEC_TYPE 0x4 | |
393 | #define QI_IWD_TYPE 0x5 | |
2f26e0a9 DW |
394 | #define QI_EIOTLB_TYPE 0x6 |
395 | #define QI_PC_TYPE 0x7 | |
396 | #define QI_DEIOTLB_TYPE 0x8 | |
a222a7f0 DW |
397 | #define QI_PGRP_RESP_TYPE 0x9 |
398 | #define QI_PSTRM_RESP_TYPE 0xa | |
fe962e90 SS |
399 | |
400 | #define QI_IEC_SELECTIVE (((u64)1) << 4) | |
401 | #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32)) | |
402 | #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27)) | |
403 | ||
404 | #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32) | |
405 | #define QI_IWD_STATUS_WRITE (((u64)1) << 5) | |
66ac4db3 | 406 | #define QI_IWD_FENCE (((u64)1) << 6) |
8a1d8246 | 407 | #define QI_IWD_PRQ_DRAIN (((u64)1) << 7) |
fe962e90 | 408 | |
3481f210 YS |
409 | #define QI_IOTLB_DID(did) (((u64)did) << 16) |
410 | #define QI_IOTLB_DR(dr) (((u64)dr) << 7) | |
411 | #define QI_IOTLB_DW(dw) (((u64)dw) << 6) | |
412 | #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4)) | |
5b6985ce | 413 | #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK) |
3481f210 | 414 | #define QI_IOTLB_IH(ih) (((u64)ih) << 6) |
61a06a16 | 415 | #define QI_IOTLB_AM(am) (((u8)am) & 0x3f) |
3481f210 YS |
416 | |
417 | #define QI_CC_FM(fm) (((u64)fm) << 48) | |
418 | #define QI_CC_SID(sid) (((u64)sid) << 32) | |
419 | #define QI_CC_DID(did) (((u64)did) << 16) | |
420 | #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4)) | |
421 | ||
6ba6c3a4 YZ |
422 | #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32) |
423 | #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16) | |
424 | #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) | |
4e7120d7 EA |
425 | #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ |
426 | ((u64)((pfsid >> 4) & 0xfff) << 52)) | |
6ba6c3a4 YZ |
427 | #define QI_DEV_IOTLB_SIZE 1 |
428 | #define QI_DEV_IOTLB_MAX_INVS 32 | |
429 | ||
2f26e0a9 DW |
430 | #define QI_PC_PASID(pasid) (((u64)pasid) << 32) |
431 | #define QI_PC_DID(did) (((u64)did) << 16) | |
432 | #define QI_PC_GRAN(gran) (((u64)gran) << 4) | |
433 | ||
61a06a16 JP |
434 | /* PASID cache invalidation granu */ |
435 | #define QI_PC_ALL_PASIDS 0 | |
436 | #define QI_PC_PASID_SEL 1 | |
c0474a60 | 437 | #define QI_PC_GLOBAL 3 |
2f26e0a9 DW |
438 | |
439 | #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) | |
2f26e0a9 | 440 | #define QI_EIOTLB_IH(ih) (((u64)ih) << 6) |
61a06a16 | 441 | #define QI_EIOTLB_AM(am) (((u64)am) & 0x3f) |
2f26e0a9 DW |
442 | #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32) |
443 | #define QI_EIOTLB_DID(did) (((u64)did) << 16) | |
444 | #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4) | |
445 | ||
61a06a16 JP |
446 | /* QI Dev-IOTLB inv granu */ |
447 | #define QI_DEV_IOTLB_GRAN_ALL 1 | |
448 | #define QI_DEV_IOTLB_GRAN_PASID_SEL 0 | |
449 | ||
2f26e0a9 DW |
450 | #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) |
451 | #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) | |
5f77d6ca | 452 | #define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32) |
aaa59306 CT |
453 | #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16) |
454 | #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) | |
4e7120d7 EA |
455 | #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ |
456 | ((u64)((pfsid >> 4) & 0xfff) << 52)) | |
2f26e0a9 DW |
457 | #define QI_DEV_EIOTLB_MAX_INVS 32 |
458 | ||
5b438f4b | 459 | /* Page group response descriptor QW0 */ |
a222a7f0 | 460 | #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4) |
5b438f4b JP |
461 | #define QI_PGRP_PDP(p) (((u64)(p)) << 5) |
462 | #define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12) | |
463 | #define QI_PGRP_DID(rid) (((u64)(rid)) << 16) | |
464 | #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32) | |
465 | ||
466 | /* Page group response descriptor QW1 */ | |
467 | #define QI_PGRP_LPIG(x) (((u64)(x)) << 2) | |
468 | #define QI_PGRP_IDX(idx) (((u64)(idx)) << 3) | |
a222a7f0 | 469 | |
a222a7f0 DW |
470 | |
471 | #define QI_RESP_SUCCESS 0x0 | |
472 | #define QI_RESP_INVALID 0x1 | |
473 | #define QI_RESP_FAILURE 0xf | |
474 | ||
2f26e0a9 DW |
475 | #define QI_GRAN_NONG_PASID 2 |
476 | #define QI_GRAN_PSI_PASID 3 | |
477 | ||
5d308fc1 LB |
478 | #define qi_shift(iommu) (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap)) |
479 | ||
fe962e90 | 480 | struct qi_desc { |
5d308fc1 LB |
481 | u64 qw0; |
482 | u64 qw1; | |
483 | u64 qw2; | |
484 | u64 qw3; | |
fe962e90 SS |
485 | }; |
486 | ||
487 | struct q_inval { | |
3b8f4048 | 488 | raw_spinlock_t q_lock; |
5d308fc1 | 489 | void *desc; /* invalidation queue */ |
fe962e90 SS |
490 | int *desc_status; /* desc status */ |
491 | int free_head; /* first free entry */ | |
492 | int free_tail; /* last free entry */ | |
493 | int free_cnt; | |
494 | }; | |
495 | ||
d82e6ae6 LB |
496 | /* Page Request Queue depth */ |
497 | #define PRQ_ORDER 4 | |
498 | #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20) | |
499 | #define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5) | |
500 | ||
85a8dfc5 TG |
501 | struct dmar_pci_notify_info; |
502 | ||
d3f13810 | 503 | #ifdef CONFIG_IRQ_REMAP |
2ae21010 SS |
504 | /* 1MB - maximum possible interrupt remapping table size */ |
505 | #define INTR_REMAP_PAGE_ORDER 8 | |
506 | #define INTR_REMAP_TABLE_REG_SIZE 0xf | |
af3b358e | 507 | #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf |
2ae21010 | 508 | |
b6fcb33a SS |
509 | #define INTR_REMAP_TABLE_ENTRIES 65536 |
510 | ||
b106ee63 JL |
511 | struct irq_domain; |
512 | ||
2ae21010 SS |
513 | struct ir_table { |
514 | struct irte *base; | |
360eb3c5 | 515 | unsigned long *bitmap; |
2ae21010 | 516 | }; |
85a8dfc5 TG |
517 | |
518 | void intel_irq_remap_add_device(struct dmar_pci_notify_info *info); | |
519 | #else | |
520 | static inline void | |
521 | intel_irq_remap_add_device(struct dmar_pci_notify_info *info) { } | |
2ae21010 SS |
522 | #endif |
523 | ||
a77b67d4 | 524 | struct iommu_flush { |
4c25a2c1 DW |
525 | void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid, |
526 | u8 fm, u64 type); | |
1f0ef2aa DW |
527 | void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr, |
528 | unsigned int size_order, u64 type); | |
a77b67d4 YS |
529 | }; |
530 | ||
f59c7b69 FY |
531 | enum { |
532 | SR_DMAR_FECTL_REG, | |
533 | SR_DMAR_FEDATA_REG, | |
534 | SR_DMAR_FEADDR_REG, | |
535 | SR_DMAR_FEUADDR_REG, | |
536 | MAX_SR_DMAR_REGS | |
537 | }; | |
538 | ||
4158c2ec JR |
539 | #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0) |
540 | #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1) | |
ff3dc652 | 541 | #define VTD_FLAG_SVM_CAPABLE (1 << 2) |
4158c2ec | 542 | |
cdd3a249 SPP |
543 | #define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap)) |
544 | #define pasid_supported(iommu) (sm_supported(iommu) && \ | |
545 | ecap_pasid((iommu)->ecap)) | |
f35f22cc JM |
546 | #define ssads_supported(iommu) (sm_supported(iommu) && \ |
547 | ecap_slads((iommu)->ecap)) | |
a2cdecdf YL |
548 | #define nested_supported(iommu) (sm_supported(iommu) && \ |
549 | ecap_nest((iommu)->ecap)) | |
cdd3a249 | 550 | |
8a94ade4 DW |
551 | struct pasid_entry; |
552 | struct pasid_state_entry; | |
a222a7f0 | 553 | struct page_req_dsc; |
8a94ade4 | 554 | |
26b86092 SM |
555 | /* |
556 | * 0: Present | |
557 | * 1-11: Reserved | |
558 | * 12-63: Context Ptr (12 - (haw-1)) | |
559 | * 64-127: Reserved | |
560 | */ | |
561 | struct root_entry { | |
562 | u64 lo; | |
563 | u64 hi; | |
564 | }; | |
565 | ||
566 | /* | |
567 | * low 64 bits: | |
568 | * 0: present | |
569 | * 1: fault processing disable | |
570 | * 2-3: translation type | |
571 | * 12-63: address space root | |
572 | * high 64 bits: | |
573 | * 0-2: address width | |
574 | * 3-6: aval | |
575 | * 8-23: domain id | |
576 | */ | |
577 | struct context_entry { | |
578 | u64 lo; | |
579 | u64 hi; | |
580 | }; | |
581 | ||
ba949f4c LB |
582 | struct iommu_domain_info { |
583 | struct intel_iommu *iommu; | |
584 | unsigned int refcnt; /* Refcount of devices per iommu */ | |
585 | u16 did; /* Domain ids per IOMMU. Use u16 since | |
9ddbfb42 LB |
586 | * domain ids are 16 bit wide according |
587 | * to VT-d spec, section 9.3 */ | |
ba949f4c LB |
588 | }; |
589 | ||
590 | struct dmar_domain { | |
591 | int nid; /* node id */ | |
592 | struct xarray iommu_array; /* Attached IOMMU array */ | |
9ddbfb42 | 593 | |
1f106ff0 PP |
594 | u8 has_iotlb_device: 1; |
595 | u8 iommu_coherency: 1; /* indicate coherency of iommu access */ | |
6043257b | 596 | u8 force_snooping : 1; /* Create IOPTEs with snoop control */ |
fc0051cb | 597 | u8 set_pte_snp:1; |
e5b0feb4 LB |
598 | u8 use_first_level:1; /* DMA translation for the domain goes |
599 | * through the first level page table, | |
600 | * otherwise, goes through the second | |
601 | * level. | |
602 | */ | |
f35f22cc | 603 | u8 dirty_tracking:1; /* Dirty tracking is enabled */ |
b41e38e2 | 604 | u8 nested_parent:1; /* Has other domains nested on it */ |
e645c20e LB |
605 | u8 has_mappings:1; /* Has mappings configured through |
606 | * iommu_map() interface. | |
607 | */ | |
1f106ff0 | 608 | |
5eaafdf0 | 609 | spinlock_t lock; /* Protect device tracking lists */ |
9ddbfb42 | 610 | struct list_head devices; /* all devices' list */ |
7d0c9da6 | 611 | struct list_head dev_pasids; /* all attached pasids */ |
9ddbfb42 | 612 | |
9ddbfb42 LB |
613 | int iommu_superpage;/* Level of superpages supported: |
614 | 0 == 4KiB (no superpages), 1 == 2MiB, | |
615 | 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ | |
04f261ac LB |
616 | union { |
617 | /* DMA remapping domain */ | |
618 | struct { | |
619 | /* virtual address */ | |
620 | struct dma_pte *pgd; | |
621 | /* max guest address width */ | |
622 | int gaw; | |
623 | /* | |
624 | * adjusted guest address width: | |
625 | * 0: level 2 30-bit | |
626 | * 1: level 3 39-bit | |
627 | * 2: level 4 48-bit | |
628 | * 3: level 5 57-bit | |
629 | */ | |
630 | int agaw; | |
631 | /* maximum mapped address */ | |
632 | u64 max_addr; | |
633 | }; | |
634 | ||
635 | /* Nested user domain */ | |
636 | struct { | |
637 | /* parent page table which the user domain is nested on */ | |
638 | struct dmar_domain *s2_domain; | |
639 | /* user page table pointer (in GPA) */ | |
640 | unsigned long s1_pgtbl; | |
641 | /* page table attributes */ | |
642 | struct iommu_hwpt_vtd_s1 s1_cfg; | |
643 | }; | |
644 | }; | |
9ddbfb42 LB |
645 | |
646 | struct iommu_domain domain; /* generic domain data structure for | |
647 | iommu core */ | |
648 | }; | |
649 | ||
7232ab8b KL |
650 | /* |
651 | * In theory, the VT-d 4.0 spec can support up to 2 ^ 16 counters. | |
652 | * But in practice, there are only 14 counters for the existing | |
653 | * platform. Setting the max number of counters to 64 should be good | |
654 | * enough for a long time. Also, supporting more than 64 counters | |
655 | * requires more extras, e.g., extra freeze and overflow registers, | |
656 | * which is not necessary for now. | |
657 | */ | |
658 | #define IOMMU_PMU_IDX_MAX 64 | |
659 | ||
a6a5006d KL |
660 | struct iommu_pmu { |
661 | struct intel_iommu *iommu; | |
662 | u32 num_cntr; /* Number of counters */ | |
663 | u32 num_eg; /* Number of event group */ | |
664 | u32 cntr_width; /* Counter width */ | |
665 | u32 cntr_stride; /* Counter Stride */ | |
666 | u32 filter; /* Bitmask of filter support */ | |
667 | void __iomem *base; /* the PerfMon base address */ | |
668 | void __iomem *cfg_reg; /* counter configuration base address */ | |
669 | void __iomem *cntr_reg; /* counter 0 address*/ | |
670 | void __iomem *overflow; /* overflow status register */ | |
671 | ||
672 | u64 *evcap; /* Indicates all supported events */ | |
673 | u32 **cntr_evcap; /* Supported events of each counter. */ | |
7232ab8b KL |
674 | |
675 | struct pmu pmu; | |
676 | DECLARE_BITMAP(used_mask, IOMMU_PMU_IDX_MAX); | |
677 | struct perf_event *event_list[IOMMU_PMU_IDX_MAX]; | |
4a0d4265 | 678 | unsigned char irq_name[16]; |
16812c96 KL |
679 | struct hlist_node cpuhp_node; |
680 | int cpu; | |
a6a5006d KL |
681 | }; |
682 | ||
4a0d4265 KL |
683 | #define IOMMU_IRQ_ID_OFFSET_PRQ (DMAR_UNITS_SUPPORTED) |
684 | #define IOMMU_IRQ_ID_OFFSET_PERF (2 * DMAR_UNITS_SUPPORTED) | |
685 | ||
ba395927 KA |
686 | struct intel_iommu { |
687 | void __iomem *reg; /* Pointer to hardware regs, virtual addr */ | |
6f5cf521 DD |
688 | u64 reg_phys; /* physical address of hw register set */ |
689 | u64 reg_size; /* size of hw register set */ | |
ba395927 KA |
690 | u64 cap; |
691 | u64 ecap; | |
3375303e | 692 | u64 vccap; |
dc578758 | 693 | u64 ecmdcap[DMA_MAX_NUM_ECMDCAP]; |
ba395927 | 694 | u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ |
1f5b3c3f | 695 | raw_spinlock_t register_lock; /* protect register handling */ |
c42d9f32 | 696 | int seq_id; /* sequence id of the iommu */ |
1b573683 | 697 | int agaw; /* agaw of this iommu */ |
4ed0d3e6 | 698 | int msagaw; /* max sagaw of this iommu */ |
4a0d4265 | 699 | unsigned int irq, pr_irq, perf_irq; |
67ccac41 | 700 | u16 segment; /* PCI segment# */ |
9d783ba0 | 701 | unsigned char name[13]; /* Device Name */ |
e61d98d8 | 702 | |
d3f13810 | 703 | #ifdef CONFIG_INTEL_IOMMU |
e61d98d8 | 704 | unsigned long *domain_ids; /* bitmap of domains */ |
0c5f6c0d | 705 | unsigned long *copied_tables; /* bitmap of copied tables */ |
e61d98d8 | 706 | spinlock_t lock; /* protect context, domain ids */ |
ba395927 KA |
707 | struct root_entry *root_entry; /* virtual address */ |
708 | ||
a77b67d4 | 709 | struct iommu_flush flush; |
8a94ade4 DW |
710 | #endif |
711 | #ifdef CONFIG_INTEL_IOMMU_SVM | |
a222a7f0 DW |
712 | struct page_req_dsc *prq; |
713 | unsigned char prq_name[16]; /* Name for PRQ interrupt */ | |
06f4b8d0 | 714 | unsigned long prq_seq_number; |
66ac4db3 | 715 | struct completion prq_complete; |
e61d98d8 | 716 | #endif |
4c82b886 LB |
717 | struct iopf_queue *iopf_queue; |
718 | unsigned char iopfq_name[16]; | |
fe962e90 | 719 | struct q_inval *qi; /* Queued invalidation info */ |
59df44bf | 720 | u32 iommu_state[MAX_SR_DMAR_REGS]; /* Store iommu states between suspend and resume.*/ |
f59c7b69 | 721 | |
d3f13810 | 722 | #ifdef CONFIG_IRQ_REMAP |
2ae21010 | 723 | struct ir_table *ir_table; /* Interrupt remapping info */ |
b106ee63 | 724 | struct irq_domain *ir_domain; |
2ae21010 | 725 | #endif |
b0119e87 | 726 | struct iommu_device iommu; /* IOMMU core code handle */ |
ee34b32d | 727 | int node; |
4158c2ec | 728 | u32 flags; /* Software defined flags */ |
b1012ca8 LB |
729 | |
730 | struct dmar_drhd_unit *drhd; | |
55ee5e67 | 731 | void *perf_statistic; |
a6a5006d KL |
732 | |
733 | struct iommu_pmu *pmu; | |
ba395927 KA |
734 | }; |
735 | ||
9ddbfb42 LB |
736 | /* PCI domain-device relationship */ |
737 | struct device_domain_info { | |
738 | struct list_head link; /* link to domain siblings */ | |
4fda230e | 739 | u32 segment; /* PCI segment number */ |
9ddbfb42 LB |
740 | u8 bus; /* PCI bus number */ |
741 | u8 devfn; /* PCI devfn number */ | |
742 | u16 pfsid; /* SRIOV physical function source ID */ | |
743 | u8 pasid_supported:3; | |
744 | u8 pasid_enabled:1; | |
745 | u8 pri_supported:1; | |
746 | u8 pri_enabled:1; | |
747 | u8 ats_supported:1; | |
748 | u8 ats_enabled:1; | |
e65a6897 | 749 | u8 dtlb_extra_inval:1; /* Quirk for devices need extra flush */ |
9ddbfb42 LB |
750 | u8 ats_qdep; |
751 | struct device *dev; /* it's NULL for PCIe-to-PCI bridge */ | |
752 | struct intel_iommu *iommu; /* IOMMU used by this device */ | |
753 | struct dmar_domain *domain; /* pointer to domain */ | |
cc580e41 | 754 | struct pasid_table *pasid_table; /* pasid table */ |
d87731f6 JL |
755 | #ifdef CONFIG_INTEL_IOMMU_DEBUGFS |
756 | struct dentry *debugfs_dentry; /* pointer to device directory dentry */ | |
757 | #endif | |
9ddbfb42 LB |
758 | }; |
759 | ||
7d0c9da6 LB |
760 | struct dev_pasid_info { |
761 | struct list_head link_domain; /* link to domain siblings */ | |
762 | struct device *dev; | |
763 | ioasid_t pasid; | |
d87731f6 JL |
764 | #ifdef CONFIG_INTEL_IOMMU_DEBUGFS |
765 | struct dentry *debugfs_dentry; /* pointer to pasid directory dentry */ | |
766 | #endif | |
7d0c9da6 LB |
767 | }; |
768 | ||
fe962e90 SS |
769 | static inline void __iommu_flush_cache( |
770 | struct intel_iommu *iommu, void *addr, int size) | |
771 | { | |
772 | if (!ecap_coherent(iommu->ecap)) | |
773 | clflush_cache_range(addr, size); | |
774 | } | |
775 | ||
3db9983e JP |
776 | /* Convert generic struct iommu_domain to private struct dmar_domain */ |
777 | static inline struct dmar_domain *to_dmar_domain(struct iommu_domain *dom) | |
778 | { | |
779 | return container_of(dom, struct dmar_domain, domain); | |
780 | } | |
781 | ||
ba949f4c LB |
782 | /* Retrieve the domain ID which has allocated to the domain */ |
783 | static inline u16 | |
784 | domain_id_iommu(struct dmar_domain *domain, struct intel_iommu *iommu) | |
785 | { | |
786 | struct iommu_domain_info *info = | |
787 | xa_load(&domain->iommu_array, iommu->seq_id); | |
788 | ||
789 | return info->did; | |
790 | } | |
791 | ||
4f2ed183 LB |
792 | /* |
793 | * 0: readable | |
794 | * 1: writable | |
795 | * 2-6: reserved | |
796 | * 7: super page | |
797 | * 8-10: available | |
798 | * 11: snoop behavior | |
ed8188a0 | 799 | * 12-63: Host physical address |
4f2ed183 LB |
800 | */ |
801 | struct dma_pte { | |
802 | u64 val; | |
803 | }; | |
804 | ||
805 | static inline void dma_clear_pte(struct dma_pte *pte) | |
806 | { | |
807 | pte->val = 0; | |
808 | } | |
809 | ||
810 | static inline u64 dma_pte_addr(struct dma_pte *pte) | |
811 | { | |
812 | #ifdef CONFIG_64BIT | |
ddf09b6d | 813 | return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD); |
4f2ed183 LB |
814 | #else |
815 | /* Must have a full atomic 64-bit read */ | |
ddf09b6d LB |
816 | return __cmpxchg64(&pte->val, 0ULL, 0ULL) & |
817 | VTD_PAGE_MASK & (~DMA_FL_PTE_XD); | |
4f2ed183 LB |
818 | #endif |
819 | } | |
820 | ||
821 | static inline bool dma_pte_present(struct dma_pte *pte) | |
822 | { | |
823 | return (pte->val & 3) != 0; | |
824 | } | |
825 | ||
f35f22cc JM |
826 | static inline bool dma_sl_pte_test_and_clear_dirty(struct dma_pte *pte, |
827 | unsigned long flags) | |
828 | { | |
829 | if (flags & IOMMU_DIRTY_NO_CLEAR) | |
830 | return (pte->val & DMA_SL_PTE_DIRTY) != 0; | |
831 | ||
832 | return test_and_clear_bit(DMA_SL_PTE_DIRTY_BIT, | |
833 | (unsigned long *)&pte->val); | |
834 | } | |
835 | ||
4f2ed183 LB |
836 | static inline bool dma_pte_superpage(struct dma_pte *pte) |
837 | { | |
838 | return (pte->val & DMA_PTE_LARGE_PAGE); | |
839 | } | |
840 | ||
37c8041a | 841 | static inline bool first_pte_in_page(struct dma_pte *pte) |
4f2ed183 | 842 | { |
37c8041a | 843 | return IS_ALIGNED((unsigned long)pte, VTD_PAGE_SIZE); |
4f2ed183 LB |
844 | } |
845 | ||
9906b935 LM |
846 | static inline int nr_pte_to_next_page(struct dma_pte *pte) |
847 | { | |
848 | return first_pte_in_page(pte) ? BIT_ULL(VTD_STRIDE_SHIFT) : | |
849 | (struct dma_pte *)ALIGN((unsigned long)pte, VTD_PAGE_SIZE) - pte; | |
850 | } | |
851 | ||
0c5f6c0d LB |
852 | static inline bool context_present(struct context_entry *context) |
853 | { | |
854 | return (context->lo & 1); | |
855 | } | |
856 | ||
a06c2ece | 857 | struct dmar_drhd_unit *dmar_find_matched_drhd_unit(struct pci_dev *dev); |
e61d98d8 | 858 | |
a06c2ece LB |
859 | int dmar_enable_qi(struct intel_iommu *iommu); |
860 | void dmar_disable_qi(struct intel_iommu *iommu); | |
861 | int dmar_reenable_qi(struct intel_iommu *iommu); | |
862 | void qi_global_iec(struct intel_iommu *iommu); | |
e820482c | 863 | |
a06c2ece LB |
864 | void qi_flush_context(struct intel_iommu *iommu, u16 did, |
865 | u16 sid, u8 fm, u64 type); | |
866 | void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, | |
867 | unsigned int size_order, u64 type); | |
868 | void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, | |
1c48db44 | 869 | u16 qdep, u64 addr, unsigned mask); |
61a06a16 | 870 | |
33cd6e64 LB |
871 | void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, |
872 | unsigned long npages, bool ih); | |
61a06a16 JP |
873 | |
874 | void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, | |
875 | u32 pasid, u16 qdep, u64 addr, | |
78df6c86 | 876 | unsigned int size_order); |
e65a6897 JP |
877 | void quirk_extra_dev_tlb_flush(struct device_domain_info *info, |
878 | unsigned long address, unsigned long pages, | |
879 | u32 pasid, u16 qdep); | |
61a06a16 | 880 | void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, |
c7b6bac9 | 881 | u32 pasid); |
61a06a16 | 882 | |
8a1d8246 LB |
883 | int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc, |
884 | unsigned int count, unsigned long options); | |
885 | /* | |
886 | * Options used in qi_submit_sync: | |
887 | * QI_OPT_WAIT_DRAIN - Wait for PRQ drain completion, spec 6.5.2.8. | |
888 | */ | |
889 | #define QI_OPT_WAIT_DRAIN BIT(0) | |
38717946 | 890 | |
d86724d4 YL |
891 | int domain_attach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu); |
892 | void domain_detach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu); | |
893 | void device_block_translation(struct device *dev); | |
894 | int prepare_domain_attach_device(struct iommu_domain *domain, | |
895 | struct device *dev); | |
896 | void domain_update_iommu_cap(struct dmar_domain *domain); | |
897 | ||
a06c2ece | 898 | int dmar_ir_support(void); |
074835f0 | 899 | |
2552d3a2 | 900 | void *alloc_pgtable_page(int node, gfp_t gfp); |
9ddbfb42 | 901 | void free_pgtable_page(void *vaddr); |
6f7db75e | 902 | void iommu_flush_write_buffer(struct intel_iommu *iommu); |
dd6692f1 | 903 | struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn); |
79ae1ecc LB |
904 | struct iommu_domain *intel_nested_domain_alloc(struct iommu_domain *parent, |
905 | const struct iommu_user_data *user_data); | |
9ddbfb42 | 906 | |
2f26e0a9 | 907 | #ifdef CONFIG_INTEL_IOMMU_SVM |
a06c2ece LB |
908 | void intel_svm_check(struct intel_iommu *iommu); |
909 | int intel_svm_enable_prq(struct intel_iommu *iommu); | |
910 | int intel_svm_finish_prq(struct intel_iommu *iommu); | |
8b737121 LB |
911 | int intel_svm_page_response(struct device *dev, struct iommu_fault_event *evt, |
912 | struct iommu_page_response *msg); | |
eaca8889 LB |
913 | struct iommu_domain *intel_svm_domain_alloc(void); |
914 | void intel_svm_remove_dev_pasid(struct device *dev, ioasid_t pasid); | |
15478623 | 915 | void intel_drain_pasid_prq(struct device *dev, u32 pasid); |
8b737121 | 916 | |
2f26e0a9 DW |
917 | struct intel_svm_dev { |
918 | struct list_head list; | |
919 | struct rcu_head rcu; | |
920 | struct device *dev; | |
9ad9f45b | 921 | struct intel_iommu *iommu; |
2f26e0a9 | 922 | u16 did; |
2f26e0a9 DW |
923 | u16 sid, qdep; |
924 | }; | |
925 | ||
926 | struct intel_svm { | |
927 | struct mmu_notifier notifier; | |
928 | struct mm_struct *mm; | |
c7b6bac9 | 929 | u32 pasid; |
2f26e0a9 DW |
930 | struct list_head devs; |
931 | }; | |
ff3dc652 JP |
932 | #else |
933 | static inline void intel_svm_check(struct intel_iommu *iommu) {} | |
15478623 | 934 | static inline void intel_drain_pasid_prq(struct device *dev, u32 pasid) {} |
eaca8889 LB |
935 | static inline struct iommu_domain *intel_svm_domain_alloc(void) |
936 | { | |
937 | return NULL; | |
938 | } | |
939 | ||
940 | static inline void intel_svm_remove_dev_pasid(struct device *dev, ioasid_t pasid) | |
941 | { | |
942 | } | |
2f26e0a9 DW |
943 | #endif |
944 | ||
ee2636b8 SM |
945 | #ifdef CONFIG_INTEL_IOMMU_DEBUGFS |
946 | void intel_iommu_debugfs_init(void); | |
d87731f6 JL |
947 | void intel_iommu_debugfs_create_dev(struct device_domain_info *info); |
948 | void intel_iommu_debugfs_remove_dev(struct device_domain_info *info); | |
949 | void intel_iommu_debugfs_create_dev_pasid(struct dev_pasid_info *dev_pasid); | |
950 | void intel_iommu_debugfs_remove_dev_pasid(struct dev_pasid_info *dev_pasid); | |
ee2636b8 SM |
951 | #else |
952 | static inline void intel_iommu_debugfs_init(void) {} | |
d87731f6 JL |
953 | static inline void intel_iommu_debugfs_create_dev(struct device_domain_info *info) {} |
954 | static inline void intel_iommu_debugfs_remove_dev(struct device_domain_info *info) {} | |
955 | static inline void intel_iommu_debugfs_create_dev_pasid(struct dev_pasid_info *dev_pasid) {} | |
956 | static inline void intel_iommu_debugfs_remove_dev_pasid(struct dev_pasid_info *dev_pasid) {} | |
ee2636b8 SM |
957 | #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */ |
958 | ||
a5459cfe | 959 | extern const struct attribute_group *intel_iommu_groups[]; |
26b86092 SM |
960 | struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, |
961 | u8 devfn, int alloc); | |
a5459cfe | 962 | |
2852631d AS |
963 | extern const struct iommu_ops intel_iommu_ops; |
964 | ||
daedaa33 | 965 | #ifdef CONFIG_INTEL_IOMMU |
1adf3cc2 | 966 | extern int intel_iommu_sm; |
a06c2ece LB |
967 | int iommu_calculate_agaw(struct intel_iommu *iommu); |
968 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu); | |
dc578758 KL |
969 | int ecmd_submit_sync(struct intel_iommu *iommu, u8 ecmd, u64 oa, u64 ob); |
970 | ||
971 | static inline bool ecmd_has_pmu_essential(struct intel_iommu *iommu) | |
972 | { | |
973 | return (iommu->ecmdcap[DMA_ECMD_ECCAP3] & DMA_ECMD_ECCAP3_ESSENTIAL) == | |
974 | DMA_ECMD_ECCAP3_ESSENTIAL; | |
975 | } | |
976 | ||
daedaa33 LB |
977 | extern int dmar_disabled; |
978 | extern int intel_iommu_enabled; | |
daedaa33 LB |
979 | #else |
980 | static inline int iommu_calculate_agaw(struct intel_iommu *iommu) | |
981 | { | |
982 | return 0; | |
983 | } | |
984 | static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu) | |
985 | { | |
986 | return 0; | |
987 | } | |
988 | #define dmar_disabled (1) | |
989 | #define intel_iommu_enabled (0) | |
1adf3cc2 | 990 | #define intel_iommu_sm (0) |
daedaa33 LB |
991 | #endif |
992 | ||
e93a67f5 LB |
993 | static inline const char *decode_prq_descriptor(char *str, size_t size, |
994 | u64 dw0, u64 dw1, u64 dw2, u64 dw3) | |
995 | { | |
996 | char *buf = str; | |
997 | int bytes; | |
998 | ||
999 | bytes = snprintf(buf, size, | |
1000 | "rid=0x%llx addr=0x%llx %c%c%c%c%c pasid=0x%llx index=0x%llx", | |
1001 | FIELD_GET(GENMASK_ULL(31, 16), dw0), | |
1002 | FIELD_GET(GENMASK_ULL(63, 12), dw1), | |
1003 | dw1 & BIT_ULL(0) ? 'r' : '-', | |
1004 | dw1 & BIT_ULL(1) ? 'w' : '-', | |
1005 | dw0 & BIT_ULL(52) ? 'x' : '-', | |
1006 | dw0 & BIT_ULL(53) ? 'p' : '-', | |
1007 | dw1 & BIT_ULL(2) ? 'l' : '-', | |
1008 | FIELD_GET(GENMASK_ULL(51, 32), dw0), | |
1009 | FIELD_GET(GENMASK_ULL(11, 3), dw1)); | |
1010 | ||
1011 | /* Private Data */ | |
1012 | if (dw0 & BIT_ULL(9)) { | |
1013 | size -= bytes; | |
1014 | buf += bytes; | |
1015 | snprintf(buf, size, " private=0x%llx/0x%llx\n", dw2, dw3); | |
1016 | } | |
1017 | ||
1018 | return str; | |
1019 | } | |
1020 | ||
ba395927 | 1021 | #endif |