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ba395927 | 1 | /* |
ea8ea460 | 2 | * Copyright © 2006-2014 Intel Corporation. |
ba395927 KA |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
ea8ea460 DW |
13 | * Authors: David Woodhouse <dwmw2@infradead.org>, |
14 | * Ashok Raj <ashok.raj@intel.com>, | |
15 | * Shaohua Li <shaohua.li@intel.com>, | |
16 | * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>, | |
17 | * Fenghua Yu <fenghua.yu@intel.com> | |
ba395927 KA |
18 | */ |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/bitmap.h> | |
5e0d2a6f | 22 | #include <linux/debugfs.h> |
54485c30 | 23 | #include <linux/export.h> |
ba395927 KA |
24 | #include <linux/slab.h> |
25 | #include <linux/irq.h> | |
26 | #include <linux/interrupt.h> | |
ba395927 KA |
27 | #include <linux/spinlock.h> |
28 | #include <linux/pci.h> | |
29 | #include <linux/dmar.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/mempool.h> | |
75f05569 | 32 | #include <linux/memory.h> |
5e0d2a6f | 33 | #include <linux/timer.h> |
38717946 | 34 | #include <linux/iova.h> |
5d450806 | 35 | #include <linux/iommu.h> |
38717946 | 36 | #include <linux/intel-iommu.h> |
134fac3f | 37 | #include <linux/syscore_ops.h> |
69575d38 | 38 | #include <linux/tboot.h> |
adb2fe02 | 39 | #include <linux/dmi.h> |
5cdede24 | 40 | #include <linux/pci-ats.h> |
0ee332c1 | 41 | #include <linux/memblock.h> |
36746436 | 42 | #include <linux/dma-contiguous.h> |
8a8f422d | 43 | #include <asm/irq_remapping.h> |
ba395927 | 44 | #include <asm/cacheflush.h> |
46a7fa27 | 45 | #include <asm/iommu.h> |
ba395927 | 46 | |
078e1ee2 JR |
47 | #include "irq_remapping.h" |
48 | ||
5b6985ce FY |
49 | #define ROOT_SIZE VTD_PAGE_SIZE |
50 | #define CONTEXT_SIZE VTD_PAGE_SIZE | |
51 | ||
ba395927 KA |
52 | #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
53 | #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) | |
e0fc7e0b | 54 | #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e) |
ba395927 KA |
55 | |
56 | #define IOAPIC_RANGE_START (0xfee00000) | |
57 | #define IOAPIC_RANGE_END (0xfeefffff) | |
58 | #define IOVA_START_ADDR (0x1000) | |
59 | ||
60 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 | |
61 | ||
4ed0d3e6 | 62 | #define MAX_AGAW_WIDTH 64 |
5c645b35 | 63 | #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT) |
4ed0d3e6 | 64 | |
2ebe3151 DW |
65 | #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1) |
66 | #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1) | |
67 | ||
68 | /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR | |
69 | to match. That way, we can use 'unsigned long' for PFNs with impunity. */ | |
70 | #define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \ | |
71 | __DOMAIN_MAX_PFN(gaw), (unsigned long)-1)) | |
72 | #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT) | |
ba395927 | 73 | |
f27be03b | 74 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
284901a9 | 75 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) |
6a35528a | 76 | #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64)) |
5e0d2a6f | 77 | |
df08cdc7 AM |
78 | /* page table handling */ |
79 | #define LEVEL_STRIDE (9) | |
80 | #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) | |
81 | ||
6d1c56a9 OBC |
82 | /* |
83 | * This bitmap is used to advertise the page sizes our hardware support | |
84 | * to the IOMMU core, which will then use this information to split | |
85 | * physically contiguous memory regions it is mapping into page sizes | |
86 | * that we support. | |
87 | * | |
88 | * Traditionally the IOMMU core just handed us the mappings directly, | |
89 | * after making sure the size is an order of a 4KiB page and that the | |
90 | * mapping has natural alignment. | |
91 | * | |
92 | * To retain this behavior, we currently advertise that we support | |
93 | * all page sizes that are an order of 4KiB. | |
94 | * | |
95 | * If at some point we'd like to utilize the IOMMU core's new behavior, | |
96 | * we could change this to advertise the real page sizes we support. | |
97 | */ | |
98 | #define INTEL_IOMMU_PGSIZES (~0xFFFUL) | |
99 | ||
df08cdc7 AM |
100 | static inline int agaw_to_level(int agaw) |
101 | { | |
102 | return agaw + 2; | |
103 | } | |
104 | ||
105 | static inline int agaw_to_width(int agaw) | |
106 | { | |
5c645b35 | 107 | return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH); |
df08cdc7 AM |
108 | } |
109 | ||
110 | static inline int width_to_agaw(int width) | |
111 | { | |
5c645b35 | 112 | return DIV_ROUND_UP(width - 30, LEVEL_STRIDE); |
df08cdc7 AM |
113 | } |
114 | ||
115 | static inline unsigned int level_to_offset_bits(int level) | |
116 | { | |
117 | return (level - 1) * LEVEL_STRIDE; | |
118 | } | |
119 | ||
120 | static inline int pfn_level_offset(unsigned long pfn, int level) | |
121 | { | |
122 | return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; | |
123 | } | |
124 | ||
125 | static inline unsigned long level_mask(int level) | |
126 | { | |
127 | return -1UL << level_to_offset_bits(level); | |
128 | } | |
129 | ||
130 | static inline unsigned long level_size(int level) | |
131 | { | |
132 | return 1UL << level_to_offset_bits(level); | |
133 | } | |
134 | ||
135 | static inline unsigned long align_to_level(unsigned long pfn, int level) | |
136 | { | |
137 | return (pfn + level_size(level) - 1) & level_mask(level); | |
138 | } | |
fd18de50 | 139 | |
6dd9a7c7 YS |
140 | static inline unsigned long lvl_to_nr_pages(unsigned int lvl) |
141 | { | |
5c645b35 | 142 | return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH); |
6dd9a7c7 YS |
143 | } |
144 | ||
dd4e8319 DW |
145 | /* VT-d pages must always be _smaller_ than MM pages. Otherwise things |
146 | are never going to work. */ | |
147 | static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) | |
148 | { | |
149 | return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
150 | } | |
151 | ||
152 | static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn) | |
153 | { | |
154 | return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
155 | } | |
156 | static inline unsigned long page_to_dma_pfn(struct page *pg) | |
157 | { | |
158 | return mm_to_dma_pfn(page_to_pfn(pg)); | |
159 | } | |
160 | static inline unsigned long virt_to_dma_pfn(void *p) | |
161 | { | |
162 | return page_to_dma_pfn(virt_to_page(p)); | |
163 | } | |
164 | ||
d9630fe9 WH |
165 | /* global iommu list, set NULL for ignored DMAR units */ |
166 | static struct intel_iommu **g_iommus; | |
167 | ||
e0fc7e0b | 168 | static void __init check_tylersburg_isoch(void); |
9af88143 DW |
169 | static int rwbf_quirk; |
170 | ||
b779260b JC |
171 | /* |
172 | * set to 1 to panic kernel if can't successfully enable VT-d | |
173 | * (used when kernel is launched w/ TXT) | |
174 | */ | |
175 | static int force_on = 0; | |
176 | ||
46b08e1a MM |
177 | /* |
178 | * 0: Present | |
179 | * 1-11: Reserved | |
180 | * 12-63: Context Ptr (12 - (haw-1)) | |
181 | * 64-127: Reserved | |
182 | */ | |
183 | struct root_entry { | |
184 | u64 val; | |
185 | u64 rsvd1; | |
186 | }; | |
187 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) | |
188 | static inline bool root_present(struct root_entry *root) | |
189 | { | |
190 | return (root->val & 1); | |
191 | } | |
192 | static inline void set_root_present(struct root_entry *root) | |
193 | { | |
194 | root->val |= 1; | |
195 | } | |
196 | static inline void set_root_value(struct root_entry *root, unsigned long value) | |
197 | { | |
1a2262f9 | 198 | root->val &= ~VTD_PAGE_MASK; |
46b08e1a MM |
199 | root->val |= value & VTD_PAGE_MASK; |
200 | } | |
201 | ||
202 | static inline struct context_entry * | |
203 | get_context_addr_from_root(struct root_entry *root) | |
204 | { | |
205 | return (struct context_entry *) | |
206 | (root_present(root)?phys_to_virt( | |
207 | root->val & VTD_PAGE_MASK) : | |
208 | NULL); | |
209 | } | |
210 | ||
7a8fc25e MM |
211 | /* |
212 | * low 64 bits: | |
213 | * 0: present | |
214 | * 1: fault processing disable | |
215 | * 2-3: translation type | |
216 | * 12-63: address space root | |
217 | * high 64 bits: | |
218 | * 0-2: address width | |
219 | * 3-6: aval | |
220 | * 8-23: domain id | |
221 | */ | |
222 | struct context_entry { | |
223 | u64 lo; | |
224 | u64 hi; | |
225 | }; | |
c07e7d21 MM |
226 | |
227 | static inline bool context_present(struct context_entry *context) | |
228 | { | |
229 | return (context->lo & 1); | |
230 | } | |
231 | static inline void context_set_present(struct context_entry *context) | |
232 | { | |
233 | context->lo |= 1; | |
234 | } | |
235 | ||
236 | static inline void context_set_fault_enable(struct context_entry *context) | |
237 | { | |
238 | context->lo &= (((u64)-1) << 2) | 1; | |
239 | } | |
240 | ||
c07e7d21 MM |
241 | static inline void context_set_translation_type(struct context_entry *context, |
242 | unsigned long value) | |
243 | { | |
244 | context->lo &= (((u64)-1) << 4) | 3; | |
245 | context->lo |= (value & 3) << 2; | |
246 | } | |
247 | ||
248 | static inline void context_set_address_root(struct context_entry *context, | |
249 | unsigned long value) | |
250 | { | |
1a2262f9 | 251 | context->lo &= ~VTD_PAGE_MASK; |
c07e7d21 MM |
252 | context->lo |= value & VTD_PAGE_MASK; |
253 | } | |
254 | ||
255 | static inline void context_set_address_width(struct context_entry *context, | |
256 | unsigned long value) | |
257 | { | |
258 | context->hi |= value & 7; | |
259 | } | |
260 | ||
261 | static inline void context_set_domain_id(struct context_entry *context, | |
262 | unsigned long value) | |
263 | { | |
264 | context->hi |= (value & ((1 << 16) - 1)) << 8; | |
265 | } | |
266 | ||
267 | static inline void context_clear_entry(struct context_entry *context) | |
268 | { | |
269 | context->lo = 0; | |
270 | context->hi = 0; | |
271 | } | |
7a8fc25e | 272 | |
622ba12a MM |
273 | /* |
274 | * 0: readable | |
275 | * 1: writable | |
276 | * 2-6: reserved | |
277 | * 7: super page | |
9cf06697 SY |
278 | * 8-10: available |
279 | * 11: snoop behavior | |
622ba12a MM |
280 | * 12-63: Host physcial address |
281 | */ | |
282 | struct dma_pte { | |
283 | u64 val; | |
284 | }; | |
622ba12a | 285 | |
19c239ce MM |
286 | static inline void dma_clear_pte(struct dma_pte *pte) |
287 | { | |
288 | pte->val = 0; | |
289 | } | |
290 | ||
19c239ce MM |
291 | static inline u64 dma_pte_addr(struct dma_pte *pte) |
292 | { | |
c85994e4 DW |
293 | #ifdef CONFIG_64BIT |
294 | return pte->val & VTD_PAGE_MASK; | |
295 | #else | |
296 | /* Must have a full atomic 64-bit read */ | |
1a8bd481 | 297 | return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK; |
c85994e4 | 298 | #endif |
19c239ce MM |
299 | } |
300 | ||
19c239ce MM |
301 | static inline bool dma_pte_present(struct dma_pte *pte) |
302 | { | |
303 | return (pte->val & 3) != 0; | |
304 | } | |
622ba12a | 305 | |
4399c8bf AK |
306 | static inline bool dma_pte_superpage(struct dma_pte *pte) |
307 | { | |
c3c75eb7 | 308 | return (pte->val & DMA_PTE_LARGE_PAGE); |
4399c8bf AK |
309 | } |
310 | ||
75e6bf96 DW |
311 | static inline int first_pte_in_page(struct dma_pte *pte) |
312 | { | |
313 | return !((unsigned long)pte & ~VTD_PAGE_MASK); | |
314 | } | |
315 | ||
2c2e2c38 FY |
316 | /* |
317 | * This domain is a statically identity mapping domain. | |
318 | * 1. This domain creats a static 1:1 mapping to all usable memory. | |
319 | * 2. It maps to each iommu if successful. | |
320 | * 3. Each iommu mapps to this domain if successful. | |
321 | */ | |
19943b0e DW |
322 | static struct dmar_domain *si_domain; |
323 | static int hw_pass_through = 1; | |
2c2e2c38 | 324 | |
1ce28feb WH |
325 | /* domain represents a virtual machine, more than one devices |
326 | * across iommus may be owned in one domain, e.g. kvm guest. | |
327 | */ | |
ab8dfe25 | 328 | #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 0) |
1ce28feb | 329 | |
2c2e2c38 | 330 | /* si_domain contains mulitple devices */ |
ab8dfe25 | 331 | #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 1) |
2c2e2c38 | 332 | |
99126f7c MM |
333 | struct dmar_domain { |
334 | int id; /* domain id */ | |
4c923d47 | 335 | int nid; /* node id */ |
78d8e704 | 336 | DECLARE_BITMAP(iommu_bmp, DMAR_UNITS_SUPPORTED); |
1b198bb0 | 337 | /* bitmap of iommus this domain uses*/ |
99126f7c MM |
338 | |
339 | struct list_head devices; /* all devices' list */ | |
340 | struct iova_domain iovad; /* iova's that belong to this domain */ | |
341 | ||
342 | struct dma_pte *pgd; /* virtual address */ | |
99126f7c MM |
343 | int gaw; /* max guest address width */ |
344 | ||
345 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
346 | int agaw; | |
347 | ||
3b5410e7 | 348 | int flags; /* flags to find out type of domain */ |
8e604097 WH |
349 | |
350 | int iommu_coherency;/* indicate coherency of iommu access */ | |
58c610bd | 351 | int iommu_snooping; /* indicate snooping control feature*/ |
c7151a8d | 352 | int iommu_count; /* reference count of iommu */ |
6dd9a7c7 YS |
353 | int iommu_superpage;/* Level of superpages supported: |
354 | 0 == 4KiB (no superpages), 1 == 2MiB, | |
355 | 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ | |
c7151a8d | 356 | spinlock_t iommu_lock; /* protect iommu set in domain */ |
fe40f1e0 | 357 | u64 max_addr; /* maximum mapped address */ |
99126f7c MM |
358 | }; |
359 | ||
a647dacb MM |
360 | /* PCI domain-device relationship */ |
361 | struct device_domain_info { | |
362 | struct list_head link; /* link to domain siblings */ | |
363 | struct list_head global; /* link to global list */ | |
276dbf99 | 364 | u8 bus; /* PCI bus number */ |
a647dacb | 365 | u8 devfn; /* PCI devfn number */ |
0bcb3e28 | 366 | struct device *dev; /* it's NULL for PCIe-to-PCI bridge */ |
93a23a72 | 367 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
a647dacb MM |
368 | struct dmar_domain *domain; /* pointer to domain */ |
369 | }; | |
370 | ||
b94e4117 JL |
371 | struct dmar_rmrr_unit { |
372 | struct list_head list; /* list of rmrr units */ | |
373 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
374 | u64 base_address; /* reserved base address*/ | |
375 | u64 end_address; /* reserved end address */ | |
832bd858 | 376 | struct dmar_dev_scope *devices; /* target devices */ |
b94e4117 JL |
377 | int devices_cnt; /* target device count */ |
378 | }; | |
379 | ||
380 | struct dmar_atsr_unit { | |
381 | struct list_head list; /* list of ATSR units */ | |
382 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
832bd858 | 383 | struct dmar_dev_scope *devices; /* target devices */ |
b94e4117 JL |
384 | int devices_cnt; /* target device count */ |
385 | u8 include_all:1; /* include all ports */ | |
386 | }; | |
387 | ||
388 | static LIST_HEAD(dmar_atsr_units); | |
389 | static LIST_HEAD(dmar_rmrr_units); | |
390 | ||
391 | #define for_each_rmrr_units(rmrr) \ | |
392 | list_for_each_entry(rmrr, &dmar_rmrr_units, list) | |
393 | ||
5e0d2a6f | 394 | static void flush_unmaps_timeout(unsigned long data); |
395 | ||
b707cb02 | 396 | static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); |
5e0d2a6f | 397 | |
80b20dd8 | 398 | #define HIGH_WATER_MARK 250 |
399 | struct deferred_flush_tables { | |
400 | int next; | |
401 | struct iova *iova[HIGH_WATER_MARK]; | |
402 | struct dmar_domain *domain[HIGH_WATER_MARK]; | |
ea8ea460 | 403 | struct page *freelist[HIGH_WATER_MARK]; |
80b20dd8 | 404 | }; |
405 | ||
406 | static struct deferred_flush_tables *deferred_flush; | |
407 | ||
5e0d2a6f | 408 | /* bitmap for indexing intel_iommus */ |
5e0d2a6f | 409 | static int g_num_of_iommus; |
410 | ||
411 | static DEFINE_SPINLOCK(async_umap_flush_lock); | |
412 | static LIST_HEAD(unmaps_to_do); | |
413 | ||
414 | static int timer_on; | |
415 | static long list_size; | |
5e0d2a6f | 416 | |
92d03cc8 | 417 | static void domain_exit(struct dmar_domain *domain); |
ba395927 | 418 | static void domain_remove_dev_info(struct dmar_domain *domain); |
b94e4117 | 419 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
bf9c9eda | 420 | struct device *dev); |
92d03cc8 | 421 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
0bcb3e28 | 422 | struct device *dev); |
2a46ddf7 JL |
423 | static int domain_detach_iommu(struct dmar_domain *domain, |
424 | struct intel_iommu *iommu); | |
ba395927 | 425 | |
d3f13810 | 426 | #ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON |
0cd5c3c8 KM |
427 | int dmar_disabled = 0; |
428 | #else | |
429 | int dmar_disabled = 1; | |
d3f13810 | 430 | #endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/ |
0cd5c3c8 | 431 | |
8bc1f85c ED |
432 | int intel_iommu_enabled = 0; |
433 | EXPORT_SYMBOL_GPL(intel_iommu_enabled); | |
434 | ||
2d9e667e | 435 | static int dmar_map_gfx = 1; |
7d3b03ce | 436 | static int dmar_forcedac; |
5e0d2a6f | 437 | static int intel_iommu_strict; |
6dd9a7c7 | 438 | static int intel_iommu_superpage = 1; |
ba395927 | 439 | |
c0771df8 DW |
440 | int intel_iommu_gfx_mapped; |
441 | EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped); | |
442 | ||
ba395927 KA |
443 | #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) |
444 | static DEFINE_SPINLOCK(device_domain_lock); | |
445 | static LIST_HEAD(device_domain_list); | |
446 | ||
b22f6434 | 447 | static const struct iommu_ops intel_iommu_ops; |
a8bcbb0d | 448 | |
ba395927 KA |
449 | static int __init intel_iommu_setup(char *str) |
450 | { | |
451 | if (!str) | |
452 | return -EINVAL; | |
453 | while (*str) { | |
0cd5c3c8 KM |
454 | if (!strncmp(str, "on", 2)) { |
455 | dmar_disabled = 0; | |
456 | printk(KERN_INFO "Intel-IOMMU: enabled\n"); | |
457 | } else if (!strncmp(str, "off", 3)) { | |
ba395927 | 458 | dmar_disabled = 1; |
0cd5c3c8 | 459 | printk(KERN_INFO "Intel-IOMMU: disabled\n"); |
ba395927 KA |
460 | } else if (!strncmp(str, "igfx_off", 8)) { |
461 | dmar_map_gfx = 0; | |
462 | printk(KERN_INFO | |
463 | "Intel-IOMMU: disable GFX device mapping\n"); | |
7d3b03ce | 464 | } else if (!strncmp(str, "forcedac", 8)) { |
5e0d2a6f | 465 | printk(KERN_INFO |
7d3b03ce KA |
466 | "Intel-IOMMU: Forcing DAC for PCI devices\n"); |
467 | dmar_forcedac = 1; | |
5e0d2a6f | 468 | } else if (!strncmp(str, "strict", 6)) { |
469 | printk(KERN_INFO | |
470 | "Intel-IOMMU: disable batched IOTLB flush\n"); | |
471 | intel_iommu_strict = 1; | |
6dd9a7c7 YS |
472 | } else if (!strncmp(str, "sp_off", 6)) { |
473 | printk(KERN_INFO | |
474 | "Intel-IOMMU: disable supported super page\n"); | |
475 | intel_iommu_superpage = 0; | |
ba395927 KA |
476 | } |
477 | ||
478 | str += strcspn(str, ","); | |
479 | while (*str == ',') | |
480 | str++; | |
481 | } | |
482 | return 0; | |
483 | } | |
484 | __setup("intel_iommu=", intel_iommu_setup); | |
485 | ||
486 | static struct kmem_cache *iommu_domain_cache; | |
487 | static struct kmem_cache *iommu_devinfo_cache; | |
488 | static struct kmem_cache *iommu_iova_cache; | |
489 | ||
4c923d47 | 490 | static inline void *alloc_pgtable_page(int node) |
eb3fa7cb | 491 | { |
4c923d47 SS |
492 | struct page *page; |
493 | void *vaddr = NULL; | |
eb3fa7cb | 494 | |
4c923d47 SS |
495 | page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0); |
496 | if (page) | |
497 | vaddr = page_address(page); | |
eb3fa7cb | 498 | return vaddr; |
ba395927 KA |
499 | } |
500 | ||
501 | static inline void free_pgtable_page(void *vaddr) | |
502 | { | |
503 | free_page((unsigned long)vaddr); | |
504 | } | |
505 | ||
506 | static inline void *alloc_domain_mem(void) | |
507 | { | |
354bb65e | 508 | return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC); |
ba395927 KA |
509 | } |
510 | ||
38717946 | 511 | static void free_domain_mem(void *vaddr) |
ba395927 KA |
512 | { |
513 | kmem_cache_free(iommu_domain_cache, vaddr); | |
514 | } | |
515 | ||
516 | static inline void * alloc_devinfo_mem(void) | |
517 | { | |
354bb65e | 518 | return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC); |
ba395927 KA |
519 | } |
520 | ||
521 | static inline void free_devinfo_mem(void *vaddr) | |
522 | { | |
523 | kmem_cache_free(iommu_devinfo_cache, vaddr); | |
524 | } | |
525 | ||
526 | struct iova *alloc_iova_mem(void) | |
527 | { | |
354bb65e | 528 | return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC); |
ba395927 KA |
529 | } |
530 | ||
531 | void free_iova_mem(struct iova *iova) | |
532 | { | |
533 | kmem_cache_free(iommu_iova_cache, iova); | |
534 | } | |
535 | ||
ab8dfe25 JL |
536 | static inline int domain_type_is_vm(struct dmar_domain *domain) |
537 | { | |
538 | return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE; | |
539 | } | |
540 | ||
541 | static inline int domain_type_is_vm_or_si(struct dmar_domain *domain) | |
542 | { | |
543 | return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE | | |
544 | DOMAIN_FLAG_STATIC_IDENTITY); | |
545 | } | |
1b573683 | 546 | |
162d1b10 JL |
547 | static inline int domain_pfn_supported(struct dmar_domain *domain, |
548 | unsigned long pfn) | |
549 | { | |
550 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; | |
551 | ||
552 | return !(addr_width < BITS_PER_LONG && pfn >> addr_width); | |
553 | } | |
554 | ||
4ed0d3e6 | 555 | static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) |
1b573683 WH |
556 | { |
557 | unsigned long sagaw; | |
558 | int agaw = -1; | |
559 | ||
560 | sagaw = cap_sagaw(iommu->cap); | |
4ed0d3e6 | 561 | for (agaw = width_to_agaw(max_gaw); |
1b573683 WH |
562 | agaw >= 0; agaw--) { |
563 | if (test_bit(agaw, &sagaw)) | |
564 | break; | |
565 | } | |
566 | ||
567 | return agaw; | |
568 | } | |
569 | ||
4ed0d3e6 FY |
570 | /* |
571 | * Calculate max SAGAW for each iommu. | |
572 | */ | |
573 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu) | |
574 | { | |
575 | return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); | |
576 | } | |
577 | ||
578 | /* | |
579 | * calculate agaw for each iommu. | |
580 | * "SAGAW" may be different across iommus, use a default agaw, and | |
581 | * get a supported less agaw for iommus that don't support the default agaw. | |
582 | */ | |
583 | int iommu_calculate_agaw(struct intel_iommu *iommu) | |
584 | { | |
585 | return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
586 | } | |
587 | ||
2c2e2c38 | 588 | /* This functionin only returns single iommu in a domain */ |
8c11e798 WH |
589 | static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) |
590 | { | |
591 | int iommu_id; | |
592 | ||
2c2e2c38 | 593 | /* si_domain and vm domain should not get here. */ |
ab8dfe25 | 594 | BUG_ON(domain_type_is_vm_or_si(domain)); |
1b198bb0 | 595 | iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus); |
8c11e798 WH |
596 | if (iommu_id < 0 || iommu_id >= g_num_of_iommus) |
597 | return NULL; | |
598 | ||
599 | return g_iommus[iommu_id]; | |
600 | } | |
601 | ||
8e604097 WH |
602 | static void domain_update_iommu_coherency(struct dmar_domain *domain) |
603 | { | |
d0501960 DW |
604 | struct dmar_drhd_unit *drhd; |
605 | struct intel_iommu *iommu; | |
606 | int i, found = 0; | |
2e12bc29 | 607 | |
d0501960 | 608 | domain->iommu_coherency = 1; |
8e604097 | 609 | |
1b198bb0 | 610 | for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) { |
d0501960 | 611 | found = 1; |
8e604097 WH |
612 | if (!ecap_coherent(g_iommus[i]->ecap)) { |
613 | domain->iommu_coherency = 0; | |
614 | break; | |
615 | } | |
8e604097 | 616 | } |
d0501960 DW |
617 | if (found) |
618 | return; | |
619 | ||
620 | /* No hardware attached; use lowest common denominator */ | |
621 | rcu_read_lock(); | |
622 | for_each_active_iommu(iommu, drhd) { | |
623 | if (!ecap_coherent(iommu->ecap)) { | |
624 | domain->iommu_coherency = 0; | |
625 | break; | |
626 | } | |
627 | } | |
628 | rcu_read_unlock(); | |
8e604097 WH |
629 | } |
630 | ||
161f6934 | 631 | static int domain_update_iommu_snooping(struct intel_iommu *skip) |
58c610bd | 632 | { |
161f6934 JL |
633 | struct dmar_drhd_unit *drhd; |
634 | struct intel_iommu *iommu; | |
635 | int ret = 1; | |
58c610bd | 636 | |
161f6934 JL |
637 | rcu_read_lock(); |
638 | for_each_active_iommu(iommu, drhd) { | |
639 | if (iommu != skip) { | |
640 | if (!ecap_sc_support(iommu->ecap)) { | |
641 | ret = 0; | |
642 | break; | |
643 | } | |
58c610bd | 644 | } |
58c610bd | 645 | } |
161f6934 JL |
646 | rcu_read_unlock(); |
647 | ||
648 | return ret; | |
58c610bd SY |
649 | } |
650 | ||
161f6934 | 651 | static int domain_update_iommu_superpage(struct intel_iommu *skip) |
6dd9a7c7 | 652 | { |
8140a95d | 653 | struct dmar_drhd_unit *drhd; |
161f6934 | 654 | struct intel_iommu *iommu; |
8140a95d | 655 | int mask = 0xf; |
6dd9a7c7 YS |
656 | |
657 | if (!intel_iommu_superpage) { | |
161f6934 | 658 | return 0; |
6dd9a7c7 YS |
659 | } |
660 | ||
8140a95d | 661 | /* set iommu_superpage to the smallest common denominator */ |
0e242612 | 662 | rcu_read_lock(); |
8140a95d | 663 | for_each_active_iommu(iommu, drhd) { |
161f6934 JL |
664 | if (iommu != skip) { |
665 | mask &= cap_super_page_val(iommu->cap); | |
666 | if (!mask) | |
667 | break; | |
6dd9a7c7 YS |
668 | } |
669 | } | |
0e242612 JL |
670 | rcu_read_unlock(); |
671 | ||
161f6934 | 672 | return fls(mask); |
6dd9a7c7 YS |
673 | } |
674 | ||
58c610bd SY |
675 | /* Some capabilities may be different across iommus */ |
676 | static void domain_update_iommu_cap(struct dmar_domain *domain) | |
677 | { | |
678 | domain_update_iommu_coherency(domain); | |
161f6934 JL |
679 | domain->iommu_snooping = domain_update_iommu_snooping(NULL); |
680 | domain->iommu_superpage = domain_update_iommu_superpage(NULL); | |
58c610bd SY |
681 | } |
682 | ||
156baca8 | 683 | static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn) |
c7151a8d WH |
684 | { |
685 | struct dmar_drhd_unit *drhd = NULL; | |
b683b230 | 686 | struct intel_iommu *iommu; |
156baca8 DW |
687 | struct device *tmp; |
688 | struct pci_dev *ptmp, *pdev = NULL; | |
aa4d066a | 689 | u16 segment = 0; |
c7151a8d WH |
690 | int i; |
691 | ||
156baca8 DW |
692 | if (dev_is_pci(dev)) { |
693 | pdev = to_pci_dev(dev); | |
694 | segment = pci_domain_nr(pdev->bus); | |
695 | } else if (ACPI_COMPANION(dev)) | |
696 | dev = &ACPI_COMPANION(dev)->dev; | |
697 | ||
0e242612 | 698 | rcu_read_lock(); |
b683b230 | 699 | for_each_active_iommu(iommu, drhd) { |
156baca8 | 700 | if (pdev && segment != drhd->segment) |
276dbf99 | 701 | continue; |
c7151a8d | 702 | |
b683b230 | 703 | for_each_active_dev_scope(drhd->devices, |
156baca8 DW |
704 | drhd->devices_cnt, i, tmp) { |
705 | if (tmp == dev) { | |
706 | *bus = drhd->devices[i].bus; | |
707 | *devfn = drhd->devices[i].devfn; | |
b683b230 | 708 | goto out; |
156baca8 DW |
709 | } |
710 | ||
711 | if (!pdev || !dev_is_pci(tmp)) | |
712 | continue; | |
713 | ||
714 | ptmp = to_pci_dev(tmp); | |
715 | if (ptmp->subordinate && | |
716 | ptmp->subordinate->number <= pdev->bus->number && | |
717 | ptmp->subordinate->busn_res.end >= pdev->bus->number) | |
718 | goto got_pdev; | |
924b6231 | 719 | } |
c7151a8d | 720 | |
156baca8 DW |
721 | if (pdev && drhd->include_all) { |
722 | got_pdev: | |
723 | *bus = pdev->bus->number; | |
724 | *devfn = pdev->devfn; | |
b683b230 | 725 | goto out; |
156baca8 | 726 | } |
c7151a8d | 727 | } |
b683b230 | 728 | iommu = NULL; |
156baca8 | 729 | out: |
0e242612 | 730 | rcu_read_unlock(); |
c7151a8d | 731 | |
b683b230 | 732 | return iommu; |
c7151a8d WH |
733 | } |
734 | ||
5331fe6f WH |
735 | static void domain_flush_cache(struct dmar_domain *domain, |
736 | void *addr, int size) | |
737 | { | |
738 | if (!domain->iommu_coherency) | |
739 | clflush_cache_range(addr, size); | |
740 | } | |
741 | ||
ba395927 KA |
742 | /* Gets context entry for a given bus and devfn */ |
743 | static struct context_entry * device_to_context_entry(struct intel_iommu *iommu, | |
744 | u8 bus, u8 devfn) | |
745 | { | |
746 | struct root_entry *root; | |
747 | struct context_entry *context; | |
748 | unsigned long phy_addr; | |
749 | unsigned long flags; | |
750 | ||
751 | spin_lock_irqsave(&iommu->lock, flags); | |
752 | root = &iommu->root_entry[bus]; | |
753 | context = get_context_addr_from_root(root); | |
754 | if (!context) { | |
4c923d47 SS |
755 | context = (struct context_entry *) |
756 | alloc_pgtable_page(iommu->node); | |
ba395927 KA |
757 | if (!context) { |
758 | spin_unlock_irqrestore(&iommu->lock, flags); | |
759 | return NULL; | |
760 | } | |
5b6985ce | 761 | __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); |
ba395927 KA |
762 | phy_addr = virt_to_phys((void *)context); |
763 | set_root_value(root, phy_addr); | |
764 | set_root_present(root); | |
765 | __iommu_flush_cache(iommu, root, sizeof(*root)); | |
766 | } | |
767 | spin_unlock_irqrestore(&iommu->lock, flags); | |
768 | return &context[devfn]; | |
769 | } | |
770 | ||
771 | static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
772 | { | |
773 | struct root_entry *root; | |
774 | struct context_entry *context; | |
775 | int ret; | |
776 | unsigned long flags; | |
777 | ||
778 | spin_lock_irqsave(&iommu->lock, flags); | |
779 | root = &iommu->root_entry[bus]; | |
780 | context = get_context_addr_from_root(root); | |
781 | if (!context) { | |
782 | ret = 0; | |
783 | goto out; | |
784 | } | |
c07e7d21 | 785 | ret = context_present(&context[devfn]); |
ba395927 KA |
786 | out: |
787 | spin_unlock_irqrestore(&iommu->lock, flags); | |
788 | return ret; | |
789 | } | |
790 | ||
791 | static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
792 | { | |
793 | struct root_entry *root; | |
794 | struct context_entry *context; | |
795 | unsigned long flags; | |
796 | ||
797 | spin_lock_irqsave(&iommu->lock, flags); | |
798 | root = &iommu->root_entry[bus]; | |
799 | context = get_context_addr_from_root(root); | |
800 | if (context) { | |
c07e7d21 | 801 | context_clear_entry(&context[devfn]); |
ba395927 KA |
802 | __iommu_flush_cache(iommu, &context[devfn], \ |
803 | sizeof(*context)); | |
804 | } | |
805 | spin_unlock_irqrestore(&iommu->lock, flags); | |
806 | } | |
807 | ||
808 | static void free_context_table(struct intel_iommu *iommu) | |
809 | { | |
810 | struct root_entry *root; | |
811 | int i; | |
812 | unsigned long flags; | |
813 | struct context_entry *context; | |
814 | ||
815 | spin_lock_irqsave(&iommu->lock, flags); | |
816 | if (!iommu->root_entry) { | |
817 | goto out; | |
818 | } | |
819 | for (i = 0; i < ROOT_ENTRY_NR; i++) { | |
820 | root = &iommu->root_entry[i]; | |
821 | context = get_context_addr_from_root(root); | |
822 | if (context) | |
823 | free_pgtable_page(context); | |
824 | } | |
825 | free_pgtable_page(iommu->root_entry); | |
826 | iommu->root_entry = NULL; | |
827 | out: | |
828 | spin_unlock_irqrestore(&iommu->lock, flags); | |
829 | } | |
830 | ||
b026fd28 | 831 | static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, |
5cf0a76f | 832 | unsigned long pfn, int *target_level) |
ba395927 | 833 | { |
ba395927 KA |
834 | struct dma_pte *parent, *pte = NULL; |
835 | int level = agaw_to_level(domain->agaw); | |
4399c8bf | 836 | int offset; |
ba395927 KA |
837 | |
838 | BUG_ON(!domain->pgd); | |
f9423606 | 839 | |
162d1b10 | 840 | if (!domain_pfn_supported(domain, pfn)) |
f9423606 JS |
841 | /* Address beyond IOMMU's addressing capabilities. */ |
842 | return NULL; | |
843 | ||
ba395927 KA |
844 | parent = domain->pgd; |
845 | ||
5cf0a76f | 846 | while (1) { |
ba395927 KA |
847 | void *tmp_page; |
848 | ||
b026fd28 | 849 | offset = pfn_level_offset(pfn, level); |
ba395927 | 850 | pte = &parent[offset]; |
5cf0a76f | 851 | if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte))) |
6dd9a7c7 | 852 | break; |
5cf0a76f | 853 | if (level == *target_level) |
ba395927 KA |
854 | break; |
855 | ||
19c239ce | 856 | if (!dma_pte_present(pte)) { |
c85994e4 DW |
857 | uint64_t pteval; |
858 | ||
4c923d47 | 859 | tmp_page = alloc_pgtable_page(domain->nid); |
ba395927 | 860 | |
206a73c1 | 861 | if (!tmp_page) |
ba395927 | 862 | return NULL; |
206a73c1 | 863 | |
c85994e4 | 864 | domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); |
64de5af0 | 865 | pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; |
effad4b5 | 866 | if (cmpxchg64(&pte->val, 0ULL, pteval)) |
c85994e4 DW |
867 | /* Someone else set it while we were thinking; use theirs. */ |
868 | free_pgtable_page(tmp_page); | |
effad4b5 | 869 | else |
c85994e4 | 870 | domain_flush_cache(domain, pte, sizeof(*pte)); |
ba395927 | 871 | } |
5cf0a76f DW |
872 | if (level == 1) |
873 | break; | |
874 | ||
19c239ce | 875 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
876 | level--; |
877 | } | |
878 | ||
5cf0a76f DW |
879 | if (!*target_level) |
880 | *target_level = level; | |
881 | ||
ba395927 KA |
882 | return pte; |
883 | } | |
884 | ||
6dd9a7c7 | 885 | |
ba395927 | 886 | /* return address's pte at specific level */ |
90dcfb5e DW |
887 | static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, |
888 | unsigned long pfn, | |
6dd9a7c7 | 889 | int level, int *large_page) |
ba395927 KA |
890 | { |
891 | struct dma_pte *parent, *pte = NULL; | |
892 | int total = agaw_to_level(domain->agaw); | |
893 | int offset; | |
894 | ||
895 | parent = domain->pgd; | |
896 | while (level <= total) { | |
90dcfb5e | 897 | offset = pfn_level_offset(pfn, total); |
ba395927 KA |
898 | pte = &parent[offset]; |
899 | if (level == total) | |
900 | return pte; | |
901 | ||
6dd9a7c7 YS |
902 | if (!dma_pte_present(pte)) { |
903 | *large_page = total; | |
ba395927 | 904 | break; |
6dd9a7c7 YS |
905 | } |
906 | ||
e16922af | 907 | if (dma_pte_superpage(pte)) { |
6dd9a7c7 YS |
908 | *large_page = total; |
909 | return pte; | |
910 | } | |
911 | ||
19c239ce | 912 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
913 | total--; |
914 | } | |
915 | return NULL; | |
916 | } | |
917 | ||
ba395927 | 918 | /* clear last level pte, a tlb flush should be followed */ |
5cf0a76f | 919 | static void dma_pte_clear_range(struct dmar_domain *domain, |
595badf5 DW |
920 | unsigned long start_pfn, |
921 | unsigned long last_pfn) | |
ba395927 | 922 | { |
6dd9a7c7 | 923 | unsigned int large_page = 1; |
310a5ab9 | 924 | struct dma_pte *first_pte, *pte; |
66eae846 | 925 | |
162d1b10 JL |
926 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
927 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); | |
59c36286 | 928 | BUG_ON(start_pfn > last_pfn); |
ba395927 | 929 | |
04b18e65 | 930 | /* we don't need lock here; nobody else touches the iova range */ |
59c36286 | 931 | do { |
6dd9a7c7 YS |
932 | large_page = 1; |
933 | first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page); | |
310a5ab9 | 934 | if (!pte) { |
6dd9a7c7 | 935 | start_pfn = align_to_level(start_pfn + 1, large_page + 1); |
310a5ab9 DW |
936 | continue; |
937 | } | |
6dd9a7c7 | 938 | do { |
310a5ab9 | 939 | dma_clear_pte(pte); |
6dd9a7c7 | 940 | start_pfn += lvl_to_nr_pages(large_page); |
310a5ab9 | 941 | pte++; |
75e6bf96 DW |
942 | } while (start_pfn <= last_pfn && !first_pte_in_page(pte)); |
943 | ||
310a5ab9 DW |
944 | domain_flush_cache(domain, first_pte, |
945 | (void *)pte - (void *)first_pte); | |
59c36286 DW |
946 | |
947 | } while (start_pfn && start_pfn <= last_pfn); | |
ba395927 KA |
948 | } |
949 | ||
3269ee0b AW |
950 | static void dma_pte_free_level(struct dmar_domain *domain, int level, |
951 | struct dma_pte *pte, unsigned long pfn, | |
952 | unsigned long start_pfn, unsigned long last_pfn) | |
953 | { | |
954 | pfn = max(start_pfn, pfn); | |
955 | pte = &pte[pfn_level_offset(pfn, level)]; | |
956 | ||
957 | do { | |
958 | unsigned long level_pfn; | |
959 | struct dma_pte *level_pte; | |
960 | ||
961 | if (!dma_pte_present(pte) || dma_pte_superpage(pte)) | |
962 | goto next; | |
963 | ||
964 | level_pfn = pfn & level_mask(level - 1); | |
965 | level_pte = phys_to_virt(dma_pte_addr(pte)); | |
966 | ||
967 | if (level > 2) | |
968 | dma_pte_free_level(domain, level - 1, level_pte, | |
969 | level_pfn, start_pfn, last_pfn); | |
970 | ||
971 | /* If range covers entire pagetable, free it */ | |
972 | if (!(start_pfn > level_pfn || | |
08336fd2 | 973 | last_pfn < level_pfn + level_size(level) - 1)) { |
3269ee0b AW |
974 | dma_clear_pte(pte); |
975 | domain_flush_cache(domain, pte, sizeof(*pte)); | |
976 | free_pgtable_page(level_pte); | |
977 | } | |
978 | next: | |
979 | pfn += level_size(level); | |
980 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); | |
981 | } | |
982 | ||
ba395927 KA |
983 | /* free page table pages. last level pte should already be cleared */ |
984 | static void dma_pte_free_pagetable(struct dmar_domain *domain, | |
d794dc9b DW |
985 | unsigned long start_pfn, |
986 | unsigned long last_pfn) | |
ba395927 | 987 | { |
162d1b10 JL |
988 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
989 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); | |
59c36286 | 990 | BUG_ON(start_pfn > last_pfn); |
ba395927 | 991 | |
d41a4adb JL |
992 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
993 | ||
f3a0a52f | 994 | /* We don't need lock here; nobody else touches the iova range */ |
3269ee0b AW |
995 | dma_pte_free_level(domain, agaw_to_level(domain->agaw), |
996 | domain->pgd, 0, start_pfn, last_pfn); | |
6660c63a | 997 | |
ba395927 | 998 | /* free pgd */ |
d794dc9b | 999 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
ba395927 KA |
1000 | free_pgtable_page(domain->pgd); |
1001 | domain->pgd = NULL; | |
1002 | } | |
1003 | } | |
1004 | ||
ea8ea460 DW |
1005 | /* When a page at a given level is being unlinked from its parent, we don't |
1006 | need to *modify* it at all. All we need to do is make a list of all the | |
1007 | pages which can be freed just as soon as we've flushed the IOTLB and we | |
1008 | know the hardware page-walk will no longer touch them. | |
1009 | The 'pte' argument is the *parent* PTE, pointing to the page that is to | |
1010 | be freed. */ | |
1011 | static struct page *dma_pte_list_pagetables(struct dmar_domain *domain, | |
1012 | int level, struct dma_pte *pte, | |
1013 | struct page *freelist) | |
1014 | { | |
1015 | struct page *pg; | |
1016 | ||
1017 | pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT); | |
1018 | pg->freelist = freelist; | |
1019 | freelist = pg; | |
1020 | ||
1021 | if (level == 1) | |
1022 | return freelist; | |
1023 | ||
adeb2590 JL |
1024 | pte = page_address(pg); |
1025 | do { | |
ea8ea460 DW |
1026 | if (dma_pte_present(pte) && !dma_pte_superpage(pte)) |
1027 | freelist = dma_pte_list_pagetables(domain, level - 1, | |
1028 | pte, freelist); | |
adeb2590 JL |
1029 | pte++; |
1030 | } while (!first_pte_in_page(pte)); | |
ea8ea460 DW |
1031 | |
1032 | return freelist; | |
1033 | } | |
1034 | ||
1035 | static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level, | |
1036 | struct dma_pte *pte, unsigned long pfn, | |
1037 | unsigned long start_pfn, | |
1038 | unsigned long last_pfn, | |
1039 | struct page *freelist) | |
1040 | { | |
1041 | struct dma_pte *first_pte = NULL, *last_pte = NULL; | |
1042 | ||
1043 | pfn = max(start_pfn, pfn); | |
1044 | pte = &pte[pfn_level_offset(pfn, level)]; | |
1045 | ||
1046 | do { | |
1047 | unsigned long level_pfn; | |
1048 | ||
1049 | if (!dma_pte_present(pte)) | |
1050 | goto next; | |
1051 | ||
1052 | level_pfn = pfn & level_mask(level); | |
1053 | ||
1054 | /* If range covers entire pagetable, free it */ | |
1055 | if (start_pfn <= level_pfn && | |
1056 | last_pfn >= level_pfn + level_size(level) - 1) { | |
1057 | /* These suborbinate page tables are going away entirely. Don't | |
1058 | bother to clear them; we're just going to *free* them. */ | |
1059 | if (level > 1 && !dma_pte_superpage(pte)) | |
1060 | freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist); | |
1061 | ||
1062 | dma_clear_pte(pte); | |
1063 | if (!first_pte) | |
1064 | first_pte = pte; | |
1065 | last_pte = pte; | |
1066 | } else if (level > 1) { | |
1067 | /* Recurse down into a level that isn't *entirely* obsolete */ | |
1068 | freelist = dma_pte_clear_level(domain, level - 1, | |
1069 | phys_to_virt(dma_pte_addr(pte)), | |
1070 | level_pfn, start_pfn, last_pfn, | |
1071 | freelist); | |
1072 | } | |
1073 | next: | |
1074 | pfn += level_size(level); | |
1075 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); | |
1076 | ||
1077 | if (first_pte) | |
1078 | domain_flush_cache(domain, first_pte, | |
1079 | (void *)++last_pte - (void *)first_pte); | |
1080 | ||
1081 | return freelist; | |
1082 | } | |
1083 | ||
1084 | /* We can't just free the pages because the IOMMU may still be walking | |
1085 | the page tables, and may have cached the intermediate levels. The | |
1086 | pages can only be freed after the IOTLB flush has been done. */ | |
1087 | struct page *domain_unmap(struct dmar_domain *domain, | |
1088 | unsigned long start_pfn, | |
1089 | unsigned long last_pfn) | |
1090 | { | |
ea8ea460 DW |
1091 | struct page *freelist = NULL; |
1092 | ||
162d1b10 JL |
1093 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
1094 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); | |
ea8ea460 DW |
1095 | BUG_ON(start_pfn > last_pfn); |
1096 | ||
1097 | /* we don't need lock here; nobody else touches the iova range */ | |
1098 | freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw), | |
1099 | domain->pgd, 0, start_pfn, last_pfn, NULL); | |
1100 | ||
1101 | /* free pgd */ | |
1102 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { | |
1103 | struct page *pgd_page = virt_to_page(domain->pgd); | |
1104 | pgd_page->freelist = freelist; | |
1105 | freelist = pgd_page; | |
1106 | ||
1107 | domain->pgd = NULL; | |
1108 | } | |
1109 | ||
1110 | return freelist; | |
1111 | } | |
1112 | ||
1113 | void dma_free_pagelist(struct page *freelist) | |
1114 | { | |
1115 | struct page *pg; | |
1116 | ||
1117 | while ((pg = freelist)) { | |
1118 | freelist = pg->freelist; | |
1119 | free_pgtable_page(page_address(pg)); | |
1120 | } | |
1121 | } | |
1122 | ||
ba395927 KA |
1123 | /* iommu handling */ |
1124 | static int iommu_alloc_root_entry(struct intel_iommu *iommu) | |
1125 | { | |
1126 | struct root_entry *root; | |
1127 | unsigned long flags; | |
1128 | ||
4c923d47 | 1129 | root = (struct root_entry *)alloc_pgtable_page(iommu->node); |
ba395927 KA |
1130 | if (!root) |
1131 | return -ENOMEM; | |
1132 | ||
5b6985ce | 1133 | __iommu_flush_cache(iommu, root, ROOT_SIZE); |
ba395927 KA |
1134 | |
1135 | spin_lock_irqsave(&iommu->lock, flags); | |
1136 | iommu->root_entry = root; | |
1137 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
ba395927 KA |
1142 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
1143 | { | |
1144 | void *addr; | |
c416daa9 | 1145 | u32 sts; |
ba395927 KA |
1146 | unsigned long flag; |
1147 | ||
1148 | addr = iommu->root_entry; | |
1149 | ||
1f5b3c3f | 1150 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1151 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr)); |
1152 | ||
c416daa9 | 1153 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
1154 | |
1155 | /* Make sure hardware complete it */ | |
1156 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1157 | readl, (sts & DMA_GSTS_RTPS), sts); |
ba395927 | 1158 | |
1f5b3c3f | 1159 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1160 | } |
1161 | ||
1162 | static void iommu_flush_write_buffer(struct intel_iommu *iommu) | |
1163 | { | |
1164 | u32 val; | |
1165 | unsigned long flag; | |
1166 | ||
9af88143 | 1167 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
ba395927 | 1168 | return; |
ba395927 | 1169 | |
1f5b3c3f | 1170 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
462b60f6 | 1171 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
1172 | |
1173 | /* Make sure hardware complete it */ | |
1174 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1175 | readl, (!(val & DMA_GSTS_WBFS)), val); |
ba395927 | 1176 | |
1f5b3c3f | 1177 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1178 | } |
1179 | ||
1180 | /* return value determine if we need a write buffer flush */ | |
4c25a2c1 DW |
1181 | static void __iommu_flush_context(struct intel_iommu *iommu, |
1182 | u16 did, u16 source_id, u8 function_mask, | |
1183 | u64 type) | |
ba395927 KA |
1184 | { |
1185 | u64 val = 0; | |
1186 | unsigned long flag; | |
1187 | ||
ba395927 KA |
1188 | switch (type) { |
1189 | case DMA_CCMD_GLOBAL_INVL: | |
1190 | val = DMA_CCMD_GLOBAL_INVL; | |
1191 | break; | |
1192 | case DMA_CCMD_DOMAIN_INVL: | |
1193 | val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); | |
1194 | break; | |
1195 | case DMA_CCMD_DEVICE_INVL: | |
1196 | val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) | |
1197 | | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask); | |
1198 | break; | |
1199 | default: | |
1200 | BUG(); | |
1201 | } | |
1202 | val |= DMA_CCMD_ICC; | |
1203 | ||
1f5b3c3f | 1204 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1205 | dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); |
1206 | ||
1207 | /* Make sure hardware complete it */ | |
1208 | IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, | |
1209 | dmar_readq, (!(val & DMA_CCMD_ICC)), val); | |
1210 | ||
1f5b3c3f | 1211 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1212 | } |
1213 | ||
ba395927 | 1214 | /* return value determine if we need a write buffer flush */ |
1f0ef2aa DW |
1215 | static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, |
1216 | u64 addr, unsigned int size_order, u64 type) | |
ba395927 KA |
1217 | { |
1218 | int tlb_offset = ecap_iotlb_offset(iommu->ecap); | |
1219 | u64 val = 0, val_iva = 0; | |
1220 | unsigned long flag; | |
1221 | ||
ba395927 KA |
1222 | switch (type) { |
1223 | case DMA_TLB_GLOBAL_FLUSH: | |
1224 | /* global flush doesn't need set IVA_REG */ | |
1225 | val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; | |
1226 | break; | |
1227 | case DMA_TLB_DSI_FLUSH: | |
1228 | val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
1229 | break; | |
1230 | case DMA_TLB_PSI_FLUSH: | |
1231 | val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
ea8ea460 | 1232 | /* IH bit is passed in as part of address */ |
ba395927 KA |
1233 | val_iva = size_order | addr; |
1234 | break; | |
1235 | default: | |
1236 | BUG(); | |
1237 | } | |
1238 | /* Note: set drain read/write */ | |
1239 | #if 0 | |
1240 | /* | |
1241 | * This is probably to be super secure.. Looks like we can | |
1242 | * ignore it without any impact. | |
1243 | */ | |
1244 | if (cap_read_drain(iommu->cap)) | |
1245 | val |= DMA_TLB_READ_DRAIN; | |
1246 | #endif | |
1247 | if (cap_write_drain(iommu->cap)) | |
1248 | val |= DMA_TLB_WRITE_DRAIN; | |
1249 | ||
1f5b3c3f | 1250 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1251 | /* Note: Only uses first TLB reg currently */ |
1252 | if (val_iva) | |
1253 | dmar_writeq(iommu->reg + tlb_offset, val_iva); | |
1254 | dmar_writeq(iommu->reg + tlb_offset + 8, val); | |
1255 | ||
1256 | /* Make sure hardware complete it */ | |
1257 | IOMMU_WAIT_OP(iommu, tlb_offset + 8, | |
1258 | dmar_readq, (!(val & DMA_TLB_IVT)), val); | |
1259 | ||
1f5b3c3f | 1260 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1261 | |
1262 | /* check IOTLB invalidation granularity */ | |
1263 | if (DMA_TLB_IAIG(val) == 0) | |
1264 | printk(KERN_ERR"IOMMU: flush IOTLB failed\n"); | |
1265 | if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) | |
1266 | pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n", | |
5b6985ce FY |
1267 | (unsigned long long)DMA_TLB_IIRG(type), |
1268 | (unsigned long long)DMA_TLB_IAIG(val)); | |
ba395927 KA |
1269 | } |
1270 | ||
64ae892b DW |
1271 | static struct device_domain_info * |
1272 | iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu, | |
1273 | u8 bus, u8 devfn) | |
93a23a72 YZ |
1274 | { |
1275 | int found = 0; | |
1276 | unsigned long flags; | |
1277 | struct device_domain_info *info; | |
0bcb3e28 | 1278 | struct pci_dev *pdev; |
93a23a72 YZ |
1279 | |
1280 | if (!ecap_dev_iotlb_support(iommu->ecap)) | |
1281 | return NULL; | |
1282 | ||
1283 | if (!iommu->qi) | |
1284 | return NULL; | |
1285 | ||
1286 | spin_lock_irqsave(&device_domain_lock, flags); | |
1287 | list_for_each_entry(info, &domain->devices, link) | |
c3b497c6 JL |
1288 | if (info->iommu == iommu && info->bus == bus && |
1289 | info->devfn == devfn) { | |
93a23a72 YZ |
1290 | found = 1; |
1291 | break; | |
1292 | } | |
1293 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1294 | ||
0bcb3e28 | 1295 | if (!found || !info->dev || !dev_is_pci(info->dev)) |
93a23a72 YZ |
1296 | return NULL; |
1297 | ||
0bcb3e28 DW |
1298 | pdev = to_pci_dev(info->dev); |
1299 | ||
1300 | if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS)) | |
93a23a72 YZ |
1301 | return NULL; |
1302 | ||
0bcb3e28 | 1303 | if (!dmar_find_matched_atsr_unit(pdev)) |
93a23a72 YZ |
1304 | return NULL; |
1305 | ||
93a23a72 YZ |
1306 | return info; |
1307 | } | |
1308 | ||
1309 | static void iommu_enable_dev_iotlb(struct device_domain_info *info) | |
ba395927 | 1310 | { |
0bcb3e28 | 1311 | if (!info || !dev_is_pci(info->dev)) |
93a23a72 YZ |
1312 | return; |
1313 | ||
0bcb3e28 | 1314 | pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT); |
93a23a72 YZ |
1315 | } |
1316 | ||
1317 | static void iommu_disable_dev_iotlb(struct device_domain_info *info) | |
1318 | { | |
0bcb3e28 DW |
1319 | if (!info->dev || !dev_is_pci(info->dev) || |
1320 | !pci_ats_enabled(to_pci_dev(info->dev))) | |
93a23a72 YZ |
1321 | return; |
1322 | ||
0bcb3e28 | 1323 | pci_disable_ats(to_pci_dev(info->dev)); |
93a23a72 YZ |
1324 | } |
1325 | ||
1326 | static void iommu_flush_dev_iotlb(struct dmar_domain *domain, | |
1327 | u64 addr, unsigned mask) | |
1328 | { | |
1329 | u16 sid, qdep; | |
1330 | unsigned long flags; | |
1331 | struct device_domain_info *info; | |
1332 | ||
1333 | spin_lock_irqsave(&device_domain_lock, flags); | |
1334 | list_for_each_entry(info, &domain->devices, link) { | |
0bcb3e28 DW |
1335 | struct pci_dev *pdev; |
1336 | if (!info->dev || !dev_is_pci(info->dev)) | |
1337 | continue; | |
1338 | ||
1339 | pdev = to_pci_dev(info->dev); | |
1340 | if (!pci_ats_enabled(pdev)) | |
93a23a72 YZ |
1341 | continue; |
1342 | ||
1343 | sid = info->bus << 8 | info->devfn; | |
0bcb3e28 | 1344 | qdep = pci_ats_queue_depth(pdev); |
93a23a72 YZ |
1345 | qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask); |
1346 | } | |
1347 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1348 | } | |
1349 | ||
1f0ef2aa | 1350 | static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did, |
ea8ea460 | 1351 | unsigned long pfn, unsigned int pages, int ih, int map) |
ba395927 | 1352 | { |
9dd2fe89 | 1353 | unsigned int mask = ilog2(__roundup_pow_of_two(pages)); |
03d6a246 | 1354 | uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; |
ba395927 | 1355 | |
ba395927 KA |
1356 | BUG_ON(pages == 0); |
1357 | ||
ea8ea460 DW |
1358 | if (ih) |
1359 | ih = 1 << 6; | |
ba395927 | 1360 | /* |
9dd2fe89 YZ |
1361 | * Fallback to domain selective flush if no PSI support or the size is |
1362 | * too big. | |
ba395927 KA |
1363 | * PSI requires page size to be 2 ^ x, and the base address is naturally |
1364 | * aligned to the size | |
1365 | */ | |
9dd2fe89 YZ |
1366 | if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |
1367 | iommu->flush.flush_iotlb(iommu, did, 0, 0, | |
1f0ef2aa | 1368 | DMA_TLB_DSI_FLUSH); |
9dd2fe89 | 1369 | else |
ea8ea460 | 1370 | iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, |
9dd2fe89 | 1371 | DMA_TLB_PSI_FLUSH); |
bf92df30 YZ |
1372 | |
1373 | /* | |
82653633 NA |
1374 | * In caching mode, changes of pages from non-present to present require |
1375 | * flush. However, device IOTLB doesn't need to be flushed in this case. | |
bf92df30 | 1376 | */ |
82653633 | 1377 | if (!cap_caching_mode(iommu->cap) || !map) |
93a23a72 | 1378 | iommu_flush_dev_iotlb(iommu->domains[did], addr, mask); |
ba395927 KA |
1379 | } |
1380 | ||
f8bab735 | 1381 | static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) |
1382 | { | |
1383 | u32 pmen; | |
1384 | unsigned long flags; | |
1385 | ||
1f5b3c3f | 1386 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
f8bab735 | 1387 | pmen = readl(iommu->reg + DMAR_PMEN_REG); |
1388 | pmen &= ~DMA_PMEN_EPM; | |
1389 | writel(pmen, iommu->reg + DMAR_PMEN_REG); | |
1390 | ||
1391 | /* wait for the protected region status bit to clear */ | |
1392 | IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, | |
1393 | readl, !(pmen & DMA_PMEN_PRS), pmen); | |
1394 | ||
1f5b3c3f | 1395 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
f8bab735 | 1396 | } |
1397 | ||
2a41ccee | 1398 | static void iommu_enable_translation(struct intel_iommu *iommu) |
ba395927 KA |
1399 | { |
1400 | u32 sts; | |
1401 | unsigned long flags; | |
1402 | ||
1f5b3c3f | 1403 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
c416daa9 DW |
1404 | iommu->gcmd |= DMA_GCMD_TE; |
1405 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
ba395927 KA |
1406 | |
1407 | /* Make sure hardware complete it */ | |
1408 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1409 | readl, (sts & DMA_GSTS_TES), sts); |
ba395927 | 1410 | |
1f5b3c3f | 1411 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
ba395927 KA |
1412 | } |
1413 | ||
2a41ccee | 1414 | static void iommu_disable_translation(struct intel_iommu *iommu) |
ba395927 KA |
1415 | { |
1416 | u32 sts; | |
1417 | unsigned long flag; | |
1418 | ||
1f5b3c3f | 1419 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1420 | iommu->gcmd &= ~DMA_GCMD_TE; |
1421 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
1422 | ||
1423 | /* Make sure hardware complete it */ | |
1424 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1425 | readl, (!(sts & DMA_GSTS_TES)), sts); |
ba395927 | 1426 | |
1f5b3c3f | 1427 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1428 | } |
1429 | ||
3460a6d9 | 1430 | |
ba395927 KA |
1431 | static int iommu_init_domains(struct intel_iommu *iommu) |
1432 | { | |
1433 | unsigned long ndomains; | |
1434 | unsigned long nlongs; | |
1435 | ||
1436 | ndomains = cap_ndoms(iommu->cap); | |
852bdb04 JL |
1437 | pr_debug("IOMMU%d: Number of Domains supported <%ld>\n", |
1438 | iommu->seq_id, ndomains); | |
ba395927 KA |
1439 | nlongs = BITS_TO_LONGS(ndomains); |
1440 | ||
94a91b50 DD |
1441 | spin_lock_init(&iommu->lock); |
1442 | ||
ba395927 KA |
1443 | /* TBD: there might be 64K domains, |
1444 | * consider other allocation for future chip | |
1445 | */ | |
1446 | iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); | |
1447 | if (!iommu->domain_ids) { | |
852bdb04 JL |
1448 | pr_err("IOMMU%d: allocating domain id array failed\n", |
1449 | iommu->seq_id); | |
ba395927 KA |
1450 | return -ENOMEM; |
1451 | } | |
1452 | iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *), | |
1453 | GFP_KERNEL); | |
1454 | if (!iommu->domains) { | |
852bdb04 JL |
1455 | pr_err("IOMMU%d: allocating domain array failed\n", |
1456 | iommu->seq_id); | |
1457 | kfree(iommu->domain_ids); | |
1458 | iommu->domain_ids = NULL; | |
ba395927 KA |
1459 | return -ENOMEM; |
1460 | } | |
1461 | ||
1462 | /* | |
1463 | * if Caching mode is set, then invalid translations are tagged | |
1464 | * with domainid 0. Hence we need to pre-allocate it. | |
1465 | */ | |
1466 | if (cap_caching_mode(iommu->cap)) | |
1467 | set_bit(0, iommu->domain_ids); | |
1468 | return 0; | |
1469 | } | |
ba395927 | 1470 | |
a868e6b7 | 1471 | static void free_dmar_iommu(struct intel_iommu *iommu) |
ba395927 KA |
1472 | { |
1473 | struct dmar_domain *domain; | |
2a46ddf7 | 1474 | int i; |
ba395927 | 1475 | |
94a91b50 | 1476 | if ((iommu->domains) && (iommu->domain_ids)) { |
a45946ab | 1477 | for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) { |
a4eaa86c JL |
1478 | /* |
1479 | * Domain id 0 is reserved for invalid translation | |
1480 | * if hardware supports caching mode. | |
1481 | */ | |
1482 | if (cap_caching_mode(iommu->cap) && i == 0) | |
1483 | continue; | |
1484 | ||
94a91b50 DD |
1485 | domain = iommu->domains[i]; |
1486 | clear_bit(i, iommu->domain_ids); | |
129ad281 JL |
1487 | if (domain_detach_iommu(domain, iommu) == 0 && |
1488 | !domain_type_is_vm(domain)) | |
92d03cc8 | 1489 | domain_exit(domain); |
5e98c4b1 | 1490 | } |
ba395927 KA |
1491 | } |
1492 | ||
1493 | if (iommu->gcmd & DMA_GCMD_TE) | |
1494 | iommu_disable_translation(iommu); | |
1495 | ||
ba395927 KA |
1496 | kfree(iommu->domains); |
1497 | kfree(iommu->domain_ids); | |
a868e6b7 JL |
1498 | iommu->domains = NULL; |
1499 | iommu->domain_ids = NULL; | |
ba395927 | 1500 | |
d9630fe9 WH |
1501 | g_iommus[iommu->seq_id] = NULL; |
1502 | ||
ba395927 KA |
1503 | /* free context mapping */ |
1504 | free_context_table(iommu); | |
ba395927 KA |
1505 | } |
1506 | ||
ab8dfe25 | 1507 | static struct dmar_domain *alloc_domain(int flags) |
ba395927 | 1508 | { |
92d03cc8 JL |
1509 | /* domain id for virtual machine, it won't be set in context */ |
1510 | static atomic_t vm_domid = ATOMIC_INIT(0); | |
ba395927 | 1511 | struct dmar_domain *domain; |
ba395927 KA |
1512 | |
1513 | domain = alloc_domain_mem(); | |
1514 | if (!domain) | |
1515 | return NULL; | |
1516 | ||
ab8dfe25 | 1517 | memset(domain, 0, sizeof(*domain)); |
4c923d47 | 1518 | domain->nid = -1; |
ab8dfe25 | 1519 | domain->flags = flags; |
92d03cc8 JL |
1520 | spin_lock_init(&domain->iommu_lock); |
1521 | INIT_LIST_HEAD(&domain->devices); | |
ab8dfe25 | 1522 | if (flags & DOMAIN_FLAG_VIRTUAL_MACHINE) |
92d03cc8 | 1523 | domain->id = atomic_inc_return(&vm_domid); |
2c2e2c38 FY |
1524 | |
1525 | return domain; | |
1526 | } | |
1527 | ||
fb170fb4 JL |
1528 | static int __iommu_attach_domain(struct dmar_domain *domain, |
1529 | struct intel_iommu *iommu) | |
2c2e2c38 FY |
1530 | { |
1531 | int num; | |
1532 | unsigned long ndomains; | |
2c2e2c38 | 1533 | |
ba395927 | 1534 | ndomains = cap_ndoms(iommu->cap); |
ba395927 | 1535 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
fb170fb4 JL |
1536 | if (num < ndomains) { |
1537 | set_bit(num, iommu->domain_ids); | |
1538 | iommu->domains[num] = domain; | |
1539 | } else { | |
1540 | num = -ENOSPC; | |
ba395927 KA |
1541 | } |
1542 | ||
fb170fb4 JL |
1543 | return num; |
1544 | } | |
1545 | ||
1546 | static int iommu_attach_domain(struct dmar_domain *domain, | |
1547 | struct intel_iommu *iommu) | |
1548 | { | |
1549 | int num; | |
1550 | unsigned long flags; | |
1551 | ||
1552 | spin_lock_irqsave(&iommu->lock, flags); | |
1553 | num = __iommu_attach_domain(domain, iommu); | |
44bde614 | 1554 | spin_unlock_irqrestore(&iommu->lock, flags); |
fb170fb4 JL |
1555 | if (num < 0) |
1556 | pr_err("IOMMU: no free domain ids\n"); | |
ba395927 | 1557 | |
fb170fb4 | 1558 | return num; |
ba395927 KA |
1559 | } |
1560 | ||
44bde614 JL |
1561 | static int iommu_attach_vm_domain(struct dmar_domain *domain, |
1562 | struct intel_iommu *iommu) | |
1563 | { | |
1564 | int num; | |
1565 | unsigned long ndomains; | |
1566 | ||
1567 | ndomains = cap_ndoms(iommu->cap); | |
1568 | for_each_set_bit(num, iommu->domain_ids, ndomains) | |
1569 | if (iommu->domains[num] == domain) | |
1570 | return num; | |
1571 | ||
1572 | return __iommu_attach_domain(domain, iommu); | |
1573 | } | |
1574 | ||
2c2e2c38 FY |
1575 | static void iommu_detach_domain(struct dmar_domain *domain, |
1576 | struct intel_iommu *iommu) | |
ba395927 KA |
1577 | { |
1578 | unsigned long flags; | |
2c2e2c38 | 1579 | int num, ndomains; |
ba395927 | 1580 | |
8c11e798 | 1581 | spin_lock_irqsave(&iommu->lock, flags); |
fb170fb4 JL |
1582 | if (domain_type_is_vm_or_si(domain)) { |
1583 | ndomains = cap_ndoms(iommu->cap); | |
1584 | for_each_set_bit(num, iommu->domain_ids, ndomains) { | |
1585 | if (iommu->domains[num] == domain) { | |
1586 | clear_bit(num, iommu->domain_ids); | |
1587 | iommu->domains[num] = NULL; | |
1588 | break; | |
1589 | } | |
2c2e2c38 | 1590 | } |
fb170fb4 JL |
1591 | } else { |
1592 | clear_bit(domain->id, iommu->domain_ids); | |
1593 | iommu->domains[domain->id] = NULL; | |
2c2e2c38 | 1594 | } |
8c11e798 | 1595 | spin_unlock_irqrestore(&iommu->lock, flags); |
ba395927 KA |
1596 | } |
1597 | ||
fb170fb4 JL |
1598 | static void domain_attach_iommu(struct dmar_domain *domain, |
1599 | struct intel_iommu *iommu) | |
1600 | { | |
1601 | unsigned long flags; | |
1602 | ||
1603 | spin_lock_irqsave(&domain->iommu_lock, flags); | |
1604 | if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) { | |
1605 | domain->iommu_count++; | |
1606 | if (domain->iommu_count == 1) | |
1607 | domain->nid = iommu->node; | |
1608 | domain_update_iommu_cap(domain); | |
1609 | } | |
1610 | spin_unlock_irqrestore(&domain->iommu_lock, flags); | |
1611 | } | |
1612 | ||
1613 | static int domain_detach_iommu(struct dmar_domain *domain, | |
1614 | struct intel_iommu *iommu) | |
1615 | { | |
1616 | unsigned long flags; | |
1617 | int count = INT_MAX; | |
1618 | ||
1619 | spin_lock_irqsave(&domain->iommu_lock, flags); | |
1620 | if (test_and_clear_bit(iommu->seq_id, domain->iommu_bmp)) { | |
1621 | count = --domain->iommu_count; | |
1622 | domain_update_iommu_cap(domain); | |
1623 | } | |
1624 | spin_unlock_irqrestore(&domain->iommu_lock, flags); | |
1625 | ||
1626 | return count; | |
1627 | } | |
1628 | ||
ba395927 | 1629 | static struct iova_domain reserved_iova_list; |
8a443df4 | 1630 | static struct lock_class_key reserved_rbtree_key; |
ba395927 | 1631 | |
51a63e67 | 1632 | static int dmar_init_reserved_ranges(void) |
ba395927 KA |
1633 | { |
1634 | struct pci_dev *pdev = NULL; | |
1635 | struct iova *iova; | |
1636 | int i; | |
ba395927 | 1637 | |
f661197e | 1638 | init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN); |
ba395927 | 1639 | |
8a443df4 MG |
1640 | lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, |
1641 | &reserved_rbtree_key); | |
1642 | ||
ba395927 KA |
1643 | /* IOAPIC ranges shouldn't be accessed by DMA */ |
1644 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START), | |
1645 | IOVA_PFN(IOAPIC_RANGE_END)); | |
51a63e67 | 1646 | if (!iova) { |
ba395927 | 1647 | printk(KERN_ERR "Reserve IOAPIC range failed\n"); |
51a63e67 JC |
1648 | return -ENODEV; |
1649 | } | |
ba395927 KA |
1650 | |
1651 | /* Reserve all PCI MMIO to avoid peer-to-peer access */ | |
1652 | for_each_pci_dev(pdev) { | |
1653 | struct resource *r; | |
1654 | ||
1655 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1656 | r = &pdev->resource[i]; | |
1657 | if (!r->flags || !(r->flags & IORESOURCE_MEM)) | |
1658 | continue; | |
1a4a4551 DW |
1659 | iova = reserve_iova(&reserved_iova_list, |
1660 | IOVA_PFN(r->start), | |
1661 | IOVA_PFN(r->end)); | |
51a63e67 | 1662 | if (!iova) { |
ba395927 | 1663 | printk(KERN_ERR "Reserve iova failed\n"); |
51a63e67 JC |
1664 | return -ENODEV; |
1665 | } | |
ba395927 KA |
1666 | } |
1667 | } | |
51a63e67 | 1668 | return 0; |
ba395927 KA |
1669 | } |
1670 | ||
1671 | static void domain_reserve_special_ranges(struct dmar_domain *domain) | |
1672 | { | |
1673 | copy_reserved_iova(&reserved_iova_list, &domain->iovad); | |
1674 | } | |
1675 | ||
1676 | static inline int guestwidth_to_adjustwidth(int gaw) | |
1677 | { | |
1678 | int agaw; | |
1679 | int r = (gaw - 12) % 9; | |
1680 | ||
1681 | if (r == 0) | |
1682 | agaw = gaw; | |
1683 | else | |
1684 | agaw = gaw + 9 - r; | |
1685 | if (agaw > 64) | |
1686 | agaw = 64; | |
1687 | return agaw; | |
1688 | } | |
1689 | ||
1690 | static int domain_init(struct dmar_domain *domain, int guest_width) | |
1691 | { | |
1692 | struct intel_iommu *iommu; | |
1693 | int adjust_width, agaw; | |
1694 | unsigned long sagaw; | |
1695 | ||
f661197e | 1696 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); |
ba395927 KA |
1697 | domain_reserve_special_ranges(domain); |
1698 | ||
1699 | /* calculate AGAW */ | |
8c11e798 | 1700 | iommu = domain_get_iommu(domain); |
ba395927 KA |
1701 | if (guest_width > cap_mgaw(iommu->cap)) |
1702 | guest_width = cap_mgaw(iommu->cap); | |
1703 | domain->gaw = guest_width; | |
1704 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
1705 | agaw = width_to_agaw(adjust_width); | |
1706 | sagaw = cap_sagaw(iommu->cap); | |
1707 | if (!test_bit(agaw, &sagaw)) { | |
1708 | /* hardware doesn't support it, choose a bigger one */ | |
1709 | pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw); | |
1710 | agaw = find_next_bit(&sagaw, 5, agaw); | |
1711 | if (agaw >= 5) | |
1712 | return -ENODEV; | |
1713 | } | |
1714 | domain->agaw = agaw; | |
ba395927 | 1715 | |
8e604097 WH |
1716 | if (ecap_coherent(iommu->ecap)) |
1717 | domain->iommu_coherency = 1; | |
1718 | else | |
1719 | domain->iommu_coherency = 0; | |
1720 | ||
58c610bd SY |
1721 | if (ecap_sc_support(iommu->ecap)) |
1722 | domain->iommu_snooping = 1; | |
1723 | else | |
1724 | domain->iommu_snooping = 0; | |
1725 | ||
214e39aa DW |
1726 | if (intel_iommu_superpage) |
1727 | domain->iommu_superpage = fls(cap_super_page_val(iommu->cap)); | |
1728 | else | |
1729 | domain->iommu_superpage = 0; | |
1730 | ||
4c923d47 | 1731 | domain->nid = iommu->node; |
c7151a8d | 1732 | |
ba395927 | 1733 | /* always allocate the top pgd */ |
4c923d47 | 1734 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
ba395927 KA |
1735 | if (!domain->pgd) |
1736 | return -ENOMEM; | |
5b6985ce | 1737 | __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE); |
ba395927 KA |
1738 | return 0; |
1739 | } | |
1740 | ||
1741 | static void domain_exit(struct dmar_domain *domain) | |
1742 | { | |
2c2e2c38 FY |
1743 | struct dmar_drhd_unit *drhd; |
1744 | struct intel_iommu *iommu; | |
ea8ea460 | 1745 | struct page *freelist = NULL; |
ba395927 KA |
1746 | |
1747 | /* Domain 0 is reserved, so dont process it */ | |
1748 | if (!domain) | |
1749 | return; | |
1750 | ||
7b668357 AW |
1751 | /* Flush any lazy unmaps that may reference this domain */ |
1752 | if (!intel_iommu_strict) | |
1753 | flush_unmaps_timeout(0); | |
1754 | ||
92d03cc8 | 1755 | /* remove associated devices */ |
ba395927 | 1756 | domain_remove_dev_info(domain); |
92d03cc8 | 1757 | |
ba395927 KA |
1758 | /* destroy iovas */ |
1759 | put_iova_domain(&domain->iovad); | |
ba395927 | 1760 | |
ea8ea460 | 1761 | freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
ba395927 | 1762 | |
92d03cc8 | 1763 | /* clear attached or cached domains */ |
0e242612 | 1764 | rcu_read_lock(); |
2c2e2c38 | 1765 | for_each_active_iommu(iommu, drhd) |
fb170fb4 | 1766 | iommu_detach_domain(domain, iommu); |
0e242612 | 1767 | rcu_read_unlock(); |
2c2e2c38 | 1768 | |
ea8ea460 DW |
1769 | dma_free_pagelist(freelist); |
1770 | ||
ba395927 KA |
1771 | free_domain_mem(domain); |
1772 | } | |
1773 | ||
64ae892b DW |
1774 | static int domain_context_mapping_one(struct dmar_domain *domain, |
1775 | struct intel_iommu *iommu, | |
1776 | u8 bus, u8 devfn, int translation) | |
ba395927 KA |
1777 | { |
1778 | struct context_entry *context; | |
ba395927 | 1779 | unsigned long flags; |
ea6606b0 | 1780 | struct dma_pte *pgd; |
ea6606b0 WH |
1781 | int id; |
1782 | int agaw; | |
93a23a72 | 1783 | struct device_domain_info *info = NULL; |
ba395927 KA |
1784 | |
1785 | pr_debug("Set context mapping for %02x:%02x.%d\n", | |
1786 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
4ed0d3e6 | 1787 | |
ba395927 | 1788 | BUG_ON(!domain->pgd); |
4ed0d3e6 FY |
1789 | BUG_ON(translation != CONTEXT_TT_PASS_THROUGH && |
1790 | translation != CONTEXT_TT_MULTI_LEVEL); | |
5331fe6f | 1791 | |
ba395927 KA |
1792 | context = device_to_context_entry(iommu, bus, devfn); |
1793 | if (!context) | |
1794 | return -ENOMEM; | |
1795 | spin_lock_irqsave(&iommu->lock, flags); | |
c07e7d21 | 1796 | if (context_present(context)) { |
ba395927 KA |
1797 | spin_unlock_irqrestore(&iommu->lock, flags); |
1798 | return 0; | |
1799 | } | |
1800 | ||
ea6606b0 WH |
1801 | id = domain->id; |
1802 | pgd = domain->pgd; | |
1803 | ||
ab8dfe25 | 1804 | if (domain_type_is_vm_or_si(domain)) { |
44bde614 JL |
1805 | if (domain_type_is_vm(domain)) { |
1806 | id = iommu_attach_vm_domain(domain, iommu); | |
fb170fb4 | 1807 | if (id < 0) { |
ea6606b0 | 1808 | spin_unlock_irqrestore(&iommu->lock, flags); |
fb170fb4 | 1809 | pr_err("IOMMU: no free domain ids\n"); |
ea6606b0 WH |
1810 | return -EFAULT; |
1811 | } | |
ea6606b0 WH |
1812 | } |
1813 | ||
1814 | /* Skip top levels of page tables for | |
1815 | * iommu which has less agaw than default. | |
1672af11 | 1816 | * Unnecessary for PT mode. |
ea6606b0 | 1817 | */ |
1672af11 CW |
1818 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
1819 | for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) { | |
1820 | pgd = phys_to_virt(dma_pte_addr(pgd)); | |
1821 | if (!dma_pte_present(pgd)) { | |
1822 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1823 | return -ENOMEM; | |
1824 | } | |
ea6606b0 WH |
1825 | } |
1826 | } | |
1827 | } | |
1828 | ||
1829 | context_set_domain_id(context, id); | |
4ed0d3e6 | 1830 | |
93a23a72 | 1831 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
64ae892b | 1832 | info = iommu_support_dev_iotlb(domain, iommu, bus, devfn); |
93a23a72 YZ |
1833 | translation = info ? CONTEXT_TT_DEV_IOTLB : |
1834 | CONTEXT_TT_MULTI_LEVEL; | |
1835 | } | |
4ed0d3e6 FY |
1836 | /* |
1837 | * In pass through mode, AW must be programmed to indicate the largest | |
1838 | * AGAW value supported by hardware. And ASR is ignored by hardware. | |
1839 | */ | |
93a23a72 | 1840 | if (unlikely(translation == CONTEXT_TT_PASS_THROUGH)) |
4ed0d3e6 | 1841 | context_set_address_width(context, iommu->msagaw); |
93a23a72 YZ |
1842 | else { |
1843 | context_set_address_root(context, virt_to_phys(pgd)); | |
1844 | context_set_address_width(context, iommu->agaw); | |
1845 | } | |
4ed0d3e6 FY |
1846 | |
1847 | context_set_translation_type(context, translation); | |
c07e7d21 MM |
1848 | context_set_fault_enable(context); |
1849 | context_set_present(context); | |
5331fe6f | 1850 | domain_flush_cache(domain, context, sizeof(*context)); |
ba395927 | 1851 | |
4c25a2c1 DW |
1852 | /* |
1853 | * It's a non-present to present mapping. If hardware doesn't cache | |
1854 | * non-present entry we only need to flush the write-buffer. If the | |
1855 | * _does_ cache non-present entries, then it does so in the special | |
1856 | * domain #0, which we have to flush: | |
1857 | */ | |
1858 | if (cap_caching_mode(iommu->cap)) { | |
1859 | iommu->flush.flush_context(iommu, 0, | |
1860 | (((u16)bus) << 8) | devfn, | |
1861 | DMA_CCMD_MASK_NOBIT, | |
1862 | DMA_CCMD_DEVICE_INVL); | |
18fd779a | 1863 | iommu->flush.flush_iotlb(iommu, id, 0, 0, DMA_TLB_DSI_FLUSH); |
4c25a2c1 | 1864 | } else { |
ba395927 | 1865 | iommu_flush_write_buffer(iommu); |
4c25a2c1 | 1866 | } |
93a23a72 | 1867 | iommu_enable_dev_iotlb(info); |
ba395927 | 1868 | spin_unlock_irqrestore(&iommu->lock, flags); |
c7151a8d | 1869 | |
fb170fb4 JL |
1870 | domain_attach_iommu(domain, iommu); |
1871 | ||
ba395927 KA |
1872 | return 0; |
1873 | } | |
1874 | ||
579305f7 AW |
1875 | struct domain_context_mapping_data { |
1876 | struct dmar_domain *domain; | |
1877 | struct intel_iommu *iommu; | |
1878 | int translation; | |
1879 | }; | |
1880 | ||
1881 | static int domain_context_mapping_cb(struct pci_dev *pdev, | |
1882 | u16 alias, void *opaque) | |
1883 | { | |
1884 | struct domain_context_mapping_data *data = opaque; | |
1885 | ||
1886 | return domain_context_mapping_one(data->domain, data->iommu, | |
1887 | PCI_BUS_NUM(alias), alias & 0xff, | |
1888 | data->translation); | |
1889 | } | |
1890 | ||
ba395927 | 1891 | static int |
e1f167f3 DW |
1892 | domain_context_mapping(struct dmar_domain *domain, struct device *dev, |
1893 | int translation) | |
ba395927 | 1894 | { |
64ae892b | 1895 | struct intel_iommu *iommu; |
156baca8 | 1896 | u8 bus, devfn; |
579305f7 | 1897 | struct domain_context_mapping_data data; |
64ae892b | 1898 | |
e1f167f3 | 1899 | iommu = device_to_iommu(dev, &bus, &devfn); |
64ae892b DW |
1900 | if (!iommu) |
1901 | return -ENODEV; | |
ba395927 | 1902 | |
579305f7 AW |
1903 | if (!dev_is_pci(dev)) |
1904 | return domain_context_mapping_one(domain, iommu, bus, devfn, | |
4ed0d3e6 | 1905 | translation); |
579305f7 AW |
1906 | |
1907 | data.domain = domain; | |
1908 | data.iommu = iommu; | |
1909 | data.translation = translation; | |
1910 | ||
1911 | return pci_for_each_dma_alias(to_pci_dev(dev), | |
1912 | &domain_context_mapping_cb, &data); | |
1913 | } | |
1914 | ||
1915 | static int domain_context_mapped_cb(struct pci_dev *pdev, | |
1916 | u16 alias, void *opaque) | |
1917 | { | |
1918 | struct intel_iommu *iommu = opaque; | |
1919 | ||
1920 | return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff); | |
ba395927 KA |
1921 | } |
1922 | ||
e1f167f3 | 1923 | static int domain_context_mapped(struct device *dev) |
ba395927 | 1924 | { |
5331fe6f | 1925 | struct intel_iommu *iommu; |
156baca8 | 1926 | u8 bus, devfn; |
5331fe6f | 1927 | |
e1f167f3 | 1928 | iommu = device_to_iommu(dev, &bus, &devfn); |
5331fe6f WH |
1929 | if (!iommu) |
1930 | return -ENODEV; | |
ba395927 | 1931 | |
579305f7 AW |
1932 | if (!dev_is_pci(dev)) |
1933 | return device_context_mapped(iommu, bus, devfn); | |
e1f167f3 | 1934 | |
579305f7 AW |
1935 | return !pci_for_each_dma_alias(to_pci_dev(dev), |
1936 | domain_context_mapped_cb, iommu); | |
ba395927 KA |
1937 | } |
1938 | ||
f532959b FY |
1939 | /* Returns a number of VTD pages, but aligned to MM page size */ |
1940 | static inline unsigned long aligned_nrpages(unsigned long host_addr, | |
1941 | size_t size) | |
1942 | { | |
1943 | host_addr &= ~PAGE_MASK; | |
1944 | return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; | |
1945 | } | |
1946 | ||
6dd9a7c7 YS |
1947 | /* Return largest possible superpage level for a given mapping */ |
1948 | static inline int hardware_largepage_caps(struct dmar_domain *domain, | |
1949 | unsigned long iov_pfn, | |
1950 | unsigned long phy_pfn, | |
1951 | unsigned long pages) | |
1952 | { | |
1953 | int support, level = 1; | |
1954 | unsigned long pfnmerge; | |
1955 | ||
1956 | support = domain->iommu_superpage; | |
1957 | ||
1958 | /* To use a large page, the virtual *and* physical addresses | |
1959 | must be aligned to 2MiB/1GiB/etc. Lower bits set in either | |
1960 | of them will mean we have to use smaller pages. So just | |
1961 | merge them and check both at once. */ | |
1962 | pfnmerge = iov_pfn | phy_pfn; | |
1963 | ||
1964 | while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) { | |
1965 | pages >>= VTD_STRIDE_SHIFT; | |
1966 | if (!pages) | |
1967 | break; | |
1968 | pfnmerge >>= VTD_STRIDE_SHIFT; | |
1969 | level++; | |
1970 | support--; | |
1971 | } | |
1972 | return level; | |
1973 | } | |
1974 | ||
9051aa02 DW |
1975 | static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
1976 | struct scatterlist *sg, unsigned long phys_pfn, | |
1977 | unsigned long nr_pages, int prot) | |
e1605495 DW |
1978 | { |
1979 | struct dma_pte *first_pte = NULL, *pte = NULL; | |
9051aa02 | 1980 | phys_addr_t uninitialized_var(pteval); |
9051aa02 | 1981 | unsigned long sg_res; |
6dd9a7c7 YS |
1982 | unsigned int largepage_lvl = 0; |
1983 | unsigned long lvl_pages = 0; | |
e1605495 | 1984 | |
162d1b10 | 1985 | BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1)); |
e1605495 DW |
1986 | |
1987 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) | |
1988 | return -EINVAL; | |
1989 | ||
1990 | prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP; | |
1991 | ||
9051aa02 DW |
1992 | if (sg) |
1993 | sg_res = 0; | |
1994 | else { | |
1995 | sg_res = nr_pages + 1; | |
1996 | pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot; | |
1997 | } | |
1998 | ||
6dd9a7c7 | 1999 | while (nr_pages > 0) { |
c85994e4 DW |
2000 | uint64_t tmp; |
2001 | ||
e1605495 | 2002 | if (!sg_res) { |
f532959b | 2003 | sg_res = aligned_nrpages(sg->offset, sg->length); |
e1605495 DW |
2004 | sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; |
2005 | sg->dma_length = sg->length; | |
2006 | pteval = page_to_phys(sg_page(sg)) | prot; | |
6dd9a7c7 | 2007 | phys_pfn = pteval >> VTD_PAGE_SHIFT; |
e1605495 | 2008 | } |
6dd9a7c7 | 2009 | |
e1605495 | 2010 | if (!pte) { |
6dd9a7c7 YS |
2011 | largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res); |
2012 | ||
5cf0a76f | 2013 | first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl); |
e1605495 DW |
2014 | if (!pte) |
2015 | return -ENOMEM; | |
6dd9a7c7 | 2016 | /* It is large page*/ |
6491d4d0 | 2017 | if (largepage_lvl > 1) { |
6dd9a7c7 | 2018 | pteval |= DMA_PTE_LARGE_PAGE; |
d41a4adb JL |
2019 | lvl_pages = lvl_to_nr_pages(largepage_lvl); |
2020 | /* | |
2021 | * Ensure that old small page tables are | |
2022 | * removed to make room for superpage, | |
2023 | * if they exist. | |
2024 | */ | |
6491d4d0 | 2025 | dma_pte_free_pagetable(domain, iov_pfn, |
d41a4adb | 2026 | iov_pfn + lvl_pages - 1); |
6491d4d0 | 2027 | } else { |
6dd9a7c7 | 2028 | pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE; |
6491d4d0 | 2029 | } |
6dd9a7c7 | 2030 | |
e1605495 DW |
2031 | } |
2032 | /* We don't need lock here, nobody else | |
2033 | * touches the iova range | |
2034 | */ | |
7766a3fb | 2035 | tmp = cmpxchg64_local(&pte->val, 0ULL, pteval); |
c85994e4 | 2036 | if (tmp) { |
1bf20f0d | 2037 | static int dumps = 5; |
c85994e4 DW |
2038 | printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n", |
2039 | iov_pfn, tmp, (unsigned long long)pteval); | |
1bf20f0d DW |
2040 | if (dumps) { |
2041 | dumps--; | |
2042 | debug_dma_dump_mappings(NULL); | |
2043 | } | |
2044 | WARN_ON(1); | |
2045 | } | |
6dd9a7c7 YS |
2046 | |
2047 | lvl_pages = lvl_to_nr_pages(largepage_lvl); | |
2048 | ||
2049 | BUG_ON(nr_pages < lvl_pages); | |
2050 | BUG_ON(sg_res < lvl_pages); | |
2051 | ||
2052 | nr_pages -= lvl_pages; | |
2053 | iov_pfn += lvl_pages; | |
2054 | phys_pfn += lvl_pages; | |
2055 | pteval += lvl_pages * VTD_PAGE_SIZE; | |
2056 | sg_res -= lvl_pages; | |
2057 | ||
2058 | /* If the next PTE would be the first in a new page, then we | |
2059 | need to flush the cache on the entries we've just written. | |
2060 | And then we'll need to recalculate 'pte', so clear it and | |
2061 | let it get set again in the if (!pte) block above. | |
2062 | ||
2063 | If we're done (!nr_pages) we need to flush the cache too. | |
2064 | ||
2065 | Also if we've been setting superpages, we may need to | |
2066 | recalculate 'pte' and switch back to smaller pages for the | |
2067 | end of the mapping, if the trailing size is not enough to | |
2068 | use another superpage (i.e. sg_res < lvl_pages). */ | |
e1605495 | 2069 | pte++; |
6dd9a7c7 YS |
2070 | if (!nr_pages || first_pte_in_page(pte) || |
2071 | (largepage_lvl > 1 && sg_res < lvl_pages)) { | |
e1605495 DW |
2072 | domain_flush_cache(domain, first_pte, |
2073 | (void *)pte - (void *)first_pte); | |
2074 | pte = NULL; | |
2075 | } | |
6dd9a7c7 YS |
2076 | |
2077 | if (!sg_res && nr_pages) | |
e1605495 DW |
2078 | sg = sg_next(sg); |
2079 | } | |
2080 | return 0; | |
2081 | } | |
2082 | ||
9051aa02 DW |
2083 | static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
2084 | struct scatterlist *sg, unsigned long nr_pages, | |
2085 | int prot) | |
ba395927 | 2086 | { |
9051aa02 DW |
2087 | return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot); |
2088 | } | |
6f6a00e4 | 2089 | |
9051aa02 DW |
2090 | static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
2091 | unsigned long phys_pfn, unsigned long nr_pages, | |
2092 | int prot) | |
2093 | { | |
2094 | return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot); | |
ba395927 KA |
2095 | } |
2096 | ||
c7151a8d | 2097 | static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn) |
ba395927 | 2098 | { |
c7151a8d WH |
2099 | if (!iommu) |
2100 | return; | |
8c11e798 WH |
2101 | |
2102 | clear_context_table(iommu, bus, devfn); | |
2103 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
4c25a2c1 | 2104 | DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 2105 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
ba395927 KA |
2106 | } |
2107 | ||
109b9b04 DW |
2108 | static inline void unlink_domain_info(struct device_domain_info *info) |
2109 | { | |
2110 | assert_spin_locked(&device_domain_lock); | |
2111 | list_del(&info->link); | |
2112 | list_del(&info->global); | |
2113 | if (info->dev) | |
0bcb3e28 | 2114 | info->dev->archdata.iommu = NULL; |
109b9b04 DW |
2115 | } |
2116 | ||
ba395927 KA |
2117 | static void domain_remove_dev_info(struct dmar_domain *domain) |
2118 | { | |
3a74ca01 | 2119 | struct device_domain_info *info, *tmp; |
fb170fb4 | 2120 | unsigned long flags; |
ba395927 KA |
2121 | |
2122 | spin_lock_irqsave(&device_domain_lock, flags); | |
3a74ca01 | 2123 | list_for_each_entry_safe(info, tmp, &domain->devices, link) { |
109b9b04 | 2124 | unlink_domain_info(info); |
ba395927 KA |
2125 | spin_unlock_irqrestore(&device_domain_lock, flags); |
2126 | ||
93a23a72 | 2127 | iommu_disable_dev_iotlb(info); |
7c7faa11 | 2128 | iommu_detach_dev(info->iommu, info->bus, info->devfn); |
ba395927 | 2129 | |
ab8dfe25 | 2130 | if (domain_type_is_vm(domain)) { |
7c7faa11 | 2131 | iommu_detach_dependent_devices(info->iommu, info->dev); |
fb170fb4 | 2132 | domain_detach_iommu(domain, info->iommu); |
92d03cc8 JL |
2133 | } |
2134 | ||
2135 | free_devinfo_mem(info); | |
ba395927 KA |
2136 | spin_lock_irqsave(&device_domain_lock, flags); |
2137 | } | |
2138 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2139 | } | |
2140 | ||
2141 | /* | |
2142 | * find_domain | |
1525a29a | 2143 | * Note: we use struct device->archdata.iommu stores the info |
ba395927 | 2144 | */ |
1525a29a | 2145 | static struct dmar_domain *find_domain(struct device *dev) |
ba395927 KA |
2146 | { |
2147 | struct device_domain_info *info; | |
2148 | ||
2149 | /* No lock here, assumes no domain exit in normal case */ | |
1525a29a | 2150 | info = dev->archdata.iommu; |
ba395927 KA |
2151 | if (info) |
2152 | return info->domain; | |
2153 | return NULL; | |
2154 | } | |
2155 | ||
5a8f40e8 | 2156 | static inline struct device_domain_info * |
745f2586 JL |
2157 | dmar_search_domain_by_dev_info(int segment, int bus, int devfn) |
2158 | { | |
2159 | struct device_domain_info *info; | |
2160 | ||
2161 | list_for_each_entry(info, &device_domain_list, global) | |
41e80dca | 2162 | if (info->iommu->segment == segment && info->bus == bus && |
745f2586 | 2163 | info->devfn == devfn) |
5a8f40e8 | 2164 | return info; |
745f2586 JL |
2165 | |
2166 | return NULL; | |
2167 | } | |
2168 | ||
5a8f40e8 | 2169 | static struct dmar_domain *dmar_insert_dev_info(struct intel_iommu *iommu, |
41e80dca | 2170 | int bus, int devfn, |
b718cd3d DW |
2171 | struct device *dev, |
2172 | struct dmar_domain *domain) | |
745f2586 | 2173 | { |
5a8f40e8 | 2174 | struct dmar_domain *found = NULL; |
745f2586 JL |
2175 | struct device_domain_info *info; |
2176 | unsigned long flags; | |
2177 | ||
2178 | info = alloc_devinfo_mem(); | |
2179 | if (!info) | |
b718cd3d | 2180 | return NULL; |
745f2586 | 2181 | |
745f2586 JL |
2182 | info->bus = bus; |
2183 | info->devfn = devfn; | |
2184 | info->dev = dev; | |
2185 | info->domain = domain; | |
5a8f40e8 | 2186 | info->iommu = iommu; |
745f2586 JL |
2187 | |
2188 | spin_lock_irqsave(&device_domain_lock, flags); | |
2189 | if (dev) | |
0bcb3e28 | 2190 | found = find_domain(dev); |
5a8f40e8 DW |
2191 | else { |
2192 | struct device_domain_info *info2; | |
41e80dca | 2193 | info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn); |
5a8f40e8 DW |
2194 | if (info2) |
2195 | found = info2->domain; | |
2196 | } | |
745f2586 JL |
2197 | if (found) { |
2198 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2199 | free_devinfo_mem(info); | |
b718cd3d DW |
2200 | /* Caller must free the original domain */ |
2201 | return found; | |
745f2586 JL |
2202 | } |
2203 | ||
b718cd3d DW |
2204 | list_add(&info->link, &domain->devices); |
2205 | list_add(&info->global, &device_domain_list); | |
2206 | if (dev) | |
2207 | dev->archdata.iommu = info; | |
2208 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2209 | ||
2210 | return domain; | |
745f2586 JL |
2211 | } |
2212 | ||
579305f7 AW |
2213 | static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque) |
2214 | { | |
2215 | *(u16 *)opaque = alias; | |
2216 | return 0; | |
2217 | } | |
2218 | ||
ba395927 | 2219 | /* domain is initialized */ |
146922ec | 2220 | static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw) |
ba395927 | 2221 | { |
579305f7 AW |
2222 | struct dmar_domain *domain, *tmp; |
2223 | struct intel_iommu *iommu; | |
5a8f40e8 | 2224 | struct device_domain_info *info; |
579305f7 | 2225 | u16 dma_alias; |
ba395927 | 2226 | unsigned long flags; |
aa4d066a | 2227 | u8 bus, devfn; |
ba395927 | 2228 | |
146922ec | 2229 | domain = find_domain(dev); |
ba395927 KA |
2230 | if (domain) |
2231 | return domain; | |
2232 | ||
579305f7 AW |
2233 | iommu = device_to_iommu(dev, &bus, &devfn); |
2234 | if (!iommu) | |
2235 | return NULL; | |
2236 | ||
146922ec DW |
2237 | if (dev_is_pci(dev)) { |
2238 | struct pci_dev *pdev = to_pci_dev(dev); | |
276dbf99 | 2239 | |
579305f7 AW |
2240 | pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias); |
2241 | ||
2242 | spin_lock_irqsave(&device_domain_lock, flags); | |
2243 | info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus), | |
2244 | PCI_BUS_NUM(dma_alias), | |
2245 | dma_alias & 0xff); | |
2246 | if (info) { | |
2247 | iommu = info->iommu; | |
2248 | domain = info->domain; | |
5a8f40e8 | 2249 | } |
579305f7 | 2250 | spin_unlock_irqrestore(&device_domain_lock, flags); |
ba395927 | 2251 | |
579305f7 AW |
2252 | /* DMA alias already has a domain, uses it */ |
2253 | if (info) | |
2254 | goto found_domain; | |
2255 | } | |
ba395927 | 2256 | |
146922ec | 2257 | /* Allocate and initialize new domain for the device */ |
ab8dfe25 | 2258 | domain = alloc_domain(0); |
745f2586 | 2259 | if (!domain) |
579305f7 | 2260 | return NULL; |
44bde614 JL |
2261 | domain->id = iommu_attach_domain(domain, iommu); |
2262 | if (domain->id < 0) { | |
2fe9723d | 2263 | free_domain_mem(domain); |
579305f7 | 2264 | return NULL; |
2c2e2c38 | 2265 | } |
fb170fb4 | 2266 | domain_attach_iommu(domain, iommu); |
579305f7 AW |
2267 | if (domain_init(domain, gaw)) { |
2268 | domain_exit(domain); | |
2269 | return NULL; | |
2c2e2c38 | 2270 | } |
ba395927 | 2271 | |
579305f7 AW |
2272 | /* register PCI DMA alias device */ |
2273 | if (dev_is_pci(dev)) { | |
2274 | tmp = dmar_insert_dev_info(iommu, PCI_BUS_NUM(dma_alias), | |
2275 | dma_alias & 0xff, NULL, domain); | |
2276 | ||
2277 | if (!tmp || tmp != domain) { | |
2278 | domain_exit(domain); | |
2279 | domain = tmp; | |
2280 | } | |
2281 | ||
b718cd3d | 2282 | if (!domain) |
579305f7 | 2283 | return NULL; |
ba395927 KA |
2284 | } |
2285 | ||
2286 | found_domain: | |
579305f7 AW |
2287 | tmp = dmar_insert_dev_info(iommu, bus, devfn, dev, domain); |
2288 | ||
2289 | if (!tmp || tmp != domain) { | |
2290 | domain_exit(domain); | |
2291 | domain = tmp; | |
2292 | } | |
b718cd3d DW |
2293 | |
2294 | return domain; | |
ba395927 KA |
2295 | } |
2296 | ||
2c2e2c38 | 2297 | static int iommu_identity_mapping; |
e0fc7e0b DW |
2298 | #define IDENTMAP_ALL 1 |
2299 | #define IDENTMAP_GFX 2 | |
2300 | #define IDENTMAP_AZALIA 4 | |
2c2e2c38 | 2301 | |
b213203e DW |
2302 | static int iommu_domain_identity_map(struct dmar_domain *domain, |
2303 | unsigned long long start, | |
2304 | unsigned long long end) | |
ba395927 | 2305 | { |
c5395d5c DW |
2306 | unsigned long first_vpfn = start >> VTD_PAGE_SHIFT; |
2307 | unsigned long last_vpfn = end >> VTD_PAGE_SHIFT; | |
2308 | ||
2309 | if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn), | |
2310 | dma_to_mm_pfn(last_vpfn))) { | |
ba395927 | 2311 | printk(KERN_ERR "IOMMU: reserve iova failed\n"); |
b213203e | 2312 | return -ENOMEM; |
ba395927 KA |
2313 | } |
2314 | ||
c5395d5c DW |
2315 | pr_debug("Mapping reserved region %llx-%llx for domain %d\n", |
2316 | start, end, domain->id); | |
ba395927 KA |
2317 | /* |
2318 | * RMRR range might have overlap with physical memory range, | |
2319 | * clear it first | |
2320 | */ | |
c5395d5c | 2321 | dma_pte_clear_range(domain, first_vpfn, last_vpfn); |
ba395927 | 2322 | |
c5395d5c DW |
2323 | return domain_pfn_mapping(domain, first_vpfn, first_vpfn, |
2324 | last_vpfn - first_vpfn + 1, | |
61df7443 | 2325 | DMA_PTE_READ|DMA_PTE_WRITE); |
b213203e DW |
2326 | } |
2327 | ||
0b9d9753 | 2328 | static int iommu_prepare_identity_map(struct device *dev, |
b213203e DW |
2329 | unsigned long long start, |
2330 | unsigned long long end) | |
2331 | { | |
2332 | struct dmar_domain *domain; | |
2333 | int ret; | |
2334 | ||
0b9d9753 | 2335 | domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
b213203e DW |
2336 | if (!domain) |
2337 | return -ENOMEM; | |
2338 | ||
19943b0e DW |
2339 | /* For _hardware_ passthrough, don't bother. But for software |
2340 | passthrough, we do it anyway -- it may indicate a memory | |
2341 | range which is reserved in E820, so which didn't get set | |
2342 | up to start with in si_domain */ | |
2343 | if (domain == si_domain && hw_pass_through) { | |
2344 | printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n", | |
0b9d9753 | 2345 | dev_name(dev), start, end); |
19943b0e DW |
2346 | return 0; |
2347 | } | |
2348 | ||
2349 | printk(KERN_INFO | |
2350 | "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n", | |
0b9d9753 | 2351 | dev_name(dev), start, end); |
2ff729f5 | 2352 | |
5595b528 DW |
2353 | if (end < start) { |
2354 | WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n" | |
2355 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
2356 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
2357 | dmi_get_system_info(DMI_BIOS_VERSION), | |
2358 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
2359 | ret = -EIO; | |
2360 | goto error; | |
2361 | } | |
2362 | ||
2ff729f5 DW |
2363 | if (end >> agaw_to_width(domain->agaw)) { |
2364 | WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n" | |
2365 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
2366 | agaw_to_width(domain->agaw), | |
2367 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
2368 | dmi_get_system_info(DMI_BIOS_VERSION), | |
2369 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
2370 | ret = -EIO; | |
2371 | goto error; | |
2372 | } | |
19943b0e | 2373 | |
b213203e | 2374 | ret = iommu_domain_identity_map(domain, start, end); |
ba395927 KA |
2375 | if (ret) |
2376 | goto error; | |
2377 | ||
2378 | /* context entry init */ | |
0b9d9753 | 2379 | ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL); |
b213203e DW |
2380 | if (ret) |
2381 | goto error; | |
2382 | ||
2383 | return 0; | |
2384 | ||
2385 | error: | |
ba395927 KA |
2386 | domain_exit(domain); |
2387 | return ret; | |
ba395927 KA |
2388 | } |
2389 | ||
2390 | static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr, | |
0b9d9753 | 2391 | struct device *dev) |
ba395927 | 2392 | { |
0b9d9753 | 2393 | if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) |
ba395927 | 2394 | return 0; |
0b9d9753 DW |
2395 | return iommu_prepare_identity_map(dev, rmrr->base_address, |
2396 | rmrr->end_address); | |
ba395927 KA |
2397 | } |
2398 | ||
d3f13810 | 2399 | #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA |
49a0429e KA |
2400 | static inline void iommu_prepare_isa(void) |
2401 | { | |
2402 | struct pci_dev *pdev; | |
2403 | int ret; | |
2404 | ||
2405 | pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
2406 | if (!pdev) | |
2407 | return; | |
2408 | ||
c7ab48d2 | 2409 | printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n"); |
0b9d9753 | 2410 | ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1); |
49a0429e KA |
2411 | |
2412 | if (ret) | |
c7ab48d2 DW |
2413 | printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; " |
2414 | "floppy might not work\n"); | |
49a0429e | 2415 | |
9b27e82d | 2416 | pci_dev_put(pdev); |
49a0429e KA |
2417 | } |
2418 | #else | |
2419 | static inline void iommu_prepare_isa(void) | |
2420 | { | |
2421 | return; | |
2422 | } | |
d3f13810 | 2423 | #endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */ |
49a0429e | 2424 | |
2c2e2c38 | 2425 | static int md_domain_init(struct dmar_domain *domain, int guest_width); |
c7ab48d2 | 2426 | |
071e1374 | 2427 | static int __init si_domain_init(int hw) |
2c2e2c38 FY |
2428 | { |
2429 | struct dmar_drhd_unit *drhd; | |
2430 | struct intel_iommu *iommu; | |
c7ab48d2 | 2431 | int nid, ret = 0; |
44bde614 | 2432 | bool first = true; |
2c2e2c38 | 2433 | |
ab8dfe25 | 2434 | si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY); |
2c2e2c38 FY |
2435 | if (!si_domain) |
2436 | return -EFAULT; | |
2437 | ||
2c2e2c38 FY |
2438 | for_each_active_iommu(iommu, drhd) { |
2439 | ret = iommu_attach_domain(si_domain, iommu); | |
fb170fb4 | 2440 | if (ret < 0) { |
2c2e2c38 FY |
2441 | domain_exit(si_domain); |
2442 | return -EFAULT; | |
44bde614 JL |
2443 | } else if (first) { |
2444 | si_domain->id = ret; | |
2445 | first = false; | |
2446 | } else if (si_domain->id != ret) { | |
2447 | domain_exit(si_domain); | |
2448 | return -EFAULT; | |
2c2e2c38 | 2449 | } |
fb170fb4 | 2450 | domain_attach_iommu(si_domain, iommu); |
2c2e2c38 FY |
2451 | } |
2452 | ||
2453 | if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { | |
2454 | domain_exit(si_domain); | |
2455 | return -EFAULT; | |
2456 | } | |
2457 | ||
9544c003 JL |
2458 | pr_debug("IOMMU: identity mapping domain is domain %d\n", |
2459 | si_domain->id); | |
2c2e2c38 | 2460 | |
19943b0e DW |
2461 | if (hw) |
2462 | return 0; | |
2463 | ||
c7ab48d2 | 2464 | for_each_online_node(nid) { |
5dfe8660 TH |
2465 | unsigned long start_pfn, end_pfn; |
2466 | int i; | |
2467 | ||
2468 | for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) { | |
2469 | ret = iommu_domain_identity_map(si_domain, | |
2470 | PFN_PHYS(start_pfn), PFN_PHYS(end_pfn)); | |
2471 | if (ret) | |
2472 | return ret; | |
2473 | } | |
c7ab48d2 DW |
2474 | } |
2475 | ||
2c2e2c38 FY |
2476 | return 0; |
2477 | } | |
2478 | ||
9b226624 | 2479 | static int identity_mapping(struct device *dev) |
2c2e2c38 FY |
2480 | { |
2481 | struct device_domain_info *info; | |
2482 | ||
2483 | if (likely(!iommu_identity_mapping)) | |
2484 | return 0; | |
2485 | ||
9b226624 | 2486 | info = dev->archdata.iommu; |
cb452a40 MT |
2487 | if (info && info != DUMMY_DEVICE_DOMAIN_INFO) |
2488 | return (info->domain == si_domain); | |
2c2e2c38 | 2489 | |
2c2e2c38 FY |
2490 | return 0; |
2491 | } | |
2492 | ||
2493 | static int domain_add_dev_info(struct dmar_domain *domain, | |
5913c9bf | 2494 | struct device *dev, int translation) |
2c2e2c38 | 2495 | { |
0ac72664 | 2496 | struct dmar_domain *ndomain; |
5a8f40e8 | 2497 | struct intel_iommu *iommu; |
156baca8 | 2498 | u8 bus, devfn; |
5fe60f4e | 2499 | int ret; |
2c2e2c38 | 2500 | |
5913c9bf | 2501 | iommu = device_to_iommu(dev, &bus, &devfn); |
5a8f40e8 DW |
2502 | if (!iommu) |
2503 | return -ENODEV; | |
2504 | ||
5913c9bf | 2505 | ndomain = dmar_insert_dev_info(iommu, bus, devfn, dev, domain); |
0ac72664 DW |
2506 | if (ndomain != domain) |
2507 | return -EBUSY; | |
2c2e2c38 | 2508 | |
5913c9bf | 2509 | ret = domain_context_mapping(domain, dev, translation); |
e2ad23d0 | 2510 | if (ret) { |
5913c9bf | 2511 | domain_remove_one_dev_info(domain, dev); |
e2ad23d0 DW |
2512 | return ret; |
2513 | } | |
2514 | ||
2c2e2c38 FY |
2515 | return 0; |
2516 | } | |
2517 | ||
0b9d9753 | 2518 | static bool device_has_rmrr(struct device *dev) |
ea2447f7 TM |
2519 | { |
2520 | struct dmar_rmrr_unit *rmrr; | |
832bd858 | 2521 | struct device *tmp; |
ea2447f7 TM |
2522 | int i; |
2523 | ||
0e242612 | 2524 | rcu_read_lock(); |
ea2447f7 | 2525 | for_each_rmrr_units(rmrr) { |
b683b230 JL |
2526 | /* |
2527 | * Return TRUE if this RMRR contains the device that | |
2528 | * is passed in. | |
2529 | */ | |
2530 | for_each_active_dev_scope(rmrr->devices, | |
2531 | rmrr->devices_cnt, i, tmp) | |
0b9d9753 | 2532 | if (tmp == dev) { |
0e242612 | 2533 | rcu_read_unlock(); |
ea2447f7 | 2534 | return true; |
b683b230 | 2535 | } |
ea2447f7 | 2536 | } |
0e242612 | 2537 | rcu_read_unlock(); |
ea2447f7 TM |
2538 | return false; |
2539 | } | |
2540 | ||
c875d2c1 AW |
2541 | /* |
2542 | * There are a couple cases where we need to restrict the functionality of | |
2543 | * devices associated with RMRRs. The first is when evaluating a device for | |
2544 | * identity mapping because problems exist when devices are moved in and out | |
2545 | * of domains and their respective RMRR information is lost. This means that | |
2546 | * a device with associated RMRRs will never be in a "passthrough" domain. | |
2547 | * The second is use of the device through the IOMMU API. This interface | |
2548 | * expects to have full control of the IOVA space for the device. We cannot | |
2549 | * satisfy both the requirement that RMRR access is maintained and have an | |
2550 | * unencumbered IOVA space. We also have no ability to quiesce the device's | |
2551 | * use of the RMRR space or even inform the IOMMU API user of the restriction. | |
2552 | * We therefore prevent devices associated with an RMRR from participating in | |
2553 | * the IOMMU API, which eliminates them from device assignment. | |
2554 | * | |
2555 | * In both cases we assume that PCI USB devices with RMRRs have them largely | |
2556 | * for historical reasons and that the RMRR space is not actively used post | |
2557 | * boot. This exclusion may change if vendors begin to abuse it. | |
2558 | */ | |
2559 | static bool device_is_rmrr_locked(struct device *dev) | |
2560 | { | |
2561 | if (!device_has_rmrr(dev)) | |
2562 | return false; | |
2563 | ||
2564 | if (dev_is_pci(dev)) { | |
2565 | struct pci_dev *pdev = to_pci_dev(dev); | |
2566 | ||
2567 | if ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB) | |
2568 | return false; | |
2569 | } | |
2570 | ||
2571 | return true; | |
2572 | } | |
2573 | ||
3bdb2591 | 2574 | static int iommu_should_identity_map(struct device *dev, int startup) |
6941af28 | 2575 | { |
ea2447f7 | 2576 | |
3bdb2591 DW |
2577 | if (dev_is_pci(dev)) { |
2578 | struct pci_dev *pdev = to_pci_dev(dev); | |
ea2447f7 | 2579 | |
c875d2c1 | 2580 | if (device_is_rmrr_locked(dev)) |
3bdb2591 | 2581 | return 0; |
e0fc7e0b | 2582 | |
3bdb2591 DW |
2583 | if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev)) |
2584 | return 1; | |
e0fc7e0b | 2585 | |
3bdb2591 DW |
2586 | if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev)) |
2587 | return 1; | |
6941af28 | 2588 | |
3bdb2591 | 2589 | if (!(iommu_identity_mapping & IDENTMAP_ALL)) |
3dfc813d | 2590 | return 0; |
3bdb2591 DW |
2591 | |
2592 | /* | |
2593 | * We want to start off with all devices in the 1:1 domain, and | |
2594 | * take them out later if we find they can't access all of memory. | |
2595 | * | |
2596 | * However, we can't do this for PCI devices behind bridges, | |
2597 | * because all PCI devices behind the same bridge will end up | |
2598 | * with the same source-id on their transactions. | |
2599 | * | |
2600 | * Practically speaking, we can't change things around for these | |
2601 | * devices at run-time, because we can't be sure there'll be no | |
2602 | * DMA transactions in flight for any of their siblings. | |
2603 | * | |
2604 | * So PCI devices (unless they're on the root bus) as well as | |
2605 | * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of | |
2606 | * the 1:1 domain, just in _case_ one of their siblings turns out | |
2607 | * not to be able to map all of memory. | |
2608 | */ | |
2609 | if (!pci_is_pcie(pdev)) { | |
2610 | if (!pci_is_root_bus(pdev->bus)) | |
2611 | return 0; | |
2612 | if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI) | |
2613 | return 0; | |
2614 | } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE) | |
3dfc813d | 2615 | return 0; |
3bdb2591 DW |
2616 | } else { |
2617 | if (device_has_rmrr(dev)) | |
2618 | return 0; | |
2619 | } | |
3dfc813d | 2620 | |
3bdb2591 | 2621 | /* |
3dfc813d | 2622 | * At boot time, we don't yet know if devices will be 64-bit capable. |
3bdb2591 | 2623 | * Assume that they will — if they turn out not to be, then we can |
3dfc813d DW |
2624 | * take them out of the 1:1 domain later. |
2625 | */ | |
8fcc5372 CW |
2626 | if (!startup) { |
2627 | /* | |
2628 | * If the device's dma_mask is less than the system's memory | |
2629 | * size then this is not a candidate for identity mapping. | |
2630 | */ | |
3bdb2591 | 2631 | u64 dma_mask = *dev->dma_mask; |
8fcc5372 | 2632 | |
3bdb2591 DW |
2633 | if (dev->coherent_dma_mask && |
2634 | dev->coherent_dma_mask < dma_mask) | |
2635 | dma_mask = dev->coherent_dma_mask; | |
8fcc5372 | 2636 | |
3bdb2591 | 2637 | return dma_mask >= dma_get_required_mask(dev); |
8fcc5372 | 2638 | } |
6941af28 DW |
2639 | |
2640 | return 1; | |
2641 | } | |
2642 | ||
cf04eee8 DW |
2643 | static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw) |
2644 | { | |
2645 | int ret; | |
2646 | ||
2647 | if (!iommu_should_identity_map(dev, 1)) | |
2648 | return 0; | |
2649 | ||
2650 | ret = domain_add_dev_info(si_domain, dev, | |
2651 | hw ? CONTEXT_TT_PASS_THROUGH : | |
2652 | CONTEXT_TT_MULTI_LEVEL); | |
2653 | if (!ret) | |
2654 | pr_info("IOMMU: %s identity mapping for device %s\n", | |
2655 | hw ? "hardware" : "software", dev_name(dev)); | |
2656 | else if (ret == -ENODEV) | |
2657 | /* device not associated with an iommu */ | |
2658 | ret = 0; | |
2659 | ||
2660 | return ret; | |
2661 | } | |
2662 | ||
2663 | ||
071e1374 | 2664 | static int __init iommu_prepare_static_identity_mapping(int hw) |
2c2e2c38 | 2665 | { |
2c2e2c38 | 2666 | struct pci_dev *pdev = NULL; |
cf04eee8 DW |
2667 | struct dmar_drhd_unit *drhd; |
2668 | struct intel_iommu *iommu; | |
2669 | struct device *dev; | |
2670 | int i; | |
2671 | int ret = 0; | |
2c2e2c38 | 2672 | |
19943b0e | 2673 | ret = si_domain_init(hw); |
2c2e2c38 FY |
2674 | if (ret) |
2675 | return -EFAULT; | |
2676 | ||
2c2e2c38 | 2677 | for_each_pci_dev(pdev) { |
cf04eee8 DW |
2678 | ret = dev_prepare_static_identity_mapping(&pdev->dev, hw); |
2679 | if (ret) | |
2680 | return ret; | |
2681 | } | |
2682 | ||
2683 | for_each_active_iommu(iommu, drhd) | |
2684 | for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) { | |
2685 | struct acpi_device_physical_node *pn; | |
2686 | struct acpi_device *adev; | |
2687 | ||
2688 | if (dev->bus != &acpi_bus_type) | |
2689 | continue; | |
2690 | ||
2691 | adev= to_acpi_device(dev); | |
2692 | mutex_lock(&adev->physical_node_lock); | |
2693 | list_for_each_entry(pn, &adev->physical_node_list, node) { | |
2694 | ret = dev_prepare_static_identity_mapping(pn->dev, hw); | |
2695 | if (ret) | |
2696 | break; | |
eae460b6 | 2697 | } |
cf04eee8 DW |
2698 | mutex_unlock(&adev->physical_node_lock); |
2699 | if (ret) | |
2700 | return ret; | |
62edf5dc | 2701 | } |
2c2e2c38 FY |
2702 | |
2703 | return 0; | |
2704 | } | |
2705 | ||
b779260b | 2706 | static int __init init_dmars(void) |
ba395927 KA |
2707 | { |
2708 | struct dmar_drhd_unit *drhd; | |
2709 | struct dmar_rmrr_unit *rmrr; | |
832bd858 | 2710 | struct device *dev; |
ba395927 | 2711 | struct intel_iommu *iommu; |
9d783ba0 | 2712 | int i, ret; |
2c2e2c38 | 2713 | |
ba395927 KA |
2714 | /* |
2715 | * for each drhd | |
2716 | * allocate root | |
2717 | * initialize and program root entry to not present | |
2718 | * endfor | |
2719 | */ | |
2720 | for_each_drhd_unit(drhd) { | |
5e0d2a6f | 2721 | /* |
2722 | * lock not needed as this is only incremented in the single | |
2723 | * threaded kernel __init code path all other access are read | |
2724 | * only | |
2725 | */ | |
78d8e704 | 2726 | if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) { |
1b198bb0 MT |
2727 | g_num_of_iommus++; |
2728 | continue; | |
2729 | } | |
2730 | printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n", | |
78d8e704 | 2731 | DMAR_UNITS_SUPPORTED); |
5e0d2a6f | 2732 | } |
2733 | ||
d9630fe9 WH |
2734 | g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), |
2735 | GFP_KERNEL); | |
2736 | if (!g_iommus) { | |
2737 | printk(KERN_ERR "Allocating global iommu array failed\n"); | |
2738 | ret = -ENOMEM; | |
2739 | goto error; | |
2740 | } | |
2741 | ||
80b20dd8 | 2742 | deferred_flush = kzalloc(g_num_of_iommus * |
2743 | sizeof(struct deferred_flush_tables), GFP_KERNEL); | |
2744 | if (!deferred_flush) { | |
5e0d2a6f | 2745 | ret = -ENOMEM; |
989d51fc | 2746 | goto free_g_iommus; |
5e0d2a6f | 2747 | } |
2748 | ||
7c919779 | 2749 | for_each_active_iommu(iommu, drhd) { |
d9630fe9 | 2750 | g_iommus[iommu->seq_id] = iommu; |
ba395927 | 2751 | |
e61d98d8 SS |
2752 | ret = iommu_init_domains(iommu); |
2753 | if (ret) | |
989d51fc | 2754 | goto free_iommu; |
e61d98d8 | 2755 | |
ba395927 KA |
2756 | /* |
2757 | * TBD: | |
2758 | * we could share the same root & context tables | |
25985edc | 2759 | * among all IOMMU's. Need to Split it later. |
ba395927 KA |
2760 | */ |
2761 | ret = iommu_alloc_root_entry(iommu); | |
2762 | if (ret) { | |
2763 | printk(KERN_ERR "IOMMU: allocate root entry failed\n"); | |
989d51fc | 2764 | goto free_iommu; |
ba395927 | 2765 | } |
4ed0d3e6 | 2766 | if (!ecap_pass_through(iommu->ecap)) |
19943b0e | 2767 | hw_pass_through = 0; |
ba395927 KA |
2768 | } |
2769 | ||
1531a6a6 SS |
2770 | /* |
2771 | * Start from the sane iommu hardware state. | |
2772 | */ | |
7c919779 | 2773 | for_each_active_iommu(iommu, drhd) { |
1531a6a6 SS |
2774 | /* |
2775 | * If the queued invalidation is already initialized by us | |
2776 | * (for example, while enabling interrupt-remapping) then | |
2777 | * we got the things already rolling from a sane state. | |
2778 | */ | |
2779 | if (iommu->qi) | |
2780 | continue; | |
2781 | ||
2782 | /* | |
2783 | * Clear any previous faults. | |
2784 | */ | |
2785 | dmar_fault(-1, iommu); | |
2786 | /* | |
2787 | * Disable queued invalidation if supported and already enabled | |
2788 | * before OS handover. | |
2789 | */ | |
2790 | dmar_disable_qi(iommu); | |
2791 | } | |
2792 | ||
7c919779 | 2793 | for_each_active_iommu(iommu, drhd) { |
a77b67d4 YS |
2794 | if (dmar_enable_qi(iommu)) { |
2795 | /* | |
2796 | * Queued Invalidate not enabled, use Register Based | |
2797 | * Invalidate | |
2798 | */ | |
2799 | iommu->flush.flush_context = __iommu_flush_context; | |
2800 | iommu->flush.flush_iotlb = __iommu_flush_iotlb; | |
680a7524 | 2801 | printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based " |
b4e0f9eb | 2802 | "invalidation\n", |
680a7524 | 2803 | iommu->seq_id, |
b4e0f9eb | 2804 | (unsigned long long)drhd->reg_base_addr); |
a77b67d4 YS |
2805 | } else { |
2806 | iommu->flush.flush_context = qi_flush_context; | |
2807 | iommu->flush.flush_iotlb = qi_flush_iotlb; | |
680a7524 | 2808 | printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued " |
b4e0f9eb | 2809 | "invalidation\n", |
680a7524 | 2810 | iommu->seq_id, |
b4e0f9eb | 2811 | (unsigned long long)drhd->reg_base_addr); |
a77b67d4 YS |
2812 | } |
2813 | } | |
2814 | ||
19943b0e | 2815 | if (iommu_pass_through) |
e0fc7e0b DW |
2816 | iommu_identity_mapping |= IDENTMAP_ALL; |
2817 | ||
d3f13810 | 2818 | #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA |
e0fc7e0b | 2819 | iommu_identity_mapping |= IDENTMAP_GFX; |
19943b0e | 2820 | #endif |
e0fc7e0b DW |
2821 | |
2822 | check_tylersburg_isoch(); | |
2823 | ||
ba395927 | 2824 | /* |
19943b0e DW |
2825 | * If pass through is not set or not enabled, setup context entries for |
2826 | * identity mappings for rmrr, gfx, and isa and may fall back to static | |
2827 | * identity mapping if iommu_identity_mapping is set. | |
ba395927 | 2828 | */ |
19943b0e DW |
2829 | if (iommu_identity_mapping) { |
2830 | ret = iommu_prepare_static_identity_mapping(hw_pass_through); | |
4ed0d3e6 | 2831 | if (ret) { |
19943b0e | 2832 | printk(KERN_CRIT "Failed to setup IOMMU pass-through\n"); |
989d51fc | 2833 | goto free_iommu; |
ba395927 KA |
2834 | } |
2835 | } | |
ba395927 | 2836 | /* |
19943b0e DW |
2837 | * For each rmrr |
2838 | * for each dev attached to rmrr | |
2839 | * do | |
2840 | * locate drhd for dev, alloc domain for dev | |
2841 | * allocate free domain | |
2842 | * allocate page table entries for rmrr | |
2843 | * if context not allocated for bus | |
2844 | * allocate and init context | |
2845 | * set present in root table for this bus | |
2846 | * init context with domain, translation etc | |
2847 | * endfor | |
2848 | * endfor | |
ba395927 | 2849 | */ |
19943b0e DW |
2850 | printk(KERN_INFO "IOMMU: Setting RMRR:\n"); |
2851 | for_each_rmrr_units(rmrr) { | |
b683b230 JL |
2852 | /* some BIOS lists non-exist devices in DMAR table. */ |
2853 | for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt, | |
832bd858 | 2854 | i, dev) { |
0b9d9753 | 2855 | ret = iommu_prepare_rmrr_dev(rmrr, dev); |
19943b0e DW |
2856 | if (ret) |
2857 | printk(KERN_ERR | |
2858 | "IOMMU: mapping reserved region failed\n"); | |
ba395927 | 2859 | } |
4ed0d3e6 | 2860 | } |
49a0429e | 2861 | |
19943b0e DW |
2862 | iommu_prepare_isa(); |
2863 | ||
ba395927 KA |
2864 | /* |
2865 | * for each drhd | |
2866 | * enable fault log | |
2867 | * global invalidate context cache | |
2868 | * global invalidate iotlb | |
2869 | * enable translation | |
2870 | */ | |
7c919779 | 2871 | for_each_iommu(iommu, drhd) { |
51a63e67 JC |
2872 | if (drhd->ignored) { |
2873 | /* | |
2874 | * we always have to disable PMRs or DMA may fail on | |
2875 | * this device | |
2876 | */ | |
2877 | if (force_on) | |
7c919779 | 2878 | iommu_disable_protect_mem_regions(iommu); |
ba395927 | 2879 | continue; |
51a63e67 | 2880 | } |
ba395927 KA |
2881 | |
2882 | iommu_flush_write_buffer(iommu); | |
2883 | ||
3460a6d9 KA |
2884 | ret = dmar_set_interrupt(iommu); |
2885 | if (ret) | |
989d51fc | 2886 | goto free_iommu; |
3460a6d9 | 2887 | |
ba395927 KA |
2888 | iommu_set_root_entry(iommu); |
2889 | ||
4c25a2c1 | 2890 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 2891 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
2a41ccee | 2892 | iommu_enable_translation(iommu); |
b94996c9 | 2893 | iommu_disable_protect_mem_regions(iommu); |
ba395927 KA |
2894 | } |
2895 | ||
2896 | return 0; | |
989d51fc JL |
2897 | |
2898 | free_iommu: | |
7c919779 | 2899 | for_each_active_iommu(iommu, drhd) |
a868e6b7 | 2900 | free_dmar_iommu(iommu); |
9bdc531e | 2901 | kfree(deferred_flush); |
989d51fc | 2902 | free_g_iommus: |
d9630fe9 | 2903 | kfree(g_iommus); |
989d51fc | 2904 | error: |
ba395927 KA |
2905 | return ret; |
2906 | } | |
2907 | ||
5a5e02a6 | 2908 | /* This takes a number of _MM_ pages, not VTD pages */ |
875764de DW |
2909 | static struct iova *intel_alloc_iova(struct device *dev, |
2910 | struct dmar_domain *domain, | |
2911 | unsigned long nrpages, uint64_t dma_mask) | |
ba395927 | 2912 | { |
ba395927 | 2913 | struct iova *iova = NULL; |
ba395927 | 2914 | |
875764de DW |
2915 | /* Restrict dma_mask to the width that the iommu can handle */ |
2916 | dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask); | |
2917 | ||
2918 | if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) { | |
ba395927 KA |
2919 | /* |
2920 | * First try to allocate an io virtual address in | |
284901a9 | 2921 | * DMA_BIT_MASK(32) and if that fails then try allocating |
3609801e | 2922 | * from higher range |
ba395927 | 2923 | */ |
875764de DW |
2924 | iova = alloc_iova(&domain->iovad, nrpages, |
2925 | IOVA_PFN(DMA_BIT_MASK(32)), 1); | |
2926 | if (iova) | |
2927 | return iova; | |
2928 | } | |
2929 | iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1); | |
2930 | if (unlikely(!iova)) { | |
2931 | printk(KERN_ERR "Allocating %ld-page iova for %s failed", | |
207e3592 | 2932 | nrpages, dev_name(dev)); |
f76aec76 KA |
2933 | return NULL; |
2934 | } | |
2935 | ||
2936 | return iova; | |
2937 | } | |
2938 | ||
d4b709f4 | 2939 | static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev) |
f76aec76 KA |
2940 | { |
2941 | struct dmar_domain *domain; | |
2942 | int ret; | |
2943 | ||
d4b709f4 | 2944 | domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
f76aec76 | 2945 | if (!domain) { |
d4b709f4 DW |
2946 | printk(KERN_ERR "Allocating domain for %s failed", |
2947 | dev_name(dev)); | |
4fe05bbc | 2948 | return NULL; |
ba395927 KA |
2949 | } |
2950 | ||
2951 | /* make sure context mapping is ok */ | |
d4b709f4 DW |
2952 | if (unlikely(!domain_context_mapped(dev))) { |
2953 | ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL); | |
f76aec76 | 2954 | if (ret) { |
d4b709f4 DW |
2955 | printk(KERN_ERR "Domain context map for %s failed", |
2956 | dev_name(dev)); | |
4fe05bbc | 2957 | return NULL; |
f76aec76 | 2958 | } |
ba395927 KA |
2959 | } |
2960 | ||
f76aec76 KA |
2961 | return domain; |
2962 | } | |
2963 | ||
d4b709f4 | 2964 | static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev) |
147202aa DW |
2965 | { |
2966 | struct device_domain_info *info; | |
2967 | ||
2968 | /* No lock here, assumes no domain exit in normal case */ | |
d4b709f4 | 2969 | info = dev->archdata.iommu; |
147202aa DW |
2970 | if (likely(info)) |
2971 | return info->domain; | |
2972 | ||
2973 | return __get_valid_domain_for_dev(dev); | |
2974 | } | |
2975 | ||
3d89194a | 2976 | static int iommu_dummy(struct device *dev) |
2c2e2c38 | 2977 | { |
3d89194a | 2978 | return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; |
2c2e2c38 FY |
2979 | } |
2980 | ||
ecb509ec | 2981 | /* Check if the dev needs to go through non-identity map and unmap process.*/ |
73676832 | 2982 | static int iommu_no_mapping(struct device *dev) |
2c2e2c38 FY |
2983 | { |
2984 | int found; | |
2985 | ||
3d89194a | 2986 | if (iommu_dummy(dev)) |
1e4c64c4 DW |
2987 | return 1; |
2988 | ||
2c2e2c38 | 2989 | if (!iommu_identity_mapping) |
1e4c64c4 | 2990 | return 0; |
2c2e2c38 | 2991 | |
9b226624 | 2992 | found = identity_mapping(dev); |
2c2e2c38 | 2993 | if (found) { |
ecb509ec | 2994 | if (iommu_should_identity_map(dev, 0)) |
2c2e2c38 FY |
2995 | return 1; |
2996 | else { | |
2997 | /* | |
2998 | * 32 bit DMA is removed from si_domain and fall back | |
2999 | * to non-identity mapping. | |
3000 | */ | |
bf9c9eda | 3001 | domain_remove_one_dev_info(si_domain, dev); |
2c2e2c38 | 3002 | printk(KERN_INFO "32bit %s uses non-identity mapping\n", |
ecb509ec | 3003 | dev_name(dev)); |
2c2e2c38 FY |
3004 | return 0; |
3005 | } | |
3006 | } else { | |
3007 | /* | |
3008 | * In case of a detached 64 bit DMA device from vm, the device | |
3009 | * is put into si_domain for identity mapping. | |
3010 | */ | |
ecb509ec | 3011 | if (iommu_should_identity_map(dev, 0)) { |
2c2e2c38 | 3012 | int ret; |
5913c9bf | 3013 | ret = domain_add_dev_info(si_domain, dev, |
5fe60f4e DW |
3014 | hw_pass_through ? |
3015 | CONTEXT_TT_PASS_THROUGH : | |
3016 | CONTEXT_TT_MULTI_LEVEL); | |
2c2e2c38 FY |
3017 | if (!ret) { |
3018 | printk(KERN_INFO "64bit %s uses identity mapping\n", | |
ecb509ec | 3019 | dev_name(dev)); |
2c2e2c38 FY |
3020 | return 1; |
3021 | } | |
3022 | } | |
3023 | } | |
3024 | ||
1e4c64c4 | 3025 | return 0; |
2c2e2c38 FY |
3026 | } |
3027 | ||
5040a918 | 3028 | static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr, |
bb9e6d65 | 3029 | size_t size, int dir, u64 dma_mask) |
f76aec76 | 3030 | { |
f76aec76 | 3031 | struct dmar_domain *domain; |
5b6985ce | 3032 | phys_addr_t start_paddr; |
f76aec76 KA |
3033 | struct iova *iova; |
3034 | int prot = 0; | |
6865f0d1 | 3035 | int ret; |
8c11e798 | 3036 | struct intel_iommu *iommu; |
33041ec0 | 3037 | unsigned long paddr_pfn = paddr >> PAGE_SHIFT; |
f76aec76 KA |
3038 | |
3039 | BUG_ON(dir == DMA_NONE); | |
2c2e2c38 | 3040 | |
5040a918 | 3041 | if (iommu_no_mapping(dev)) |
6865f0d1 | 3042 | return paddr; |
f76aec76 | 3043 | |
5040a918 | 3044 | domain = get_valid_domain_for_dev(dev); |
f76aec76 KA |
3045 | if (!domain) |
3046 | return 0; | |
3047 | ||
8c11e798 | 3048 | iommu = domain_get_iommu(domain); |
88cb6a74 | 3049 | size = aligned_nrpages(paddr, size); |
f76aec76 | 3050 | |
5040a918 | 3051 | iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask); |
f76aec76 KA |
3052 | if (!iova) |
3053 | goto error; | |
3054 | ||
ba395927 KA |
3055 | /* |
3056 | * Check if DMAR supports zero-length reads on write only | |
3057 | * mappings.. | |
3058 | */ | |
3059 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 3060 | !cap_zlr(iommu->cap)) |
ba395927 KA |
3061 | prot |= DMA_PTE_READ; |
3062 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
3063 | prot |= DMA_PTE_WRITE; | |
3064 | /* | |
6865f0d1 | 3065 | * paddr - (paddr + size) might be partial page, we should map the whole |
ba395927 | 3066 | * page. Note: if two part of one page are separately mapped, we |
6865f0d1 | 3067 | * might have two guest_addr mapping to the same host paddr, but this |
ba395927 KA |
3068 | * is not a big problem |
3069 | */ | |
0ab36de2 | 3070 | ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo), |
33041ec0 | 3071 | mm_to_dma_pfn(paddr_pfn), size, prot); |
ba395927 KA |
3072 | if (ret) |
3073 | goto error; | |
3074 | ||
1f0ef2aa DW |
3075 | /* it's a non-present to present mapping. Only flush if caching mode */ |
3076 | if (cap_caching_mode(iommu->cap)) | |
ea8ea460 | 3077 | iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1); |
1f0ef2aa | 3078 | else |
8c11e798 | 3079 | iommu_flush_write_buffer(iommu); |
f76aec76 | 3080 | |
03d6a246 DW |
3081 | start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT; |
3082 | start_paddr += paddr & ~PAGE_MASK; | |
3083 | return start_paddr; | |
ba395927 | 3084 | |
ba395927 | 3085 | error: |
f76aec76 KA |
3086 | if (iova) |
3087 | __free_iova(&domain->iovad, iova); | |
4cf2e75d | 3088 | printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n", |
5040a918 | 3089 | dev_name(dev), size, (unsigned long long)paddr, dir); |
ba395927 KA |
3090 | return 0; |
3091 | } | |
3092 | ||
ffbbef5c FT |
3093 | static dma_addr_t intel_map_page(struct device *dev, struct page *page, |
3094 | unsigned long offset, size_t size, | |
3095 | enum dma_data_direction dir, | |
3096 | struct dma_attrs *attrs) | |
bb9e6d65 | 3097 | { |
ffbbef5c | 3098 | return __intel_map_single(dev, page_to_phys(page) + offset, size, |
46333e37 | 3099 | dir, *dev->dma_mask); |
bb9e6d65 FT |
3100 | } |
3101 | ||
5e0d2a6f | 3102 | static void flush_unmaps(void) |
3103 | { | |
80b20dd8 | 3104 | int i, j; |
5e0d2a6f | 3105 | |
5e0d2a6f | 3106 | timer_on = 0; |
3107 | ||
3108 | /* just flush them all */ | |
3109 | for (i = 0; i < g_num_of_iommus; i++) { | |
a2bb8459 WH |
3110 | struct intel_iommu *iommu = g_iommus[i]; |
3111 | if (!iommu) | |
3112 | continue; | |
c42d9f32 | 3113 | |
9dd2fe89 YZ |
3114 | if (!deferred_flush[i].next) |
3115 | continue; | |
3116 | ||
78d5f0f5 NA |
3117 | /* In caching mode, global flushes turn emulation expensive */ |
3118 | if (!cap_caching_mode(iommu->cap)) | |
3119 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, | |
93a23a72 | 3120 | DMA_TLB_GLOBAL_FLUSH); |
9dd2fe89 | 3121 | for (j = 0; j < deferred_flush[i].next; j++) { |
93a23a72 YZ |
3122 | unsigned long mask; |
3123 | struct iova *iova = deferred_flush[i].iova[j]; | |
78d5f0f5 NA |
3124 | struct dmar_domain *domain = deferred_flush[i].domain[j]; |
3125 | ||
3126 | /* On real hardware multiple invalidations are expensive */ | |
3127 | if (cap_caching_mode(iommu->cap)) | |
3128 | iommu_flush_iotlb_psi(iommu, domain->id, | |
a156ef99 | 3129 | iova->pfn_lo, iova_size(iova), |
ea8ea460 | 3130 | !deferred_flush[i].freelist[j], 0); |
78d5f0f5 | 3131 | else { |
a156ef99 | 3132 | mask = ilog2(mm_to_dma_pfn(iova_size(iova))); |
78d5f0f5 NA |
3133 | iommu_flush_dev_iotlb(deferred_flush[i].domain[j], |
3134 | (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask); | |
3135 | } | |
93a23a72 | 3136 | __free_iova(&deferred_flush[i].domain[j]->iovad, iova); |
ea8ea460 DW |
3137 | if (deferred_flush[i].freelist[j]) |
3138 | dma_free_pagelist(deferred_flush[i].freelist[j]); | |
80b20dd8 | 3139 | } |
9dd2fe89 | 3140 | deferred_flush[i].next = 0; |
5e0d2a6f | 3141 | } |
3142 | ||
5e0d2a6f | 3143 | list_size = 0; |
5e0d2a6f | 3144 | } |
3145 | ||
3146 | static void flush_unmaps_timeout(unsigned long data) | |
3147 | { | |
80b20dd8 | 3148 | unsigned long flags; |
3149 | ||
3150 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
5e0d2a6f | 3151 | flush_unmaps(); |
80b20dd8 | 3152 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
5e0d2a6f | 3153 | } |
3154 | ||
ea8ea460 | 3155 | static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist) |
5e0d2a6f | 3156 | { |
3157 | unsigned long flags; | |
80b20dd8 | 3158 | int next, iommu_id; |
8c11e798 | 3159 | struct intel_iommu *iommu; |
5e0d2a6f | 3160 | |
3161 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
80b20dd8 | 3162 | if (list_size == HIGH_WATER_MARK) |
3163 | flush_unmaps(); | |
3164 | ||
8c11e798 WH |
3165 | iommu = domain_get_iommu(dom); |
3166 | iommu_id = iommu->seq_id; | |
c42d9f32 | 3167 | |
80b20dd8 | 3168 | next = deferred_flush[iommu_id].next; |
3169 | deferred_flush[iommu_id].domain[next] = dom; | |
3170 | deferred_flush[iommu_id].iova[next] = iova; | |
ea8ea460 | 3171 | deferred_flush[iommu_id].freelist[next] = freelist; |
80b20dd8 | 3172 | deferred_flush[iommu_id].next++; |
5e0d2a6f | 3173 | |
3174 | if (!timer_on) { | |
3175 | mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10)); | |
3176 | timer_on = 1; | |
3177 | } | |
3178 | list_size++; | |
3179 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); | |
3180 | } | |
3181 | ||
d41a4adb | 3182 | static void intel_unmap(struct device *dev, dma_addr_t dev_addr) |
ba395927 | 3183 | { |
f76aec76 | 3184 | struct dmar_domain *domain; |
d794dc9b | 3185 | unsigned long start_pfn, last_pfn; |
ba395927 | 3186 | struct iova *iova; |
8c11e798 | 3187 | struct intel_iommu *iommu; |
ea8ea460 | 3188 | struct page *freelist; |
ba395927 | 3189 | |
73676832 | 3190 | if (iommu_no_mapping(dev)) |
f76aec76 | 3191 | return; |
2c2e2c38 | 3192 | |
1525a29a | 3193 | domain = find_domain(dev); |
ba395927 KA |
3194 | BUG_ON(!domain); |
3195 | ||
8c11e798 WH |
3196 | iommu = domain_get_iommu(domain); |
3197 | ||
ba395927 | 3198 | iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr)); |
85b98276 DW |
3199 | if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n", |
3200 | (unsigned long long)dev_addr)) | |
ba395927 | 3201 | return; |
ba395927 | 3202 | |
d794dc9b DW |
3203 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
3204 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
ba395927 | 3205 | |
d794dc9b | 3206 | pr_debug("Device %s unmapping: pfn %lx-%lx\n", |
207e3592 | 3207 | dev_name(dev), start_pfn, last_pfn); |
ba395927 | 3208 | |
ea8ea460 | 3209 | freelist = domain_unmap(domain, start_pfn, last_pfn); |
d794dc9b | 3210 | |
5e0d2a6f | 3211 | if (intel_iommu_strict) { |
03d6a246 | 3212 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, |
ea8ea460 | 3213 | last_pfn - start_pfn + 1, !freelist, 0); |
5e0d2a6f | 3214 | /* free iova */ |
3215 | __free_iova(&domain->iovad, iova); | |
ea8ea460 | 3216 | dma_free_pagelist(freelist); |
5e0d2a6f | 3217 | } else { |
ea8ea460 | 3218 | add_unmap(domain, iova, freelist); |
5e0d2a6f | 3219 | /* |
3220 | * queue up the release of the unmap to save the 1/6th of the | |
3221 | * cpu used up by the iotlb flush operation... | |
3222 | */ | |
5e0d2a6f | 3223 | } |
ba395927 KA |
3224 | } |
3225 | ||
d41a4adb JL |
3226 | static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, |
3227 | size_t size, enum dma_data_direction dir, | |
3228 | struct dma_attrs *attrs) | |
3229 | { | |
3230 | intel_unmap(dev, dev_addr); | |
3231 | } | |
3232 | ||
5040a918 | 3233 | static void *intel_alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
3234 | dma_addr_t *dma_handle, gfp_t flags, |
3235 | struct dma_attrs *attrs) | |
ba395927 | 3236 | { |
36746436 | 3237 | struct page *page = NULL; |
ba395927 KA |
3238 | int order; |
3239 | ||
5b6985ce | 3240 | size = PAGE_ALIGN(size); |
ba395927 | 3241 | order = get_order(size); |
e8bb910d | 3242 | |
5040a918 | 3243 | if (!iommu_no_mapping(dev)) |
e8bb910d | 3244 | flags &= ~(GFP_DMA | GFP_DMA32); |
5040a918 DW |
3245 | else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) { |
3246 | if (dev->coherent_dma_mask < DMA_BIT_MASK(32)) | |
e8bb910d AW |
3247 | flags |= GFP_DMA; |
3248 | else | |
3249 | flags |= GFP_DMA32; | |
3250 | } | |
ba395927 | 3251 | |
36746436 AM |
3252 | if (flags & __GFP_WAIT) { |
3253 | unsigned int count = size >> PAGE_SHIFT; | |
3254 | ||
3255 | page = dma_alloc_from_contiguous(dev, count, order); | |
3256 | if (page && iommu_no_mapping(dev) && | |
3257 | page_to_phys(page) + size > dev->coherent_dma_mask) { | |
3258 | dma_release_from_contiguous(dev, page, count); | |
3259 | page = NULL; | |
3260 | } | |
3261 | } | |
3262 | ||
3263 | if (!page) | |
3264 | page = alloc_pages(flags, order); | |
3265 | if (!page) | |
ba395927 | 3266 | return NULL; |
36746436 | 3267 | memset(page_address(page), 0, size); |
ba395927 | 3268 | |
36746436 | 3269 | *dma_handle = __intel_map_single(dev, page_to_phys(page), size, |
bb9e6d65 | 3270 | DMA_BIDIRECTIONAL, |
5040a918 | 3271 | dev->coherent_dma_mask); |
ba395927 | 3272 | if (*dma_handle) |
36746436 AM |
3273 | return page_address(page); |
3274 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) | |
3275 | __free_pages(page, order); | |
3276 | ||
ba395927 KA |
3277 | return NULL; |
3278 | } | |
3279 | ||
5040a918 | 3280 | static void intel_free_coherent(struct device *dev, size_t size, void *vaddr, |
baa676fc | 3281 | dma_addr_t dma_handle, struct dma_attrs *attrs) |
ba395927 KA |
3282 | { |
3283 | int order; | |
36746436 | 3284 | struct page *page = virt_to_page(vaddr); |
ba395927 | 3285 | |
5b6985ce | 3286 | size = PAGE_ALIGN(size); |
ba395927 KA |
3287 | order = get_order(size); |
3288 | ||
d41a4adb | 3289 | intel_unmap(dev, dma_handle); |
36746436 AM |
3290 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
3291 | __free_pages(page, order); | |
ba395927 KA |
3292 | } |
3293 | ||
5040a918 | 3294 | static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist, |
d7ab5c46 FT |
3295 | int nelems, enum dma_data_direction dir, |
3296 | struct dma_attrs *attrs) | |
ba395927 | 3297 | { |
d41a4adb | 3298 | intel_unmap(dev, sglist[0].dma_address); |
ba395927 KA |
3299 | } |
3300 | ||
ba395927 | 3301 | static int intel_nontranslate_map_sg(struct device *hddev, |
c03ab37c | 3302 | struct scatterlist *sglist, int nelems, int dir) |
ba395927 KA |
3303 | { |
3304 | int i; | |
c03ab37c | 3305 | struct scatterlist *sg; |
ba395927 | 3306 | |
c03ab37c | 3307 | for_each_sg(sglist, sg, nelems, i) { |
12d4d40e | 3308 | BUG_ON(!sg_page(sg)); |
4cf2e75d | 3309 | sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset; |
c03ab37c | 3310 | sg->dma_length = sg->length; |
ba395927 KA |
3311 | } |
3312 | return nelems; | |
3313 | } | |
3314 | ||
5040a918 | 3315 | static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems, |
d7ab5c46 | 3316 | enum dma_data_direction dir, struct dma_attrs *attrs) |
ba395927 | 3317 | { |
ba395927 | 3318 | int i; |
ba395927 | 3319 | struct dmar_domain *domain; |
f76aec76 KA |
3320 | size_t size = 0; |
3321 | int prot = 0; | |
f76aec76 KA |
3322 | struct iova *iova = NULL; |
3323 | int ret; | |
c03ab37c | 3324 | struct scatterlist *sg; |
b536d24d | 3325 | unsigned long start_vpfn; |
8c11e798 | 3326 | struct intel_iommu *iommu; |
ba395927 KA |
3327 | |
3328 | BUG_ON(dir == DMA_NONE); | |
5040a918 DW |
3329 | if (iommu_no_mapping(dev)) |
3330 | return intel_nontranslate_map_sg(dev, sglist, nelems, dir); | |
ba395927 | 3331 | |
5040a918 | 3332 | domain = get_valid_domain_for_dev(dev); |
f76aec76 KA |
3333 | if (!domain) |
3334 | return 0; | |
3335 | ||
8c11e798 WH |
3336 | iommu = domain_get_iommu(domain); |
3337 | ||
b536d24d | 3338 | for_each_sg(sglist, sg, nelems, i) |
88cb6a74 | 3339 | size += aligned_nrpages(sg->offset, sg->length); |
f76aec76 | 3340 | |
5040a918 DW |
3341 | iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), |
3342 | *dev->dma_mask); | |
f76aec76 | 3343 | if (!iova) { |
c03ab37c | 3344 | sglist->dma_length = 0; |
f76aec76 KA |
3345 | return 0; |
3346 | } | |
3347 | ||
3348 | /* | |
3349 | * Check if DMAR supports zero-length reads on write only | |
3350 | * mappings.. | |
3351 | */ | |
3352 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 3353 | !cap_zlr(iommu->cap)) |
f76aec76 KA |
3354 | prot |= DMA_PTE_READ; |
3355 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
3356 | prot |= DMA_PTE_WRITE; | |
3357 | ||
b536d24d | 3358 | start_vpfn = mm_to_dma_pfn(iova->pfn_lo); |
e1605495 | 3359 | |
f532959b | 3360 | ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot); |
e1605495 | 3361 | if (unlikely(ret)) { |
e1605495 DW |
3362 | dma_pte_free_pagetable(domain, start_vpfn, |
3363 | start_vpfn + size - 1); | |
e1605495 DW |
3364 | __free_iova(&domain->iovad, iova); |
3365 | return 0; | |
ba395927 KA |
3366 | } |
3367 | ||
1f0ef2aa DW |
3368 | /* it's a non-present to present mapping. Only flush if caching mode */ |
3369 | if (cap_caching_mode(iommu->cap)) | |
ea8ea460 | 3370 | iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1); |
1f0ef2aa | 3371 | else |
8c11e798 | 3372 | iommu_flush_write_buffer(iommu); |
1f0ef2aa | 3373 | |
ba395927 KA |
3374 | return nelems; |
3375 | } | |
3376 | ||
dfb805e8 FT |
3377 | static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr) |
3378 | { | |
3379 | return !dma_addr; | |
3380 | } | |
3381 | ||
160c1d8e | 3382 | struct dma_map_ops intel_dma_ops = { |
baa676fc AP |
3383 | .alloc = intel_alloc_coherent, |
3384 | .free = intel_free_coherent, | |
ba395927 KA |
3385 | .map_sg = intel_map_sg, |
3386 | .unmap_sg = intel_unmap_sg, | |
ffbbef5c FT |
3387 | .map_page = intel_map_page, |
3388 | .unmap_page = intel_unmap_page, | |
dfb805e8 | 3389 | .mapping_error = intel_mapping_error, |
ba395927 KA |
3390 | }; |
3391 | ||
3392 | static inline int iommu_domain_cache_init(void) | |
3393 | { | |
3394 | int ret = 0; | |
3395 | ||
3396 | iommu_domain_cache = kmem_cache_create("iommu_domain", | |
3397 | sizeof(struct dmar_domain), | |
3398 | 0, | |
3399 | SLAB_HWCACHE_ALIGN, | |
3400 | ||
3401 | NULL); | |
3402 | if (!iommu_domain_cache) { | |
3403 | printk(KERN_ERR "Couldn't create iommu_domain cache\n"); | |
3404 | ret = -ENOMEM; | |
3405 | } | |
3406 | ||
3407 | return ret; | |
3408 | } | |
3409 | ||
3410 | static inline int iommu_devinfo_cache_init(void) | |
3411 | { | |
3412 | int ret = 0; | |
3413 | ||
3414 | iommu_devinfo_cache = kmem_cache_create("iommu_devinfo", | |
3415 | sizeof(struct device_domain_info), | |
3416 | 0, | |
3417 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
3418 | NULL); |
3419 | if (!iommu_devinfo_cache) { | |
3420 | printk(KERN_ERR "Couldn't create devinfo cache\n"); | |
3421 | ret = -ENOMEM; | |
3422 | } | |
3423 | ||
3424 | return ret; | |
3425 | } | |
3426 | ||
3427 | static inline int iommu_iova_cache_init(void) | |
3428 | { | |
3429 | int ret = 0; | |
3430 | ||
3431 | iommu_iova_cache = kmem_cache_create("iommu_iova", | |
3432 | sizeof(struct iova), | |
3433 | 0, | |
3434 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
3435 | NULL); |
3436 | if (!iommu_iova_cache) { | |
3437 | printk(KERN_ERR "Couldn't create iova cache\n"); | |
3438 | ret = -ENOMEM; | |
3439 | } | |
3440 | ||
3441 | return ret; | |
3442 | } | |
3443 | ||
3444 | static int __init iommu_init_mempool(void) | |
3445 | { | |
3446 | int ret; | |
3447 | ret = iommu_iova_cache_init(); | |
3448 | if (ret) | |
3449 | return ret; | |
3450 | ||
3451 | ret = iommu_domain_cache_init(); | |
3452 | if (ret) | |
3453 | goto domain_error; | |
3454 | ||
3455 | ret = iommu_devinfo_cache_init(); | |
3456 | if (!ret) | |
3457 | return ret; | |
3458 | ||
3459 | kmem_cache_destroy(iommu_domain_cache); | |
3460 | domain_error: | |
3461 | kmem_cache_destroy(iommu_iova_cache); | |
3462 | ||
3463 | return -ENOMEM; | |
3464 | } | |
3465 | ||
3466 | static void __init iommu_exit_mempool(void) | |
3467 | { | |
3468 | kmem_cache_destroy(iommu_devinfo_cache); | |
3469 | kmem_cache_destroy(iommu_domain_cache); | |
3470 | kmem_cache_destroy(iommu_iova_cache); | |
3471 | ||
3472 | } | |
3473 | ||
556ab45f DW |
3474 | static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev) |
3475 | { | |
3476 | struct dmar_drhd_unit *drhd; | |
3477 | u32 vtbar; | |
3478 | int rc; | |
3479 | ||
3480 | /* We know that this device on this chipset has its own IOMMU. | |
3481 | * If we find it under a different IOMMU, then the BIOS is lying | |
3482 | * to us. Hope that the IOMMU for this device is actually | |
3483 | * disabled, and it needs no translation... | |
3484 | */ | |
3485 | rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar); | |
3486 | if (rc) { | |
3487 | /* "can't" happen */ | |
3488 | dev_info(&pdev->dev, "failed to run vt-d quirk\n"); | |
3489 | return; | |
3490 | } | |
3491 | vtbar &= 0xffff0000; | |
3492 | ||
3493 | /* we know that the this iommu should be at offset 0xa000 from vtbar */ | |
3494 | drhd = dmar_find_matched_drhd_unit(pdev); | |
3495 | if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000, | |
3496 | TAINT_FIRMWARE_WORKAROUND, | |
3497 | "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n")) | |
3498 | pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; | |
3499 | } | |
3500 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu); | |
3501 | ||
ba395927 KA |
3502 | static void __init init_no_remapping_devices(void) |
3503 | { | |
3504 | struct dmar_drhd_unit *drhd; | |
832bd858 | 3505 | struct device *dev; |
b683b230 | 3506 | int i; |
ba395927 KA |
3507 | |
3508 | for_each_drhd_unit(drhd) { | |
3509 | if (!drhd->include_all) { | |
b683b230 JL |
3510 | for_each_active_dev_scope(drhd->devices, |
3511 | drhd->devices_cnt, i, dev) | |
3512 | break; | |
832bd858 | 3513 | /* ignore DMAR unit if no devices exist */ |
ba395927 KA |
3514 | if (i == drhd->devices_cnt) |
3515 | drhd->ignored = 1; | |
3516 | } | |
3517 | } | |
3518 | ||
7c919779 | 3519 | for_each_active_drhd_unit(drhd) { |
7c919779 | 3520 | if (drhd->include_all) |
ba395927 KA |
3521 | continue; |
3522 | ||
b683b230 JL |
3523 | for_each_active_dev_scope(drhd->devices, |
3524 | drhd->devices_cnt, i, dev) | |
832bd858 | 3525 | if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev))) |
ba395927 | 3526 | break; |
ba395927 KA |
3527 | if (i < drhd->devices_cnt) |
3528 | continue; | |
3529 | ||
c0771df8 DW |
3530 | /* This IOMMU has *only* gfx devices. Either bypass it or |
3531 | set the gfx_mapped flag, as appropriate */ | |
3532 | if (dmar_map_gfx) { | |
3533 | intel_iommu_gfx_mapped = 1; | |
3534 | } else { | |
3535 | drhd->ignored = 1; | |
b683b230 JL |
3536 | for_each_active_dev_scope(drhd->devices, |
3537 | drhd->devices_cnt, i, dev) | |
832bd858 | 3538 | dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
ba395927 KA |
3539 | } |
3540 | } | |
3541 | } | |
3542 | ||
f59c7b69 FY |
3543 | #ifdef CONFIG_SUSPEND |
3544 | static int init_iommu_hw(void) | |
3545 | { | |
3546 | struct dmar_drhd_unit *drhd; | |
3547 | struct intel_iommu *iommu = NULL; | |
3548 | ||
3549 | for_each_active_iommu(iommu, drhd) | |
3550 | if (iommu->qi) | |
3551 | dmar_reenable_qi(iommu); | |
3552 | ||
b779260b JC |
3553 | for_each_iommu(iommu, drhd) { |
3554 | if (drhd->ignored) { | |
3555 | /* | |
3556 | * we always have to disable PMRs or DMA may fail on | |
3557 | * this device | |
3558 | */ | |
3559 | if (force_on) | |
3560 | iommu_disable_protect_mem_regions(iommu); | |
3561 | continue; | |
3562 | } | |
3563 | ||
f59c7b69 FY |
3564 | iommu_flush_write_buffer(iommu); |
3565 | ||
3566 | iommu_set_root_entry(iommu); | |
3567 | ||
3568 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3569 | DMA_CCMD_GLOBAL_INVL); |
2a41ccee JL |
3570 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
3571 | iommu_enable_translation(iommu); | |
b94996c9 | 3572 | iommu_disable_protect_mem_regions(iommu); |
f59c7b69 FY |
3573 | } |
3574 | ||
3575 | return 0; | |
3576 | } | |
3577 | ||
3578 | static void iommu_flush_all(void) | |
3579 | { | |
3580 | struct dmar_drhd_unit *drhd; | |
3581 | struct intel_iommu *iommu; | |
3582 | ||
3583 | for_each_active_iommu(iommu, drhd) { | |
3584 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3585 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 3586 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 3587 | DMA_TLB_GLOBAL_FLUSH); |
f59c7b69 FY |
3588 | } |
3589 | } | |
3590 | ||
134fac3f | 3591 | static int iommu_suspend(void) |
f59c7b69 FY |
3592 | { |
3593 | struct dmar_drhd_unit *drhd; | |
3594 | struct intel_iommu *iommu = NULL; | |
3595 | unsigned long flag; | |
3596 | ||
3597 | for_each_active_iommu(iommu, drhd) { | |
3598 | iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS, | |
3599 | GFP_ATOMIC); | |
3600 | if (!iommu->iommu_state) | |
3601 | goto nomem; | |
3602 | } | |
3603 | ||
3604 | iommu_flush_all(); | |
3605 | ||
3606 | for_each_active_iommu(iommu, drhd) { | |
3607 | iommu_disable_translation(iommu); | |
3608 | ||
1f5b3c3f | 3609 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
f59c7b69 FY |
3610 | |
3611 | iommu->iommu_state[SR_DMAR_FECTL_REG] = | |
3612 | readl(iommu->reg + DMAR_FECTL_REG); | |
3613 | iommu->iommu_state[SR_DMAR_FEDATA_REG] = | |
3614 | readl(iommu->reg + DMAR_FEDATA_REG); | |
3615 | iommu->iommu_state[SR_DMAR_FEADDR_REG] = | |
3616 | readl(iommu->reg + DMAR_FEADDR_REG); | |
3617 | iommu->iommu_state[SR_DMAR_FEUADDR_REG] = | |
3618 | readl(iommu->reg + DMAR_FEUADDR_REG); | |
3619 | ||
1f5b3c3f | 3620 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
f59c7b69 FY |
3621 | } |
3622 | return 0; | |
3623 | ||
3624 | nomem: | |
3625 | for_each_active_iommu(iommu, drhd) | |
3626 | kfree(iommu->iommu_state); | |
3627 | ||
3628 | return -ENOMEM; | |
3629 | } | |
3630 | ||
134fac3f | 3631 | static void iommu_resume(void) |
f59c7b69 FY |
3632 | { |
3633 | struct dmar_drhd_unit *drhd; | |
3634 | struct intel_iommu *iommu = NULL; | |
3635 | unsigned long flag; | |
3636 | ||
3637 | if (init_iommu_hw()) { | |
b779260b JC |
3638 | if (force_on) |
3639 | panic("tboot: IOMMU setup failed, DMAR can not resume!\n"); | |
3640 | else | |
3641 | WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); | |
134fac3f | 3642 | return; |
f59c7b69 FY |
3643 | } |
3644 | ||
3645 | for_each_active_iommu(iommu, drhd) { | |
3646 | ||
1f5b3c3f | 3647 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
f59c7b69 FY |
3648 | |
3649 | writel(iommu->iommu_state[SR_DMAR_FECTL_REG], | |
3650 | iommu->reg + DMAR_FECTL_REG); | |
3651 | writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], | |
3652 | iommu->reg + DMAR_FEDATA_REG); | |
3653 | writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], | |
3654 | iommu->reg + DMAR_FEADDR_REG); | |
3655 | writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], | |
3656 | iommu->reg + DMAR_FEUADDR_REG); | |
3657 | ||
1f5b3c3f | 3658 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
f59c7b69 FY |
3659 | } |
3660 | ||
3661 | for_each_active_iommu(iommu, drhd) | |
3662 | kfree(iommu->iommu_state); | |
f59c7b69 FY |
3663 | } |
3664 | ||
134fac3f | 3665 | static struct syscore_ops iommu_syscore_ops = { |
f59c7b69 FY |
3666 | .resume = iommu_resume, |
3667 | .suspend = iommu_suspend, | |
3668 | }; | |
3669 | ||
134fac3f | 3670 | static void __init init_iommu_pm_ops(void) |
f59c7b69 | 3671 | { |
134fac3f | 3672 | register_syscore_ops(&iommu_syscore_ops); |
f59c7b69 FY |
3673 | } |
3674 | ||
3675 | #else | |
99592ba4 | 3676 | static inline void init_iommu_pm_ops(void) {} |
f59c7b69 FY |
3677 | #endif /* CONFIG_PM */ |
3678 | ||
318fe7df | 3679 | |
c2a0b538 | 3680 | int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg) |
318fe7df SS |
3681 | { |
3682 | struct acpi_dmar_reserved_memory *rmrr; | |
3683 | struct dmar_rmrr_unit *rmrru; | |
3684 | ||
3685 | rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL); | |
3686 | if (!rmrru) | |
3687 | return -ENOMEM; | |
3688 | ||
3689 | rmrru->hdr = header; | |
3690 | rmrr = (struct acpi_dmar_reserved_memory *)header; | |
3691 | rmrru->base_address = rmrr->base_address; | |
3692 | rmrru->end_address = rmrr->end_address; | |
2e455289 JL |
3693 | rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1), |
3694 | ((void *)rmrr) + rmrr->header.length, | |
3695 | &rmrru->devices_cnt); | |
3696 | if (rmrru->devices_cnt && rmrru->devices == NULL) { | |
3697 | kfree(rmrru); | |
3698 | return -ENOMEM; | |
3699 | } | |
318fe7df | 3700 | |
2e455289 | 3701 | list_add(&rmrru->list, &dmar_rmrr_units); |
318fe7df | 3702 | |
2e455289 | 3703 | return 0; |
318fe7df SS |
3704 | } |
3705 | ||
c2a0b538 | 3706 | int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr, void *arg) |
318fe7df SS |
3707 | { |
3708 | struct acpi_dmar_atsr *atsr; | |
3709 | struct dmar_atsr_unit *atsru; | |
3710 | ||
3711 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); | |
3712 | atsru = kzalloc(sizeof(*atsru), GFP_KERNEL); | |
3713 | if (!atsru) | |
3714 | return -ENOMEM; | |
3715 | ||
3716 | atsru->hdr = hdr; | |
3717 | atsru->include_all = atsr->flags & 0x1; | |
2e455289 JL |
3718 | if (!atsru->include_all) { |
3719 | atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1), | |
3720 | (void *)atsr + atsr->header.length, | |
3721 | &atsru->devices_cnt); | |
3722 | if (atsru->devices_cnt && atsru->devices == NULL) { | |
3723 | kfree(atsru); | |
3724 | return -ENOMEM; | |
3725 | } | |
3726 | } | |
318fe7df | 3727 | |
0e242612 | 3728 | list_add_rcu(&atsru->list, &dmar_atsr_units); |
318fe7df SS |
3729 | |
3730 | return 0; | |
3731 | } | |
3732 | ||
9bdc531e JL |
3733 | static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru) |
3734 | { | |
3735 | dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt); | |
3736 | kfree(atsru); | |
3737 | } | |
3738 | ||
3739 | static void intel_iommu_free_dmars(void) | |
3740 | { | |
3741 | struct dmar_rmrr_unit *rmrru, *rmrr_n; | |
3742 | struct dmar_atsr_unit *atsru, *atsr_n; | |
3743 | ||
3744 | list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) { | |
3745 | list_del(&rmrru->list); | |
3746 | dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt); | |
3747 | kfree(rmrru); | |
318fe7df SS |
3748 | } |
3749 | ||
9bdc531e JL |
3750 | list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) { |
3751 | list_del(&atsru->list); | |
3752 | intel_iommu_free_atsr(atsru); | |
3753 | } | |
318fe7df SS |
3754 | } |
3755 | ||
3756 | int dmar_find_matched_atsr_unit(struct pci_dev *dev) | |
3757 | { | |
b683b230 | 3758 | int i, ret = 1; |
318fe7df | 3759 | struct pci_bus *bus; |
832bd858 DW |
3760 | struct pci_dev *bridge = NULL; |
3761 | struct device *tmp; | |
318fe7df SS |
3762 | struct acpi_dmar_atsr *atsr; |
3763 | struct dmar_atsr_unit *atsru; | |
3764 | ||
3765 | dev = pci_physfn(dev); | |
318fe7df | 3766 | for (bus = dev->bus; bus; bus = bus->parent) { |
b5f82ddf | 3767 | bridge = bus->self; |
318fe7df | 3768 | if (!bridge || !pci_is_pcie(bridge) || |
62f87c0e | 3769 | pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) |
318fe7df | 3770 | return 0; |
b5f82ddf | 3771 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) |
318fe7df | 3772 | break; |
318fe7df | 3773 | } |
b5f82ddf JL |
3774 | if (!bridge) |
3775 | return 0; | |
318fe7df | 3776 | |
0e242612 | 3777 | rcu_read_lock(); |
b5f82ddf JL |
3778 | list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) { |
3779 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); | |
3780 | if (atsr->segment != pci_domain_nr(dev->bus)) | |
3781 | continue; | |
3782 | ||
b683b230 | 3783 | for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp) |
832bd858 | 3784 | if (tmp == &bridge->dev) |
b683b230 | 3785 | goto out; |
b5f82ddf JL |
3786 | |
3787 | if (atsru->include_all) | |
b683b230 | 3788 | goto out; |
b5f82ddf | 3789 | } |
b683b230 JL |
3790 | ret = 0; |
3791 | out: | |
0e242612 | 3792 | rcu_read_unlock(); |
318fe7df | 3793 | |
b683b230 | 3794 | return ret; |
318fe7df SS |
3795 | } |
3796 | ||
59ce0515 JL |
3797 | int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) |
3798 | { | |
3799 | int ret = 0; | |
3800 | struct dmar_rmrr_unit *rmrru; | |
3801 | struct dmar_atsr_unit *atsru; | |
3802 | struct acpi_dmar_atsr *atsr; | |
3803 | struct acpi_dmar_reserved_memory *rmrr; | |
3804 | ||
3805 | if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING) | |
3806 | return 0; | |
3807 | ||
3808 | list_for_each_entry(rmrru, &dmar_rmrr_units, list) { | |
3809 | rmrr = container_of(rmrru->hdr, | |
3810 | struct acpi_dmar_reserved_memory, header); | |
3811 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { | |
3812 | ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1), | |
3813 | ((void *)rmrr) + rmrr->header.length, | |
3814 | rmrr->segment, rmrru->devices, | |
3815 | rmrru->devices_cnt); | |
27e24950 | 3816 | if(ret < 0) |
59ce0515 JL |
3817 | return ret; |
3818 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { | |
27e24950 JL |
3819 | dmar_remove_dev_scope(info, rmrr->segment, |
3820 | rmrru->devices, rmrru->devices_cnt); | |
59ce0515 JL |
3821 | } |
3822 | } | |
3823 | ||
3824 | list_for_each_entry(atsru, &dmar_atsr_units, list) { | |
3825 | if (atsru->include_all) | |
3826 | continue; | |
3827 | ||
3828 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); | |
3829 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { | |
3830 | ret = dmar_insert_dev_scope(info, (void *)(atsr + 1), | |
3831 | (void *)atsr + atsr->header.length, | |
3832 | atsr->segment, atsru->devices, | |
3833 | atsru->devices_cnt); | |
3834 | if (ret > 0) | |
3835 | break; | |
3836 | else if(ret < 0) | |
3837 | return ret; | |
3838 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { | |
3839 | if (dmar_remove_dev_scope(info, atsr->segment, | |
3840 | atsru->devices, atsru->devices_cnt)) | |
3841 | break; | |
3842 | } | |
3843 | } | |
3844 | ||
3845 | return 0; | |
3846 | } | |
3847 | ||
99dcaded FY |
3848 | /* |
3849 | * Here we only respond to action of unbound device from driver. | |
3850 | * | |
3851 | * Added device is not attached to its DMAR domain here yet. That will happen | |
3852 | * when mapping the device to iova. | |
3853 | */ | |
3854 | static int device_notifier(struct notifier_block *nb, | |
3855 | unsigned long action, void *data) | |
3856 | { | |
3857 | struct device *dev = data; | |
99dcaded FY |
3858 | struct dmar_domain *domain; |
3859 | ||
3d89194a | 3860 | if (iommu_dummy(dev)) |
44cd613c DW |
3861 | return 0; |
3862 | ||
1196c2fb | 3863 | if (action != BUS_NOTIFY_REMOVED_DEVICE) |
7e7dfab7 JL |
3864 | return 0; |
3865 | ||
e7f9fa54 JR |
3866 | /* |
3867 | * If the device is still attached to a device driver we can't | |
3868 | * tear down the domain yet as DMA mappings may still be in use. | |
3869 | * Wait for the BUS_NOTIFY_UNBOUND_DRIVER event to do that. | |
3870 | */ | |
3871 | if (action == BUS_NOTIFY_DEL_DEVICE && dev->driver != NULL) | |
3872 | return 0; | |
3873 | ||
1525a29a | 3874 | domain = find_domain(dev); |
99dcaded FY |
3875 | if (!domain) |
3876 | return 0; | |
3877 | ||
3a5670e8 | 3878 | down_read(&dmar_global_lock); |
bf9c9eda | 3879 | domain_remove_one_dev_info(domain, dev); |
ab8dfe25 | 3880 | if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices)) |
7e7dfab7 | 3881 | domain_exit(domain); |
3a5670e8 | 3882 | up_read(&dmar_global_lock); |
a97590e5 | 3883 | |
99dcaded FY |
3884 | return 0; |
3885 | } | |
3886 | ||
3887 | static struct notifier_block device_nb = { | |
3888 | .notifier_call = device_notifier, | |
3889 | }; | |
3890 | ||
75f05569 JL |
3891 | static int intel_iommu_memory_notifier(struct notifier_block *nb, |
3892 | unsigned long val, void *v) | |
3893 | { | |
3894 | struct memory_notify *mhp = v; | |
3895 | unsigned long long start, end; | |
3896 | unsigned long start_vpfn, last_vpfn; | |
3897 | ||
3898 | switch (val) { | |
3899 | case MEM_GOING_ONLINE: | |
3900 | start = mhp->start_pfn << PAGE_SHIFT; | |
3901 | end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1; | |
3902 | if (iommu_domain_identity_map(si_domain, start, end)) { | |
3903 | pr_warn("dmar: failed to build identity map for [%llx-%llx]\n", | |
3904 | start, end); | |
3905 | return NOTIFY_BAD; | |
3906 | } | |
3907 | break; | |
3908 | ||
3909 | case MEM_OFFLINE: | |
3910 | case MEM_CANCEL_ONLINE: | |
3911 | start_vpfn = mm_to_dma_pfn(mhp->start_pfn); | |
3912 | last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1); | |
3913 | while (start_vpfn <= last_vpfn) { | |
3914 | struct iova *iova; | |
3915 | struct dmar_drhd_unit *drhd; | |
3916 | struct intel_iommu *iommu; | |
ea8ea460 | 3917 | struct page *freelist; |
75f05569 JL |
3918 | |
3919 | iova = find_iova(&si_domain->iovad, start_vpfn); | |
3920 | if (iova == NULL) { | |
3921 | pr_debug("dmar: failed get IOVA for PFN %lx\n", | |
3922 | start_vpfn); | |
3923 | break; | |
3924 | } | |
3925 | ||
3926 | iova = split_and_remove_iova(&si_domain->iovad, iova, | |
3927 | start_vpfn, last_vpfn); | |
3928 | if (iova == NULL) { | |
3929 | pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n", | |
3930 | start_vpfn, last_vpfn); | |
3931 | return NOTIFY_BAD; | |
3932 | } | |
3933 | ||
ea8ea460 DW |
3934 | freelist = domain_unmap(si_domain, iova->pfn_lo, |
3935 | iova->pfn_hi); | |
3936 | ||
75f05569 JL |
3937 | rcu_read_lock(); |
3938 | for_each_active_iommu(iommu, drhd) | |
3939 | iommu_flush_iotlb_psi(iommu, si_domain->id, | |
a156ef99 | 3940 | iova->pfn_lo, iova_size(iova), |
ea8ea460 | 3941 | !freelist, 0); |
75f05569 | 3942 | rcu_read_unlock(); |
ea8ea460 | 3943 | dma_free_pagelist(freelist); |
75f05569 JL |
3944 | |
3945 | start_vpfn = iova->pfn_hi + 1; | |
3946 | free_iova_mem(iova); | |
3947 | } | |
3948 | break; | |
3949 | } | |
3950 | ||
3951 | return NOTIFY_OK; | |
3952 | } | |
3953 | ||
3954 | static struct notifier_block intel_iommu_memory_nb = { | |
3955 | .notifier_call = intel_iommu_memory_notifier, | |
3956 | .priority = 0 | |
3957 | }; | |
3958 | ||
a5459cfe AW |
3959 | |
3960 | static ssize_t intel_iommu_show_version(struct device *dev, | |
3961 | struct device_attribute *attr, | |
3962 | char *buf) | |
3963 | { | |
3964 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
3965 | u32 ver = readl(iommu->reg + DMAR_VER_REG); | |
3966 | return sprintf(buf, "%d:%d\n", | |
3967 | DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver)); | |
3968 | } | |
3969 | static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL); | |
3970 | ||
3971 | static ssize_t intel_iommu_show_address(struct device *dev, | |
3972 | struct device_attribute *attr, | |
3973 | char *buf) | |
3974 | { | |
3975 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
3976 | return sprintf(buf, "%llx\n", iommu->reg_phys); | |
3977 | } | |
3978 | static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL); | |
3979 | ||
3980 | static ssize_t intel_iommu_show_cap(struct device *dev, | |
3981 | struct device_attribute *attr, | |
3982 | char *buf) | |
3983 | { | |
3984 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
3985 | return sprintf(buf, "%llx\n", iommu->cap); | |
3986 | } | |
3987 | static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL); | |
3988 | ||
3989 | static ssize_t intel_iommu_show_ecap(struct device *dev, | |
3990 | struct device_attribute *attr, | |
3991 | char *buf) | |
3992 | { | |
3993 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
3994 | return sprintf(buf, "%llx\n", iommu->ecap); | |
3995 | } | |
3996 | static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL); | |
3997 | ||
3998 | static struct attribute *intel_iommu_attrs[] = { | |
3999 | &dev_attr_version.attr, | |
4000 | &dev_attr_address.attr, | |
4001 | &dev_attr_cap.attr, | |
4002 | &dev_attr_ecap.attr, | |
4003 | NULL, | |
4004 | }; | |
4005 | ||
4006 | static struct attribute_group intel_iommu_group = { | |
4007 | .name = "intel-iommu", | |
4008 | .attrs = intel_iommu_attrs, | |
4009 | }; | |
4010 | ||
4011 | const struct attribute_group *intel_iommu_groups[] = { | |
4012 | &intel_iommu_group, | |
4013 | NULL, | |
4014 | }; | |
4015 | ||
ba395927 KA |
4016 | int __init intel_iommu_init(void) |
4017 | { | |
9bdc531e | 4018 | int ret = -ENODEV; |
3a93c841 | 4019 | struct dmar_drhd_unit *drhd; |
7c919779 | 4020 | struct intel_iommu *iommu; |
ba395927 | 4021 | |
a59b50e9 JC |
4022 | /* VT-d is required for a TXT/tboot launch, so enforce that */ |
4023 | force_on = tboot_force_iommu(); | |
4024 | ||
3a5670e8 JL |
4025 | if (iommu_init_mempool()) { |
4026 | if (force_on) | |
4027 | panic("tboot: Failed to initialize iommu memory\n"); | |
4028 | return -ENOMEM; | |
4029 | } | |
4030 | ||
4031 | down_write(&dmar_global_lock); | |
a59b50e9 JC |
4032 | if (dmar_table_init()) { |
4033 | if (force_on) | |
4034 | panic("tboot: Failed to initialize DMAR table\n"); | |
9bdc531e | 4035 | goto out_free_dmar; |
a59b50e9 | 4036 | } |
ba395927 | 4037 | |
3a93c841 TI |
4038 | /* |
4039 | * Disable translation if already enabled prior to OS handover. | |
4040 | */ | |
7c919779 | 4041 | for_each_active_iommu(iommu, drhd) |
3a93c841 TI |
4042 | if (iommu->gcmd & DMA_GCMD_TE) |
4043 | iommu_disable_translation(iommu); | |
3a93c841 | 4044 | |
c2c7286a | 4045 | if (dmar_dev_scope_init() < 0) { |
a59b50e9 JC |
4046 | if (force_on) |
4047 | panic("tboot: Failed to initialize DMAR device scope\n"); | |
9bdc531e | 4048 | goto out_free_dmar; |
a59b50e9 | 4049 | } |
1886e8a9 | 4050 | |
75f1cdf1 | 4051 | if (no_iommu || dmar_disabled) |
9bdc531e | 4052 | goto out_free_dmar; |
2ae21010 | 4053 | |
318fe7df SS |
4054 | if (list_empty(&dmar_rmrr_units)) |
4055 | printk(KERN_INFO "DMAR: No RMRR found\n"); | |
4056 | ||
4057 | if (list_empty(&dmar_atsr_units)) | |
4058 | printk(KERN_INFO "DMAR: No ATSR found\n"); | |
4059 | ||
51a63e67 JC |
4060 | if (dmar_init_reserved_ranges()) { |
4061 | if (force_on) | |
4062 | panic("tboot: Failed to reserve iommu ranges\n"); | |
3a5670e8 | 4063 | goto out_free_reserved_range; |
51a63e67 | 4064 | } |
ba395927 KA |
4065 | |
4066 | init_no_remapping_devices(); | |
4067 | ||
b779260b | 4068 | ret = init_dmars(); |
ba395927 | 4069 | if (ret) { |
a59b50e9 JC |
4070 | if (force_on) |
4071 | panic("tboot: Failed to initialize DMARs\n"); | |
ba395927 | 4072 | printk(KERN_ERR "IOMMU: dmar init failed\n"); |
9bdc531e | 4073 | goto out_free_reserved_range; |
ba395927 | 4074 | } |
3a5670e8 | 4075 | up_write(&dmar_global_lock); |
ba395927 KA |
4076 | printk(KERN_INFO |
4077 | "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n"); | |
4078 | ||
5e0d2a6f | 4079 | init_timer(&unmap_timer); |
75f1cdf1 FT |
4080 | #ifdef CONFIG_SWIOTLB |
4081 | swiotlb = 0; | |
4082 | #endif | |
19943b0e | 4083 | dma_ops = &intel_dma_ops; |
4ed0d3e6 | 4084 | |
134fac3f | 4085 | init_iommu_pm_ops(); |
a8bcbb0d | 4086 | |
a5459cfe AW |
4087 | for_each_active_iommu(iommu, drhd) |
4088 | iommu->iommu_dev = iommu_device_create(NULL, iommu, | |
4089 | intel_iommu_groups, | |
4090 | iommu->name); | |
4091 | ||
4236d97d | 4092 | bus_set_iommu(&pci_bus_type, &intel_iommu_ops); |
99dcaded | 4093 | bus_register_notifier(&pci_bus_type, &device_nb); |
75f05569 JL |
4094 | if (si_domain && !hw_pass_through) |
4095 | register_memory_notifier(&intel_iommu_memory_nb); | |
99dcaded | 4096 | |
8bc1f85c ED |
4097 | intel_iommu_enabled = 1; |
4098 | ||
ba395927 | 4099 | return 0; |
9bdc531e JL |
4100 | |
4101 | out_free_reserved_range: | |
4102 | put_iova_domain(&reserved_iova_list); | |
9bdc531e JL |
4103 | out_free_dmar: |
4104 | intel_iommu_free_dmars(); | |
3a5670e8 JL |
4105 | up_write(&dmar_global_lock); |
4106 | iommu_exit_mempool(); | |
9bdc531e | 4107 | return ret; |
ba395927 | 4108 | } |
e820482c | 4109 | |
579305f7 AW |
4110 | static int iommu_detach_dev_cb(struct pci_dev *pdev, u16 alias, void *opaque) |
4111 | { | |
4112 | struct intel_iommu *iommu = opaque; | |
4113 | ||
4114 | iommu_detach_dev(iommu, PCI_BUS_NUM(alias), alias & 0xff); | |
4115 | return 0; | |
4116 | } | |
4117 | ||
4118 | /* | |
4119 | * NB - intel-iommu lacks any sort of reference counting for the users of | |
4120 | * dependent devices. If multiple endpoints have intersecting dependent | |
4121 | * devices, unbinding the driver from any one of them will possibly leave | |
4122 | * the others unable to operate. | |
4123 | */ | |
3199aa6b | 4124 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
0bcb3e28 | 4125 | struct device *dev) |
3199aa6b | 4126 | { |
0bcb3e28 | 4127 | if (!iommu || !dev || !dev_is_pci(dev)) |
3199aa6b HW |
4128 | return; |
4129 | ||
579305f7 | 4130 | pci_for_each_dma_alias(to_pci_dev(dev), &iommu_detach_dev_cb, iommu); |
3199aa6b HW |
4131 | } |
4132 | ||
2c2e2c38 | 4133 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
bf9c9eda | 4134 | struct device *dev) |
c7151a8d | 4135 | { |
bca2b916 | 4136 | struct device_domain_info *info, *tmp; |
c7151a8d WH |
4137 | struct intel_iommu *iommu; |
4138 | unsigned long flags; | |
4139 | int found = 0; | |
156baca8 | 4140 | u8 bus, devfn; |
c7151a8d | 4141 | |
bf9c9eda | 4142 | iommu = device_to_iommu(dev, &bus, &devfn); |
c7151a8d WH |
4143 | if (!iommu) |
4144 | return; | |
4145 | ||
4146 | spin_lock_irqsave(&device_domain_lock, flags); | |
bca2b916 | 4147 | list_for_each_entry_safe(info, tmp, &domain->devices, link) { |
bf9c9eda DW |
4148 | if (info->iommu == iommu && info->bus == bus && |
4149 | info->devfn == devfn) { | |
109b9b04 | 4150 | unlink_domain_info(info); |
c7151a8d WH |
4151 | spin_unlock_irqrestore(&device_domain_lock, flags); |
4152 | ||
93a23a72 | 4153 | iommu_disable_dev_iotlb(info); |
c7151a8d | 4154 | iommu_detach_dev(iommu, info->bus, info->devfn); |
bf9c9eda | 4155 | iommu_detach_dependent_devices(iommu, dev); |
c7151a8d WH |
4156 | free_devinfo_mem(info); |
4157 | ||
4158 | spin_lock_irqsave(&device_domain_lock, flags); | |
4159 | ||
4160 | if (found) | |
4161 | break; | |
4162 | else | |
4163 | continue; | |
4164 | } | |
4165 | ||
4166 | /* if there is no other devices under the same iommu | |
4167 | * owned by this domain, clear this iommu in iommu_bmp | |
4168 | * update iommu count and coherency | |
4169 | */ | |
8bbc4410 | 4170 | if (info->iommu == iommu) |
c7151a8d WH |
4171 | found = 1; |
4172 | } | |
4173 | ||
3e7abe25 RD |
4174 | spin_unlock_irqrestore(&device_domain_lock, flags); |
4175 | ||
c7151a8d | 4176 | if (found == 0) { |
fb170fb4 JL |
4177 | domain_detach_iommu(domain, iommu); |
4178 | if (!domain_type_is_vm_or_si(domain)) | |
4179 | iommu_detach_domain(domain, iommu); | |
c7151a8d | 4180 | } |
c7151a8d WH |
4181 | } |
4182 | ||
2c2e2c38 | 4183 | static int md_domain_init(struct dmar_domain *domain, int guest_width) |
5e98c4b1 WH |
4184 | { |
4185 | int adjust_width; | |
4186 | ||
4187 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); | |
5e98c4b1 WH |
4188 | domain_reserve_special_ranges(domain); |
4189 | ||
4190 | /* calculate AGAW */ | |
4191 | domain->gaw = guest_width; | |
4192 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
4193 | domain->agaw = width_to_agaw(adjust_width); | |
4194 | ||
5e98c4b1 | 4195 | domain->iommu_coherency = 0; |
c5b15255 | 4196 | domain->iommu_snooping = 0; |
6dd9a7c7 | 4197 | domain->iommu_superpage = 0; |
fe40f1e0 | 4198 | domain->max_addr = 0; |
5e98c4b1 WH |
4199 | |
4200 | /* always allocate the top pgd */ | |
4c923d47 | 4201 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
5e98c4b1 WH |
4202 | if (!domain->pgd) |
4203 | return -ENOMEM; | |
4204 | domain_flush_cache(domain, domain->pgd, PAGE_SIZE); | |
4205 | return 0; | |
4206 | } | |
4207 | ||
5d450806 | 4208 | static int intel_iommu_domain_init(struct iommu_domain *domain) |
38717946 | 4209 | { |
5d450806 | 4210 | struct dmar_domain *dmar_domain; |
38717946 | 4211 | |
ab8dfe25 | 4212 | dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE); |
5d450806 | 4213 | if (!dmar_domain) { |
38717946 | 4214 | printk(KERN_ERR |
5d450806 JR |
4215 | "intel_iommu_domain_init: dmar_domain == NULL\n"); |
4216 | return -ENOMEM; | |
38717946 | 4217 | } |
2c2e2c38 | 4218 | if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
38717946 | 4219 | printk(KERN_ERR |
5d450806 | 4220 | "intel_iommu_domain_init() failed\n"); |
92d03cc8 | 4221 | domain_exit(dmar_domain); |
5d450806 | 4222 | return -ENOMEM; |
38717946 | 4223 | } |
8140a95d | 4224 | domain_update_iommu_cap(dmar_domain); |
5d450806 | 4225 | domain->priv = dmar_domain; |
faa3d6f5 | 4226 | |
8a0e715b JR |
4227 | domain->geometry.aperture_start = 0; |
4228 | domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw); | |
4229 | domain->geometry.force_aperture = true; | |
4230 | ||
5d450806 | 4231 | return 0; |
38717946 | 4232 | } |
38717946 | 4233 | |
5d450806 | 4234 | static void intel_iommu_domain_destroy(struct iommu_domain *domain) |
38717946 | 4235 | { |
5d450806 JR |
4236 | struct dmar_domain *dmar_domain = domain->priv; |
4237 | ||
4238 | domain->priv = NULL; | |
92d03cc8 | 4239 | domain_exit(dmar_domain); |
38717946 | 4240 | } |
38717946 | 4241 | |
4c5478c9 JR |
4242 | static int intel_iommu_attach_device(struct iommu_domain *domain, |
4243 | struct device *dev) | |
38717946 | 4244 | { |
4c5478c9 | 4245 | struct dmar_domain *dmar_domain = domain->priv; |
fe40f1e0 WH |
4246 | struct intel_iommu *iommu; |
4247 | int addr_width; | |
156baca8 | 4248 | u8 bus, devfn; |
faa3d6f5 | 4249 | |
c875d2c1 AW |
4250 | if (device_is_rmrr_locked(dev)) { |
4251 | dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement. Contact your platform vendor.\n"); | |
4252 | return -EPERM; | |
4253 | } | |
4254 | ||
7207d8f9 DW |
4255 | /* normally dev is not mapped */ |
4256 | if (unlikely(domain_context_mapped(dev))) { | |
faa3d6f5 WH |
4257 | struct dmar_domain *old_domain; |
4258 | ||
1525a29a | 4259 | old_domain = find_domain(dev); |
faa3d6f5 | 4260 | if (old_domain) { |
ab8dfe25 | 4261 | if (domain_type_is_vm_or_si(dmar_domain)) |
bf9c9eda | 4262 | domain_remove_one_dev_info(old_domain, dev); |
faa3d6f5 WH |
4263 | else |
4264 | domain_remove_dev_info(old_domain); | |
4265 | } | |
4266 | } | |
4267 | ||
156baca8 | 4268 | iommu = device_to_iommu(dev, &bus, &devfn); |
fe40f1e0 WH |
4269 | if (!iommu) |
4270 | return -ENODEV; | |
4271 | ||
4272 | /* check if this iommu agaw is sufficient for max mapped address */ | |
4273 | addr_width = agaw_to_width(iommu->agaw); | |
a99c47a2 TL |
4274 | if (addr_width > cap_mgaw(iommu->cap)) |
4275 | addr_width = cap_mgaw(iommu->cap); | |
4276 | ||
4277 | if (dmar_domain->max_addr > (1LL << addr_width)) { | |
4278 | printk(KERN_ERR "%s: iommu width (%d) is not " | |
fe40f1e0 | 4279 | "sufficient for the mapped address (%llx)\n", |
a99c47a2 | 4280 | __func__, addr_width, dmar_domain->max_addr); |
fe40f1e0 WH |
4281 | return -EFAULT; |
4282 | } | |
a99c47a2 TL |
4283 | dmar_domain->gaw = addr_width; |
4284 | ||
4285 | /* | |
4286 | * Knock out extra levels of page tables if necessary | |
4287 | */ | |
4288 | while (iommu->agaw < dmar_domain->agaw) { | |
4289 | struct dma_pte *pte; | |
4290 | ||
4291 | pte = dmar_domain->pgd; | |
4292 | if (dma_pte_present(pte)) { | |
25cbff16 SY |
4293 | dmar_domain->pgd = (struct dma_pte *) |
4294 | phys_to_virt(dma_pte_addr(pte)); | |
7a661013 | 4295 | free_pgtable_page(pte); |
a99c47a2 TL |
4296 | } |
4297 | dmar_domain->agaw--; | |
4298 | } | |
fe40f1e0 | 4299 | |
5913c9bf | 4300 | return domain_add_dev_info(dmar_domain, dev, CONTEXT_TT_MULTI_LEVEL); |
38717946 | 4301 | } |
38717946 | 4302 | |
4c5478c9 JR |
4303 | static void intel_iommu_detach_device(struct iommu_domain *domain, |
4304 | struct device *dev) | |
38717946 | 4305 | { |
4c5478c9 | 4306 | struct dmar_domain *dmar_domain = domain->priv; |
4c5478c9 | 4307 | |
bf9c9eda | 4308 | domain_remove_one_dev_info(dmar_domain, dev); |
faa3d6f5 | 4309 | } |
c7151a8d | 4310 | |
b146a1c9 JR |
4311 | static int intel_iommu_map(struct iommu_domain *domain, |
4312 | unsigned long iova, phys_addr_t hpa, | |
5009065d | 4313 | size_t size, int iommu_prot) |
faa3d6f5 | 4314 | { |
dde57a21 | 4315 | struct dmar_domain *dmar_domain = domain->priv; |
fe40f1e0 | 4316 | u64 max_addr; |
dde57a21 | 4317 | int prot = 0; |
faa3d6f5 | 4318 | int ret; |
fe40f1e0 | 4319 | |
dde57a21 JR |
4320 | if (iommu_prot & IOMMU_READ) |
4321 | prot |= DMA_PTE_READ; | |
4322 | if (iommu_prot & IOMMU_WRITE) | |
4323 | prot |= DMA_PTE_WRITE; | |
9cf06697 SY |
4324 | if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) |
4325 | prot |= DMA_PTE_SNP; | |
dde57a21 | 4326 | |
163cc52c | 4327 | max_addr = iova + size; |
dde57a21 | 4328 | if (dmar_domain->max_addr < max_addr) { |
fe40f1e0 WH |
4329 | u64 end; |
4330 | ||
4331 | /* check if minimum agaw is sufficient for mapped address */ | |
8954da1f | 4332 | end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1; |
fe40f1e0 | 4333 | if (end < max_addr) { |
8954da1f | 4334 | printk(KERN_ERR "%s: iommu width (%d) is not " |
fe40f1e0 | 4335 | "sufficient for the mapped address (%llx)\n", |
8954da1f | 4336 | __func__, dmar_domain->gaw, max_addr); |
fe40f1e0 WH |
4337 | return -EFAULT; |
4338 | } | |
dde57a21 | 4339 | dmar_domain->max_addr = max_addr; |
fe40f1e0 | 4340 | } |
ad051221 DW |
4341 | /* Round up size to next multiple of PAGE_SIZE, if it and |
4342 | the low bits of hpa would take us onto the next page */ | |
88cb6a74 | 4343 | size = aligned_nrpages(hpa, size); |
ad051221 DW |
4344 | ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT, |
4345 | hpa >> VTD_PAGE_SHIFT, size, prot); | |
faa3d6f5 | 4346 | return ret; |
38717946 | 4347 | } |
38717946 | 4348 | |
5009065d | 4349 | static size_t intel_iommu_unmap(struct iommu_domain *domain, |
ea8ea460 | 4350 | unsigned long iova, size_t size) |
38717946 | 4351 | { |
dde57a21 | 4352 | struct dmar_domain *dmar_domain = domain->priv; |
ea8ea460 DW |
4353 | struct page *freelist = NULL; |
4354 | struct intel_iommu *iommu; | |
4355 | unsigned long start_pfn, last_pfn; | |
4356 | unsigned int npages; | |
4357 | int iommu_id, num, ndomains, level = 0; | |
5cf0a76f DW |
4358 | |
4359 | /* Cope with horrid API which requires us to unmap more than the | |
4360 | size argument if it happens to be a large-page mapping. */ | |
4361 | if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level)) | |
4362 | BUG(); | |
4363 | ||
4364 | if (size < VTD_PAGE_SIZE << level_to_offset_bits(level)) | |
4365 | size = VTD_PAGE_SIZE << level_to_offset_bits(level); | |
4b99d352 | 4366 | |
ea8ea460 DW |
4367 | start_pfn = iova >> VTD_PAGE_SHIFT; |
4368 | last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT; | |
4369 | ||
4370 | freelist = domain_unmap(dmar_domain, start_pfn, last_pfn); | |
4371 | ||
4372 | npages = last_pfn - start_pfn + 1; | |
4373 | ||
4374 | for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) { | |
4375 | iommu = g_iommus[iommu_id]; | |
4376 | ||
4377 | /* | |
4378 | * find bit position of dmar_domain | |
4379 | */ | |
4380 | ndomains = cap_ndoms(iommu->cap); | |
4381 | for_each_set_bit(num, iommu->domain_ids, ndomains) { | |
4382 | if (iommu->domains[num] == dmar_domain) | |
4383 | iommu_flush_iotlb_psi(iommu, num, start_pfn, | |
4384 | npages, !freelist, 0); | |
4385 | } | |
4386 | ||
4387 | } | |
4388 | ||
4389 | dma_free_pagelist(freelist); | |
fe40f1e0 | 4390 | |
163cc52c DW |
4391 | if (dmar_domain->max_addr == iova + size) |
4392 | dmar_domain->max_addr = iova; | |
b146a1c9 | 4393 | |
5cf0a76f | 4394 | return size; |
38717946 | 4395 | } |
38717946 | 4396 | |
d14d6577 | 4397 | static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, |
bb5547ac | 4398 | dma_addr_t iova) |
38717946 | 4399 | { |
d14d6577 | 4400 | struct dmar_domain *dmar_domain = domain->priv; |
38717946 | 4401 | struct dma_pte *pte; |
5cf0a76f | 4402 | int level = 0; |
faa3d6f5 | 4403 | u64 phys = 0; |
38717946 | 4404 | |
5cf0a76f | 4405 | pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level); |
38717946 | 4406 | if (pte) |
faa3d6f5 | 4407 | phys = dma_pte_addr(pte); |
38717946 | 4408 | |
faa3d6f5 | 4409 | return phys; |
38717946 | 4410 | } |
a8bcbb0d | 4411 | |
5d587b8d | 4412 | static bool intel_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 4413 | { |
dbb9fd86 | 4414 | if (cap == IOMMU_CAP_CACHE_COHERENCY) |
5d587b8d | 4415 | return domain_update_iommu_snooping(NULL) == 1; |
323f99cb | 4416 | if (cap == IOMMU_CAP_INTR_REMAP) |
5d587b8d | 4417 | return irq_remapping_enabled == 1; |
dbb9fd86 | 4418 | |
5d587b8d | 4419 | return false; |
dbb9fd86 SY |
4420 | } |
4421 | ||
abdfdde2 AW |
4422 | static int intel_iommu_add_device(struct device *dev) |
4423 | { | |
a5459cfe | 4424 | struct intel_iommu *iommu; |
abdfdde2 | 4425 | struct iommu_group *group; |
156baca8 | 4426 | u8 bus, devfn; |
70ae6f0d | 4427 | |
a5459cfe AW |
4428 | iommu = device_to_iommu(dev, &bus, &devfn); |
4429 | if (!iommu) | |
70ae6f0d AW |
4430 | return -ENODEV; |
4431 | ||
a5459cfe | 4432 | iommu_device_link(iommu->iommu_dev, dev); |
a4ff1fc2 | 4433 | |
e17f9ff4 | 4434 | group = iommu_group_get_for_dev(dev); |
783f157b | 4435 | |
e17f9ff4 AW |
4436 | if (IS_ERR(group)) |
4437 | return PTR_ERR(group); | |
bcb71abe | 4438 | |
abdfdde2 | 4439 | iommu_group_put(group); |
e17f9ff4 | 4440 | return 0; |
abdfdde2 | 4441 | } |
70ae6f0d | 4442 | |
abdfdde2 AW |
4443 | static void intel_iommu_remove_device(struct device *dev) |
4444 | { | |
a5459cfe AW |
4445 | struct intel_iommu *iommu; |
4446 | u8 bus, devfn; | |
4447 | ||
4448 | iommu = device_to_iommu(dev, &bus, &devfn); | |
4449 | if (!iommu) | |
4450 | return; | |
4451 | ||
abdfdde2 | 4452 | iommu_group_remove_device(dev); |
a5459cfe AW |
4453 | |
4454 | iommu_device_unlink(iommu->iommu_dev, dev); | |
70ae6f0d AW |
4455 | } |
4456 | ||
b22f6434 | 4457 | static const struct iommu_ops intel_iommu_ops = { |
5d587b8d | 4458 | .capable = intel_iommu_capable, |
a8bcbb0d JR |
4459 | .domain_init = intel_iommu_domain_init, |
4460 | .domain_destroy = intel_iommu_domain_destroy, | |
4461 | .attach_dev = intel_iommu_attach_device, | |
4462 | .detach_dev = intel_iommu_detach_device, | |
b146a1c9 JR |
4463 | .map = intel_iommu_map, |
4464 | .unmap = intel_iommu_unmap, | |
a8bcbb0d | 4465 | .iova_to_phys = intel_iommu_iova_to_phys, |
abdfdde2 AW |
4466 | .add_device = intel_iommu_add_device, |
4467 | .remove_device = intel_iommu_remove_device, | |
6d1c56a9 | 4468 | .pgsize_bitmap = INTEL_IOMMU_PGSIZES, |
a8bcbb0d | 4469 | }; |
9af88143 | 4470 | |
9452618e DV |
4471 | static void quirk_iommu_g4x_gfx(struct pci_dev *dev) |
4472 | { | |
4473 | /* G4x/GM45 integrated gfx dmar support is totally busted. */ | |
4474 | printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n"); | |
4475 | dmar_map_gfx = 0; | |
4476 | } | |
4477 | ||
4478 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx); | |
4479 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx); | |
4480 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx); | |
4481 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx); | |
4482 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx); | |
4483 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx); | |
4484 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx); | |
4485 | ||
d34d6517 | 4486 | static void quirk_iommu_rwbf(struct pci_dev *dev) |
9af88143 DW |
4487 | { |
4488 | /* | |
4489 | * Mobile 4 Series Chipset neglects to set RWBF capability, | |
210561ff | 4490 | * but needs it. Same seems to hold for the desktop versions. |
9af88143 DW |
4491 | */ |
4492 | printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); | |
4493 | rwbf_quirk = 1; | |
4494 | } | |
4495 | ||
4496 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); | |
210561ff DV |
4497 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf); |
4498 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf); | |
4499 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf); | |
4500 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf); | |
4501 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf); | |
4502 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf); | |
e0fc7e0b | 4503 | |
eecfd57f AJ |
4504 | #define GGC 0x52 |
4505 | #define GGC_MEMORY_SIZE_MASK (0xf << 8) | |
4506 | #define GGC_MEMORY_SIZE_NONE (0x0 << 8) | |
4507 | #define GGC_MEMORY_SIZE_1M (0x1 << 8) | |
4508 | #define GGC_MEMORY_SIZE_2M (0x3 << 8) | |
4509 | #define GGC_MEMORY_VT_ENABLED (0x8 << 8) | |
4510 | #define GGC_MEMORY_SIZE_2M_VT (0x9 << 8) | |
4511 | #define GGC_MEMORY_SIZE_3M_VT (0xa << 8) | |
4512 | #define GGC_MEMORY_SIZE_4M_VT (0xb << 8) | |
4513 | ||
d34d6517 | 4514 | static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev) |
9eecabcb DW |
4515 | { |
4516 | unsigned short ggc; | |
4517 | ||
eecfd57f | 4518 | if (pci_read_config_word(dev, GGC, &ggc)) |
9eecabcb DW |
4519 | return; |
4520 | ||
eecfd57f | 4521 | if (!(ggc & GGC_MEMORY_VT_ENABLED)) { |
9eecabcb DW |
4522 | printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); |
4523 | dmar_map_gfx = 0; | |
6fbcfb3e DW |
4524 | } else if (dmar_map_gfx) { |
4525 | /* we have to ensure the gfx device is idle before we flush */ | |
4526 | printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n"); | |
4527 | intel_iommu_strict = 1; | |
4528 | } | |
9eecabcb DW |
4529 | } |
4530 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt); | |
4531 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt); | |
4532 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt); | |
4533 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt); | |
4534 | ||
e0fc7e0b DW |
4535 | /* On Tylersburg chipsets, some BIOSes have been known to enable the |
4536 | ISOCH DMAR unit for the Azalia sound device, but not give it any | |
4537 | TLB entries, which causes it to deadlock. Check for that. We do | |
4538 | this in a function called from init_dmars(), instead of in a PCI | |
4539 | quirk, because we don't want to print the obnoxious "BIOS broken" | |
4540 | message if VT-d is actually disabled. | |
4541 | */ | |
4542 | static void __init check_tylersburg_isoch(void) | |
4543 | { | |
4544 | struct pci_dev *pdev; | |
4545 | uint32_t vtisochctrl; | |
4546 | ||
4547 | /* If there's no Azalia in the system anyway, forget it. */ | |
4548 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL); | |
4549 | if (!pdev) | |
4550 | return; | |
4551 | pci_dev_put(pdev); | |
4552 | ||
4553 | /* System Management Registers. Might be hidden, in which case | |
4554 | we can't do the sanity check. But that's OK, because the | |
4555 | known-broken BIOSes _don't_ actually hide it, so far. */ | |
4556 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL); | |
4557 | if (!pdev) | |
4558 | return; | |
4559 | ||
4560 | if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) { | |
4561 | pci_dev_put(pdev); | |
4562 | return; | |
4563 | } | |
4564 | ||
4565 | pci_dev_put(pdev); | |
4566 | ||
4567 | /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */ | |
4568 | if (vtisochctrl & 1) | |
4569 | return; | |
4570 | ||
4571 | /* Drop all bits other than the number of TLB entries */ | |
4572 | vtisochctrl &= 0x1c; | |
4573 | ||
4574 | /* If we have the recommended number of TLB entries (16), fine. */ | |
4575 | if (vtisochctrl == 0x10) | |
4576 | return; | |
4577 | ||
4578 | /* Zero TLB entries? You get to ride the short bus to school. */ | |
4579 | if (!vtisochctrl) { | |
4580 | WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n" | |
4581 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
4582 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
4583 | dmi_get_system_info(DMI_BIOS_VERSION), | |
4584 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
4585 | iommu_identity_mapping |= IDENTMAP_AZALIA; | |
4586 | return; | |
4587 | } | |
4588 | ||
4589 | printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n", | |
4590 | vtisochctrl); | |
4591 | } |