]>
Commit | Line | Data |
---|---|---|
9ad1acb4 BG |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // | |
3 | // Author: Steve Chen <schen@mvista.com> | |
4 | // Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com> | |
5 | // Author: Bartosz Golaszewski <bgolaszewski@baylibre.com> | |
6 | // Copyright (C) 2019, Texas Instruments | |
7 | // | |
8 | // TI Common Platform Interrupt Controller (cp_intc) driver | |
0521444d | 9 | |
07caba96 | 10 | #include <linux/export.h> |
0521444d | 11 | #include <linux/init.h> |
0521444d | 12 | #include <linux/irq.h> |
9a7f2fc8 | 13 | #include <linux/irqchip.h> |
6567954b | 14 | #include <linux/irqchip/irq-davinci-cp-intc.h> |
07caba96 | 15 | #include <linux/irqdomain.h> |
0521444d | 16 | #include <linux/io.h> |
961e657f HS |
17 | #include <linux/of.h> |
18 | #include <linux/of_address.h> | |
19 | #include <linux/of_irq.h> | |
0521444d | 20 | |
d0064594 | 21 | #include <asm/exception.h> |
ed4d189b | 22 | |
b35b55e7 | 23 | #define DAVINCI_CP_INTC_CTRL 0x04 |
3b5d1c50 | 24 | #define DAVINCI_CP_INTC_HOST_CTRL 0x0c |
b35b55e7 BG |
25 | #define DAVINCI_CP_INTC_GLOBAL_ENABLE 0x10 |
26 | #define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR 0x24 | |
27 | #define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET 0x28 | |
3b5d1c50 | 28 | #define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR 0x2c |
b35b55e7 BG |
29 | #define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET 0x34 |
30 | #define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR 0x38 | |
31 | #define DAVINCI_CP_INTC_PRIO_IDX 0x80 | |
32 | #define DAVINCI_CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2)) | |
33 | #define DAVINCI_CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2)) | |
34 | #define DAVINCI_CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2)) | |
3b5d1c50 BG |
35 | #define DAVINCI_CP_INTC_SYS_POLARITY(n) (0x0d00 + (n << 2)) |
36 | #define DAVINCI_CP_INTC_SYS_TYPE(n) (0x0d80 + (n << 2)) | |
b35b55e7 | 37 | #define DAVINCI_CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2)) |
d0064594 BG |
38 | #define DAVINCI_CP_INTC_PRI_INDX_MASK GENMASK(9, 0) |
39 | #define DAVINCI_CP_INTC_GPIR_NONE BIT(31) | |
40 | ||
b35b55e7 BG |
41 | static void __iomem *davinci_cp_intc_base; |
42 | static struct irq_domain *davinci_cp_intc_irq_domain; | |
fb746842 | 43 | |
b35b55e7 | 44 | static inline unsigned int davinci_cp_intc_read(unsigned int offset) |
0521444d | 45 | { |
d43da8d7 | 46 | return readl_relaxed(davinci_cp_intc_base + offset); |
0521444d SS |
47 | } |
48 | ||
b35b55e7 BG |
49 | static inline void davinci_cp_intc_write(unsigned long value, |
50 | unsigned int offset) | |
0521444d | 51 | { |
d43da8d7 | 52 | writel_relaxed(value, davinci_cp_intc_base + offset); |
0521444d SS |
53 | } |
54 | ||
b35b55e7 | 55 | static void davinci_cp_intc_ack_irq(struct irq_data *d) |
0521444d | 56 | { |
b35b55e7 | 57 | davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_STAT_IDX_CLR); |
0521444d SS |
58 | } |
59 | ||
b35b55e7 | 60 | static void davinci_cp_intc_mask_irq(struct irq_data *d) |
0521444d SS |
61 | { |
62 | /* XXX don't know why we need to disable nIRQ here... */ | |
b35b55e7 BG |
63 | davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR); |
64 | davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR); | |
65 | davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET); | |
0521444d SS |
66 | } |
67 | ||
b35b55e7 | 68 | static void davinci_cp_intc_unmask_irq(struct irq_data *d) |
0521444d | 69 | { |
b35b55e7 | 70 | davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET); |
0521444d SS |
71 | } |
72 | ||
b35b55e7 BG |
73 | static int davinci_cp_intc_set_irq_type(struct irq_data *d, |
74 | unsigned int flow_type) | |
0521444d | 75 | { |
9762d876 BG |
76 | unsigned int reg, mask, polarity, type; |
77 | ||
78 | reg = BIT_WORD(d->hwirq); | |
79 | mask = BIT_MASK(d->hwirq); | |
80 | polarity = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_POLARITY(reg)); | |
81 | type = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_TYPE(reg)); | |
0521444d SS |
82 | |
83 | switch (flow_type) { | |
84 | case IRQ_TYPE_EDGE_RISING: | |
85 | polarity |= mask; | |
86 | type |= mask; | |
87 | break; | |
88 | case IRQ_TYPE_EDGE_FALLING: | |
89 | polarity &= ~mask; | |
90 | type |= mask; | |
91 | break; | |
92 | case IRQ_TYPE_LEVEL_HIGH: | |
93 | polarity |= mask; | |
94 | type &= ~mask; | |
95 | break; | |
96 | case IRQ_TYPE_LEVEL_LOW: | |
97 | polarity &= ~mask; | |
98 | type &= ~mask; | |
99 | break; | |
100 | default: | |
101 | return -EINVAL; | |
102 | } | |
103 | ||
b35b55e7 BG |
104 | davinci_cp_intc_write(polarity, DAVINCI_CP_INTC_SYS_POLARITY(reg)); |
105 | davinci_cp_intc_write(type, DAVINCI_CP_INTC_SYS_TYPE(reg)); | |
0521444d SS |
106 | |
107 | return 0; | |
108 | } | |
109 | ||
b35b55e7 | 110 | static struct irq_chip davinci_cp_intc_irq_chip = { |
0521444d | 111 | .name = "cp_intc", |
b35b55e7 BG |
112 | .irq_ack = davinci_cp_intc_ack_irq, |
113 | .irq_mask = davinci_cp_intc_mask_irq, | |
114 | .irq_unmask = davinci_cp_intc_unmask_irq, | |
115 | .irq_set_type = davinci_cp_intc_set_irq_type, | |
3f86e570 | 116 | .flags = IRQCHIP_SKIP_SET_WAKE, |
0521444d SS |
117 | }; |
118 | ||
d0064594 | 119 | static asmlinkage void __exception_irq_entry |
b35b55e7 | 120 | davinci_cp_intc_handle_irq(struct pt_regs *regs) |
d0064594 BG |
121 | { |
122 | int gpir, irqnr, none; | |
123 | ||
124 | /* | |
125 | * The interrupt number is in first ten bits. The NONE field set to 1 | |
126 | * indicates a spurious irq. | |
127 | */ | |
128 | ||
b35b55e7 | 129 | gpir = davinci_cp_intc_read(DAVINCI_CP_INTC_PRIO_IDX); |
d0064594 BG |
130 | irqnr = gpir & DAVINCI_CP_INTC_PRI_INDX_MASK; |
131 | none = gpir & DAVINCI_CP_INTC_GPIR_NONE; | |
132 | ||
133 | if (unlikely(none)) { | |
134 | pr_err_once("%s: spurious irq!\n", __func__); | |
135 | return; | |
136 | } | |
137 | ||
b35b55e7 | 138 | handle_domain_irq(davinci_cp_intc_irq_domain, irqnr, regs); |
d0064594 BG |
139 | } |
140 | ||
b35b55e7 | 141 | static int davinci_cp_intc_host_map(struct irq_domain *h, unsigned int virq, |
07caba96 HS |
142 | irq_hw_number_t hw) |
143 | { | |
144 | pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw); | |
145 | ||
b35b55e7 | 146 | irq_set_chip(virq, &davinci_cp_intc_irq_chip); |
e8d36d5d | 147 | irq_set_probe(virq); |
07caba96 | 148 | irq_set_handler(virq, handle_edge_irq); |
9762d876 | 149 | |
07caba96 HS |
150 | return 0; |
151 | } | |
152 | ||
b35b55e7 BG |
153 | static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = { |
154 | .map = davinci_cp_intc_host_map, | |
07caba96 HS |
155 | .xlate = irq_domain_xlate_onetwocell, |
156 | }; | |
157 | ||
6567954b BG |
158 | static int __init |
159 | davinci_cp_intc_do_init(const struct davinci_cp_intc_config *config, | |
160 | struct device_node *node) | |
0521444d | 161 | { |
6567954b BG |
162 | unsigned int num_regs = BITS_TO_LONGS(config->num_irqs); |
163 | int offset, irq_base; | |
9cf58a45 BG |
164 | void __iomem *req; |
165 | ||
166 | req = request_mem_region(config->reg.start, | |
167 | resource_size(&config->reg), | |
168 | "davinci-cp-intc"); | |
169 | if (!req) { | |
170 | pr_err("%s: register range busy\n", __func__); | |
171 | return -EBUSY; | |
172 | } | |
6567954b BG |
173 | |
174 | davinci_cp_intc_base = ioremap(config->reg.start, | |
175 | resource_size(&config->reg)); | |
6c702da6 BG |
176 | if (!davinci_cp_intc_base) { |
177 | pr_err("%s: unable to ioremap register range\n", __func__); | |
07caba96 | 178 | return -EINVAL; |
6c702da6 | 179 | } |
0521444d | 180 | |
b35b55e7 | 181 | davinci_cp_intc_write(0, DAVINCI_CP_INTC_GLOBAL_ENABLE); |
0521444d SS |
182 | |
183 | /* Disable all host interrupts */ | |
b35b55e7 | 184 | davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_ENABLE(0)); |
0521444d SS |
185 | |
186 | /* Disable system interrupts */ | |
6567954b BG |
187 | for (offset = 0; offset < num_regs; offset++) |
188 | davinci_cp_intc_write(~0, | |
189 | DAVINCI_CP_INTC_SYS_ENABLE_CLR(offset)); | |
0521444d SS |
190 | |
191 | /* Set to normal mode, no nesting, no priority hold */ | |
b35b55e7 BG |
192 | davinci_cp_intc_write(0, DAVINCI_CP_INTC_CTRL); |
193 | davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_CTRL); | |
0521444d SS |
194 | |
195 | /* Clear system interrupt status */ | |
6567954b BG |
196 | for (offset = 0; offset < num_regs; offset++) |
197 | davinci_cp_intc_write(~0, | |
198 | DAVINCI_CP_INTC_SYS_STAT_CLR(offset)); | |
0521444d SS |
199 | |
200 | /* Enable nIRQ (what about nFIQ?) */ | |
b35b55e7 | 201 | davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET); |
0521444d | 202 | |
6567954b BG |
203 | /* Default all priorities to channel 7. */ |
204 | num_regs = (config->num_irqs + 3) >> 2; /* 4 channels per register */ | |
205 | for (offset = 0; offset < num_regs; offset++) | |
206 | davinci_cp_intc_write(0x07070707, | |
207 | DAVINCI_CP_INTC_CHAN_MAP(offset)); | |
0521444d | 208 | |
6567954b | 209 | irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0); |
07caba96 | 210 | if (irq_base < 0) { |
6c702da6 BG |
211 | pr_err("%s: unable to allocate interrupt descriptors: %d\n", |
212 | __func__, irq_base); | |
213 | return irq_base; | |
07caba96 HS |
214 | } |
215 | ||
b35b55e7 | 216 | davinci_cp_intc_irq_domain = irq_domain_add_legacy( |
6567954b | 217 | node, config->num_irqs, irq_base, 0, |
b35b55e7 | 218 | &davinci_cp_intc_irq_domain_ops, NULL); |
07caba96 | 219 | |
b35b55e7 | 220 | if (!davinci_cp_intc_irq_domain) { |
6c702da6 | 221 | pr_err("%s: unable to create an interrupt domain\n", __func__); |
07caba96 | 222 | return -EINVAL; |
0521444d SS |
223 | } |
224 | ||
b35b55e7 | 225 | set_handle_irq(davinci_cp_intc_handle_irq); |
d0064594 | 226 | |
0521444d | 227 | /* Enable global interrupt */ |
b35b55e7 | 228 | davinci_cp_intc_write(1, DAVINCI_CP_INTC_GLOBAL_ENABLE); |
07caba96 HS |
229 | |
230 | return 0; | |
231 | } | |
232 | ||
6567954b | 233 | int __init davinci_cp_intc_init(const struct davinci_cp_intc_config *config) |
07caba96 | 234 | { |
6567954b | 235 | return davinci_cp_intc_do_init(config, NULL); |
0521444d | 236 | } |
9a7f2fc8 | 237 | |
6567954b BG |
238 | static int __init davinci_cp_intc_of_init(struct device_node *node, |
239 | struct device_node *parent) | |
240 | { | |
241 | struct davinci_cp_intc_config config = { }; | |
242 | int ret; | |
243 | ||
244 | ret = of_address_to_resource(node, 0, &config.reg); | |
245 | if (ret) { | |
246 | pr_err("%s: unable to get the register range from device-tree\n", | |
247 | __func__); | |
248 | return ret; | |
249 | } | |
250 | ||
251 | ret = of_property_read_u32(node, "ti,intc-size", &config.num_irqs); | |
252 | if (ret) { | |
253 | pr_err("%s: unable to read the 'ti,intc-size' property\n", | |
254 | __func__); | |
255 | return ret; | |
256 | } | |
257 | ||
258 | return davinci_cp_intc_do_init(&config, node); | |
259 | } | |
b35b55e7 | 260 | IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", davinci_cp_intc_of_init); |