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021f6537 | 1 | /* |
0edc23ea | 2 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
021f6537 MZ |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
68628bb8 JG |
18 | #define pr_fmt(fmt) "GICv3: " fmt |
19 | ||
ffa7d616 | 20 | #include <linux/acpi.h> |
021f6537 | 21 | #include <linux/cpu.h> |
3708d52f | 22 | #include <linux/cpu_pm.h> |
021f6537 MZ |
23 | #include <linux/delay.h> |
24 | #include <linux/interrupt.h> | |
ffa7d616 | 25 | #include <linux/irqdomain.h> |
021f6537 MZ |
26 | #include <linux/of.h> |
27 | #include <linux/of_address.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/percpu.h> | |
101b35f7 | 30 | #include <linux/refcount.h> |
021f6537 MZ |
31 | #include <linux/slab.h> |
32 | ||
41a83e06 | 33 | #include <linux/irqchip.h> |
1839e576 | 34 | #include <linux/irqchip/arm-gic-common.h> |
021f6537 | 35 | #include <linux/irqchip/arm-gic-v3.h> |
e3825ba1 | 36 | #include <linux/irqchip/irq-partition-percpu.h> |
021f6537 MZ |
37 | |
38 | #include <asm/cputype.h> | |
39 | #include <asm/exception.h> | |
40 | #include <asm/smp_plat.h> | |
0b6a3da9 | 41 | #include <asm/virt.h> |
021f6537 MZ |
42 | |
43 | #include "irq-gic-common.h" | |
021f6537 | 44 | |
f32c9266 JT |
45 | #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80) |
46 | ||
9c8114c2 SK |
47 | #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) |
48 | ||
f5c1434c MZ |
49 | struct redist_region { |
50 | void __iomem *redist_base; | |
51 | phys_addr_t phys_base; | |
b70fb7af | 52 | bool single_redist; |
f5c1434c MZ |
53 | }; |
54 | ||
021f6537 | 55 | struct gic_chip_data { |
e3825ba1 | 56 | struct fwnode_handle *fwnode; |
021f6537 | 57 | void __iomem *dist_base; |
f5c1434c MZ |
58 | struct redist_region *redist_regions; |
59 | struct rdists rdists; | |
021f6537 MZ |
60 | struct irq_domain *domain; |
61 | u64 redist_stride; | |
f5c1434c | 62 | u32 nr_redist_regions; |
9c8114c2 | 63 | u64 flags; |
eda0d04a | 64 | bool has_rss; |
021f6537 | 65 | unsigned int irq_nr; |
e3825ba1 | 66 | struct partition_desc *ppi_descs[16]; |
021f6537 MZ |
67 | }; |
68 | ||
69 | static struct gic_chip_data gic_data __read_mostly; | |
d01d3274 | 70 | static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); |
021f6537 | 71 | |
d98d0a99 JT |
72 | /* |
73 | * The behaviours of RPR and PMR registers differ depending on the value of | |
74 | * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the | |
75 | * distributor and redistributors depends on whether security is enabled in the | |
76 | * GIC. | |
77 | * | |
78 | * When security is enabled, non-secure priority values from the (re)distributor | |
79 | * are presented to the GIC CPUIF as follow: | |
80 | * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; | |
81 | * | |
82 | * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure | |
83 | * EL1 are subject to a similar operation thus matching the priorities presented | |
84 | * from the (re)distributor when security is enabled. | |
85 | * | |
86 | * see GICv3/GICv4 Architecture Specification (IHI0069D): | |
87 | * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt | |
88 | * priorities. | |
89 | * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 | |
90 | * interrupt. | |
91 | * | |
92 | * For now, we only support pseudo-NMIs if we have non-secure view of | |
93 | * priorities. | |
94 | */ | |
95 | static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); | |
96 | ||
101b35f7 JT |
97 | /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ |
98 | static refcount_t ppi_nmi_refs[16]; | |
99 | ||
1839e576 | 100 | static struct gic_kvm_info gic_v3_kvm_info; |
eda0d04a | 101 | static DEFINE_PER_CPU(bool, has_rss); |
1839e576 | 102 | |
eda0d04a | 103 | #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) |
f5c1434c MZ |
104 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
105 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
106 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
107 | ||
108 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
109 | #define DEFAULT_PMR_VALUE 0xf0 | |
110 | ||
111 | static inline unsigned int gic_irq(struct irq_data *d) | |
112 | { | |
113 | return d->hwirq; | |
114 | } | |
115 | ||
116 | static inline int gic_irq_in_rdist(struct irq_data *d) | |
117 | { | |
118 | return gic_irq(d) < 32; | |
119 | } | |
120 | ||
121 | static inline void __iomem *gic_dist_base(struct irq_data *d) | |
122 | { | |
123 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ | |
124 | return gic_data_rdist_sgi_base(); | |
125 | ||
126 | if (d->hwirq <= 1023) /* SPI -> dist_base */ | |
127 | return gic_data.dist_base; | |
128 | ||
021f6537 MZ |
129 | return NULL; |
130 | } | |
131 | ||
132 | static void gic_do_wait_for_rwp(void __iomem *base) | |
133 | { | |
134 | u32 count = 1000000; /* 1s! */ | |
135 | ||
136 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { | |
137 | count--; | |
138 | if (!count) { | |
139 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
140 | return; | |
141 | } | |
142 | cpu_relax(); | |
143 | udelay(1); | |
144 | }; | |
145 | } | |
146 | ||
147 | /* Wait for completion of a distributor change */ | |
148 | static void gic_dist_wait_for_rwp(void) | |
149 | { | |
150 | gic_do_wait_for_rwp(gic_data.dist_base); | |
151 | } | |
152 | ||
153 | /* Wait for completion of a redistributor change */ | |
154 | static void gic_redist_wait_for_rwp(void) | |
155 | { | |
156 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); | |
157 | } | |
158 | ||
7936e914 | 159 | #ifdef CONFIG_ARM64 |
6d4e11c5 RR |
160 | |
161 | static u64 __maybe_unused gic_read_iar(void) | |
162 | { | |
a4023f68 | 163 | if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
6d4e11c5 RR |
164 | return gic_read_iar_cavium_thunderx(); |
165 | else | |
166 | return gic_read_iar_common(); | |
167 | } | |
7936e914 | 168 | #endif |
021f6537 | 169 | |
a2c22510 | 170 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
171 | { |
172 | void __iomem *rbase; | |
173 | u32 count = 1000000; /* 1s! */ | |
174 | u32 val; | |
175 | ||
9c8114c2 SK |
176 | if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) |
177 | return; | |
178 | ||
021f6537 MZ |
179 | rbase = gic_data_rdist_rd_base(); |
180 | ||
021f6537 | 181 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
182 | if (enable) |
183 | /* Wake up this CPU redistributor */ | |
184 | val &= ~GICR_WAKER_ProcessorSleep; | |
185 | else | |
186 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
187 | writel_relaxed(val, rbase + GICR_WAKER); |
188 | ||
a2c22510 SH |
189 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
190 | val = readl_relaxed(rbase + GICR_WAKER); | |
191 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
192 | return; /* No PM support in this redistributor */ | |
193 | } | |
194 | ||
d102eb5c | 195 | while (--count) { |
a2c22510 | 196 | val = readl_relaxed(rbase + GICR_WAKER); |
cf1d9d11 | 197 | if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) |
a2c22510 | 198 | break; |
021f6537 MZ |
199 | cpu_relax(); |
200 | udelay(1); | |
201 | }; | |
a2c22510 SH |
202 | if (!count) |
203 | pr_err_ratelimited("redistributor failed to %s...\n", | |
204 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
205 | } |
206 | ||
207 | /* | |
208 | * Routines to disable, enable, EOI and route interrupts | |
209 | */ | |
b594c6e2 MZ |
210 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
211 | { | |
212 | u32 mask = 1 << (gic_irq(d) % 32); | |
213 | void __iomem *base; | |
214 | ||
215 | if (gic_irq_in_rdist(d)) | |
216 | base = gic_data_rdist_sgi_base(); | |
217 | else | |
218 | base = gic_data.dist_base; | |
219 | ||
220 | return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); | |
221 | } | |
222 | ||
021f6537 MZ |
223 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
224 | { | |
225 | u32 mask = 1 << (gic_irq(d) % 32); | |
226 | void (*rwp_wait)(void); | |
227 | void __iomem *base; | |
228 | ||
229 | if (gic_irq_in_rdist(d)) { | |
230 | base = gic_data_rdist_sgi_base(); | |
231 | rwp_wait = gic_redist_wait_for_rwp; | |
232 | } else { | |
233 | base = gic_data.dist_base; | |
234 | rwp_wait = gic_dist_wait_for_rwp; | |
235 | } | |
236 | ||
237 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); | |
238 | rwp_wait(); | |
239 | } | |
240 | ||
021f6537 MZ |
241 | static void gic_mask_irq(struct irq_data *d) |
242 | { | |
243 | gic_poke_irq(d, GICD_ICENABLER); | |
244 | } | |
245 | ||
0b6a3da9 MZ |
246 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
247 | { | |
248 | gic_mask_irq(d); | |
530bf353 MZ |
249 | /* |
250 | * When masking a forwarded interrupt, make sure it is | |
251 | * deactivated as well. | |
252 | * | |
253 | * This ensures that an interrupt that is getting | |
254 | * disabled/masked will not get "stuck", because there is | |
255 | * noone to deactivate it (guest is being terminated). | |
256 | */ | |
4df7f54d | 257 | if (irqd_is_forwarded_to_vcpu(d)) |
530bf353 | 258 | gic_poke_irq(d, GICD_ICACTIVER); |
0b6a3da9 MZ |
259 | } |
260 | ||
021f6537 MZ |
261 | static void gic_unmask_irq(struct irq_data *d) |
262 | { | |
263 | gic_poke_irq(d, GICD_ISENABLER); | |
264 | } | |
265 | ||
d98d0a99 JT |
266 | static inline bool gic_supports_nmi(void) |
267 | { | |
268 | return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && | |
269 | static_branch_likely(&supports_pseudo_nmis); | |
270 | } | |
271 | ||
b594c6e2 MZ |
272 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
273 | enum irqchip_irq_state which, bool val) | |
274 | { | |
275 | u32 reg; | |
276 | ||
277 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
278 | return -EINVAL; | |
279 | ||
280 | switch (which) { | |
281 | case IRQCHIP_STATE_PENDING: | |
282 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
283 | break; | |
284 | ||
285 | case IRQCHIP_STATE_ACTIVE: | |
286 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
287 | break; | |
288 | ||
289 | case IRQCHIP_STATE_MASKED: | |
290 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; | |
291 | break; | |
292 | ||
293 | default: | |
294 | return -EINVAL; | |
295 | } | |
296 | ||
297 | gic_poke_irq(d, reg); | |
298 | return 0; | |
299 | } | |
300 | ||
301 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
302 | enum irqchip_irq_state which, bool *val) | |
303 | { | |
304 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
305 | return -EINVAL; | |
306 | ||
307 | switch (which) { | |
308 | case IRQCHIP_STATE_PENDING: | |
309 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
310 | break; | |
311 | ||
312 | case IRQCHIP_STATE_ACTIVE: | |
313 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
314 | break; | |
315 | ||
316 | case IRQCHIP_STATE_MASKED: | |
317 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
318 | break; | |
319 | ||
320 | default: | |
321 | return -EINVAL; | |
322 | } | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
101b35f7 JT |
327 | static void gic_irq_set_prio(struct irq_data *d, u8 prio) |
328 | { | |
329 | void __iomem *base = gic_dist_base(d); | |
330 | ||
331 | writeb_relaxed(prio, base + GICD_IPRIORITYR + gic_irq(d)); | |
332 | } | |
333 | ||
334 | static int gic_irq_nmi_setup(struct irq_data *d) | |
335 | { | |
336 | struct irq_desc *desc = irq_to_desc(d->irq); | |
337 | ||
338 | if (!gic_supports_nmi()) | |
339 | return -EINVAL; | |
340 | ||
341 | if (gic_peek_irq(d, GICD_ISENABLER)) { | |
342 | pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); | |
343 | return -EINVAL; | |
344 | } | |
345 | ||
346 | /* | |
347 | * A secondary irq_chip should be in charge of LPI request, | |
348 | * it should not be possible to get there | |
349 | */ | |
350 | if (WARN_ON(gic_irq(d) >= 8192)) | |
351 | return -EINVAL; | |
352 | ||
353 | /* desc lock should already be held */ | |
354 | if (gic_irq(d) < 32) { | |
355 | /* Setting up PPI as NMI, only switch handler for first NMI */ | |
356 | if (!refcount_inc_not_zero(&ppi_nmi_refs[gic_irq(d) - 16])) { | |
357 | refcount_set(&ppi_nmi_refs[gic_irq(d) - 16], 1); | |
358 | desc->handle_irq = handle_percpu_devid_fasteoi_nmi; | |
359 | } | |
360 | } else { | |
361 | desc->handle_irq = handle_fasteoi_nmi; | |
362 | } | |
363 | ||
364 | gic_irq_set_prio(d, GICD_INT_NMI_PRI); | |
365 | ||
366 | return 0; | |
367 | } | |
368 | ||
369 | static void gic_irq_nmi_teardown(struct irq_data *d) | |
370 | { | |
371 | struct irq_desc *desc = irq_to_desc(d->irq); | |
372 | ||
373 | if (WARN_ON(!gic_supports_nmi())) | |
374 | return; | |
375 | ||
376 | if (gic_peek_irq(d, GICD_ISENABLER)) { | |
377 | pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); | |
378 | return; | |
379 | } | |
380 | ||
381 | /* | |
382 | * A secondary irq_chip should be in charge of LPI request, | |
383 | * it should not be possible to get there | |
384 | */ | |
385 | if (WARN_ON(gic_irq(d) >= 8192)) | |
386 | return; | |
387 | ||
388 | /* desc lock should already be held */ | |
389 | if (gic_irq(d) < 32) { | |
390 | /* Tearing down NMI, only switch handler for last NMI */ | |
391 | if (refcount_dec_and_test(&ppi_nmi_refs[gic_irq(d) - 16])) | |
392 | desc->handle_irq = handle_percpu_devid_irq; | |
393 | } else { | |
394 | desc->handle_irq = handle_fasteoi_irq; | |
395 | } | |
396 | ||
397 | gic_irq_set_prio(d, GICD_INT_DEF_PRI); | |
398 | } | |
399 | ||
021f6537 MZ |
400 | static void gic_eoi_irq(struct irq_data *d) |
401 | { | |
402 | gic_write_eoir(gic_irq(d)); | |
403 | } | |
404 | ||
0b6a3da9 MZ |
405 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
406 | { | |
407 | /* | |
530bf353 MZ |
408 | * No need to deactivate an LPI, or an interrupt that |
409 | * is is getting forwarded to a vcpu. | |
0b6a3da9 | 410 | */ |
4df7f54d | 411 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
0b6a3da9 MZ |
412 | return; |
413 | gic_write_dir(gic_irq(d)); | |
414 | } | |
415 | ||
021f6537 MZ |
416 | static int gic_set_type(struct irq_data *d, unsigned int type) |
417 | { | |
418 | unsigned int irq = gic_irq(d); | |
419 | void (*rwp_wait)(void); | |
420 | void __iomem *base; | |
421 | ||
422 | /* Interrupt configuration for SGIs can't be changed */ | |
423 | if (irq < 16) | |
424 | return -EINVAL; | |
425 | ||
fb7e7deb LD |
426 | /* SPIs have restrictions on the supported types */ |
427 | if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
428 | type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
429 | return -EINVAL; |
430 | ||
431 | if (gic_irq_in_rdist(d)) { | |
432 | base = gic_data_rdist_sgi_base(); | |
433 | rwp_wait = gic_redist_wait_for_rwp; | |
434 | } else { | |
435 | base = gic_data.dist_base; | |
436 | rwp_wait = gic_dist_wait_for_rwp; | |
437 | } | |
438 | ||
fb7e7deb | 439 | return gic_configure_irq(irq, type, base, rwp_wait); |
021f6537 MZ |
440 | } |
441 | ||
530bf353 MZ |
442 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
443 | { | |
4df7f54d TG |
444 | if (vcpu) |
445 | irqd_set_forwarded_to_vcpu(d); | |
446 | else | |
447 | irqd_clr_forwarded_to_vcpu(d); | |
530bf353 MZ |
448 | return 0; |
449 | } | |
450 | ||
f6c86a41 | 451 | static u64 gic_mpidr_to_affinity(unsigned long mpidr) |
021f6537 MZ |
452 | { |
453 | u64 aff; | |
454 | ||
f6c86a41 | 455 | aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
021f6537 MZ |
456 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
457 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
458 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
459 | ||
460 | return aff; | |
461 | } | |
462 | ||
f32c9266 JT |
463 | static void gic_deactivate_unhandled(u32 irqnr) |
464 | { | |
465 | if (static_branch_likely(&supports_deactivate_key)) { | |
466 | if (irqnr < 8192) | |
467 | gic_write_dir(irqnr); | |
468 | } else { | |
469 | gic_write_eoir(irqnr); | |
470 | } | |
471 | } | |
472 | ||
473 | static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs) | |
474 | { | |
5c48d5d4 | 475 | bool irqs_enabled = interrupts_enabled(regs); |
f32c9266 JT |
476 | int err; |
477 | ||
5c48d5d4 JT |
478 | if (irqs_enabled) |
479 | nmi_enter(); | |
480 | ||
f32c9266 JT |
481 | if (static_branch_likely(&supports_deactivate_key)) |
482 | gic_write_eoir(irqnr); | |
483 | /* | |
484 | * Leave the PSR.I bit set to prevent other NMIs to be | |
485 | * received while handling this one. | |
486 | * PSR.I will be restored when we ERET to the | |
487 | * interrupted context. | |
488 | */ | |
489 | err = handle_domain_nmi(gic_data.domain, irqnr, regs); | |
490 | if (err) | |
491 | gic_deactivate_unhandled(irqnr); | |
5c48d5d4 JT |
492 | |
493 | if (irqs_enabled) | |
494 | nmi_exit(); | |
f32c9266 JT |
495 | } |
496 | ||
021f6537 MZ |
497 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
498 | { | |
f6c86a41 | 499 | u32 irqnr; |
021f6537 | 500 | |
342677d7 | 501 | irqnr = gic_read_iar(); |
021f6537 | 502 | |
f32c9266 JT |
503 | if (gic_supports_nmi() && |
504 | unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { | |
505 | gic_handle_nmi(irqnr, regs); | |
506 | return; | |
507 | } | |
508 | ||
3f1f3234 JT |
509 | if (gic_prio_masking_enabled()) { |
510 | gic_pmr_mask_irqs(); | |
511 | gic_arch_enable_irqs(); | |
512 | } | |
513 | ||
342677d7 JT |
514 | if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { |
515 | int err; | |
0b6a3da9 | 516 | |
342677d7 JT |
517 | if (static_branch_likely(&supports_deactivate_key)) |
518 | gic_write_eoir(irqnr); | |
519 | else | |
520 | isb(); | |
521 | ||
522 | err = handle_domain_irq(gic_data.domain, irqnr, regs); | |
523 | if (err) { | |
524 | WARN_ONCE(true, "Unexpected interrupt received!\n"); | |
f32c9266 | 525 | gic_deactivate_unhandled(irqnr); |
021f6537 | 526 | } |
342677d7 JT |
527 | return; |
528 | } | |
529 | if (irqnr < 16) { | |
530 | gic_write_eoir(irqnr); | |
531 | if (static_branch_likely(&supports_deactivate_key)) | |
532 | gic_write_dir(irqnr); | |
021f6537 | 533 | #ifdef CONFIG_SMP |
342677d7 JT |
534 | /* |
535 | * Unlike GICv2, we don't need an smp_rmb() here. | |
536 | * The control dependency from gic_read_iar to | |
537 | * the ISB in gic_write_eoir is enough to ensure | |
538 | * that any shared data read by handle_IPI will | |
539 | * be read after the ACK. | |
540 | */ | |
541 | handle_IPI(irqnr, regs); | |
021f6537 | 542 | #else |
342677d7 | 543 | WARN_ONCE(true, "Unexpected SGI received!\n"); |
021f6537 | 544 | #endif |
342677d7 | 545 | } |
021f6537 MZ |
546 | } |
547 | ||
b5cf6073 JT |
548 | static u32 gic_get_pribits(void) |
549 | { | |
550 | u32 pribits; | |
551 | ||
552 | pribits = gic_read_ctlr(); | |
553 | pribits &= ICC_CTLR_EL1_PRI_BITS_MASK; | |
554 | pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; | |
555 | pribits++; | |
556 | ||
557 | return pribits; | |
558 | } | |
559 | ||
560 | static bool gic_has_group0(void) | |
561 | { | |
562 | u32 val; | |
e7932188 JT |
563 | u32 old_pmr; |
564 | ||
565 | old_pmr = gic_read_pmr(); | |
b5cf6073 JT |
566 | |
567 | /* | |
568 | * Let's find out if Group0 is under control of EL3 or not by | |
569 | * setting the highest possible, non-zero priority in PMR. | |
570 | * | |
571 | * If SCR_EL3.FIQ is set, the priority gets shifted down in | |
572 | * order for the CPU interface to set bit 7, and keep the | |
573 | * actual priority in the non-secure range. In the process, it | |
574 | * looses the least significant bit and the actual priority | |
575 | * becomes 0x80. Reading it back returns 0, indicating that | |
576 | * we're don't have access to Group0. | |
577 | */ | |
578 | gic_write_pmr(BIT(8 - gic_get_pribits())); | |
579 | val = gic_read_pmr(); | |
580 | ||
e7932188 JT |
581 | gic_write_pmr(old_pmr); |
582 | ||
b5cf6073 JT |
583 | return val != 0; |
584 | } | |
585 | ||
021f6537 MZ |
586 | static void __init gic_dist_init(void) |
587 | { | |
588 | unsigned int i; | |
589 | u64 affinity; | |
590 | void __iomem *base = gic_data.dist_base; | |
591 | ||
592 | /* Disable the distributor */ | |
593 | writel_relaxed(0, base + GICD_CTLR); | |
594 | gic_dist_wait_for_rwp(); | |
595 | ||
7c9b9730 MZ |
596 | /* |
597 | * Configure SPIs as non-secure Group-1. This will only matter | |
598 | * if the GIC only has a single security state. This will not | |
599 | * do the right thing if the kernel is running in secure mode, | |
600 | * but that's not the intended use case anyway. | |
601 | */ | |
602 | for (i = 32; i < gic_data.irq_nr; i += 32) | |
603 | writel_relaxed(~0, base + GICD_IGROUPR + i / 8); | |
604 | ||
021f6537 MZ |
605 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); |
606 | ||
607 | /* Enable distributor with ARE, Group1 */ | |
608 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, | |
609 | base + GICD_CTLR); | |
610 | ||
611 | /* | |
612 | * Set all global interrupts to the boot CPU only. ARE must be | |
613 | * enabled. | |
614 | */ | |
615 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); | |
616 | for (i = 32; i < gic_data.irq_nr; i++) | |
72c97126 | 617 | gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); |
021f6537 MZ |
618 | } |
619 | ||
0d94ded2 | 620 | static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) |
021f6537 | 621 | { |
0d94ded2 | 622 | int ret = -ENODEV; |
021f6537 MZ |
623 | int i; |
624 | ||
f5c1434c MZ |
625 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
626 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
0d94ded2 | 627 | u64 typer; |
021f6537 MZ |
628 | u32 reg; |
629 | ||
630 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
631 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
632 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
633 | pr_warn("No redistributor present @%p\n", ptr); | |
634 | break; | |
635 | } | |
636 | ||
637 | do { | |
72c97126 | 638 | typer = gic_read_typer(ptr + GICR_TYPER); |
0d94ded2 MZ |
639 | ret = fn(gic_data.redist_regions + i, ptr); |
640 | if (!ret) | |
021f6537 | 641 | return 0; |
021f6537 | 642 | |
b70fb7af TN |
643 | if (gic_data.redist_regions[i].single_redist) |
644 | break; | |
645 | ||
021f6537 MZ |
646 | if (gic_data.redist_stride) { |
647 | ptr += gic_data.redist_stride; | |
648 | } else { | |
649 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
650 | if (typer & GICR_TYPER_VLPIS) | |
651 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
652 | } | |
653 | } while (!(typer & GICR_TYPER_LAST)); | |
654 | } | |
655 | ||
0d94ded2 MZ |
656 | return ret ? -ENODEV : 0; |
657 | } | |
658 | ||
659 | static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) | |
660 | { | |
661 | unsigned long mpidr = cpu_logical_map(smp_processor_id()); | |
662 | u64 typer; | |
663 | u32 aff; | |
664 | ||
665 | /* | |
666 | * Convert affinity to a 32bit value that can be matched to | |
667 | * GICR_TYPER bits [63:32]. | |
668 | */ | |
669 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | | |
670 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
671 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
672 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
673 | ||
674 | typer = gic_read_typer(ptr + GICR_TYPER); | |
675 | if ((typer >> 32) == aff) { | |
676 | u64 offset = ptr - region->redist_base; | |
677 | gic_data_rdist_rd_base() = ptr; | |
678 | gic_data_rdist()->phys_base = region->phys_base + offset; | |
679 | ||
680 | pr_info("CPU%d: found redistributor %lx region %d:%pa\n", | |
681 | smp_processor_id(), mpidr, | |
682 | (int)(region - gic_data.redist_regions), | |
683 | &gic_data_rdist()->phys_base); | |
684 | return 0; | |
685 | } | |
686 | ||
687 | /* Try next one */ | |
688 | return 1; | |
689 | } | |
690 | ||
691 | static int gic_populate_rdist(void) | |
692 | { | |
693 | if (gic_iterate_rdists(__gic_populate_rdist) == 0) | |
694 | return 0; | |
695 | ||
021f6537 | 696 | /* We couldn't even deal with ourselves... */ |
f6c86a41 | 697 | WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", |
0d94ded2 MZ |
698 | smp_processor_id(), |
699 | (unsigned long)cpu_logical_map(smp_processor_id())); | |
021f6537 MZ |
700 | return -ENODEV; |
701 | } | |
702 | ||
0edc23ea MZ |
703 | static int __gic_update_vlpi_properties(struct redist_region *region, |
704 | void __iomem *ptr) | |
705 | { | |
706 | u64 typer = gic_read_typer(ptr + GICR_TYPER); | |
707 | gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); | |
708 | gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS); | |
709 | ||
710 | return 1; | |
711 | } | |
712 | ||
713 | static void gic_update_vlpi_properties(void) | |
714 | { | |
715 | gic_iterate_rdists(__gic_update_vlpi_properties); | |
716 | pr_info("%sVLPI support, %sdirect LPI support\n", | |
717 | !gic_data.rdists.has_vlpis ? "no " : "", | |
718 | !gic_data.rdists.has_direct_lpi ? "no " : ""); | |
719 | } | |
720 | ||
d98d0a99 JT |
721 | /* Check whether it's single security state view */ |
722 | static inline bool gic_dist_security_disabled(void) | |
723 | { | |
724 | return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; | |
725 | } | |
726 | ||
3708d52f SH |
727 | static void gic_cpu_sys_reg_init(void) |
728 | { | |
eda0d04a SD |
729 | int i, cpu = smp_processor_id(); |
730 | u64 mpidr = cpu_logical_map(cpu); | |
731 | u64 need_rss = MPIDR_RS(mpidr); | |
33625282 | 732 | bool group0; |
b5cf6073 | 733 | u32 pribits; |
eda0d04a | 734 | |
7cabd008 MZ |
735 | /* |
736 | * Need to check that the SRE bit has actually been set. If | |
737 | * not, it means that SRE is disabled at EL2. We're going to | |
738 | * die painfully, and there is nothing we can do about it. | |
739 | * | |
740 | * Kindly inform the luser. | |
741 | */ | |
742 | if (!gic_enable_sre()) | |
743 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
3708d52f | 744 | |
b5cf6073 | 745 | pribits = gic_get_pribits(); |
33625282 | 746 | |
b5cf6073 | 747 | group0 = gic_has_group0(); |
33625282 | 748 | |
3708d52f | 749 | /* Set priority mask register */ |
d98d0a99 | 750 | if (!gic_prio_masking_enabled()) { |
e7932188 | 751 | write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); |
d98d0a99 JT |
752 | } else { |
753 | /* | |
754 | * Mismatch configuration with boot CPU, the system is likely | |
755 | * to die as interrupt masking will not work properly on all | |
756 | * CPUs | |
757 | */ | |
758 | WARN_ON(gic_supports_nmi() && group0 && | |
759 | !gic_dist_security_disabled()); | |
760 | } | |
3708d52f | 761 | |
91ef8442 DT |
762 | /* |
763 | * Some firmwares hand over to the kernel with the BPR changed from | |
764 | * its reset value (and with a value large enough to prevent | |
765 | * any pre-emptive interrupts from working at all). Writing a zero | |
766 | * to BPR restores is reset value. | |
767 | */ | |
768 | gic_write_bpr1(0); | |
769 | ||
d01d3274 | 770 | if (static_branch_likely(&supports_deactivate_key)) { |
0b6a3da9 MZ |
771 | /* EOI drops priority only (mode 1) */ |
772 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
773 | } else { | |
774 | /* EOI deactivates interrupt too (mode 0) */ | |
775 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
776 | } | |
3708d52f | 777 | |
33625282 MZ |
778 | /* Always whack Group0 before Group1 */ |
779 | if (group0) { | |
780 | switch(pribits) { | |
781 | case 8: | |
782 | case 7: | |
783 | write_gicreg(0, ICC_AP0R3_EL1); | |
784 | write_gicreg(0, ICC_AP0R2_EL1); | |
785 | case 6: | |
786 | write_gicreg(0, ICC_AP0R1_EL1); | |
787 | case 5: | |
788 | case 4: | |
789 | write_gicreg(0, ICC_AP0R0_EL1); | |
790 | } | |
791 | ||
792 | isb(); | |
793 | } | |
d6062a6d | 794 | |
33625282 | 795 | switch(pribits) { |
d6062a6d MZ |
796 | case 8: |
797 | case 7: | |
d6062a6d | 798 | write_gicreg(0, ICC_AP1R3_EL1); |
d6062a6d MZ |
799 | write_gicreg(0, ICC_AP1R2_EL1); |
800 | case 6: | |
d6062a6d MZ |
801 | write_gicreg(0, ICC_AP1R1_EL1); |
802 | case 5: | |
803 | case 4: | |
d6062a6d MZ |
804 | write_gicreg(0, ICC_AP1R0_EL1); |
805 | } | |
806 | ||
807 | isb(); | |
808 | ||
3708d52f SH |
809 | /* ... and let's hit the road... */ |
810 | gic_write_grpen1(1); | |
eda0d04a SD |
811 | |
812 | /* Keep the RSS capability status in per_cpu variable */ | |
813 | per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); | |
814 | ||
815 | /* Check all the CPUs have capable of sending SGIs to other CPUs */ | |
816 | for_each_online_cpu(i) { | |
817 | bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); | |
818 | ||
819 | need_rss |= MPIDR_RS(cpu_logical_map(i)); | |
820 | if (need_rss && (!have_rss)) | |
821 | pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", | |
822 | cpu, (unsigned long)mpidr, | |
823 | i, (unsigned long)cpu_logical_map(i)); | |
824 | } | |
825 | ||
826 | /** | |
827 | * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, | |
828 | * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED | |
829 | * UNPREDICTABLE choice of : | |
830 | * - The write is ignored. | |
831 | * - The RS field is treated as 0. | |
832 | */ | |
833 | if (need_rss && (!gic_data.has_rss)) | |
834 | pr_crit_once("RSS is required but GICD doesn't support it\n"); | |
3708d52f SH |
835 | } |
836 | ||
f736d65d MZ |
837 | static bool gicv3_nolpi; |
838 | ||
839 | static int __init gicv3_nolpi_cfg(char *buf) | |
840 | { | |
841 | return strtobool(buf, &gicv3_nolpi); | |
842 | } | |
843 | early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg); | |
844 | ||
da33f31d MZ |
845 | static int gic_dist_supports_lpis(void) |
846 | { | |
d38a71c5 MZ |
847 | return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && |
848 | !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) && | |
849 | !gicv3_nolpi); | |
da33f31d MZ |
850 | } |
851 | ||
021f6537 MZ |
852 | static void gic_cpu_init(void) |
853 | { | |
854 | void __iomem *rbase; | |
855 | ||
856 | /* Register ourselves with the rest of the world */ | |
857 | if (gic_populate_rdist()) | |
858 | return; | |
859 | ||
a2c22510 | 860 | gic_enable_redist(true); |
021f6537 MZ |
861 | |
862 | rbase = gic_data_rdist_sgi_base(); | |
863 | ||
7c9b9730 MZ |
864 | /* Configure SGIs/PPIs as non-secure Group-1 */ |
865 | writel_relaxed(~0, rbase + GICR_IGROUPR0); | |
866 | ||
021f6537 MZ |
867 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); |
868 | ||
3708d52f SH |
869 | /* initialise system registers */ |
870 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
871 | } |
872 | ||
873 | #ifdef CONFIG_SMP | |
6670a6d8 | 874 | |
eda0d04a SD |
875 | #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) |
876 | #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) | |
877 | ||
6670a6d8 | 878 | static int gic_starting_cpu(unsigned int cpu) |
021f6537 | 879 | { |
6670a6d8 | 880 | gic_cpu_init(); |
d38a71c5 MZ |
881 | |
882 | if (gic_dist_supports_lpis()) | |
883 | its_cpu_init(); | |
884 | ||
6670a6d8 | 885 | return 0; |
021f6537 MZ |
886 | } |
887 | ||
021f6537 | 888 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, |
f6c86a41 | 889 | unsigned long cluster_id) |
021f6537 | 890 | { |
727653d6 | 891 | int next_cpu, cpu = *base_cpu; |
f6c86a41 | 892 | unsigned long mpidr = cpu_logical_map(cpu); |
021f6537 MZ |
893 | u16 tlist = 0; |
894 | ||
895 | while (cpu < nr_cpu_ids) { | |
021f6537 MZ |
896 | tlist |= 1 << (mpidr & 0xf); |
897 | ||
727653d6 JM |
898 | next_cpu = cpumask_next(cpu, mask); |
899 | if (next_cpu >= nr_cpu_ids) | |
021f6537 | 900 | goto out; |
727653d6 | 901 | cpu = next_cpu; |
021f6537 MZ |
902 | |
903 | mpidr = cpu_logical_map(cpu); | |
904 | ||
eda0d04a | 905 | if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { |
021f6537 MZ |
906 | cpu--; |
907 | goto out; | |
908 | } | |
909 | } | |
910 | out: | |
911 | *base_cpu = cpu; | |
912 | return tlist; | |
913 | } | |
914 | ||
7e580278 AP |
915 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
916 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
917 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
918 | ||
021f6537 MZ |
919 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
920 | { | |
921 | u64 val; | |
922 | ||
7e580278 AP |
923 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
924 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
925 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
926 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
eda0d04a | 927 | MPIDR_TO_SGI_RS(cluster_id) | |
7e580278 | 928 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); |
021f6537 | 929 | |
b6dd4d83 | 930 | pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); |
021f6537 MZ |
931 | gic_write_sgi1r(val); |
932 | } | |
933 | ||
934 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |
935 | { | |
936 | int cpu; | |
937 | ||
938 | if (WARN_ON(irq >= 16)) | |
939 | return; | |
940 | ||
941 | /* | |
942 | * Ensure that stores to Normal memory are visible to the | |
943 | * other CPUs before issuing the IPI. | |
944 | */ | |
21ec30c0 | 945 | wmb(); |
021f6537 | 946 | |
f9b531fe | 947 | for_each_cpu(cpu, mask) { |
eda0d04a | 948 | u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); |
021f6537 MZ |
949 | u16 tlist; |
950 | ||
951 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
952 | gic_send_sgi(cluster_id, tlist, irq); | |
953 | } | |
954 | ||
955 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
956 | isb(); | |
957 | } | |
958 | ||
959 | static void gic_smp_init(void) | |
960 | { | |
961 | set_smp_cross_call(gic_raise_softirq); | |
6896bcd1 | 962 | cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, |
73c1b41e TG |
963 | "irqchip/arm/gicv3:starting", |
964 | gic_starting_cpu, NULL); | |
021f6537 MZ |
965 | } |
966 | ||
967 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
968 | bool force) | |
969 | { | |
65a30f8b | 970 | unsigned int cpu; |
021f6537 MZ |
971 | void __iomem *reg; |
972 | int enabled; | |
973 | u64 val; | |
974 | ||
65a30f8b SP |
975 | if (force) |
976 | cpu = cpumask_first(mask_val); | |
977 | else | |
978 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
979 | ||
866d7c1b SP |
980 | if (cpu >= nr_cpu_ids) |
981 | return -EINVAL; | |
982 | ||
021f6537 MZ |
983 | if (gic_irq_in_rdist(d)) |
984 | return -EINVAL; | |
985 | ||
986 | /* If interrupt was enabled, disable it first */ | |
987 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
988 | if (enabled) | |
989 | gic_mask_irq(d); | |
990 | ||
991 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); | |
992 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); | |
993 | ||
72c97126 | 994 | gic_write_irouter(val, reg); |
021f6537 MZ |
995 | |
996 | /* | |
997 | * If the interrupt was enabled, enabled it again. Otherwise, | |
998 | * just wait for the distributor to have digested our changes. | |
999 | */ | |
1000 | if (enabled) | |
1001 | gic_unmask_irq(d); | |
1002 | else | |
1003 | gic_dist_wait_for_rwp(); | |
1004 | ||
956ae91a MZ |
1005 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
1006 | ||
0fc6fa29 | 1007 | return IRQ_SET_MASK_OK_DONE; |
021f6537 MZ |
1008 | } |
1009 | #else | |
1010 | #define gic_set_affinity NULL | |
1011 | #define gic_smp_init() do { } while(0) | |
1012 | #endif | |
1013 | ||
3708d52f SH |
1014 | #ifdef CONFIG_CPU_PM |
1015 | static int gic_cpu_pm_notifier(struct notifier_block *self, | |
1016 | unsigned long cmd, void *v) | |
1017 | { | |
1018 | if (cmd == CPU_PM_EXIT) { | |
ccd9432a SH |
1019 | if (gic_dist_security_disabled()) |
1020 | gic_enable_redist(true); | |
3708d52f | 1021 | gic_cpu_sys_reg_init(); |
ccd9432a | 1022 | } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { |
3708d52f SH |
1023 | gic_write_grpen1(0); |
1024 | gic_enable_redist(false); | |
1025 | } | |
1026 | return NOTIFY_OK; | |
1027 | } | |
1028 | ||
1029 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
1030 | .notifier_call = gic_cpu_pm_notifier, | |
1031 | }; | |
1032 | ||
1033 | static void gic_cpu_pm_init(void) | |
1034 | { | |
1035 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
1036 | } | |
1037 | ||
1038 | #else | |
1039 | static inline void gic_cpu_pm_init(void) { } | |
1040 | #endif /* CONFIG_CPU_PM */ | |
1041 | ||
021f6537 MZ |
1042 | static struct irq_chip gic_chip = { |
1043 | .name = "GICv3", | |
1044 | .irq_mask = gic_mask_irq, | |
1045 | .irq_unmask = gic_unmask_irq, | |
1046 | .irq_eoi = gic_eoi_irq, | |
1047 | .irq_set_type = gic_set_type, | |
1048 | .irq_set_affinity = gic_set_affinity, | |
b594c6e2 MZ |
1049 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
1050 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
101b35f7 JT |
1051 | .irq_nmi_setup = gic_irq_nmi_setup, |
1052 | .irq_nmi_teardown = gic_irq_nmi_teardown, | |
4110b5cb MZ |
1053 | .flags = IRQCHIP_SET_TYPE_MASKED | |
1054 | IRQCHIP_SKIP_SET_WAKE | | |
1055 | IRQCHIP_MASK_ON_SUSPEND, | |
021f6537 MZ |
1056 | }; |
1057 | ||
0b6a3da9 MZ |
1058 | static struct irq_chip gic_eoimode1_chip = { |
1059 | .name = "GICv3", | |
1060 | .irq_mask = gic_eoimode1_mask_irq, | |
1061 | .irq_unmask = gic_unmask_irq, | |
1062 | .irq_eoi = gic_eoimode1_eoi_irq, | |
1063 | .irq_set_type = gic_set_type, | |
1064 | .irq_set_affinity = gic_set_affinity, | |
1065 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
1066 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
530bf353 | 1067 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
101b35f7 JT |
1068 | .irq_nmi_setup = gic_irq_nmi_setup, |
1069 | .irq_nmi_teardown = gic_irq_nmi_teardown, | |
4110b5cb MZ |
1070 | .flags = IRQCHIP_SET_TYPE_MASKED | |
1071 | IRQCHIP_SKIP_SET_WAKE | | |
1072 | IRQCHIP_MASK_ON_SUSPEND, | |
0b6a3da9 MZ |
1073 | }; |
1074 | ||
a4f9edb2 | 1075 | #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer)) |
da33f31d | 1076 | |
021f6537 MZ |
1077 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
1078 | irq_hw_number_t hw) | |
1079 | { | |
0b6a3da9 MZ |
1080 | struct irq_chip *chip = &gic_chip; |
1081 | ||
d01d3274 | 1082 | if (static_branch_likely(&supports_deactivate_key)) |
0b6a3da9 MZ |
1083 | chip = &gic_eoimode1_chip; |
1084 | ||
021f6537 MZ |
1085 | /* SGIs are private to the core kernel */ |
1086 | if (hw < 16) | |
1087 | return -EPERM; | |
da33f31d MZ |
1088 | /* Nothing here */ |
1089 | if (hw >= gic_data.irq_nr && hw < 8192) | |
1090 | return -EPERM; | |
1091 | /* Off limits */ | |
1092 | if (hw >= GIC_ID_NR) | |
1093 | return -EPERM; | |
1094 | ||
021f6537 MZ |
1095 | /* PPIs */ |
1096 | if (hw < 32) { | |
1097 | irq_set_percpu_devid(irq); | |
0b6a3da9 | 1098 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 1099 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 1100 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
021f6537 MZ |
1101 | } |
1102 | /* SPIs */ | |
1103 | if (hw >= 32 && hw < gic_data.irq_nr) { | |
0b6a3da9 | 1104 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 1105 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 1106 | irq_set_probe(irq); |
956ae91a | 1107 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); |
021f6537 | 1108 | } |
da33f31d MZ |
1109 | /* LPIs */ |
1110 | if (hw >= 8192 && hw < GIC_ID_NR) { | |
1111 | if (!gic_dist_supports_lpis()) | |
1112 | return -EPERM; | |
0b6a3da9 | 1113 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d | 1114 | handle_fasteoi_irq, NULL, NULL); |
da33f31d MZ |
1115 | } |
1116 | ||
021f6537 MZ |
1117 | return 0; |
1118 | } | |
1119 | ||
65da7d19 MZ |
1120 | #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) |
1121 | ||
f833f57f MZ |
1122 | static int gic_irq_domain_translate(struct irq_domain *d, |
1123 | struct irq_fwspec *fwspec, | |
1124 | unsigned long *hwirq, | |
1125 | unsigned int *type) | |
021f6537 | 1126 | { |
f833f57f MZ |
1127 | if (is_of_node(fwspec->fwnode)) { |
1128 | if (fwspec->param_count < 3) | |
1129 | return -EINVAL; | |
021f6537 | 1130 | |
db8c70ec MZ |
1131 | switch (fwspec->param[0]) { |
1132 | case 0: /* SPI */ | |
1133 | *hwirq = fwspec->param[1] + 32; | |
1134 | break; | |
1135 | case 1: /* PPI */ | |
65da7d19 | 1136 | case GIC_IRQ_TYPE_PARTITION: |
db8c70ec MZ |
1137 | *hwirq = fwspec->param[1] + 16; |
1138 | break; | |
1139 | case GIC_IRQ_TYPE_LPI: /* LPI */ | |
1140 | *hwirq = fwspec->param[1]; | |
1141 | break; | |
1142 | default: | |
1143 | return -EINVAL; | |
1144 | } | |
f833f57f MZ |
1145 | |
1146 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
6ef6386e | 1147 | |
65da7d19 MZ |
1148 | /* |
1149 | * Make it clear that broken DTs are... broken. | |
1150 | * Partitionned PPIs are an unfortunate exception. | |
1151 | */ | |
1152 | WARN_ON(*type == IRQ_TYPE_NONE && | |
1153 | fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); | |
f833f57f | 1154 | return 0; |
021f6537 MZ |
1155 | } |
1156 | ||
ffa7d616 TN |
1157 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
1158 | if(fwspec->param_count != 2) | |
1159 | return -EINVAL; | |
1160 | ||
1161 | *hwirq = fwspec->param[0]; | |
1162 | *type = fwspec->param[1]; | |
6ef6386e MZ |
1163 | |
1164 | WARN_ON(*type == IRQ_TYPE_NONE); | |
ffa7d616 TN |
1165 | return 0; |
1166 | } | |
1167 | ||
f833f57f | 1168 | return -EINVAL; |
021f6537 MZ |
1169 | } |
1170 | ||
443acc4f MZ |
1171 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
1172 | unsigned int nr_irqs, void *arg) | |
1173 | { | |
1174 | int i, ret; | |
1175 | irq_hw_number_t hwirq; | |
1176 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 1177 | struct irq_fwspec *fwspec = arg; |
443acc4f | 1178 | |
f833f57f | 1179 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
443acc4f MZ |
1180 | if (ret) |
1181 | return ret; | |
1182 | ||
63c16c6e SP |
1183 | for (i = 0; i < nr_irqs; i++) { |
1184 | ret = gic_irq_domain_map(domain, virq + i, hwirq + i); | |
1185 | if (ret) | |
1186 | return ret; | |
1187 | } | |
443acc4f MZ |
1188 | |
1189 | return 0; | |
1190 | } | |
1191 | ||
1192 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
1193 | unsigned int nr_irqs) | |
1194 | { | |
1195 | int i; | |
1196 | ||
1197 | for (i = 0; i < nr_irqs; i++) { | |
1198 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
1199 | irq_set_handler(virq + i, NULL); | |
1200 | irq_domain_reset_irq_data(d); | |
1201 | } | |
1202 | } | |
1203 | ||
e3825ba1 MZ |
1204 | static int gic_irq_domain_select(struct irq_domain *d, |
1205 | struct irq_fwspec *fwspec, | |
1206 | enum irq_domain_bus_token bus_token) | |
1207 | { | |
1208 | /* Not for us */ | |
1209 | if (fwspec->fwnode != d->fwnode) | |
1210 | return 0; | |
1211 | ||
1212 | /* If this is not DT, then we have a single domain */ | |
1213 | if (!is_of_node(fwspec->fwnode)) | |
1214 | return 1; | |
1215 | ||
1216 | /* | |
1217 | * If this is a PPI and we have a 4th (non-null) parameter, | |
1218 | * then we need to match the partition domain. | |
1219 | */ | |
1220 | if (fwspec->param_count >= 4 && | |
1221 | fwspec->param[0] == 1 && fwspec->param[3] != 0) | |
1222 | return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); | |
1223 | ||
1224 | return d == gic_data.domain; | |
1225 | } | |
1226 | ||
021f6537 | 1227 | static const struct irq_domain_ops gic_irq_domain_ops = { |
f833f57f | 1228 | .translate = gic_irq_domain_translate, |
443acc4f MZ |
1229 | .alloc = gic_irq_domain_alloc, |
1230 | .free = gic_irq_domain_free, | |
e3825ba1 MZ |
1231 | .select = gic_irq_domain_select, |
1232 | }; | |
1233 | ||
1234 | static int partition_domain_translate(struct irq_domain *d, | |
1235 | struct irq_fwspec *fwspec, | |
1236 | unsigned long *hwirq, | |
1237 | unsigned int *type) | |
1238 | { | |
1239 | struct device_node *np; | |
1240 | int ret; | |
1241 | ||
1242 | np = of_find_node_by_phandle(fwspec->param[3]); | |
1243 | if (WARN_ON(!np)) | |
1244 | return -EINVAL; | |
1245 | ||
1246 | ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], | |
1247 | of_node_to_fwnode(np)); | |
1248 | if (ret < 0) | |
1249 | return ret; | |
1250 | ||
1251 | *hwirq = ret; | |
1252 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
1253 | ||
1254 | return 0; | |
1255 | } | |
1256 | ||
1257 | static const struct irq_domain_ops partition_domain_ops = { | |
1258 | .translate = partition_domain_translate, | |
1259 | .select = gic_irq_domain_select, | |
021f6537 MZ |
1260 | }; |
1261 | ||
9c8114c2 SK |
1262 | static bool gic_enable_quirk_msm8996(void *data) |
1263 | { | |
1264 | struct gic_chip_data *d = data; | |
1265 | ||
1266 | d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; | |
1267 | ||
1268 | return true; | |
1269 | } | |
1270 | ||
d98d0a99 JT |
1271 | static void gic_enable_nmi_support(void) |
1272 | { | |
101b35f7 JT |
1273 | int i; |
1274 | ||
1275 | for (i = 0; i < 16; i++) | |
1276 | refcount_set(&ppi_nmi_refs[i], 0); | |
1277 | ||
d98d0a99 | 1278 | static_branch_enable(&supports_pseudo_nmis); |
101b35f7 JT |
1279 | |
1280 | if (static_branch_likely(&supports_deactivate_key)) | |
1281 | gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI; | |
1282 | else | |
1283 | gic_chip.flags |= IRQCHIP_SUPPORTS_NMI; | |
d98d0a99 JT |
1284 | } |
1285 | ||
db57d746 TN |
1286 | static int __init gic_init_bases(void __iomem *dist_base, |
1287 | struct redist_region *rdist_regs, | |
1288 | u32 nr_redist_regions, | |
1289 | u64 redist_stride, | |
1290 | struct fwnode_handle *handle) | |
021f6537 | 1291 | { |
f5c1434c | 1292 | u32 typer; |
021f6537 MZ |
1293 | int gic_irqs; |
1294 | int err; | |
021f6537 | 1295 | |
0b6a3da9 | 1296 | if (!is_hyp_mode_available()) |
d01d3274 | 1297 | static_branch_disable(&supports_deactivate_key); |
0b6a3da9 | 1298 | |
d01d3274 | 1299 | if (static_branch_likely(&supports_deactivate_key)) |
0b6a3da9 MZ |
1300 | pr_info("GIC: Using split EOI/Deactivate mode\n"); |
1301 | ||
e3825ba1 | 1302 | gic_data.fwnode = handle; |
021f6537 | 1303 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
1304 | gic_data.redist_regions = rdist_regs; |
1305 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
1306 | gic_data.redist_stride = redist_stride; |
1307 | ||
1308 | /* | |
1309 | * Find out how many interrupts are supported. | |
1310 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) | |
1311 | */ | |
f5c1434c | 1312 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
a4f9edb2 | 1313 | gic_data.rdists.gicd_typer = typer; |
f5c1434c | 1314 | gic_irqs = GICD_TYPER_IRQS(typer); |
021f6537 MZ |
1315 | if (gic_irqs > 1020) |
1316 | gic_irqs = 1020; | |
1317 | gic_data.irq_nr = gic_irqs; | |
1318 | ||
db57d746 TN |
1319 | gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, |
1320 | &gic_data); | |
b2425b51 | 1321 | irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); |
f5c1434c | 1322 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
0edc23ea MZ |
1323 | gic_data.rdists.has_vlpis = true; |
1324 | gic_data.rdists.has_direct_lpi = true; | |
021f6537 | 1325 | |
f5c1434c | 1326 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
1327 | err = -ENOMEM; |
1328 | goto out_free; | |
1329 | } | |
1330 | ||
eda0d04a SD |
1331 | gic_data.has_rss = !!(typer & GICD_TYPER_RSS); |
1332 | pr_info("Distributor has %sRange Selector support\n", | |
1333 | gic_data.has_rss ? "" : "no "); | |
1334 | ||
50528752 MZ |
1335 | if (typer & GICD_TYPER_MBIS) { |
1336 | err = mbi_init(handle, gic_data.domain); | |
1337 | if (err) | |
1338 | pr_err("Failed to initialize MBIs\n"); | |
1339 | } | |
1340 | ||
021f6537 MZ |
1341 | set_handle_irq(gic_handle_irq); |
1342 | ||
0edc23ea MZ |
1343 | gic_update_vlpi_properties(); |
1344 | ||
021f6537 MZ |
1345 | gic_smp_init(); |
1346 | gic_dist_init(); | |
1347 | gic_cpu_init(); | |
3708d52f | 1348 | gic_cpu_pm_init(); |
021f6537 | 1349 | |
d38a71c5 MZ |
1350 | if (gic_dist_supports_lpis()) { |
1351 | its_init(handle, &gic_data.rdists, gic_data.domain); | |
1352 | its_cpu_init(); | |
1353 | } | |
1354 | ||
d98d0a99 JT |
1355 | if (gic_prio_masking_enabled()) { |
1356 | if (!gic_has_group0() || gic_dist_security_disabled()) | |
1357 | gic_enable_nmi_support(); | |
1358 | else | |
1359 | pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n"); | |
1360 | } | |
1361 | ||
021f6537 MZ |
1362 | return 0; |
1363 | ||
1364 | out_free: | |
1365 | if (gic_data.domain) | |
1366 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 1367 | free_percpu(gic_data.rdists.rdist); |
db57d746 TN |
1368 | return err; |
1369 | } | |
1370 | ||
1371 | static int __init gic_validate_dist_version(void __iomem *dist_base) | |
1372 | { | |
1373 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1374 | ||
1375 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) | |
1376 | return -ENODEV; | |
1377 | ||
1378 | return 0; | |
1379 | } | |
1380 | ||
e3825ba1 | 1381 | /* Create all possible partitions at boot time */ |
7beaa24b | 1382 | static void __init gic_populate_ppi_partitions(struct device_node *gic_node) |
e3825ba1 MZ |
1383 | { |
1384 | struct device_node *parts_node, *child_part; | |
1385 | int part_idx = 0, i; | |
1386 | int nr_parts; | |
1387 | struct partition_affinity *parts; | |
1388 | ||
00ee9a1c | 1389 | parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); |
e3825ba1 MZ |
1390 | if (!parts_node) |
1391 | return; | |
1392 | ||
1393 | nr_parts = of_get_child_count(parts_node); | |
1394 | ||
1395 | if (!nr_parts) | |
00ee9a1c | 1396 | goto out_put_node; |
e3825ba1 | 1397 | |
6396bb22 | 1398 | parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); |
e3825ba1 | 1399 | if (WARN_ON(!parts)) |
00ee9a1c | 1400 | goto out_put_node; |
e3825ba1 MZ |
1401 | |
1402 | for_each_child_of_node(parts_node, child_part) { | |
1403 | struct partition_affinity *part; | |
1404 | int n; | |
1405 | ||
1406 | part = &parts[part_idx]; | |
1407 | ||
1408 | part->partition_id = of_node_to_fwnode(child_part); | |
1409 | ||
2ef790dc RH |
1410 | pr_info("GIC: PPI partition %pOFn[%d] { ", |
1411 | child_part, part_idx); | |
e3825ba1 MZ |
1412 | |
1413 | n = of_property_count_elems_of_size(child_part, "affinity", | |
1414 | sizeof(u32)); | |
1415 | WARN_ON(n <= 0); | |
1416 | ||
1417 | for (i = 0; i < n; i++) { | |
1418 | int err, cpu; | |
1419 | u32 cpu_phandle; | |
1420 | struct device_node *cpu_node; | |
1421 | ||
1422 | err = of_property_read_u32_index(child_part, "affinity", | |
1423 | i, &cpu_phandle); | |
1424 | if (WARN_ON(err)) | |
1425 | continue; | |
1426 | ||
1427 | cpu_node = of_find_node_by_phandle(cpu_phandle); | |
1428 | if (WARN_ON(!cpu_node)) | |
1429 | continue; | |
1430 | ||
c08ec7da SP |
1431 | cpu = of_cpu_node_to_id(cpu_node); |
1432 | if (WARN_ON(cpu < 0)) | |
e3825ba1 MZ |
1433 | continue; |
1434 | ||
e81f54c6 | 1435 | pr_cont("%pOF[%d] ", cpu_node, cpu); |
e3825ba1 MZ |
1436 | |
1437 | cpumask_set_cpu(cpu, &part->mask); | |
1438 | } | |
1439 | ||
1440 | pr_cont("}\n"); | |
1441 | part_idx++; | |
1442 | } | |
1443 | ||
1444 | for (i = 0; i < 16; i++) { | |
1445 | unsigned int irq; | |
1446 | struct partition_desc *desc; | |
1447 | struct irq_fwspec ppi_fwspec = { | |
1448 | .fwnode = gic_data.fwnode, | |
1449 | .param_count = 3, | |
1450 | .param = { | |
65da7d19 | 1451 | [0] = GIC_IRQ_TYPE_PARTITION, |
e3825ba1 MZ |
1452 | [1] = i, |
1453 | [2] = IRQ_TYPE_NONE, | |
1454 | }, | |
1455 | }; | |
1456 | ||
1457 | irq = irq_create_fwspec_mapping(&ppi_fwspec); | |
1458 | if (WARN_ON(!irq)) | |
1459 | continue; | |
1460 | desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, | |
1461 | irq, &partition_domain_ops); | |
1462 | if (WARN_ON(!desc)) | |
1463 | continue; | |
1464 | ||
1465 | gic_data.ppi_descs[i] = desc; | |
1466 | } | |
00ee9a1c JH |
1467 | |
1468 | out_put_node: | |
1469 | of_node_put(parts_node); | |
e3825ba1 MZ |
1470 | } |
1471 | ||
1839e576 JG |
1472 | static void __init gic_of_setup_kvm_info(struct device_node *node) |
1473 | { | |
1474 | int ret; | |
1475 | struct resource r; | |
1476 | u32 gicv_idx; | |
1477 | ||
1478 | gic_v3_kvm_info.type = GIC_V3; | |
1479 | ||
1480 | gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); | |
1481 | if (!gic_v3_kvm_info.maint_irq) | |
1482 | return; | |
1483 | ||
1484 | if (of_property_read_u32(node, "#redistributor-regions", | |
1485 | &gicv_idx)) | |
1486 | gicv_idx = 1; | |
1487 | ||
1488 | gicv_idx += 3; /* Also skip GICD, GICC, GICH */ | |
1489 | ret = of_address_to_resource(node, gicv_idx, &r); | |
1490 | if (!ret) | |
1491 | gic_v3_kvm_info.vcpu = r; | |
1492 | ||
4bdf5025 | 1493 | gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; |
1839e576 JG |
1494 | gic_set_kvm_info(&gic_v3_kvm_info); |
1495 | } | |
1496 | ||
f70fdb42 | 1497 | static const struct gic_quirk gic_quirks[] = { |
9c8114c2 SK |
1498 | { |
1499 | .desc = "GICv3: Qualcomm MSM8996 broken firmware", | |
1500 | .compatible = "qcom,msm8996-gic-v3", | |
1501 | .init = gic_enable_quirk_msm8996, | |
1502 | }, | |
f70fdb42 SK |
1503 | { |
1504 | } | |
1505 | }; | |
1506 | ||
db57d746 TN |
1507 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) |
1508 | { | |
1509 | void __iomem *dist_base; | |
1510 | struct redist_region *rdist_regs; | |
1511 | u64 redist_stride; | |
1512 | u32 nr_redist_regions; | |
1513 | int err, i; | |
1514 | ||
1515 | dist_base = of_iomap(node, 0); | |
1516 | if (!dist_base) { | |
e81f54c6 | 1517 | pr_err("%pOF: unable to map gic dist registers\n", node); |
db57d746 TN |
1518 | return -ENXIO; |
1519 | } | |
1520 | ||
1521 | err = gic_validate_dist_version(dist_base); | |
1522 | if (err) { | |
e81f54c6 | 1523 | pr_err("%pOF: no distributor detected, giving up\n", node); |
db57d746 TN |
1524 | goto out_unmap_dist; |
1525 | } | |
1526 | ||
1527 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) | |
1528 | nr_redist_regions = 1; | |
1529 | ||
6396bb22 KC |
1530 | rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs), |
1531 | GFP_KERNEL); | |
db57d746 TN |
1532 | if (!rdist_regs) { |
1533 | err = -ENOMEM; | |
1534 | goto out_unmap_dist; | |
1535 | } | |
1536 | ||
1537 | for (i = 0; i < nr_redist_regions; i++) { | |
1538 | struct resource res; | |
1539 | int ret; | |
1540 | ||
1541 | ret = of_address_to_resource(node, 1 + i, &res); | |
1542 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); | |
1543 | if (ret || !rdist_regs[i].redist_base) { | |
e81f54c6 | 1544 | pr_err("%pOF: couldn't map region %d\n", node, i); |
db57d746 TN |
1545 | err = -ENODEV; |
1546 | goto out_unmap_rdist; | |
1547 | } | |
1548 | rdist_regs[i].phys_base = res.start; | |
1549 | } | |
1550 | ||
1551 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
1552 | redist_stride = 0; | |
1553 | ||
f70fdb42 SK |
1554 | gic_enable_of_quirks(node, gic_quirks, &gic_data); |
1555 | ||
db57d746 TN |
1556 | err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, |
1557 | redist_stride, &node->fwnode); | |
e3825ba1 MZ |
1558 | if (err) |
1559 | goto out_unmap_rdist; | |
1560 | ||
1561 | gic_populate_ppi_partitions(node); | |
d33a3c8c | 1562 | |
d01d3274 | 1563 | if (static_branch_likely(&supports_deactivate_key)) |
d33a3c8c | 1564 | gic_of_setup_kvm_info(node); |
e3825ba1 | 1565 | return 0; |
db57d746 | 1566 | |
021f6537 | 1567 | out_unmap_rdist: |
f5c1434c MZ |
1568 | for (i = 0; i < nr_redist_regions; i++) |
1569 | if (rdist_regs[i].redist_base) | |
1570 | iounmap(rdist_regs[i].redist_base); | |
1571 | kfree(rdist_regs); | |
021f6537 MZ |
1572 | out_unmap_dist: |
1573 | iounmap(dist_base); | |
1574 | return err; | |
1575 | } | |
1576 | ||
1577 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); | |
ffa7d616 TN |
1578 | |
1579 | #ifdef CONFIG_ACPI | |
611f039f JG |
1580 | static struct |
1581 | { | |
1582 | void __iomem *dist_base; | |
1583 | struct redist_region *redist_regs; | |
1584 | u32 nr_redist_regions; | |
1585 | bool single_redist; | |
1839e576 JG |
1586 | u32 maint_irq; |
1587 | int maint_irq_mode; | |
1588 | phys_addr_t vcpu_base; | |
611f039f | 1589 | } acpi_data __initdata; |
b70fb7af TN |
1590 | |
1591 | static void __init | |
1592 | gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) | |
1593 | { | |
1594 | static int count = 0; | |
1595 | ||
611f039f JG |
1596 | acpi_data.redist_regs[count].phys_base = phys_base; |
1597 | acpi_data.redist_regs[count].redist_base = redist_base; | |
1598 | acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; | |
b70fb7af TN |
1599 | count++; |
1600 | } | |
ffa7d616 TN |
1601 | |
1602 | static int __init | |
1603 | gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, | |
1604 | const unsigned long end) | |
1605 | { | |
1606 | struct acpi_madt_generic_redistributor *redist = | |
1607 | (struct acpi_madt_generic_redistributor *)header; | |
1608 | void __iomem *redist_base; | |
ffa7d616 TN |
1609 | |
1610 | redist_base = ioremap(redist->base_address, redist->length); | |
1611 | if (!redist_base) { | |
1612 | pr_err("Couldn't map GICR region @%llx\n", redist->base_address); | |
1613 | return -ENOMEM; | |
1614 | } | |
1615 | ||
b70fb7af | 1616 | gic_acpi_register_redist(redist->base_address, redist_base); |
ffa7d616 TN |
1617 | return 0; |
1618 | } | |
1619 | ||
b70fb7af TN |
1620 | static int __init |
1621 | gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, | |
1622 | const unsigned long end) | |
1623 | { | |
1624 | struct acpi_madt_generic_interrupt *gicc = | |
1625 | (struct acpi_madt_generic_interrupt *)header; | |
611f039f | 1626 | u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; |
b70fb7af TN |
1627 | u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; |
1628 | void __iomem *redist_base; | |
1629 | ||
ebe2f871 SD |
1630 | /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ |
1631 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
1632 | return 0; | |
1633 | ||
b70fb7af TN |
1634 | redist_base = ioremap(gicc->gicr_base_address, size); |
1635 | if (!redist_base) | |
1636 | return -ENOMEM; | |
1637 | ||
1638 | gic_acpi_register_redist(gicc->gicr_base_address, redist_base); | |
1639 | return 0; | |
1640 | } | |
1641 | ||
1642 | static int __init gic_acpi_collect_gicr_base(void) | |
1643 | { | |
1644 | acpi_tbl_entry_handler redist_parser; | |
1645 | enum acpi_madt_type type; | |
1646 | ||
611f039f | 1647 | if (acpi_data.single_redist) { |
b70fb7af TN |
1648 | type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; |
1649 | redist_parser = gic_acpi_parse_madt_gicc; | |
1650 | } else { | |
1651 | type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; | |
1652 | redist_parser = gic_acpi_parse_madt_redist; | |
1653 | } | |
1654 | ||
1655 | /* Collect redistributor base addresses in GICR entries */ | |
1656 | if (acpi_table_parse_madt(type, redist_parser, 0) > 0) | |
1657 | return 0; | |
1658 | ||
1659 | pr_info("No valid GICR entries exist\n"); | |
1660 | return -ENODEV; | |
1661 | } | |
1662 | ||
ffa7d616 TN |
1663 | static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, |
1664 | const unsigned long end) | |
1665 | { | |
1666 | /* Subtable presence means that redist exists, that's it */ | |
1667 | return 0; | |
1668 | } | |
1669 | ||
b70fb7af TN |
1670 | static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, |
1671 | const unsigned long end) | |
1672 | { | |
1673 | struct acpi_madt_generic_interrupt *gicc = | |
1674 | (struct acpi_madt_generic_interrupt *)header; | |
1675 | ||
1676 | /* | |
1677 | * If GICC is enabled and has valid gicr base address, then it means | |
1678 | * GICR base is presented via GICC | |
1679 | */ | |
1680 | if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) | |
1681 | return 0; | |
1682 | ||
ebe2f871 SD |
1683 | /* |
1684 | * It's perfectly valid firmware can pass disabled GICC entry, driver | |
1685 | * should not treat as errors, skip the entry instead of probe fail. | |
1686 | */ | |
1687 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
1688 | return 0; | |
1689 | ||
b70fb7af TN |
1690 | return -ENODEV; |
1691 | } | |
1692 | ||
1693 | static int __init gic_acpi_count_gicr_regions(void) | |
1694 | { | |
1695 | int count; | |
1696 | ||
1697 | /* | |
1698 | * Count how many redistributor regions we have. It is not allowed | |
1699 | * to mix redistributor description, GICR and GICC subtables have to be | |
1700 | * mutually exclusive. | |
1701 | */ | |
1702 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1703 | gic_acpi_match_gicr, 0); | |
1704 | if (count > 0) { | |
611f039f | 1705 | acpi_data.single_redist = false; |
b70fb7af TN |
1706 | return count; |
1707 | } | |
1708 | ||
1709 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
1710 | gic_acpi_match_gicc, 0); | |
1711 | if (count > 0) | |
611f039f | 1712 | acpi_data.single_redist = true; |
b70fb7af TN |
1713 | |
1714 | return count; | |
1715 | } | |
1716 | ||
ffa7d616 TN |
1717 | static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, |
1718 | struct acpi_probe_entry *ape) | |
1719 | { | |
1720 | struct acpi_madt_generic_distributor *dist; | |
1721 | int count; | |
1722 | ||
1723 | dist = (struct acpi_madt_generic_distributor *)header; | |
1724 | if (dist->version != ape->driver_data) | |
1725 | return false; | |
1726 | ||
1727 | /* We need to do that exercise anyway, the sooner the better */ | |
b70fb7af | 1728 | count = gic_acpi_count_gicr_regions(); |
ffa7d616 TN |
1729 | if (count <= 0) |
1730 | return false; | |
1731 | ||
611f039f | 1732 | acpi_data.nr_redist_regions = count; |
ffa7d616 TN |
1733 | return true; |
1734 | } | |
1735 | ||
1839e576 JG |
1736 | static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, |
1737 | const unsigned long end) | |
1738 | { | |
1739 | struct acpi_madt_generic_interrupt *gicc = | |
1740 | (struct acpi_madt_generic_interrupt *)header; | |
1741 | int maint_irq_mode; | |
1742 | static int first_madt = true; | |
1743 | ||
1744 | /* Skip unusable CPUs */ | |
1745 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
1746 | return 0; | |
1747 | ||
1748 | maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? | |
1749 | ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; | |
1750 | ||
1751 | if (first_madt) { | |
1752 | first_madt = false; | |
1753 | ||
1754 | acpi_data.maint_irq = gicc->vgic_interrupt; | |
1755 | acpi_data.maint_irq_mode = maint_irq_mode; | |
1756 | acpi_data.vcpu_base = gicc->gicv_base_address; | |
1757 | ||
1758 | return 0; | |
1759 | } | |
1760 | ||
1761 | /* | |
1762 | * The maintenance interrupt and GICV should be the same for every CPU | |
1763 | */ | |
1764 | if ((acpi_data.maint_irq != gicc->vgic_interrupt) || | |
1765 | (acpi_data.maint_irq_mode != maint_irq_mode) || | |
1766 | (acpi_data.vcpu_base != gicc->gicv_base_address)) | |
1767 | return -EINVAL; | |
1768 | ||
1769 | return 0; | |
1770 | } | |
1771 | ||
1772 | static bool __init gic_acpi_collect_virt_info(void) | |
1773 | { | |
1774 | int count; | |
1775 | ||
1776 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
1777 | gic_acpi_parse_virt_madt_gicc, 0); | |
1778 | ||
1779 | return (count > 0); | |
1780 | } | |
1781 | ||
ffa7d616 | 1782 | #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) |
1839e576 JG |
1783 | #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) |
1784 | #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) | |
1785 | ||
1786 | static void __init gic_acpi_setup_kvm_info(void) | |
1787 | { | |
1788 | int irq; | |
1789 | ||
1790 | if (!gic_acpi_collect_virt_info()) { | |
1791 | pr_warn("Unable to get hardware information used for virtualization\n"); | |
1792 | return; | |
1793 | } | |
1794 | ||
1795 | gic_v3_kvm_info.type = GIC_V3; | |
1796 | ||
1797 | irq = acpi_register_gsi(NULL, acpi_data.maint_irq, | |
1798 | acpi_data.maint_irq_mode, | |
1799 | ACPI_ACTIVE_HIGH); | |
1800 | if (irq <= 0) | |
1801 | return; | |
1802 | ||
1803 | gic_v3_kvm_info.maint_irq = irq; | |
1804 | ||
1805 | if (acpi_data.vcpu_base) { | |
1806 | struct resource *vcpu = &gic_v3_kvm_info.vcpu; | |
1807 | ||
1808 | vcpu->flags = IORESOURCE_MEM; | |
1809 | vcpu->start = acpi_data.vcpu_base; | |
1810 | vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; | |
1811 | } | |
1812 | ||
4bdf5025 | 1813 | gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; |
1839e576 JG |
1814 | gic_set_kvm_info(&gic_v3_kvm_info); |
1815 | } | |
ffa7d616 TN |
1816 | |
1817 | static int __init | |
1818 | gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) | |
1819 | { | |
1820 | struct acpi_madt_generic_distributor *dist; | |
1821 | struct fwnode_handle *domain_handle; | |
611f039f | 1822 | size_t size; |
b70fb7af | 1823 | int i, err; |
ffa7d616 TN |
1824 | |
1825 | /* Get distributor base address */ | |
1826 | dist = (struct acpi_madt_generic_distributor *)header; | |
611f039f JG |
1827 | acpi_data.dist_base = ioremap(dist->base_address, |
1828 | ACPI_GICV3_DIST_MEM_SIZE); | |
1829 | if (!acpi_data.dist_base) { | |
ffa7d616 TN |
1830 | pr_err("Unable to map GICD registers\n"); |
1831 | return -ENOMEM; | |
1832 | } | |
1833 | ||
611f039f | 1834 | err = gic_validate_dist_version(acpi_data.dist_base); |
ffa7d616 | 1835 | if (err) { |
71192a68 | 1836 | pr_err("No distributor detected at @%p, giving up\n", |
611f039f | 1837 | acpi_data.dist_base); |
ffa7d616 TN |
1838 | goto out_dist_unmap; |
1839 | } | |
1840 | ||
611f039f JG |
1841 | size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; |
1842 | acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); | |
1843 | if (!acpi_data.redist_regs) { | |
ffa7d616 TN |
1844 | err = -ENOMEM; |
1845 | goto out_dist_unmap; | |
1846 | } | |
1847 | ||
b70fb7af TN |
1848 | err = gic_acpi_collect_gicr_base(); |
1849 | if (err) | |
ffa7d616 | 1850 | goto out_redist_unmap; |
ffa7d616 | 1851 | |
611f039f | 1852 | domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); |
ffa7d616 TN |
1853 | if (!domain_handle) { |
1854 | err = -ENOMEM; | |
1855 | goto out_redist_unmap; | |
1856 | } | |
1857 | ||
611f039f JG |
1858 | err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, |
1859 | acpi_data.nr_redist_regions, 0, domain_handle); | |
ffa7d616 TN |
1860 | if (err) |
1861 | goto out_fwhandle_free; | |
1862 | ||
1863 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); | |
d33a3c8c | 1864 | |
d01d3274 | 1865 | if (static_branch_likely(&supports_deactivate_key)) |
d33a3c8c | 1866 | gic_acpi_setup_kvm_info(); |
1839e576 | 1867 | |
ffa7d616 TN |
1868 | return 0; |
1869 | ||
1870 | out_fwhandle_free: | |
1871 | irq_domain_free_fwnode(domain_handle); | |
1872 | out_redist_unmap: | |
611f039f JG |
1873 | for (i = 0; i < acpi_data.nr_redist_regions; i++) |
1874 | if (acpi_data.redist_regs[i].redist_base) | |
1875 | iounmap(acpi_data.redist_regs[i].redist_base); | |
1876 | kfree(acpi_data.redist_regs); | |
ffa7d616 | 1877 | out_dist_unmap: |
611f039f | 1878 | iounmap(acpi_data.dist_base); |
ffa7d616 TN |
1879 | return err; |
1880 | } | |
1881 | IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1882 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, | |
1883 | gic_acpi_init); | |
1884 | IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1885 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, | |
1886 | gic_acpi_init); | |
1887 | IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1888 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, | |
1889 | gic_acpi_init); | |
1890 | #endif |