[thirdparty/linux.git] / drivers / irqchip / irq-gic-v3.c

/*
 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/percpu.h>
#include <linux/slab.h>

#include <linux/irqchip/arm-gic-v3.h>

#include <asm/cputype.h>
#include <asm/exception.h>
#include <asm/smp_plat.h>

#include "irq-gic-common.h"
#include "irqchip.h"

struct gic_chip_data {
	void __iomem		*dist_base;
	void __iomem		**redist_base;
	void __percpu __iomem	**rdist;
	struct irq_domain	*domain;
	u64			redist_stride;
	u32			redist_regions;
	unsigned int		irq_nr;
};

static struct gic_chip_data gic_data __read_mostly;

#define gic_data_rdist()		(this_cpu_ptr(gic_data.rdist))
#define gic_data_rdist_rd_base()	(*gic_data_rdist())
#define gic_data_rdist_sgi_base()	(gic_data_rdist_rd_base() + SZ_64K)

/* Our default, arbitrary priority value. Linux only uses one anyway. */
#define DEFAULT_PMR_VALUE	0xf0

static inline unsigned int gic_irq(struct irq_data *d)
{
	return d->hwirq;
}

static inline int gic_irq_in_rdist(struct irq_data *d)
{
	return gic_irq(d) < 32;
}

static inline void __iomem *gic_dist_base(struct irq_data *d)
{
	if (gic_irq_in_rdist(d))	/* SGI+PPI -> SGI_base for this CPU */
		return gic_data_rdist_sgi_base();

	if (d->hwirq <= 1023)		/* SPI -> dist_base */
		return gic_data.dist_base;

	if (d->hwirq >= 8192)
		BUG();		/* LPI Detected!!! */

	return NULL;
}

static void gic_do_wait_for_rwp(void __iomem *base)
{
	u32 count = 1000000;	/* 1s! */

	while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
		count--;
		if (!count) {
			pr_err_ratelimited("RWP timeout, gone fishing\n");
			return;
		}
		cpu_relax();
		udelay(1);
	};
}

/* Wait for completion of a distributor change */
static void gic_dist_wait_for_rwp(void)
{
	gic_do_wait_for_rwp(gic_data.dist_base);
}

/* Wait for completion of a redistributor change */
static void gic_redist_wait_for_rwp(void)
{
	gic_do_wait_for_rwp(gic_data_rdist_rd_base());
}

/* Low level accessors */
static u64 gic_read_iar(void)
{
	u64 irqstat;

	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
	return irqstat;
}

static void gic_write_pmr(u64 val)
{
	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
}

static void gic_write_ctlr(u64 val)
{
	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
	isb();
}

static void gic_write_grpen1(u64 val)
{
	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
	isb();
}

static void gic_write_sgi1r(u64 val)
{
	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
}

static void gic_enable_sre(void)
{
	u64 val;

	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
	val |= ICC_SRE_EL1_SRE;
	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
	isb();

	/*
	 * Need to check that the SRE bit has actually been set. If
	 * not, it means that SRE is disabled at EL2. We're going to
	 * die painfully, and there is nothing we can do about it.
	 *
	 * Kindly inform the luser.
	 */
	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
	if (!(val & ICC_SRE_EL1_SRE))
		pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
}

static void gic_enable_redist(bool enable)
{
	void __iomem *rbase;
	u32 count = 1000000;	/* 1s! */
	u32 val;

	rbase = gic_data_rdist_rd_base();

	val = readl_relaxed(rbase + GICR_WAKER);
	if (enable)
		/* Wake up this CPU redistributor */
		val &= ~GICR_WAKER_ProcessorSleep;
	else
		val |= GICR_WAKER_ProcessorSleep;
	writel_relaxed(val, rbase + GICR_WAKER);

	if (!enable) {		/* Check that GICR_WAKER is writeable */
		val = readl_relaxed(rbase + GICR_WAKER);
		if (!(val & GICR_WAKER_ProcessorSleep))
			return;	/* No PM support in this redistributor */
	}

	while (count--) {
		val = readl_relaxed(rbase + GICR_WAKER);
		if (enable ^ (val & GICR_WAKER_ChildrenAsleep))
			break;
		cpu_relax();
		udelay(1);
	};
	if (!count)
		pr_err_ratelimited("redistributor failed to %s...\n",
				   enable ? "wakeup" : "sleep");
}

/*
 * Routines to disable, enable, EOI and route interrupts
 */
static void gic_poke_irq(struct irq_data *d, u32 offset)
{
	u32 mask = 1 << (gic_irq(d) % 32);
	void (*rwp_wait)(void);
	void __iomem *base;

	if (gic_irq_in_rdist(d)) {
		base = gic_data_rdist_sgi_base();
		rwp_wait = gic_redist_wait_for_rwp;
	} else {
		base = gic_data.dist_base;
		rwp_wait = gic_dist_wait_for_rwp;
	}

	writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
	rwp_wait();
}

static int gic_peek_irq(struct irq_data *d, u32 offset)
{
	u32 mask = 1 << (gic_irq(d) % 32);
	void __iomem *base;

	if (gic_irq_in_rdist(d))
		base = gic_data_rdist_sgi_base();
	else
		base = gic_data.dist_base;

	return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
}

static void gic_mask_irq(struct irq_data *d)
{
	gic_poke_irq(d, GICD_ICENABLER);
}

static void gic_unmask_irq(struct irq_data *d)
{
	gic_poke_irq(d, GICD_ISENABLER);
}

static void gic_eoi_irq(struct irq_data *d)
{
	gic_write_eoir(gic_irq(d));
}

static int gic_set_type(struct irq_data *d, unsigned int type)
{
	unsigned int irq = gic_irq(d);
	void (*rwp_wait)(void);
	void __iomem *base;

	/* Interrupt configuration for SGIs can't be changed */
	if (irq < 16)
		return -EINVAL;

	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
		return -EINVAL;

	if (gic_irq_in_rdist(d)) {
		base = gic_data_rdist_sgi_base();
		rwp_wait = gic_redist_wait_for_rwp;
	} else {
		base = gic_data.dist_base;
		rwp_wait = gic_dist_wait_for_rwp;
	}

	gic_configure_irq(irq, type, base, rwp_wait);

	return 0;
}

static u64 gic_mpidr_to_affinity(u64 mpidr)
{
	u64 aff;

	aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
	       MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
	       MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8  |
	       MPIDR_AFFINITY_LEVEL(mpidr, 0));

	return aff;
}

static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
{
	u64 irqnr;

	do {
		irqnr = gic_read_iar();

		if (likely(irqnr > 15 && irqnr < 1020)) {
			u64 irq = irq_find_mapping(gic_data.domain, irqnr);
			if (likely(irq)) {
				handle_IRQ(irq, regs);
				continue;
			}

			WARN_ONCE(true, "Unexpected SPI received!\n");
			gic_write_eoir(irqnr);
		}
		if (irqnr < 16) {
			gic_write_eoir(irqnr);
#ifdef CONFIG_SMP
			handle_IPI(irqnr, regs);
#else
			WARN_ONCE(true, "Unexpected SGI received!\n");
#endif
			continue;
		}
	} while (irqnr != ICC_IAR1_EL1_SPURIOUS);
}

static void __init gic_dist_init(void)
{
	unsigned int i;
	u64 affinity;
	void __iomem *base = gic_data.dist_base;

	/* Disable the distributor */
	writel_relaxed(0, base + GICD_CTLR);
	gic_dist_wait_for_rwp();

	gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);

	/* Enable distributor with ARE, Group1 */
	writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
		       base + GICD_CTLR);

	/*
	 * Set all global interrupts to the boot CPU only. ARE must be
	 * enabled.
	 */
	affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
	for (i = 32; i < gic_data.irq_nr; i++)
		writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
}

static int gic_populate_rdist(void)
{
	u64 mpidr = cpu_logical_map(smp_processor_id());
	u64 typer;
	u32 aff;
	int i;

	/*
	 * Convert affinity to a 32bit value that can be matched to
	 * GICR_TYPER bits [63:32].
	 */
	aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
	       MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
	       MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
	       MPIDR_AFFINITY_LEVEL(mpidr, 0));

	for (i = 0; i < gic_data.redist_regions; i++) {
		void __iomem *ptr = gic_data.redist_base[i];
		u32 reg;

		reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
		if (reg != GIC_PIDR2_ARCH_GICv3 &&
		    reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
			pr_warn("No redistributor present @%p\n", ptr);
			break;
		}

		do {
			typer = readq_relaxed(ptr + GICR_TYPER);
			if ((typer >> 32) == aff) {
				gic_data_rdist_rd_base() = ptr;
				pr_info("CPU%d: found redistributor %llx @%p\n",
					smp_processor_id(),
					(unsigned long long)mpidr, ptr);
				return 0;
			}

			if (gic_data.redist_stride) {
				ptr += gic_data.redist_stride;
			} else {
				ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
				if (typer & GICR_TYPER_VLPIS)
					ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
			}
		} while (!(typer & GICR_TYPER_LAST));
	}

	/* We couldn't even deal with ourselves... */
	WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
	     smp_processor_id(), (unsigned long long)mpidr);
	return -ENODEV;
}

static void gic_cpu_init(void)
{
	void __iomem *rbase;

	/* Register ourselves with the rest of the world */
	if (gic_populate_rdist())
		return;

	gic_enable_redist(true);

	rbase = gic_data_rdist_sgi_base();

	gic_cpu_config(rbase, gic_redist_wait_for_rwp);

	/* Enable system registers */
	gic_enable_sre();

	/* Set priority mask register */
	gic_write_pmr(DEFAULT_PMR_VALUE);

	/* EOI deactivates interrupt too (mode 0) */
	gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);

	/* ... and let's hit the road... */
	gic_write_grpen1(1);
}

#ifdef CONFIG_SMP
static int gic_secondary_init(struct notifier_block *nfb,
			      unsigned long action, void *hcpu)
{
	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
		gic_cpu_init();
	return NOTIFY_OK;
}

/*
 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
 * priority because the GIC needs to be up before the ARM generic timers.
 */
static struct notifier_block gic_cpu_notifier = {
	.notifier_call = gic_secondary_init,
	.priority = 100,
};

static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
				   u64 cluster_id)
{
	int cpu = *base_cpu;
	u64 mpidr = cpu_logical_map(cpu);
	u16 tlist = 0;

	while (cpu < nr_cpu_ids) {
		/*
		 * If we ever get a cluster of more than 16 CPUs, just
		 * scream and skip that CPU.
		 */
		if (WARN_ON((mpidr & 0xff) >= 16))
			goto out;

		tlist |= 1 << (mpidr & 0xf);

		cpu = cpumask_next(cpu, mask);
		if (cpu == nr_cpu_ids)
			goto out;

		mpidr = cpu_logical_map(cpu);

		if (cluster_id != (mpidr & ~0xffUL)) {
			cpu--;
			goto out;
		}
	}
out:
	*base_cpu = cpu;
	return tlist;
}

static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
{
	u64 val;

	val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48	|
	       MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32	|
	       irq << 24			    		|
	       MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16	|
	       tlist);

	pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
	gic_write_sgi1r(val);
}

static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
{
	int cpu;

	if (WARN_ON(irq >= 16))
		return;

	/*
	 * Ensure that stores to Normal memory are visible to the
	 * other CPUs before issuing the IPI.
	 */
	smp_wmb();

	for_each_cpu_mask(cpu, *mask) {
		u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL;
		u16 tlist;

		tlist = gic_compute_target_list(&cpu, mask, cluster_id);
		gic_send_sgi(cluster_id, tlist, irq);
	}

	/* Force the above writes to ICC_SGI1R_EL1 to be executed */
	isb();
}

static void gic_smp_init(void)
{
	set_smp_cross_call(gic_raise_softirq);
	register_cpu_notifier(&gic_cpu_notifier);
}

static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
			    bool force)
{
	unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
	void __iomem *reg;
	int enabled;
	u64 val;

	if (gic_irq_in_rdist(d))
		return -EINVAL;

	/* If interrupt was enabled, disable it first */
	enabled = gic_peek_irq(d, GICD_ISENABLER);
	if (enabled)
		gic_mask_irq(d);

	reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
	val = gic_mpidr_to_affinity(cpu_logical_map(cpu));

	writeq_relaxed(val, reg);

	/*
	 * If the interrupt was enabled, enabled it again. Otherwise,
	 * just wait for the distributor to have digested our changes.
	 */
	if (enabled)
		gic_unmask_irq(d);
	else
		gic_dist_wait_for_rwp();

	return IRQ_SET_MASK_OK;
}
#else
#define gic_set_affinity	NULL
#define gic_smp_init()		do { } while(0)
#endif

static struct irq_chip gic_chip = {
	.name			= "GICv3",
	.irq_mask		= gic_mask_irq,
	.irq_unmask		= gic_unmask_irq,
	.irq_eoi		= gic_eoi_irq,
	.irq_set_type		= gic_set_type,
	.irq_set_affinity	= gic_set_affinity,
};

static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
			      irq_hw_number_t hw)
{
	/* SGIs are private to the core kernel */
	if (hw < 16)
		return -EPERM;
	/* PPIs */
	if (hw < 32) {
		irq_set_percpu_devid(irq);
		irq_set_chip_and_handler(irq, &gic_chip,
					 handle_percpu_devid_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
	}
	/* SPIs */
	if (hw >= 32 && hw < gic_data.irq_nr) {
		irq_set_chip_and_handler(irq, &gic_chip,
					 handle_fasteoi_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}
	irq_set_chip_data(irq, d->host_data);
	return 0;
}

static int gic_irq_domain_xlate(struct irq_domain *d,
				struct device_node *controller,
				const u32 *intspec, unsigned int intsize,
				unsigned long *out_hwirq, unsigned int *out_type)
{
	if (d->of_node != controller)
		return -EINVAL;
	if (intsize < 3)
		return -EINVAL;

	switch(intspec[0]) {
	case 0:			/* SPI */
		*out_hwirq = intspec[1] + 32;
		break;
	case 1:			/* PPI */
		*out_hwirq = intspec[1] + 16;
		break;
	default:
		return -EINVAL;
	}

	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
	return 0;
}

static const struct irq_domain_ops gic_irq_domain_ops = {
	.map = gic_irq_domain_map,
	.xlate = gic_irq_domain_xlate,
};

static int __init gic_of_init(struct device_node *node, struct device_node *parent)
{
	void __iomem *dist_base;
	void __iomem **redist_base;
	u64 redist_stride;
	u32 redist_regions;
	u32 reg;
	int gic_irqs;
	int err;
	int i;

	dist_base = of_iomap(node, 0);
	if (!dist_base) {
		pr_err("%s: unable to map gic dist registers\n",
			node->full_name);
		return -ENXIO;
	}

	reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
	if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
		pr_err("%s: no distributor detected, giving up\n",
			node->full_name);
		err = -ENODEV;
		goto out_unmap_dist;
	}

	if (of_property_read_u32(node, "#redistributor-regions", &redist_regions))
		redist_regions = 1;

	redist_base = kzalloc(sizeof(*redist_base) * redist_regions, GFP_KERNEL);
	if (!redist_base) {
		err = -ENOMEM;
		goto out_unmap_dist;
	}

	for (i = 0; i < redist_regions; i++) {
		redist_base[i] = of_iomap(node, 1 + i);
		if (!redist_base[i]) {
			pr_err("%s: couldn't map region %d\n",
			       node->full_name, i);
			err = -ENODEV;
			goto out_unmap_rdist;
		}
	}

	if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
		redist_stride = 0;

	gic_data.dist_base = dist_base;
	gic_data.redist_base = redist_base;
	gic_data.redist_regions = redist_regions;
	gic_data.redist_stride = redist_stride;

	/*
	 * Find out how many interrupts are supported.
	 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
	 */
	gic_irqs = readl_relaxed(gic_data.dist_base + GICD_TYPER) & 0x1f;
	gic_irqs = (gic_irqs + 1) * 32;
	if (gic_irqs > 1020)
		gic_irqs = 1020;
	gic_data.irq_nr = gic_irqs;

	gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
					      &gic_data);
	gic_data.rdist = alloc_percpu(typeof(*gic_data.rdist));

	if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdist)) {
		err = -ENOMEM;
		goto out_free;
	}

	set_handle_irq(gic_handle_irq);

	gic_smp_init();
	gic_dist_init();
	gic_cpu_init();

	return 0;

out_free:
	if (gic_data.domain)
		irq_domain_remove(gic_data.domain);
	free_percpu(gic_data.rdist);
out_unmap_rdist:
	for (i = 0; i < redist_regions; i++)
		if (redist_base[i])
			iounmap(redist_base[i]);
	kfree(redist_base);
out_unmap_dist:
	iounmap(dist_base);
	return err;
}

IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
Commit	Line	Data
021f6537 MZ	1	/*
	2	* Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#include <linux/cpu.h>
	19	#include <linux/delay.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/of.h>
	22	#include <linux/of_address.h>
	23	#include <linux/of_irq.h>
	24	#include <linux/percpu.h>
	25	#include <linux/slab.h>
	26
	27	#include <linux/irqchip/arm-gic-v3.h>
	28
	29	#include <asm/cputype.h>
	30	#include <asm/exception.h>
	31	#include <asm/smp_plat.h>
	32
	33	#include "irq-gic-common.h"
	34	#include "irqchip.h"
	35
	36	struct gic_chip_data {
	37	void __iomem *dist_base;
	38	void __iomem **redist_base;
	39	void __percpu __iomem **rdist;
	40	struct irq_domain *domain;
	41	u64 redist_stride;
	42	u32 redist_regions;
	43	unsigned int irq_nr;
	44	};
	45
	46	static struct gic_chip_data gic_data __read_mostly;
	47
	48	#define gic_data_rdist() (this_cpu_ptr(gic_data.rdist))
	49	#define gic_data_rdist_rd_base() (*gic_data_rdist())
	50	#define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
	51
	52	/* Our default, arbitrary priority value. Linux only uses one anyway. */
	53	#define DEFAULT_PMR_VALUE 0xf0
	54
	55	static inline unsigned int gic_irq(struct irq_data *d)
	56	{
	57	return d->hwirq;
	58	}
	59
	60	static inline int gic_irq_in_rdist(struct irq_data *d)
	61	{
	62	return gic_irq(d) < 32;
	63	}
	64
65	static inline void __iomem gic_dist_base(struct irq_data d)
66	{
67	if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
68	return gic_data_rdist_sgi_base();
69
70	if (d->hwirq <= 1023) /* SPI -> dist_base */
71	return gic_data.dist_base;
72
73	if (d->hwirq >= 8192)
74	BUG(); /* LPI Detected!!! */
75
76	return NULL;
77	}
78
79	static void gic_do_wait_for_rwp(void __iomem *base)
80	{
81	u32 count = 1000000; /* 1s! */
82
83	while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
84	count--;
85	if (!count) {
86	pr_err_ratelimited("RWP timeout, gone fishing\n");
87	return;
88	}
89	cpu_relax();
90	udelay(1);
91	};
92	}
93
94	/* Wait for completion of a distributor change */
95	static void gic_dist_wait_for_rwp(void)
96	{
97	gic_do_wait_for_rwp(gic_data.dist_base);
98	}
99
100	/* Wait for completion of a redistributor change */
101	static void gic_redist_wait_for_rwp(void)
102	{
103	gic_do_wait_for_rwp(gic_data_rdist_rd_base());
104	}
105
106	/* Low level accessors */
107	static u64 gic_read_iar(void)
108	{
109	u64 irqstat;
110
72c58395	111	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
021f6537 MZ	112	return irqstat;
	113	}
	114
	115	static void gic_write_pmr(u64 val)
	116	{
72c58395	117	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
021f6537 MZ	118	}
	119
	120	static void gic_write_ctlr(u64 val)
	121	{
72c58395	122	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
021f6537 MZ	123	isb();
	124	}
	125
	126	static void gic_write_grpen1(u64 val)
	127	{
72c58395	128	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
021f6537 MZ	129	isb();
	130	}
	131
	132	static void gic_write_sgi1r(u64 val)
	133	{
72c58395	134	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
021f6537 MZ	135	}
	136
	137	static void gic_enable_sre(void)
	138	{
	139	u64 val;
	140
72c58395	141	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
021f6537	142	val \|= ICC_SRE_EL1_SRE;
72c58395	143	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
021f6537 MZ	144	isb();
	145
	146	/*
	147	* Need to check that the SRE bit has actually been set. If
	148	* not, it means that SRE is disabled at EL2. We're going to
	149	* die painfully, and there is nothing we can do about it.
	150	*
	151	* Kindly inform the luser.
	152	*/
72c58395	153	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
021f6537 MZ	154	if (!(val & ICC_SRE_EL1_SRE))
	155	pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
	156	}
	157
a2c22510	158	static void gic_enable_redist(bool enable)
021f6537 MZ	159	{
	160	void __iomem *rbase;
	161	u32 count = 1000000; /* 1s! */
	162	u32 val;
	163
	164	rbase = gic_data_rdist_rd_base();
	165
021f6537	166	val = readl_relaxed(rbase + GICR_WAKER);
a2c22510 SH	167	if (enable)
	168	/* Wake up this CPU redistributor */
	169	val &= ~GICR_WAKER_ProcessorSleep;
	170	else
	171	val \|= GICR_WAKER_ProcessorSleep;
021f6537 MZ	172	writel_relaxed(val, rbase + GICR_WAKER);
021f6537 MZ	173
a2c22510 SH	174	if (!enable) { /* Check that GICR_WAKER is writeable */
	175	val = readl_relaxed(rbase + GICR_WAKER);
	176	if (!(val & GICR_WAKER_ProcessorSleep))
	177	return; /* No PM support in this redistributor */
	178	}
	179
	180	while (count--) {
	181	val = readl_relaxed(rbase + GICR_WAKER);
	182	if (enable ^ (val & GICR_WAKER_ChildrenAsleep))
	183	break;
021f6537 MZ	184	cpu_relax();
	185	udelay(1);
	186	};
a2c22510 SH	187	if (!count)
	188	pr_err_ratelimited("redistributor failed to %s...\n",
	189	enable ? "wakeup" : "sleep");
021f6537 MZ	190	}
	191
	192	/*
	193	* Routines to disable, enable, EOI and route interrupts
	194	*/
	195	static void gic_poke_irq(struct irq_data *d, u32 offset)
	196	{
	197	u32 mask = 1 << (gic_irq(d) % 32);
	198	void (*rwp_wait)(void);
	199	void __iomem *base;
	200
	201	if (gic_irq_in_rdist(d)) {
	202	base = gic_data_rdist_sgi_base();
	203	rwp_wait = gic_redist_wait_for_rwp;
	204	} else {
	205	base = gic_data.dist_base;
	206	rwp_wait = gic_dist_wait_for_rwp;
	207	}
	208
	209	writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
	210	rwp_wait();
	211	}
	212
	213	static int gic_peek_irq(struct irq_data *d, u32 offset)
	214	{
	215	u32 mask = 1 << (gic_irq(d) % 32);
	216	void __iomem *base;
	217
	218	if (gic_irq_in_rdist(d))
	219	base = gic_data_rdist_sgi_base();
	220	else
	221	base = gic_data.dist_base;
	222
	223	return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
	224	}
	225
	226	static void gic_mask_irq(struct irq_data *d)
	227	{
	228	gic_poke_irq(d, GICD_ICENABLER);
	229	}
	230
	231	static void gic_unmask_irq(struct irq_data *d)
	232	{
	233	gic_poke_irq(d, GICD_ISENABLER);
	234	}
	235
	236	static void gic_eoi_irq(struct irq_data *d)
	237	{
	238	gic_write_eoir(gic_irq(d));
	239	}
	240
	241	static int gic_set_type(struct irq_data *d, unsigned int type)
	242	{
	243	unsigned int irq = gic_irq(d);
	244	void (*rwp_wait)(void);
	245	void __iomem *base;
	246
	247	/* Interrupt configuration for SGIs can't be changed */
	248	if (irq < 16)
	249	return -EINVAL;
	250
	251	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
	252	return -EINVAL;
	253
254	if (gic_irq_in_rdist(d)) {
255	base = gic_data_rdist_sgi_base();
256	rwp_wait = gic_redist_wait_for_rwp;
257	} else {
258	base = gic_data.dist_base;
259	rwp_wait = gic_dist_wait_for_rwp;
260	}
261
262	gic_configure_irq(irq, type, base, rwp_wait);
263
264	return 0;
265	}
266
267	static u64 gic_mpidr_to_affinity(u64 mpidr)
268	{
269	u64 aff;
270
271	aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 \|
272	MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 \|
273	MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 \|
274	MPIDR_AFFINITY_LEVEL(mpidr, 0));
275
276	return aff;
277	}
278
279	static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
280	{
281	u64 irqnr;
282
283	do {
284	irqnr = gic_read_iar();
285
286	if (likely(irqnr > 15 && irqnr < 1020)) {
287	u64 irq = irq_find_mapping(gic_data.domain, irqnr);
288	if (likely(irq)) {
289	handle_IRQ(irq, regs);
290	continue;
291	}
292
293	WARN_ONCE(true, "Unexpected SPI received!\n");
294	gic_write_eoir(irqnr);
295	}
296	if (irqnr < 16) {
297	gic_write_eoir(irqnr);
298	#ifdef CONFIG_SMP
299	handle_IPI(irqnr, regs);
300	#else
301	WARN_ONCE(true, "Unexpected SGI received!\n");
302	#endif
303	continue;
304	}
305	} while (irqnr != ICC_IAR1_EL1_SPURIOUS);
306	}
307
308	static void __init gic_dist_init(void)
309	{
310	unsigned int i;
311	u64 affinity;
312	void __iomem *base = gic_data.dist_base;
313
314	/* Disable the distributor */
315	writel_relaxed(0, base + GICD_CTLR);
316	gic_dist_wait_for_rwp();
317
318	gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
319
320	/* Enable distributor with ARE, Group1 */
321	writel_relaxed(GICD_CTLR_ARE_NS \| GICD_CTLR_ENABLE_G1A \| GICD_CTLR_ENABLE_G1,
322	base + GICD_CTLR);
323
324	/*
325	* Set all global interrupts to the boot CPU only. ARE must be
326	* enabled.
327	*/
328	affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
329	for (i = 32; i < gic_data.irq_nr; i++)
330	writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
331	}
332
333	static int gic_populate_rdist(void)
334	{
335	u64 mpidr = cpu_logical_map(smp_processor_id());
336	u64 typer;
337	u32 aff;
338	int i;
339
340	/*
341	* Convert affinity to a 32bit value that can be matched to
342	* GICR_TYPER bits [63:32].
343	*/
344	aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 \|
345	MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 \|
346	MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 \|
347	MPIDR_AFFINITY_LEVEL(mpidr, 0));
348
349	for (i = 0; i < gic_data.redist_regions; i++) {
350	void __iomem *ptr = gic_data.redist_base[i];
351	u32 reg;
352
353	reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
354	if (reg != GIC_PIDR2_ARCH_GICv3 &&
355	reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
356	pr_warn("No redistributor present @%p\n", ptr);
357	break;
358	}
359
360	do {
361	typer = readq_relaxed(ptr + GICR_TYPER);
362	if ((typer >> 32) == aff) {
363	gic_data_rdist_rd_base() = ptr;
364	pr_info("CPU%d: found redistributor %llx @%p\n",
365	smp_processor_id(),
366	(unsigned long long)mpidr, ptr);
367	return 0;
368	}
369
370	if (gic_data.redist_stride) {
371	ptr += gic_data.redist_stride;
372	} else {
373	ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
374	if (typer & GICR_TYPER_VLPIS)
375	ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
376	}
377	} while (!(typer & GICR_TYPER_LAST));
378	}
379
380	/* We couldn't even deal with ourselves... */
381	WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
382	smp_processor_id(), (unsigned long long)mpidr);
383	return -ENODEV;
384	}
385
386	static void gic_cpu_init(void)
387	{
388	void __iomem *rbase;
389
390	/* Register ourselves with the rest of the world */
391	if (gic_populate_rdist())
392	return;
393
a2c22510	394	gic_enable_redist(true);
021f6537 MZ	395
	396	rbase = gic_data_rdist_sgi_base();
	397
	398	gic_cpu_config(rbase, gic_redist_wait_for_rwp);
	399
	400	/* Enable system registers */
	401	gic_enable_sre();
	402
	403	/* Set priority mask register */
	404	gic_write_pmr(DEFAULT_PMR_VALUE);
	405
	406	/* EOI deactivates interrupt too (mode 0) */
	407	gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
	408
	409	/* ... and let's hit the road... */
	410	gic_write_grpen1(1);
	411	}
	412
	413	#ifdef CONFIG_SMP
	414	static int gic_secondary_init(struct notifier_block *nfb,
	415	unsigned long action, void *hcpu)
	416	{
	417	if (action == CPU_STARTING \|\| action == CPU_STARTING_FROZEN)
	418	gic_cpu_init();
	419	return NOTIFY_OK;
	420	}
	421
	422	/*
	423	* Notifier for enabling the GIC CPU interface. Set an arbitrarily high
	424	* priority because the GIC needs to be up before the ARM generic timers.
	425	*/
	426	static struct notifier_block gic_cpu_notifier = {
	427	.notifier_call = gic_secondary_init,
	428	.priority = 100,
	429	};
	430
	431	static u16 gic_compute_target_list(int base_cpu, const struct cpumask mask,
	432	u64 cluster_id)
	433	{
	434	int cpu = *base_cpu;
	435	u64 mpidr = cpu_logical_map(cpu);
	436	u16 tlist = 0;
	437
	438	while (cpu < nr_cpu_ids) {
	439	/*
	440	* If we ever get a cluster of more than 16 CPUs, just
	441	* scream and skip that CPU.
	442	*/
	443	if (WARN_ON((mpidr & 0xff) >= 16))
	444	goto out;
	445
	446	tlist \|= 1 << (mpidr & 0xf);
	447
	448	cpu = cpumask_next(cpu, mask);
	449	if (cpu == nr_cpu_ids)
	450	goto out;
	451
	452	mpidr = cpu_logical_map(cpu);
	453
	454	if (cluster_id != (mpidr & ~0xffUL)) {
	455	cpu--;
	456	goto out;
	457	}
	458	}
459	out:
460	*base_cpu = cpu;
461	return tlist;
462	}
463
464	static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
465	{
466	u64 val;
467
468	val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 \|
469	MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32 \|
470	irq << 24 \|
471	MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16 \|
472	tlist);
473
474	pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
475	gic_write_sgi1r(val);
476	}
477
478	static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
479	{
480	int cpu;
481
482	if (WARN_ON(irq >= 16))
483	return;
484
485	/*
486	* Ensure that stores to Normal memory are visible to the
487	* other CPUs before issuing the IPI.
488	*/
489	smp_wmb();
490
491	for_each_cpu_mask(cpu, *mask) {
492	u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL;
493	u16 tlist;
494
495	tlist = gic_compute_target_list(&cpu, mask, cluster_id);
496	gic_send_sgi(cluster_id, tlist, irq);
497	}
498
499	/* Force the above writes to ICC_SGI1R_EL1 to be executed */
500	isb();
501	}
502
503	static void gic_smp_init(void)
504	{
505	set_smp_cross_call(gic_raise_softirq);
506	register_cpu_notifier(&gic_cpu_notifier);
507	}
508
509	static int gic_set_affinity(struct irq_data d, const struct cpumask mask_val,
510	bool force)
511	{
512	unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
513	void __iomem *reg;
514	int enabled;
515	u64 val;
516
517	if (gic_irq_in_rdist(d))
518	return -EINVAL;
519
520	/* If interrupt was enabled, disable it first */
521	enabled = gic_peek_irq(d, GICD_ISENABLER);
522	if (enabled)
523	gic_mask_irq(d);
524
525	reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
526	val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
527
528	writeq_relaxed(val, reg);
529
530	/*
531	* If the interrupt was enabled, enabled it again. Otherwise,
532	* just wait for the distributor to have digested our changes.
533	*/
534	if (enabled)
535	gic_unmask_irq(d);
536	else
537	gic_dist_wait_for_rwp();
538
539	return IRQ_SET_MASK_OK;
540	}
541	#else
542	#define gic_set_affinity NULL
543	#define gic_smp_init() do { } while(0)
544	#endif
545
546	static struct irq_chip gic_chip = {
547	.name = "GICv3",
548	.irq_mask = gic_mask_irq,
549	.irq_unmask = gic_unmask_irq,
550	.irq_eoi = gic_eoi_irq,
551	.irq_set_type = gic_set_type,
552	.irq_set_affinity = gic_set_affinity,
553	};
554
555	static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
556	irq_hw_number_t hw)
557	{
558	/* SGIs are private to the core kernel */
559	if (hw < 16)
560	return -EPERM;
561	/* PPIs */
562	if (hw < 32) {
563	irq_set_percpu_devid(irq);
564	irq_set_chip_and_handler(irq, &gic_chip,
565	handle_percpu_devid_irq);
566	set_irq_flags(irq, IRQF_VALID \| IRQF_NOAUTOEN);
567	}
568	/* SPIs */
569	if (hw >= 32 && hw < gic_data.irq_nr) {
570	irq_set_chip_and_handler(irq, &gic_chip,
571	handle_fasteoi_irq);
572	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
573	}
574	irq_set_chip_data(irq, d->host_data);
575	return 0;
576	}
577
578	static int gic_irq_domain_xlate(struct irq_domain *d,
579	struct device_node *controller,
580	const u32 *intspec, unsigned int intsize,
581	unsigned long out_hwirq, unsigned int out_type)
582	{
583	if (d->of_node != controller)
584	return -EINVAL;
585	if (intsize < 3)
586	return -EINVAL;
587
588	switch(intspec[0]) {
589	case 0: /* SPI */
590	*out_hwirq = intspec[1] + 32;
591	break;
592	case 1: /* PPI */
593	*out_hwirq = intspec[1] + 16;
594	break;
595	default:
596	return -EINVAL;
597	}
598
599	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
600	return 0;
601	}
602
603	static const struct irq_domain_ops gic_irq_domain_ops = {
604	.map = gic_irq_domain_map,
605	.xlate = gic_irq_domain_xlate,
606	};
607
608	static int __init gic_of_init(struct device_node node, struct device_node parent)
609	{
610	void __iomem *dist_base;
611	void __iomem **redist_base;
612	u64 redist_stride;
613	u32 redist_regions;
614	u32 reg;
615	int gic_irqs;
616	int err;
617	int i;
618
619	dist_base = of_iomap(node, 0);
620	if (!dist_base) {
621	pr_err("%s: unable to map gic dist registers\n",
622	node->full_name);
623	return -ENXIO;
624	}
625
626	reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
627	if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
628	pr_err("%s: no distributor detected, giving up\n",
629	node->full_name);
630	err = -ENODEV;
631	goto out_unmap_dist;
632	}
633
634	if (of_property_read_u32(node, "#redistributor-regions", &redist_regions))
635	redist_regions = 1;
636
637	redist_base = kzalloc(sizeof(redist_base) redist_regions, GFP_KERNEL);
638	if (!redist_base) {
639	err = -ENOMEM;
640	goto out_unmap_dist;
641	}
642
643	for (i = 0; i < redist_regions; i++) {
644	redist_base[i] = of_iomap(node, 1 + i);
645	if (!redist_base[i]) {
646	pr_err("%s: couldn't map region %d\n",
647	node->full_name, i);
648	err = -ENODEV;
649	goto out_unmap_rdist;
650	}
651	}
652
653	if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
654	redist_stride = 0;
655
656	gic_data.dist_base = dist_base;
657	gic_data.redist_base = redist_base;
658	gic_data.redist_regions = redist_regions;
659	gic_data.redist_stride = redist_stride;
660
661	/*
662	* Find out how many interrupts are supported.
663	* The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
664	*/
665	gic_irqs = readl_relaxed(gic_data.dist_base + GICD_TYPER) & 0x1f;
666	gic_irqs = (gic_irqs + 1) * 32;
667	if (gic_irqs > 1020)
668	gic_irqs = 1020;
669	gic_data.irq_nr = gic_irqs;
670
671	gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
672	&gic_data);
673	gic_data.rdist = alloc_percpu(typeof(*gic_data.rdist));
674
675	if (WARN_ON(!gic_data.domain) \|\| WARN_ON(!gic_data.rdist)) {
676	err = -ENOMEM;
677	goto out_free;
678	}
679
680	set_handle_irq(gic_handle_irq);
681
682	gic_smp_init();
683	gic_dist_init();
684	gic_cpu_init();
685
686	return 0;
687
688	out_free:
689	if (gic_data.domain)
690	irq_domain_remove(gic_data.domain);
691	free_percpu(gic_data.rdist);
692	out_unmap_rdist:
693	for (i = 0; i < redist_regions; i++)
694	if (redist_base[i])
695	iounmap(redist_base[i]);
696	kfree(redist_base);
697	out_unmap_dist:
698	iounmap(dist_base);
699	return err;
700	}
701
702	IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);