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021f6537 | 1 | /* |
0edc23ea | 2 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
021f6537 MZ |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
68628bb8 JG |
18 | #define pr_fmt(fmt) "GICv3: " fmt |
19 | ||
ffa7d616 | 20 | #include <linux/acpi.h> |
021f6537 | 21 | #include <linux/cpu.h> |
3708d52f | 22 | #include <linux/cpu_pm.h> |
021f6537 MZ |
23 | #include <linux/delay.h> |
24 | #include <linux/interrupt.h> | |
ffa7d616 | 25 | #include <linux/irqdomain.h> |
021f6537 MZ |
26 | #include <linux/of.h> |
27 | #include <linux/of_address.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/percpu.h> | |
30 | #include <linux/slab.h> | |
31 | ||
41a83e06 | 32 | #include <linux/irqchip.h> |
1839e576 | 33 | #include <linux/irqchip/arm-gic-common.h> |
021f6537 | 34 | #include <linux/irqchip/arm-gic-v3.h> |
e3825ba1 | 35 | #include <linux/irqchip/irq-partition-percpu.h> |
021f6537 MZ |
36 | |
37 | #include <asm/cputype.h> | |
38 | #include <asm/exception.h> | |
39 | #include <asm/smp_plat.h> | |
0b6a3da9 | 40 | #include <asm/virt.h> |
021f6537 MZ |
41 | |
42 | #include "irq-gic-common.h" | |
021f6537 | 43 | |
f5c1434c MZ |
44 | struct redist_region { |
45 | void __iomem *redist_base; | |
46 | phys_addr_t phys_base; | |
b70fb7af | 47 | bool single_redist; |
f5c1434c MZ |
48 | }; |
49 | ||
021f6537 | 50 | struct gic_chip_data { |
e3825ba1 | 51 | struct fwnode_handle *fwnode; |
021f6537 | 52 | void __iomem *dist_base; |
f5c1434c MZ |
53 | struct redist_region *redist_regions; |
54 | struct rdists rdists; | |
021f6537 MZ |
55 | struct irq_domain *domain; |
56 | u64 redist_stride; | |
f5c1434c | 57 | u32 nr_redist_regions; |
eda0d04a | 58 | bool has_rss; |
021f6537 | 59 | unsigned int irq_nr; |
e3825ba1 | 60 | struct partition_desc *ppi_descs[16]; |
021f6537 MZ |
61 | }; |
62 | ||
63 | static struct gic_chip_data gic_data __read_mostly; | |
0b6a3da9 | 64 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
021f6537 | 65 | |
1839e576 | 66 | static struct gic_kvm_info gic_v3_kvm_info; |
eda0d04a | 67 | static DEFINE_PER_CPU(bool, has_rss); |
1839e576 | 68 | |
eda0d04a | 69 | #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) |
f5c1434c MZ |
70 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
71 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
72 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
73 | ||
74 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
75 | #define DEFAULT_PMR_VALUE 0xf0 | |
76 | ||
77 | static inline unsigned int gic_irq(struct irq_data *d) | |
78 | { | |
79 | return d->hwirq; | |
80 | } | |
81 | ||
82 | static inline int gic_irq_in_rdist(struct irq_data *d) | |
83 | { | |
84 | return gic_irq(d) < 32; | |
85 | } | |
86 | ||
87 | static inline void __iomem *gic_dist_base(struct irq_data *d) | |
88 | { | |
89 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ | |
90 | return gic_data_rdist_sgi_base(); | |
91 | ||
92 | if (d->hwirq <= 1023) /* SPI -> dist_base */ | |
93 | return gic_data.dist_base; | |
94 | ||
021f6537 MZ |
95 | return NULL; |
96 | } | |
97 | ||
98 | static void gic_do_wait_for_rwp(void __iomem *base) | |
99 | { | |
100 | u32 count = 1000000; /* 1s! */ | |
101 | ||
102 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { | |
103 | count--; | |
104 | if (!count) { | |
105 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
106 | return; | |
107 | } | |
108 | cpu_relax(); | |
109 | udelay(1); | |
110 | }; | |
111 | } | |
112 | ||
113 | /* Wait for completion of a distributor change */ | |
114 | static void gic_dist_wait_for_rwp(void) | |
115 | { | |
116 | gic_do_wait_for_rwp(gic_data.dist_base); | |
117 | } | |
118 | ||
119 | /* Wait for completion of a redistributor change */ | |
120 | static void gic_redist_wait_for_rwp(void) | |
121 | { | |
122 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); | |
123 | } | |
124 | ||
7936e914 | 125 | #ifdef CONFIG_ARM64 |
6d4e11c5 RR |
126 | |
127 | static u64 __maybe_unused gic_read_iar(void) | |
128 | { | |
a4023f68 | 129 | if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
6d4e11c5 RR |
130 | return gic_read_iar_cavium_thunderx(); |
131 | else | |
132 | return gic_read_iar_common(); | |
133 | } | |
7936e914 | 134 | #endif |
021f6537 | 135 | |
a2c22510 | 136 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
137 | { |
138 | void __iomem *rbase; | |
139 | u32 count = 1000000; /* 1s! */ | |
140 | u32 val; | |
141 | ||
142 | rbase = gic_data_rdist_rd_base(); | |
143 | ||
021f6537 | 144 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
145 | if (enable) |
146 | /* Wake up this CPU redistributor */ | |
147 | val &= ~GICR_WAKER_ProcessorSleep; | |
148 | else | |
149 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
150 | writel_relaxed(val, rbase + GICR_WAKER); |
151 | ||
a2c22510 SH |
152 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
153 | val = readl_relaxed(rbase + GICR_WAKER); | |
154 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
155 | return; /* No PM support in this redistributor */ | |
156 | } | |
157 | ||
d102eb5c | 158 | while (--count) { |
a2c22510 | 159 | val = readl_relaxed(rbase + GICR_WAKER); |
cf1d9d11 | 160 | if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) |
a2c22510 | 161 | break; |
021f6537 MZ |
162 | cpu_relax(); |
163 | udelay(1); | |
164 | }; | |
a2c22510 SH |
165 | if (!count) |
166 | pr_err_ratelimited("redistributor failed to %s...\n", | |
167 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
168 | } |
169 | ||
170 | /* | |
171 | * Routines to disable, enable, EOI and route interrupts | |
172 | */ | |
b594c6e2 MZ |
173 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
174 | { | |
175 | u32 mask = 1 << (gic_irq(d) % 32); | |
176 | void __iomem *base; | |
177 | ||
178 | if (gic_irq_in_rdist(d)) | |
179 | base = gic_data_rdist_sgi_base(); | |
180 | else | |
181 | base = gic_data.dist_base; | |
182 | ||
183 | return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); | |
184 | } | |
185 | ||
021f6537 MZ |
186 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
187 | { | |
188 | u32 mask = 1 << (gic_irq(d) % 32); | |
189 | void (*rwp_wait)(void); | |
190 | void __iomem *base; | |
191 | ||
192 | if (gic_irq_in_rdist(d)) { | |
193 | base = gic_data_rdist_sgi_base(); | |
194 | rwp_wait = gic_redist_wait_for_rwp; | |
195 | } else { | |
196 | base = gic_data.dist_base; | |
197 | rwp_wait = gic_dist_wait_for_rwp; | |
198 | } | |
199 | ||
200 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); | |
201 | rwp_wait(); | |
202 | } | |
203 | ||
021f6537 MZ |
204 | static void gic_mask_irq(struct irq_data *d) |
205 | { | |
206 | gic_poke_irq(d, GICD_ICENABLER); | |
207 | } | |
208 | ||
0b6a3da9 MZ |
209 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
210 | { | |
211 | gic_mask_irq(d); | |
530bf353 MZ |
212 | /* |
213 | * When masking a forwarded interrupt, make sure it is | |
214 | * deactivated as well. | |
215 | * | |
216 | * This ensures that an interrupt that is getting | |
217 | * disabled/masked will not get "stuck", because there is | |
218 | * noone to deactivate it (guest is being terminated). | |
219 | */ | |
4df7f54d | 220 | if (irqd_is_forwarded_to_vcpu(d)) |
530bf353 | 221 | gic_poke_irq(d, GICD_ICACTIVER); |
0b6a3da9 MZ |
222 | } |
223 | ||
021f6537 MZ |
224 | static void gic_unmask_irq(struct irq_data *d) |
225 | { | |
226 | gic_poke_irq(d, GICD_ISENABLER); | |
227 | } | |
228 | ||
b594c6e2 MZ |
229 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
230 | enum irqchip_irq_state which, bool val) | |
231 | { | |
232 | u32 reg; | |
233 | ||
234 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
235 | return -EINVAL; | |
236 | ||
237 | switch (which) { | |
238 | case IRQCHIP_STATE_PENDING: | |
239 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
240 | break; | |
241 | ||
242 | case IRQCHIP_STATE_ACTIVE: | |
243 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
244 | break; | |
245 | ||
246 | case IRQCHIP_STATE_MASKED: | |
247 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; | |
248 | break; | |
249 | ||
250 | default: | |
251 | return -EINVAL; | |
252 | } | |
253 | ||
254 | gic_poke_irq(d, reg); | |
255 | return 0; | |
256 | } | |
257 | ||
258 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
259 | enum irqchip_irq_state which, bool *val) | |
260 | { | |
261 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
262 | return -EINVAL; | |
263 | ||
264 | switch (which) { | |
265 | case IRQCHIP_STATE_PENDING: | |
266 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
267 | break; | |
268 | ||
269 | case IRQCHIP_STATE_ACTIVE: | |
270 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
271 | break; | |
272 | ||
273 | case IRQCHIP_STATE_MASKED: | |
274 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
275 | break; | |
276 | ||
277 | default: | |
278 | return -EINVAL; | |
279 | } | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
021f6537 MZ |
284 | static void gic_eoi_irq(struct irq_data *d) |
285 | { | |
286 | gic_write_eoir(gic_irq(d)); | |
287 | } | |
288 | ||
0b6a3da9 MZ |
289 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
290 | { | |
291 | /* | |
530bf353 MZ |
292 | * No need to deactivate an LPI, or an interrupt that |
293 | * is is getting forwarded to a vcpu. | |
0b6a3da9 | 294 | */ |
4df7f54d | 295 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
0b6a3da9 MZ |
296 | return; |
297 | gic_write_dir(gic_irq(d)); | |
298 | } | |
299 | ||
021f6537 MZ |
300 | static int gic_set_type(struct irq_data *d, unsigned int type) |
301 | { | |
302 | unsigned int irq = gic_irq(d); | |
303 | void (*rwp_wait)(void); | |
304 | void __iomem *base; | |
305 | ||
306 | /* Interrupt configuration for SGIs can't be changed */ | |
307 | if (irq < 16) | |
308 | return -EINVAL; | |
309 | ||
fb7e7deb LD |
310 | /* SPIs have restrictions on the supported types */ |
311 | if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
312 | type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
313 | return -EINVAL; |
314 | ||
315 | if (gic_irq_in_rdist(d)) { | |
316 | base = gic_data_rdist_sgi_base(); | |
317 | rwp_wait = gic_redist_wait_for_rwp; | |
318 | } else { | |
319 | base = gic_data.dist_base; | |
320 | rwp_wait = gic_dist_wait_for_rwp; | |
321 | } | |
322 | ||
fb7e7deb | 323 | return gic_configure_irq(irq, type, base, rwp_wait); |
021f6537 MZ |
324 | } |
325 | ||
530bf353 MZ |
326 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
327 | { | |
4df7f54d TG |
328 | if (vcpu) |
329 | irqd_set_forwarded_to_vcpu(d); | |
330 | else | |
331 | irqd_clr_forwarded_to_vcpu(d); | |
530bf353 MZ |
332 | return 0; |
333 | } | |
334 | ||
f6c86a41 | 335 | static u64 gic_mpidr_to_affinity(unsigned long mpidr) |
021f6537 MZ |
336 | { |
337 | u64 aff; | |
338 | ||
f6c86a41 | 339 | aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
021f6537 MZ |
340 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
341 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
342 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
343 | ||
344 | return aff; | |
345 | } | |
346 | ||
347 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) | |
348 | { | |
f6c86a41 | 349 | u32 irqnr; |
021f6537 MZ |
350 | |
351 | do { | |
352 | irqnr = gic_read_iar(); | |
353 | ||
da33f31d | 354 | if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { |
ebc6de00 | 355 | int err; |
0b6a3da9 MZ |
356 | |
357 | if (static_key_true(&supports_deactivate)) | |
358 | gic_write_eoir(irqnr); | |
39a06b67 WD |
359 | else |
360 | isb(); | |
0b6a3da9 | 361 | |
ebc6de00 MZ |
362 | err = handle_domain_irq(gic_data.domain, irqnr, regs); |
363 | if (err) { | |
da33f31d | 364 | WARN_ONCE(true, "Unexpected interrupt received!\n"); |
0b6a3da9 MZ |
365 | if (static_key_true(&supports_deactivate)) { |
366 | if (irqnr < 8192) | |
367 | gic_write_dir(irqnr); | |
368 | } else { | |
369 | gic_write_eoir(irqnr); | |
370 | } | |
021f6537 | 371 | } |
ebc6de00 | 372 | continue; |
021f6537 MZ |
373 | } |
374 | if (irqnr < 16) { | |
375 | gic_write_eoir(irqnr); | |
0b6a3da9 MZ |
376 | if (static_key_true(&supports_deactivate)) |
377 | gic_write_dir(irqnr); | |
021f6537 | 378 | #ifdef CONFIG_SMP |
f86c4fbd WD |
379 | /* |
380 | * Unlike GICv2, we don't need an smp_rmb() here. | |
381 | * The control dependency from gic_read_iar to | |
382 | * the ISB in gic_write_eoir is enough to ensure | |
383 | * that any shared data read by handle_IPI will | |
384 | * be read after the ACK. | |
385 | */ | |
021f6537 MZ |
386 | handle_IPI(irqnr, regs); |
387 | #else | |
388 | WARN_ONCE(true, "Unexpected SGI received!\n"); | |
389 | #endif | |
390 | continue; | |
391 | } | |
392 | } while (irqnr != ICC_IAR1_EL1_SPURIOUS); | |
393 | } | |
394 | ||
395 | static void __init gic_dist_init(void) | |
396 | { | |
397 | unsigned int i; | |
398 | u64 affinity; | |
399 | void __iomem *base = gic_data.dist_base; | |
400 | ||
401 | /* Disable the distributor */ | |
402 | writel_relaxed(0, base + GICD_CTLR); | |
403 | gic_dist_wait_for_rwp(); | |
404 | ||
7c9b9730 MZ |
405 | /* |
406 | * Configure SPIs as non-secure Group-1. This will only matter | |
407 | * if the GIC only has a single security state. This will not | |
408 | * do the right thing if the kernel is running in secure mode, | |
409 | * but that's not the intended use case anyway. | |
410 | */ | |
411 | for (i = 32; i < gic_data.irq_nr; i += 32) | |
412 | writel_relaxed(~0, base + GICD_IGROUPR + i / 8); | |
413 | ||
021f6537 MZ |
414 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); |
415 | ||
416 | /* Enable distributor with ARE, Group1 */ | |
417 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, | |
418 | base + GICD_CTLR); | |
419 | ||
420 | /* | |
421 | * Set all global interrupts to the boot CPU only. ARE must be | |
422 | * enabled. | |
423 | */ | |
424 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); | |
425 | for (i = 32; i < gic_data.irq_nr; i++) | |
72c97126 | 426 | gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); |
021f6537 MZ |
427 | } |
428 | ||
0d94ded2 | 429 | static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *)) |
021f6537 | 430 | { |
0d94ded2 | 431 | int ret = -ENODEV; |
021f6537 MZ |
432 | int i; |
433 | ||
f5c1434c MZ |
434 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
435 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
0d94ded2 | 436 | u64 typer; |
021f6537 MZ |
437 | u32 reg; |
438 | ||
439 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
440 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
441 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
442 | pr_warn("No redistributor present @%p\n", ptr); | |
443 | break; | |
444 | } | |
445 | ||
446 | do { | |
72c97126 | 447 | typer = gic_read_typer(ptr + GICR_TYPER); |
0d94ded2 MZ |
448 | ret = fn(gic_data.redist_regions + i, ptr); |
449 | if (!ret) | |
021f6537 | 450 | return 0; |
021f6537 | 451 | |
b70fb7af TN |
452 | if (gic_data.redist_regions[i].single_redist) |
453 | break; | |
454 | ||
021f6537 MZ |
455 | if (gic_data.redist_stride) { |
456 | ptr += gic_data.redist_stride; | |
457 | } else { | |
458 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
459 | if (typer & GICR_TYPER_VLPIS) | |
460 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
461 | } | |
462 | } while (!(typer & GICR_TYPER_LAST)); | |
463 | } | |
464 | ||
0d94ded2 MZ |
465 | return ret ? -ENODEV : 0; |
466 | } | |
467 | ||
468 | static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) | |
469 | { | |
470 | unsigned long mpidr = cpu_logical_map(smp_processor_id()); | |
471 | u64 typer; | |
472 | u32 aff; | |
473 | ||
474 | /* | |
475 | * Convert affinity to a 32bit value that can be matched to | |
476 | * GICR_TYPER bits [63:32]. | |
477 | */ | |
478 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | | |
479 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
480 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
481 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
482 | ||
483 | typer = gic_read_typer(ptr + GICR_TYPER); | |
484 | if ((typer >> 32) == aff) { | |
485 | u64 offset = ptr - region->redist_base; | |
486 | gic_data_rdist_rd_base() = ptr; | |
487 | gic_data_rdist()->phys_base = region->phys_base + offset; | |
488 | ||
489 | pr_info("CPU%d: found redistributor %lx region %d:%pa\n", | |
490 | smp_processor_id(), mpidr, | |
491 | (int)(region - gic_data.redist_regions), | |
492 | &gic_data_rdist()->phys_base); | |
493 | return 0; | |
494 | } | |
495 | ||
496 | /* Try next one */ | |
497 | return 1; | |
498 | } | |
499 | ||
500 | static int gic_populate_rdist(void) | |
501 | { | |
502 | if (gic_iterate_rdists(__gic_populate_rdist) == 0) | |
503 | return 0; | |
504 | ||
021f6537 | 505 | /* We couldn't even deal with ourselves... */ |
f6c86a41 | 506 | WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", |
0d94ded2 MZ |
507 | smp_processor_id(), |
508 | (unsigned long)cpu_logical_map(smp_processor_id())); | |
021f6537 MZ |
509 | return -ENODEV; |
510 | } | |
511 | ||
0edc23ea MZ |
512 | static int __gic_update_vlpi_properties(struct redist_region *region, |
513 | void __iomem *ptr) | |
514 | { | |
515 | u64 typer = gic_read_typer(ptr + GICR_TYPER); | |
516 | gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS); | |
517 | gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS); | |
518 | ||
519 | return 1; | |
520 | } | |
521 | ||
522 | static void gic_update_vlpi_properties(void) | |
523 | { | |
524 | gic_iterate_rdists(__gic_update_vlpi_properties); | |
525 | pr_info("%sVLPI support, %sdirect LPI support\n", | |
526 | !gic_data.rdists.has_vlpis ? "no " : "", | |
527 | !gic_data.rdists.has_direct_lpi ? "no " : ""); | |
528 | } | |
529 | ||
3708d52f SH |
530 | static void gic_cpu_sys_reg_init(void) |
531 | { | |
eda0d04a SD |
532 | int i, cpu = smp_processor_id(); |
533 | u64 mpidr = cpu_logical_map(cpu); | |
534 | u64 need_rss = MPIDR_RS(mpidr); | |
d6062a6d | 535 | u32 val; |
eda0d04a | 536 | |
7cabd008 MZ |
537 | /* |
538 | * Need to check that the SRE bit has actually been set. If | |
539 | * not, it means that SRE is disabled at EL2. We're going to | |
540 | * die painfully, and there is nothing we can do about it. | |
541 | * | |
542 | * Kindly inform the luser. | |
543 | */ | |
544 | if (!gic_enable_sre()) | |
545 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
3708d52f SH |
546 | |
547 | /* Set priority mask register */ | |
548 | gic_write_pmr(DEFAULT_PMR_VALUE); | |
549 | ||
91ef8442 DT |
550 | /* |
551 | * Some firmwares hand over to the kernel with the BPR changed from | |
552 | * its reset value (and with a value large enough to prevent | |
553 | * any pre-emptive interrupts from working at all). Writing a zero | |
554 | * to BPR restores is reset value. | |
555 | */ | |
556 | gic_write_bpr1(0); | |
557 | ||
0b6a3da9 MZ |
558 | if (static_key_true(&supports_deactivate)) { |
559 | /* EOI drops priority only (mode 1) */ | |
560 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
561 | } else { | |
562 | /* EOI deactivates interrupt too (mode 0) */ | |
563 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
564 | } | |
3708d52f | 565 | |
d6062a6d MZ |
566 | val = gic_read_ctlr(); |
567 | val &= ICC_CTLR_EL1_PRI_BITS_MASK; | |
568 | val >>= ICC_CTLR_EL1_PRI_BITS_SHIFT; | |
569 | ||
570 | switch(val + 1) { | |
571 | case 8: | |
572 | case 7: | |
573 | write_gicreg(0, ICC_AP0R3_EL1); | |
574 | write_gicreg(0, ICC_AP1R3_EL1); | |
575 | write_gicreg(0, ICC_AP0R2_EL1); | |
576 | write_gicreg(0, ICC_AP1R2_EL1); | |
577 | case 6: | |
578 | write_gicreg(0, ICC_AP0R1_EL1); | |
579 | write_gicreg(0, ICC_AP1R1_EL1); | |
580 | case 5: | |
581 | case 4: | |
582 | write_gicreg(0, ICC_AP0R0_EL1); | |
583 | write_gicreg(0, ICC_AP1R0_EL1); | |
584 | } | |
585 | ||
586 | isb(); | |
587 | ||
3708d52f SH |
588 | /* ... and let's hit the road... */ |
589 | gic_write_grpen1(1); | |
eda0d04a SD |
590 | |
591 | /* Keep the RSS capability status in per_cpu variable */ | |
592 | per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS); | |
593 | ||
594 | /* Check all the CPUs have capable of sending SGIs to other CPUs */ | |
595 | for_each_online_cpu(i) { | |
596 | bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu); | |
597 | ||
598 | need_rss |= MPIDR_RS(cpu_logical_map(i)); | |
599 | if (need_rss && (!have_rss)) | |
600 | pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n", | |
601 | cpu, (unsigned long)mpidr, | |
602 | i, (unsigned long)cpu_logical_map(i)); | |
603 | } | |
604 | ||
605 | /** | |
606 | * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, | |
607 | * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED | |
608 | * UNPREDICTABLE choice of : | |
609 | * - The write is ignored. | |
610 | * - The RS field is treated as 0. | |
611 | */ | |
612 | if (need_rss && (!gic_data.has_rss)) | |
613 | pr_crit_once("RSS is required but GICD doesn't support it\n"); | |
3708d52f SH |
614 | } |
615 | ||
da33f31d MZ |
616 | static int gic_dist_supports_lpis(void) |
617 | { | |
618 | return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); | |
619 | } | |
620 | ||
021f6537 MZ |
621 | static void gic_cpu_init(void) |
622 | { | |
623 | void __iomem *rbase; | |
624 | ||
625 | /* Register ourselves with the rest of the world */ | |
626 | if (gic_populate_rdist()) | |
627 | return; | |
628 | ||
a2c22510 | 629 | gic_enable_redist(true); |
021f6537 MZ |
630 | |
631 | rbase = gic_data_rdist_sgi_base(); | |
632 | ||
7c9b9730 MZ |
633 | /* Configure SGIs/PPIs as non-secure Group-1 */ |
634 | writel_relaxed(~0, rbase + GICR_IGROUPR0); | |
635 | ||
021f6537 MZ |
636 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); |
637 | ||
da33f31d MZ |
638 | /* Give LPIs a spin */ |
639 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) | |
640 | its_cpu_init(); | |
641 | ||
3708d52f SH |
642 | /* initialise system registers */ |
643 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
644 | } |
645 | ||
646 | #ifdef CONFIG_SMP | |
6670a6d8 | 647 | |
eda0d04a SD |
648 | #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT) |
649 | #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL) | |
650 | ||
6670a6d8 | 651 | static int gic_starting_cpu(unsigned int cpu) |
021f6537 | 652 | { |
6670a6d8 RC |
653 | gic_cpu_init(); |
654 | return 0; | |
021f6537 MZ |
655 | } |
656 | ||
021f6537 | 657 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, |
f6c86a41 | 658 | unsigned long cluster_id) |
021f6537 | 659 | { |
727653d6 | 660 | int next_cpu, cpu = *base_cpu; |
f6c86a41 | 661 | unsigned long mpidr = cpu_logical_map(cpu); |
021f6537 MZ |
662 | u16 tlist = 0; |
663 | ||
664 | while (cpu < nr_cpu_ids) { | |
021f6537 MZ |
665 | tlist |= 1 << (mpidr & 0xf); |
666 | ||
727653d6 JM |
667 | next_cpu = cpumask_next(cpu, mask); |
668 | if (next_cpu >= nr_cpu_ids) | |
021f6537 | 669 | goto out; |
727653d6 | 670 | cpu = next_cpu; |
021f6537 MZ |
671 | |
672 | mpidr = cpu_logical_map(cpu); | |
673 | ||
eda0d04a | 674 | if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) { |
021f6537 MZ |
675 | cpu--; |
676 | goto out; | |
677 | } | |
678 | } | |
679 | out: | |
680 | *base_cpu = cpu; | |
681 | return tlist; | |
682 | } | |
683 | ||
7e580278 AP |
684 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
685 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
686 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
687 | ||
021f6537 MZ |
688 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
689 | { | |
690 | u64 val; | |
691 | ||
7e580278 AP |
692 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
693 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
694 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
695 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
eda0d04a | 696 | MPIDR_TO_SGI_RS(cluster_id) | |
7e580278 | 697 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); |
021f6537 | 698 | |
b6dd4d83 | 699 | pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); |
021f6537 MZ |
700 | gic_write_sgi1r(val); |
701 | } | |
702 | ||
703 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |
704 | { | |
705 | int cpu; | |
706 | ||
707 | if (WARN_ON(irq >= 16)) | |
708 | return; | |
709 | ||
710 | /* | |
711 | * Ensure that stores to Normal memory are visible to the | |
712 | * other CPUs before issuing the IPI. | |
713 | */ | |
21ec30c0 | 714 | wmb(); |
021f6537 | 715 | |
f9b531fe | 716 | for_each_cpu(cpu, mask) { |
eda0d04a | 717 | u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu)); |
021f6537 MZ |
718 | u16 tlist; |
719 | ||
720 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
721 | gic_send_sgi(cluster_id, tlist, irq); | |
722 | } | |
723 | ||
724 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
725 | isb(); | |
726 | } | |
727 | ||
728 | static void gic_smp_init(void) | |
729 | { | |
730 | set_smp_cross_call(gic_raise_softirq); | |
6896bcd1 | 731 | cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, |
73c1b41e TG |
732 | "irqchip/arm/gicv3:starting", |
733 | gic_starting_cpu, NULL); | |
021f6537 MZ |
734 | } |
735 | ||
736 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
737 | bool force) | |
738 | { | |
65a30f8b | 739 | unsigned int cpu; |
021f6537 MZ |
740 | void __iomem *reg; |
741 | int enabled; | |
742 | u64 val; | |
743 | ||
65a30f8b SP |
744 | if (force) |
745 | cpu = cpumask_first(mask_val); | |
746 | else | |
747 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
748 | ||
866d7c1b SP |
749 | if (cpu >= nr_cpu_ids) |
750 | return -EINVAL; | |
751 | ||
021f6537 MZ |
752 | if (gic_irq_in_rdist(d)) |
753 | return -EINVAL; | |
754 | ||
755 | /* If interrupt was enabled, disable it first */ | |
756 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
757 | if (enabled) | |
758 | gic_mask_irq(d); | |
759 | ||
760 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); | |
761 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); | |
762 | ||
72c97126 | 763 | gic_write_irouter(val, reg); |
021f6537 MZ |
764 | |
765 | /* | |
766 | * If the interrupt was enabled, enabled it again. Otherwise, | |
767 | * just wait for the distributor to have digested our changes. | |
768 | */ | |
769 | if (enabled) | |
770 | gic_unmask_irq(d); | |
771 | else | |
772 | gic_dist_wait_for_rwp(); | |
773 | ||
956ae91a MZ |
774 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
775 | ||
0fc6fa29 | 776 | return IRQ_SET_MASK_OK_DONE; |
021f6537 MZ |
777 | } |
778 | #else | |
779 | #define gic_set_affinity NULL | |
780 | #define gic_smp_init() do { } while(0) | |
781 | #endif | |
782 | ||
3708d52f | 783 | #ifdef CONFIG_CPU_PM |
ccd9432a SH |
784 | /* Check whether it's single security state view */ |
785 | static bool gic_dist_security_disabled(void) | |
786 | { | |
787 | return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; | |
788 | } | |
789 | ||
3708d52f SH |
790 | static int gic_cpu_pm_notifier(struct notifier_block *self, |
791 | unsigned long cmd, void *v) | |
792 | { | |
793 | if (cmd == CPU_PM_EXIT) { | |
ccd9432a SH |
794 | if (gic_dist_security_disabled()) |
795 | gic_enable_redist(true); | |
3708d52f | 796 | gic_cpu_sys_reg_init(); |
ccd9432a | 797 | } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { |
3708d52f SH |
798 | gic_write_grpen1(0); |
799 | gic_enable_redist(false); | |
800 | } | |
801 | return NOTIFY_OK; | |
802 | } | |
803 | ||
804 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
805 | .notifier_call = gic_cpu_pm_notifier, | |
806 | }; | |
807 | ||
808 | static void gic_cpu_pm_init(void) | |
809 | { | |
810 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
811 | } | |
812 | ||
813 | #else | |
814 | static inline void gic_cpu_pm_init(void) { } | |
815 | #endif /* CONFIG_CPU_PM */ | |
816 | ||
021f6537 MZ |
817 | static struct irq_chip gic_chip = { |
818 | .name = "GICv3", | |
819 | .irq_mask = gic_mask_irq, | |
820 | .irq_unmask = gic_unmask_irq, | |
821 | .irq_eoi = gic_eoi_irq, | |
822 | .irq_set_type = gic_set_type, | |
823 | .irq_set_affinity = gic_set_affinity, | |
b594c6e2 MZ |
824 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
825 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
55963c9f | 826 | .flags = IRQCHIP_SET_TYPE_MASKED, |
021f6537 MZ |
827 | }; |
828 | ||
0b6a3da9 MZ |
829 | static struct irq_chip gic_eoimode1_chip = { |
830 | .name = "GICv3", | |
831 | .irq_mask = gic_eoimode1_mask_irq, | |
832 | .irq_unmask = gic_unmask_irq, | |
833 | .irq_eoi = gic_eoimode1_eoi_irq, | |
834 | .irq_set_type = gic_set_type, | |
835 | .irq_set_affinity = gic_set_affinity, | |
836 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
837 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
530bf353 | 838 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
0b6a3da9 MZ |
839 | .flags = IRQCHIP_SET_TYPE_MASKED, |
840 | }; | |
841 | ||
da33f31d MZ |
842 | #define GIC_ID_NR (1U << gic_data.rdists.id_bits) |
843 | ||
021f6537 MZ |
844 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
845 | irq_hw_number_t hw) | |
846 | { | |
0b6a3da9 MZ |
847 | struct irq_chip *chip = &gic_chip; |
848 | ||
849 | if (static_key_true(&supports_deactivate)) | |
850 | chip = &gic_eoimode1_chip; | |
851 | ||
021f6537 MZ |
852 | /* SGIs are private to the core kernel */ |
853 | if (hw < 16) | |
854 | return -EPERM; | |
da33f31d MZ |
855 | /* Nothing here */ |
856 | if (hw >= gic_data.irq_nr && hw < 8192) | |
857 | return -EPERM; | |
858 | /* Off limits */ | |
859 | if (hw >= GIC_ID_NR) | |
860 | return -EPERM; | |
861 | ||
021f6537 MZ |
862 | /* PPIs */ |
863 | if (hw < 32) { | |
864 | irq_set_percpu_devid(irq); | |
0b6a3da9 | 865 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 866 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 867 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
021f6537 MZ |
868 | } |
869 | /* SPIs */ | |
870 | if (hw >= 32 && hw < gic_data.irq_nr) { | |
0b6a3da9 | 871 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 872 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 873 | irq_set_probe(irq); |
956ae91a | 874 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); |
021f6537 | 875 | } |
da33f31d MZ |
876 | /* LPIs */ |
877 | if (hw >= 8192 && hw < GIC_ID_NR) { | |
878 | if (!gic_dist_supports_lpis()) | |
879 | return -EPERM; | |
0b6a3da9 | 880 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d | 881 | handle_fasteoi_irq, NULL, NULL); |
da33f31d MZ |
882 | } |
883 | ||
021f6537 MZ |
884 | return 0; |
885 | } | |
886 | ||
f833f57f MZ |
887 | static int gic_irq_domain_translate(struct irq_domain *d, |
888 | struct irq_fwspec *fwspec, | |
889 | unsigned long *hwirq, | |
890 | unsigned int *type) | |
021f6537 | 891 | { |
f833f57f MZ |
892 | if (is_of_node(fwspec->fwnode)) { |
893 | if (fwspec->param_count < 3) | |
894 | return -EINVAL; | |
021f6537 | 895 | |
db8c70ec MZ |
896 | switch (fwspec->param[0]) { |
897 | case 0: /* SPI */ | |
898 | *hwirq = fwspec->param[1] + 32; | |
899 | break; | |
900 | case 1: /* PPI */ | |
901 | *hwirq = fwspec->param[1] + 16; | |
902 | break; | |
903 | case GIC_IRQ_TYPE_LPI: /* LPI */ | |
904 | *hwirq = fwspec->param[1]; | |
905 | break; | |
906 | default: | |
907 | return -EINVAL; | |
908 | } | |
f833f57f MZ |
909 | |
910 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
911 | return 0; | |
021f6537 MZ |
912 | } |
913 | ||
ffa7d616 TN |
914 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
915 | if(fwspec->param_count != 2) | |
916 | return -EINVAL; | |
917 | ||
918 | *hwirq = fwspec->param[0]; | |
919 | *type = fwspec->param[1]; | |
920 | return 0; | |
921 | } | |
922 | ||
f833f57f | 923 | return -EINVAL; |
021f6537 MZ |
924 | } |
925 | ||
443acc4f MZ |
926 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
927 | unsigned int nr_irqs, void *arg) | |
928 | { | |
929 | int i, ret; | |
930 | irq_hw_number_t hwirq; | |
931 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 932 | struct irq_fwspec *fwspec = arg; |
443acc4f | 933 | |
f833f57f | 934 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
443acc4f MZ |
935 | if (ret) |
936 | return ret; | |
937 | ||
63c16c6e SP |
938 | for (i = 0; i < nr_irqs; i++) { |
939 | ret = gic_irq_domain_map(domain, virq + i, hwirq + i); | |
940 | if (ret) | |
941 | return ret; | |
942 | } | |
443acc4f MZ |
943 | |
944 | return 0; | |
945 | } | |
946 | ||
947 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
948 | unsigned int nr_irqs) | |
949 | { | |
950 | int i; | |
951 | ||
952 | for (i = 0; i < nr_irqs; i++) { | |
953 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
954 | irq_set_handler(virq + i, NULL); | |
955 | irq_domain_reset_irq_data(d); | |
956 | } | |
957 | } | |
958 | ||
e3825ba1 MZ |
959 | static int gic_irq_domain_select(struct irq_domain *d, |
960 | struct irq_fwspec *fwspec, | |
961 | enum irq_domain_bus_token bus_token) | |
962 | { | |
963 | /* Not for us */ | |
964 | if (fwspec->fwnode != d->fwnode) | |
965 | return 0; | |
966 | ||
967 | /* If this is not DT, then we have a single domain */ | |
968 | if (!is_of_node(fwspec->fwnode)) | |
969 | return 1; | |
970 | ||
971 | /* | |
972 | * If this is a PPI and we have a 4th (non-null) parameter, | |
973 | * then we need to match the partition domain. | |
974 | */ | |
975 | if (fwspec->param_count >= 4 && | |
976 | fwspec->param[0] == 1 && fwspec->param[3] != 0) | |
977 | return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); | |
978 | ||
979 | return d == gic_data.domain; | |
980 | } | |
981 | ||
021f6537 | 982 | static const struct irq_domain_ops gic_irq_domain_ops = { |
f833f57f | 983 | .translate = gic_irq_domain_translate, |
443acc4f MZ |
984 | .alloc = gic_irq_domain_alloc, |
985 | .free = gic_irq_domain_free, | |
e3825ba1 MZ |
986 | .select = gic_irq_domain_select, |
987 | }; | |
988 | ||
989 | static int partition_domain_translate(struct irq_domain *d, | |
990 | struct irq_fwspec *fwspec, | |
991 | unsigned long *hwirq, | |
992 | unsigned int *type) | |
993 | { | |
994 | struct device_node *np; | |
995 | int ret; | |
996 | ||
997 | np = of_find_node_by_phandle(fwspec->param[3]); | |
998 | if (WARN_ON(!np)) | |
999 | return -EINVAL; | |
1000 | ||
1001 | ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], | |
1002 | of_node_to_fwnode(np)); | |
1003 | if (ret < 0) | |
1004 | return ret; | |
1005 | ||
1006 | *hwirq = ret; | |
1007 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
1008 | ||
1009 | return 0; | |
1010 | } | |
1011 | ||
1012 | static const struct irq_domain_ops partition_domain_ops = { | |
1013 | .translate = partition_domain_translate, | |
1014 | .select = gic_irq_domain_select, | |
021f6537 MZ |
1015 | }; |
1016 | ||
db57d746 TN |
1017 | static int __init gic_init_bases(void __iomem *dist_base, |
1018 | struct redist_region *rdist_regs, | |
1019 | u32 nr_redist_regions, | |
1020 | u64 redist_stride, | |
1021 | struct fwnode_handle *handle) | |
021f6537 | 1022 | { |
f5c1434c | 1023 | u32 typer; |
021f6537 MZ |
1024 | int gic_irqs; |
1025 | int err; | |
021f6537 | 1026 | |
0b6a3da9 MZ |
1027 | if (!is_hyp_mode_available()) |
1028 | static_key_slow_dec(&supports_deactivate); | |
1029 | ||
1030 | if (static_key_true(&supports_deactivate)) | |
1031 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
1032 | ||
e3825ba1 | 1033 | gic_data.fwnode = handle; |
021f6537 | 1034 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
1035 | gic_data.redist_regions = rdist_regs; |
1036 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
1037 | gic_data.redist_stride = redist_stride; |
1038 | ||
1039 | /* | |
1040 | * Find out how many interrupts are supported. | |
1041 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) | |
1042 | */ | |
f5c1434c MZ |
1043 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
1044 | gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); | |
1045 | gic_irqs = GICD_TYPER_IRQS(typer); | |
021f6537 MZ |
1046 | if (gic_irqs > 1020) |
1047 | gic_irqs = 1020; | |
1048 | gic_data.irq_nr = gic_irqs; | |
1049 | ||
db57d746 TN |
1050 | gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, |
1051 | &gic_data); | |
f5c1434c | 1052 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
0edc23ea MZ |
1053 | gic_data.rdists.has_vlpis = true; |
1054 | gic_data.rdists.has_direct_lpi = true; | |
021f6537 | 1055 | |
f5c1434c | 1056 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
1057 | err = -ENOMEM; |
1058 | goto out_free; | |
1059 | } | |
1060 | ||
eda0d04a SD |
1061 | gic_data.has_rss = !!(typer & GICD_TYPER_RSS); |
1062 | pr_info("Distributor has %sRange Selector support\n", | |
1063 | gic_data.has_rss ? "" : "no "); | |
1064 | ||
021f6537 MZ |
1065 | set_handle_irq(gic_handle_irq); |
1066 | ||
0edc23ea MZ |
1067 | gic_update_vlpi_properties(); |
1068 | ||
db40f0a7 TN |
1069 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) |
1070 | its_init(handle, &gic_data.rdists, gic_data.domain); | |
da33f31d | 1071 | |
021f6537 MZ |
1072 | gic_smp_init(); |
1073 | gic_dist_init(); | |
1074 | gic_cpu_init(); | |
3708d52f | 1075 | gic_cpu_pm_init(); |
021f6537 MZ |
1076 | |
1077 | return 0; | |
1078 | ||
1079 | out_free: | |
1080 | if (gic_data.domain) | |
1081 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 1082 | free_percpu(gic_data.rdists.rdist); |
db57d746 TN |
1083 | return err; |
1084 | } | |
1085 | ||
1086 | static int __init gic_validate_dist_version(void __iomem *dist_base) | |
1087 | { | |
1088 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1089 | ||
1090 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) | |
1091 | return -ENODEV; | |
1092 | ||
1093 | return 0; | |
1094 | } | |
1095 | ||
e3825ba1 | 1096 | /* Create all possible partitions at boot time */ |
7beaa24b | 1097 | static void __init gic_populate_ppi_partitions(struct device_node *gic_node) |
e3825ba1 MZ |
1098 | { |
1099 | struct device_node *parts_node, *child_part; | |
1100 | int part_idx = 0, i; | |
1101 | int nr_parts; | |
1102 | struct partition_affinity *parts; | |
1103 | ||
00ee9a1c | 1104 | parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); |
e3825ba1 MZ |
1105 | if (!parts_node) |
1106 | return; | |
1107 | ||
1108 | nr_parts = of_get_child_count(parts_node); | |
1109 | ||
1110 | if (!nr_parts) | |
00ee9a1c | 1111 | goto out_put_node; |
e3825ba1 MZ |
1112 | |
1113 | parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); | |
1114 | if (WARN_ON(!parts)) | |
00ee9a1c | 1115 | goto out_put_node; |
e3825ba1 MZ |
1116 | |
1117 | for_each_child_of_node(parts_node, child_part) { | |
1118 | struct partition_affinity *part; | |
1119 | int n; | |
1120 | ||
1121 | part = &parts[part_idx]; | |
1122 | ||
1123 | part->partition_id = of_node_to_fwnode(child_part); | |
1124 | ||
1125 | pr_info("GIC: PPI partition %s[%d] { ", | |
1126 | child_part->name, part_idx); | |
1127 | ||
1128 | n = of_property_count_elems_of_size(child_part, "affinity", | |
1129 | sizeof(u32)); | |
1130 | WARN_ON(n <= 0); | |
1131 | ||
1132 | for (i = 0; i < n; i++) { | |
1133 | int err, cpu; | |
1134 | u32 cpu_phandle; | |
1135 | struct device_node *cpu_node; | |
1136 | ||
1137 | err = of_property_read_u32_index(child_part, "affinity", | |
1138 | i, &cpu_phandle); | |
1139 | if (WARN_ON(err)) | |
1140 | continue; | |
1141 | ||
1142 | cpu_node = of_find_node_by_phandle(cpu_phandle); | |
1143 | if (WARN_ON(!cpu_node)) | |
1144 | continue; | |
1145 | ||
c08ec7da SP |
1146 | cpu = of_cpu_node_to_id(cpu_node); |
1147 | if (WARN_ON(cpu < 0)) | |
e3825ba1 MZ |
1148 | continue; |
1149 | ||
e81f54c6 | 1150 | pr_cont("%pOF[%d] ", cpu_node, cpu); |
e3825ba1 MZ |
1151 | |
1152 | cpumask_set_cpu(cpu, &part->mask); | |
1153 | } | |
1154 | ||
1155 | pr_cont("}\n"); | |
1156 | part_idx++; | |
1157 | } | |
1158 | ||
1159 | for (i = 0; i < 16; i++) { | |
1160 | unsigned int irq; | |
1161 | struct partition_desc *desc; | |
1162 | struct irq_fwspec ppi_fwspec = { | |
1163 | .fwnode = gic_data.fwnode, | |
1164 | .param_count = 3, | |
1165 | .param = { | |
1166 | [0] = 1, | |
1167 | [1] = i, | |
1168 | [2] = IRQ_TYPE_NONE, | |
1169 | }, | |
1170 | }; | |
1171 | ||
1172 | irq = irq_create_fwspec_mapping(&ppi_fwspec); | |
1173 | if (WARN_ON(!irq)) | |
1174 | continue; | |
1175 | desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, | |
1176 | irq, &partition_domain_ops); | |
1177 | if (WARN_ON(!desc)) | |
1178 | continue; | |
1179 | ||
1180 | gic_data.ppi_descs[i] = desc; | |
1181 | } | |
00ee9a1c JH |
1182 | |
1183 | out_put_node: | |
1184 | of_node_put(parts_node); | |
e3825ba1 MZ |
1185 | } |
1186 | ||
1839e576 JG |
1187 | static void __init gic_of_setup_kvm_info(struct device_node *node) |
1188 | { | |
1189 | int ret; | |
1190 | struct resource r; | |
1191 | u32 gicv_idx; | |
1192 | ||
1193 | gic_v3_kvm_info.type = GIC_V3; | |
1194 | ||
1195 | gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); | |
1196 | if (!gic_v3_kvm_info.maint_irq) | |
1197 | return; | |
1198 | ||
1199 | if (of_property_read_u32(node, "#redistributor-regions", | |
1200 | &gicv_idx)) | |
1201 | gicv_idx = 1; | |
1202 | ||
1203 | gicv_idx += 3; /* Also skip GICD, GICC, GICH */ | |
1204 | ret = of_address_to_resource(node, gicv_idx, &r); | |
1205 | if (!ret) | |
1206 | gic_v3_kvm_info.vcpu = r; | |
1207 | ||
4bdf5025 | 1208 | gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; |
1839e576 JG |
1209 | gic_set_kvm_info(&gic_v3_kvm_info); |
1210 | } | |
1211 | ||
db57d746 TN |
1212 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) |
1213 | { | |
1214 | void __iomem *dist_base; | |
1215 | struct redist_region *rdist_regs; | |
1216 | u64 redist_stride; | |
1217 | u32 nr_redist_regions; | |
1218 | int err, i; | |
1219 | ||
1220 | dist_base = of_iomap(node, 0); | |
1221 | if (!dist_base) { | |
e81f54c6 | 1222 | pr_err("%pOF: unable to map gic dist registers\n", node); |
db57d746 TN |
1223 | return -ENXIO; |
1224 | } | |
1225 | ||
1226 | err = gic_validate_dist_version(dist_base); | |
1227 | if (err) { | |
e81f54c6 | 1228 | pr_err("%pOF: no distributor detected, giving up\n", node); |
db57d746 TN |
1229 | goto out_unmap_dist; |
1230 | } | |
1231 | ||
1232 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) | |
1233 | nr_redist_regions = 1; | |
1234 | ||
1235 | rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); | |
1236 | if (!rdist_regs) { | |
1237 | err = -ENOMEM; | |
1238 | goto out_unmap_dist; | |
1239 | } | |
1240 | ||
1241 | for (i = 0; i < nr_redist_regions; i++) { | |
1242 | struct resource res; | |
1243 | int ret; | |
1244 | ||
1245 | ret = of_address_to_resource(node, 1 + i, &res); | |
1246 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); | |
1247 | if (ret || !rdist_regs[i].redist_base) { | |
e81f54c6 | 1248 | pr_err("%pOF: couldn't map region %d\n", node, i); |
db57d746 TN |
1249 | err = -ENODEV; |
1250 | goto out_unmap_rdist; | |
1251 | } | |
1252 | rdist_regs[i].phys_base = res.start; | |
1253 | } | |
1254 | ||
1255 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
1256 | redist_stride = 0; | |
1257 | ||
1258 | err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, | |
1259 | redist_stride, &node->fwnode); | |
e3825ba1 MZ |
1260 | if (err) |
1261 | goto out_unmap_rdist; | |
1262 | ||
1263 | gic_populate_ppi_partitions(node); | |
d33a3c8c CD |
1264 | |
1265 | if (static_key_true(&supports_deactivate)) | |
1266 | gic_of_setup_kvm_info(node); | |
e3825ba1 | 1267 | return 0; |
db57d746 | 1268 | |
021f6537 | 1269 | out_unmap_rdist: |
f5c1434c MZ |
1270 | for (i = 0; i < nr_redist_regions; i++) |
1271 | if (rdist_regs[i].redist_base) | |
1272 | iounmap(rdist_regs[i].redist_base); | |
1273 | kfree(rdist_regs); | |
021f6537 MZ |
1274 | out_unmap_dist: |
1275 | iounmap(dist_base); | |
1276 | return err; | |
1277 | } | |
1278 | ||
1279 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); | |
ffa7d616 TN |
1280 | |
1281 | #ifdef CONFIG_ACPI | |
611f039f JG |
1282 | static struct |
1283 | { | |
1284 | void __iomem *dist_base; | |
1285 | struct redist_region *redist_regs; | |
1286 | u32 nr_redist_regions; | |
1287 | bool single_redist; | |
1839e576 JG |
1288 | u32 maint_irq; |
1289 | int maint_irq_mode; | |
1290 | phys_addr_t vcpu_base; | |
611f039f | 1291 | } acpi_data __initdata; |
b70fb7af TN |
1292 | |
1293 | static void __init | |
1294 | gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) | |
1295 | { | |
1296 | static int count = 0; | |
1297 | ||
611f039f JG |
1298 | acpi_data.redist_regs[count].phys_base = phys_base; |
1299 | acpi_data.redist_regs[count].redist_base = redist_base; | |
1300 | acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; | |
b70fb7af TN |
1301 | count++; |
1302 | } | |
ffa7d616 TN |
1303 | |
1304 | static int __init | |
1305 | gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, | |
1306 | const unsigned long end) | |
1307 | { | |
1308 | struct acpi_madt_generic_redistributor *redist = | |
1309 | (struct acpi_madt_generic_redistributor *)header; | |
1310 | void __iomem *redist_base; | |
ffa7d616 TN |
1311 | |
1312 | redist_base = ioremap(redist->base_address, redist->length); | |
1313 | if (!redist_base) { | |
1314 | pr_err("Couldn't map GICR region @%llx\n", redist->base_address); | |
1315 | return -ENOMEM; | |
1316 | } | |
1317 | ||
b70fb7af | 1318 | gic_acpi_register_redist(redist->base_address, redist_base); |
ffa7d616 TN |
1319 | return 0; |
1320 | } | |
1321 | ||
b70fb7af TN |
1322 | static int __init |
1323 | gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, | |
1324 | const unsigned long end) | |
1325 | { | |
1326 | struct acpi_madt_generic_interrupt *gicc = | |
1327 | (struct acpi_madt_generic_interrupt *)header; | |
611f039f | 1328 | u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; |
b70fb7af TN |
1329 | u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; |
1330 | void __iomem *redist_base; | |
1331 | ||
ebe2f871 SD |
1332 | /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */ |
1333 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
1334 | return 0; | |
1335 | ||
b70fb7af TN |
1336 | redist_base = ioremap(gicc->gicr_base_address, size); |
1337 | if (!redist_base) | |
1338 | return -ENOMEM; | |
1339 | ||
1340 | gic_acpi_register_redist(gicc->gicr_base_address, redist_base); | |
1341 | return 0; | |
1342 | } | |
1343 | ||
1344 | static int __init gic_acpi_collect_gicr_base(void) | |
1345 | { | |
1346 | acpi_tbl_entry_handler redist_parser; | |
1347 | enum acpi_madt_type type; | |
1348 | ||
611f039f | 1349 | if (acpi_data.single_redist) { |
b70fb7af TN |
1350 | type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; |
1351 | redist_parser = gic_acpi_parse_madt_gicc; | |
1352 | } else { | |
1353 | type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; | |
1354 | redist_parser = gic_acpi_parse_madt_redist; | |
1355 | } | |
1356 | ||
1357 | /* Collect redistributor base addresses in GICR entries */ | |
1358 | if (acpi_table_parse_madt(type, redist_parser, 0) > 0) | |
1359 | return 0; | |
1360 | ||
1361 | pr_info("No valid GICR entries exist\n"); | |
1362 | return -ENODEV; | |
1363 | } | |
1364 | ||
ffa7d616 TN |
1365 | static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, |
1366 | const unsigned long end) | |
1367 | { | |
1368 | /* Subtable presence means that redist exists, that's it */ | |
1369 | return 0; | |
1370 | } | |
1371 | ||
b70fb7af TN |
1372 | static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, |
1373 | const unsigned long end) | |
1374 | { | |
1375 | struct acpi_madt_generic_interrupt *gicc = | |
1376 | (struct acpi_madt_generic_interrupt *)header; | |
1377 | ||
1378 | /* | |
1379 | * If GICC is enabled and has valid gicr base address, then it means | |
1380 | * GICR base is presented via GICC | |
1381 | */ | |
1382 | if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) | |
1383 | return 0; | |
1384 | ||
ebe2f871 SD |
1385 | /* |
1386 | * It's perfectly valid firmware can pass disabled GICC entry, driver | |
1387 | * should not treat as errors, skip the entry instead of probe fail. | |
1388 | */ | |
1389 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
1390 | return 0; | |
1391 | ||
b70fb7af TN |
1392 | return -ENODEV; |
1393 | } | |
1394 | ||
1395 | static int __init gic_acpi_count_gicr_regions(void) | |
1396 | { | |
1397 | int count; | |
1398 | ||
1399 | /* | |
1400 | * Count how many redistributor regions we have. It is not allowed | |
1401 | * to mix redistributor description, GICR and GICC subtables have to be | |
1402 | * mutually exclusive. | |
1403 | */ | |
1404 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1405 | gic_acpi_match_gicr, 0); | |
1406 | if (count > 0) { | |
611f039f | 1407 | acpi_data.single_redist = false; |
b70fb7af TN |
1408 | return count; |
1409 | } | |
1410 | ||
1411 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
1412 | gic_acpi_match_gicc, 0); | |
1413 | if (count > 0) | |
611f039f | 1414 | acpi_data.single_redist = true; |
b70fb7af TN |
1415 | |
1416 | return count; | |
1417 | } | |
1418 | ||
ffa7d616 TN |
1419 | static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, |
1420 | struct acpi_probe_entry *ape) | |
1421 | { | |
1422 | struct acpi_madt_generic_distributor *dist; | |
1423 | int count; | |
1424 | ||
1425 | dist = (struct acpi_madt_generic_distributor *)header; | |
1426 | if (dist->version != ape->driver_data) | |
1427 | return false; | |
1428 | ||
1429 | /* We need to do that exercise anyway, the sooner the better */ | |
b70fb7af | 1430 | count = gic_acpi_count_gicr_regions(); |
ffa7d616 TN |
1431 | if (count <= 0) |
1432 | return false; | |
1433 | ||
611f039f | 1434 | acpi_data.nr_redist_regions = count; |
ffa7d616 TN |
1435 | return true; |
1436 | } | |
1437 | ||
1839e576 JG |
1438 | static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, |
1439 | const unsigned long end) | |
1440 | { | |
1441 | struct acpi_madt_generic_interrupt *gicc = | |
1442 | (struct acpi_madt_generic_interrupt *)header; | |
1443 | int maint_irq_mode; | |
1444 | static int first_madt = true; | |
1445 | ||
1446 | /* Skip unusable CPUs */ | |
1447 | if (!(gicc->flags & ACPI_MADT_ENABLED)) | |
1448 | return 0; | |
1449 | ||
1450 | maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? | |
1451 | ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; | |
1452 | ||
1453 | if (first_madt) { | |
1454 | first_madt = false; | |
1455 | ||
1456 | acpi_data.maint_irq = gicc->vgic_interrupt; | |
1457 | acpi_data.maint_irq_mode = maint_irq_mode; | |
1458 | acpi_data.vcpu_base = gicc->gicv_base_address; | |
1459 | ||
1460 | return 0; | |
1461 | } | |
1462 | ||
1463 | /* | |
1464 | * The maintenance interrupt and GICV should be the same for every CPU | |
1465 | */ | |
1466 | if ((acpi_data.maint_irq != gicc->vgic_interrupt) || | |
1467 | (acpi_data.maint_irq_mode != maint_irq_mode) || | |
1468 | (acpi_data.vcpu_base != gicc->gicv_base_address)) | |
1469 | return -EINVAL; | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | static bool __init gic_acpi_collect_virt_info(void) | |
1475 | { | |
1476 | int count; | |
1477 | ||
1478 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
1479 | gic_acpi_parse_virt_madt_gicc, 0); | |
1480 | ||
1481 | return (count > 0); | |
1482 | } | |
1483 | ||
ffa7d616 | 1484 | #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) |
1839e576 JG |
1485 | #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) |
1486 | #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) | |
1487 | ||
1488 | static void __init gic_acpi_setup_kvm_info(void) | |
1489 | { | |
1490 | int irq; | |
1491 | ||
1492 | if (!gic_acpi_collect_virt_info()) { | |
1493 | pr_warn("Unable to get hardware information used for virtualization\n"); | |
1494 | return; | |
1495 | } | |
1496 | ||
1497 | gic_v3_kvm_info.type = GIC_V3; | |
1498 | ||
1499 | irq = acpi_register_gsi(NULL, acpi_data.maint_irq, | |
1500 | acpi_data.maint_irq_mode, | |
1501 | ACPI_ACTIVE_HIGH); | |
1502 | if (irq <= 0) | |
1503 | return; | |
1504 | ||
1505 | gic_v3_kvm_info.maint_irq = irq; | |
1506 | ||
1507 | if (acpi_data.vcpu_base) { | |
1508 | struct resource *vcpu = &gic_v3_kvm_info.vcpu; | |
1509 | ||
1510 | vcpu->flags = IORESOURCE_MEM; | |
1511 | vcpu->start = acpi_data.vcpu_base; | |
1512 | vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; | |
1513 | } | |
1514 | ||
4bdf5025 | 1515 | gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; |
1839e576 JG |
1516 | gic_set_kvm_info(&gic_v3_kvm_info); |
1517 | } | |
ffa7d616 TN |
1518 | |
1519 | static int __init | |
1520 | gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) | |
1521 | { | |
1522 | struct acpi_madt_generic_distributor *dist; | |
1523 | struct fwnode_handle *domain_handle; | |
611f039f | 1524 | size_t size; |
b70fb7af | 1525 | int i, err; |
ffa7d616 TN |
1526 | |
1527 | /* Get distributor base address */ | |
1528 | dist = (struct acpi_madt_generic_distributor *)header; | |
611f039f JG |
1529 | acpi_data.dist_base = ioremap(dist->base_address, |
1530 | ACPI_GICV3_DIST_MEM_SIZE); | |
1531 | if (!acpi_data.dist_base) { | |
ffa7d616 TN |
1532 | pr_err("Unable to map GICD registers\n"); |
1533 | return -ENOMEM; | |
1534 | } | |
1535 | ||
611f039f | 1536 | err = gic_validate_dist_version(acpi_data.dist_base); |
ffa7d616 | 1537 | if (err) { |
71192a68 | 1538 | pr_err("No distributor detected at @%p, giving up\n", |
611f039f | 1539 | acpi_data.dist_base); |
ffa7d616 TN |
1540 | goto out_dist_unmap; |
1541 | } | |
1542 | ||
611f039f JG |
1543 | size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; |
1544 | acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); | |
1545 | if (!acpi_data.redist_regs) { | |
ffa7d616 TN |
1546 | err = -ENOMEM; |
1547 | goto out_dist_unmap; | |
1548 | } | |
1549 | ||
b70fb7af TN |
1550 | err = gic_acpi_collect_gicr_base(); |
1551 | if (err) | |
ffa7d616 | 1552 | goto out_redist_unmap; |
ffa7d616 | 1553 | |
611f039f | 1554 | domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); |
ffa7d616 TN |
1555 | if (!domain_handle) { |
1556 | err = -ENOMEM; | |
1557 | goto out_redist_unmap; | |
1558 | } | |
1559 | ||
611f039f JG |
1560 | err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, |
1561 | acpi_data.nr_redist_regions, 0, domain_handle); | |
ffa7d616 TN |
1562 | if (err) |
1563 | goto out_fwhandle_free; | |
1564 | ||
1565 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); | |
d33a3c8c CD |
1566 | |
1567 | if (static_key_true(&supports_deactivate)) | |
1568 | gic_acpi_setup_kvm_info(); | |
1839e576 | 1569 | |
ffa7d616 TN |
1570 | return 0; |
1571 | ||
1572 | out_fwhandle_free: | |
1573 | irq_domain_free_fwnode(domain_handle); | |
1574 | out_redist_unmap: | |
611f039f JG |
1575 | for (i = 0; i < acpi_data.nr_redist_regions; i++) |
1576 | if (acpi_data.redist_regs[i].redist_base) | |
1577 | iounmap(acpi_data.redist_regs[i].redist_base); | |
1578 | kfree(acpi_data.redist_regs); | |
ffa7d616 | 1579 | out_dist_unmap: |
611f039f | 1580 | iounmap(acpi_data.dist_base); |
ffa7d616 TN |
1581 | return err; |
1582 | } | |
1583 | IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1584 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, | |
1585 | gic_acpi_init); | |
1586 | IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1587 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, | |
1588 | gic_acpi_init); | |
1589 | IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1590 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, | |
1591 | gic_acpi_init); | |
1592 | #endif |