[thirdparty/kernel/stable.git] / drivers / irqchip / irq-imx-irqsteer.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2017 NXP
 * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/spinlock.h>

#define CTRL_STRIDE_OFF(_t, _r)	(_t * 4 * _r)
#define CHANCTRL		0x0
#define CHANMASK(n, t)		(CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4)
#define CHANSET(n, t)		(CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4)
#define CHANSTATUS(n, t)	(CTRL_STRIDE_OFF(t, 2) + 0x4 * (n) + 0x4)
#define CHAN_MINTDIS(t)		(CTRL_STRIDE_OFF(t, 3) + 0x4)
#define CHAN_MASTRSTAT(t)	(CTRL_STRIDE_OFF(t, 3) + 0x8)

#define CHAN_MAX_OUTPUT_INT	0x8

struct irqsteer_data {
	void __iomem		*regs;
	struct clk		*ipg_clk;
	int			irq[CHAN_MAX_OUTPUT_INT];
	int			irq_count;
	raw_spinlock_t		lock;
	int			reg_num;
	int			channel;
	struct irq_domain	*domain;
	u32			*saved_reg;
};

static int imx_irqsteer_get_reg_index(struct irqsteer_data *data,
				      unsigned long irqnum)
{
	return (data->reg_num - irqnum / 32 - 1);
}

static void imx_irqsteer_irq_unmask(struct irq_data *d)
{
	struct irqsteer_data *data = d->chip_data;
	int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
	unsigned long flags;
	u32 val;

	raw_spin_lock_irqsave(&data->lock, flags);
	val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
	val |= BIT(d->hwirq % 32);
	writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
	raw_spin_unlock_irqrestore(&data->lock, flags);
}

static void imx_irqsteer_irq_mask(struct irq_data *d)
{
	struct irqsteer_data *data = d->chip_data;
	int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
	unsigned long flags;
	u32 val;

	raw_spin_lock_irqsave(&data->lock, flags);
	val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
	val &= ~BIT(d->hwirq % 32);
	writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
	raw_spin_unlock_irqrestore(&data->lock, flags);
}

static struct irq_chip imx_irqsteer_irq_chip = {
	.name		= "irqsteer",
	.irq_mask	= imx_irqsteer_irq_mask,
	.irq_unmask	= imx_irqsteer_irq_unmask,
};

static int imx_irqsteer_irq_map(struct irq_domain *h, unsigned int irq,
				irq_hw_number_t hwirq)
{
	irq_set_status_flags(irq, IRQ_LEVEL);
	irq_set_chip_data(irq, h->host_data);
	irq_set_chip_and_handler(irq, &imx_irqsteer_irq_chip, handle_level_irq);

	return 0;
}

static const struct irq_domain_ops imx_irqsteer_domain_ops = {
	.map		= imx_irqsteer_irq_map,
	.xlate		= irq_domain_xlate_onecell,
};

static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq)
{
	int i;

	for (i = 0; i < data->irq_count; i++) {
		if (data->irq[i] == irq)
			return i * 64;
	}

	return -EINVAL;
}

static void imx_irqsteer_irq_handler(struct irq_desc *desc)
{
	struct irqsteer_data *data = irq_desc_get_handler_data(desc);
	int hwirq;
	int irq, i;

	chained_irq_enter(irq_desc_get_chip(desc), desc);

	irq = irq_desc_get_irq(desc);
	hwirq = imx_irqsteer_get_hwirq_base(data, irq);
	if (hwirq < 0) {
		pr_warn("%s: unable to get hwirq base for irq %d\n",
			__func__, irq);
		return;
	}

	for (i = 0; i < 2; i++, hwirq += 32) {
		int idx = imx_irqsteer_get_reg_index(data, hwirq);
		unsigned long irqmap;
		int pos, virq;

		if (hwirq >= data->reg_num * 32)
			break;

		irqmap = readl_relaxed(data->regs +
				       CHANSTATUS(idx, data->reg_num));

		for_each_set_bit(pos, &irqmap, 32) {
			virq = irq_find_mapping(data->domain, pos + hwirq);
			if (virq)
				generic_handle_irq(virq);
		}
	}

	chained_irq_exit(irq_desc_get_chip(desc), desc);
}

static int imx_irqsteer_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct irqsteer_data *data;
	struct resource *res;
	u32 irqs_num;
	int i, ret;

	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	data->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(data->regs)) {
		dev_err(&pdev->dev, "failed to initialize reg\n");
		return PTR_ERR(data->regs);
	}

	data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(data->ipg_clk)) {
		ret = PTR_ERR(data->ipg_clk);
		if (ret != -EPROBE_DEFER)
			dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
		return ret;
	}

	raw_spin_lock_init(&data->lock);

	ret = of_property_read_u32(np, "fsl,num-irqs", &irqs_num);
	if (ret)
		return ret;
	ret = of_property_read_u32(np, "fsl,channel", &data->channel);
	if (ret)
		return ret;

	/*
	 * There is one output irq for each group of 64 inputs.
	 * One register bit map can represent 32 input interrupts.
	 */
	data->irq_count = DIV_ROUND_UP(irqs_num, 64);
	data->reg_num = irqs_num / 32;

	if (IS_ENABLED(CONFIG_PM_SLEEP)) {
		data->saved_reg = devm_kzalloc(&pdev->dev,
					sizeof(u32) * data->reg_num,
					GFP_KERNEL);
		if (!data->saved_reg)
			return -ENOMEM;
	}

	ret = clk_prepare_enable(data->ipg_clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
		return ret;
	}

	/* steer all IRQs into configured channel */
	writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);

	data->domain = irq_domain_add_linear(np, data->reg_num * 32,
					     &imx_irqsteer_domain_ops, data);
	if (!data->domain) {
		dev_err(&pdev->dev, "failed to create IRQ domain\n");
		ret = -ENOMEM;
		goto out;
	}

	if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) {
		ret = -EINVAL;
		goto out;
	}

	for (i = 0; i < data->irq_count; i++) {
		data->irq[i] = irq_of_parse_and_map(np, i);
		if (!data->irq[i]) {
			ret = -EINVAL;
			goto out;
		}

		irq_set_chained_handler_and_data(data->irq[i],
						 imx_irqsteer_irq_handler,
						 data);
	}

	platform_set_drvdata(pdev, data);

	return 0;
out:
	clk_disable_unprepare(data->ipg_clk);
	return ret;
}

static int imx_irqsteer_remove(struct platform_device *pdev)
{
	struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev);
	int i;

	for (i = 0; i < irqsteer_data->irq_count; i++)
		irq_set_chained_handler_and_data(irqsteer_data->irq[i],
						 NULL, NULL);

	irq_domain_remove(irqsteer_data->domain);

	clk_disable_unprepare(irqsteer_data->ipg_clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static void imx_irqsteer_save_regs(struct irqsteer_data *data)
{
	int i;

	for (i = 0; i < data->reg_num; i++)
		data->saved_reg[i] = readl_relaxed(data->regs +
						CHANMASK(i, data->reg_num));
}

static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
{
	int i;

	writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
	for (i = 0; i < data->reg_num; i++)
		writel_relaxed(data->saved_reg[i],
			       data->regs + CHANMASK(i, data->reg_num));
}

static int imx_irqsteer_suspend(struct device *dev)
{
	struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);

	imx_irqsteer_save_regs(irqsteer_data);
	clk_disable_unprepare(irqsteer_data->ipg_clk);

	return 0;
}

static int imx_irqsteer_resume(struct device *dev)
{
	struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(irqsteer_data->ipg_clk);
	if (ret) {
		dev_err(dev, "failed to enable ipg clk: %d\n", ret);
		return ret;
	}
	imx_irqsteer_restore_regs(irqsteer_data);

	return 0;
}
#endif

static const struct dev_pm_ops imx_irqsteer_pm_ops = {
	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_irqsteer_suspend, imx_irqsteer_resume)
};

static const struct of_device_id imx_irqsteer_dt_ids[] = {
	{ .compatible = "fsl,imx-irqsteer", },
	{},
};

static struct platform_driver imx_irqsteer_driver = {
	.driver = {
		.name = "imx-irqsteer",
		.of_match_table = imx_irqsteer_dt_ids,
		.pm = &imx_irqsteer_pm_ops,
	},
	.probe = imx_irqsteer_probe,
	.remove = imx_irqsteer_remove,
};
builtin_platform_driver(imx_irqsteer_driver);
Commit	Line	Data
0136afa0 LS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright 2017 NXP
	4	* Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
	5	*/
	6
	7	#include <linux/clk.h>
	8	#include <linux/interrupt.h>
	9	#include <linux/irq.h>
	10	#include <linux/irqchip/chained_irq.h>
	11	#include <linux/irqdomain.h>
	12	#include <linux/kernel.h>
28528fca	13	#include <linux/of_irq.h>
0136afa0 LS	14	#include <linux/of_platform.h>
	15	#include <linux/spinlock.h>
	16
deb904e4	17	#define CTRL_STRIDE_OFF(_t, _r) (_t * 4 * _r)
0136afa0 LS	18	#define CHANCTRL 0x0
	19	#define CHANMASK(n, t) (CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4)
	20	#define CHANSET(n, t) (CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4)
	21	#define CHANSTATUS(n, t) (CTRL_STRIDE_OFF(t, 2) + 0x4 * (n) + 0x4)
	22	#define CHAN_MINTDIS(t) (CTRL_STRIDE_OFF(t, 3) + 0x4)
	23	#define CHAN_MASTRSTAT(t) (CTRL_STRIDE_OFF(t, 3) + 0x8)
	24
28528fca AD	25	#define CHAN_MAX_OUTPUT_INT 0x8
28528fca AD	26
0136afa0 LS	27	struct irqsteer_data {
	28	void __iomem *regs;
	29	struct clk *ipg_clk;
28528fca AD	30	int irq[CHAN_MAX_OUTPUT_INT];
28528fca AD	31	int irq_count;
0136afa0	32	raw_spinlock_t lock;
deb904e4	33	int reg_num;
0136afa0 LS	34	int channel;
	35	struct irq_domain *domain;
	36	u32 *saved_reg;
	37	};
	38
	39	static int imx_irqsteer_get_reg_index(struct irqsteer_data *data,
	40	unsigned long irqnum)
	41	{
deb904e4	42	return (data->reg_num - irqnum / 32 - 1);
0136afa0 LS	43	}
	44
	45	static void imx_irqsteer_irq_unmask(struct irq_data *d)
	46	{
	47	struct irqsteer_data *data = d->chip_data;
	48	int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
	49	unsigned long flags;
	50	u32 val;
	51
	52	raw_spin_lock_irqsave(&data->lock, flags);
deb904e4	53	val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
0136afa0	54	val \|= BIT(d->hwirq % 32);
deb904e4	55	writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
0136afa0 LS	56	raw_spin_unlock_irqrestore(&data->lock, flags);
	57	}
	58
	59	static void imx_irqsteer_irq_mask(struct irq_data *d)
	60	{
	61	struct irqsteer_data *data = d->chip_data;
	62	int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
	63	unsigned long flags;
	64	u32 val;
	65
	66	raw_spin_lock_irqsave(&data->lock, flags);
deb904e4	67	val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
0136afa0	68	val &= ~BIT(d->hwirq % 32);
deb904e4	69	writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
0136afa0 LS	70	raw_spin_unlock_irqrestore(&data->lock, flags);
	71	}
	72
	73	static struct irq_chip imx_irqsteer_irq_chip = {
	74	.name = "irqsteer",
	75	.irq_mask = imx_irqsteer_irq_mask,
	76	.irq_unmask = imx_irqsteer_irq_unmask,
	77	};
	78
	79	static int imx_irqsteer_irq_map(struct irq_domain *h, unsigned int irq,
	80	irq_hw_number_t hwirq)
	81	{
	82	irq_set_status_flags(irq, IRQ_LEVEL);
	83	irq_set_chip_data(irq, h->host_data);
	84	irq_set_chip_and_handler(irq, &imx_irqsteer_irq_chip, handle_level_irq);
	85
	86	return 0;
	87	}
	88
	89	static const struct irq_domain_ops imx_irqsteer_domain_ops = {
	90	.map = imx_irqsteer_irq_map,
	91	.xlate = irq_domain_xlate_onecell,
	92	};
	93
28528fca AD	94	static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq)
	95	{
	96	int i;
	97
	98	for (i = 0; i < data->irq_count; i++) {
	99	if (data->irq[i] == irq)
	100	return i * 64;
	101	}
	102
	103	return -EINVAL;
	104	}
	105
0136afa0 LS	106	static void imx_irqsteer_irq_handler(struct irq_desc *desc)
	107	{
	108	struct irqsteer_data *data = irq_desc_get_handler_data(desc);
28528fca AD	109	int hwirq;
28528fca AD	110	int irq, i;
0136afa0 LS	111
	112	chained_irq_enter(irq_desc_get_chip(desc), desc);
	113
28528fca AD	114	irq = irq_desc_get_irq(desc);
	115	hwirq = imx_irqsteer_get_hwirq_base(data, irq);
	116	if (hwirq < 0) {
	117	pr_warn("%s: unable to get hwirq base for irq %d\n",
	118	__func__, irq);
	119	return;
	120	}
	121
	122	for (i = 0; i < 2; i++, hwirq += 32) {
	123	int idx = imx_irqsteer_get_reg_index(data, hwirq);
0136afa0 LS	124	unsigned long irqmap;
	125	int pos, virq;
	126
28528fca AD	127	if (hwirq >= data->reg_num * 32)
	128	break;
	129
0136afa0	130	irqmap = readl_relaxed(data->regs +
deb904e4	131	CHANSTATUS(idx, data->reg_num));
0136afa0 LS	132
0136afa0 LS	133	for_each_set_bit(pos, &irqmap, 32) {
28528fca	134	virq = irq_find_mapping(data->domain, pos + hwirq);
0136afa0 LS	135	if (virq)
	136	generic_handle_irq(virq);
	137	}
	138	}
	139
	140	chained_irq_exit(irq_desc_get_chip(desc), desc);
	141	}
	142
	143	static int imx_irqsteer_probe(struct platform_device *pdev)
	144	{
	145	struct device_node *np = pdev->dev.of_node;
	146	struct irqsteer_data *data;
	147	struct resource *res;
28528fca AD	148	u32 irqs_num;
28528fca AD	149	int i, ret;
0136afa0 LS	150
	151	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
	152	if (!data)
	153	return -ENOMEM;
	154
	155	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	156	data->regs = devm_ioremap_resource(&pdev->dev, res);
	157	if (IS_ERR(data->regs)) {
	158	dev_err(&pdev->dev, "failed to initialize reg\n");
	159	return PTR_ERR(data->regs);
	160	}
	161
0136afa0 LS	162	data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	163	if (IS_ERR(data->ipg_clk)) {
	164	ret = PTR_ERR(data->ipg_clk);
	165	if (ret != -EPROBE_DEFER)
	166	dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
	167	return ret;
	168	}
	169
	170	raw_spin_lock_init(&data->lock);
	171
7d3a5eb7 AB	172	ret = of_property_read_u32(np, "fsl,num-irqs", &irqs_num);
	173	if (ret)
	174	return ret;
	175	ret = of_property_read_u32(np, "fsl,channel", &data->channel);
	176	if (ret)
	177	return ret;
0136afa0	178
28528fca AD	179	/*
	180	* There is one output irq for each group of 64 inputs.
	181	* One register bit map can represent 32 input interrupts.
	182	*/
	183	data->irq_count = DIV_ROUND_UP(irqs_num, 64);
	184	data->reg_num = irqs_num / 32;
deb904e4	185
0136afa0 LS	186	if (IS_ENABLED(CONFIG_PM_SLEEP)) {
0136afa0 LS	187	data->saved_reg = devm_kzalloc(&pdev->dev,
deb904e4	188	sizeof(u32) * data->reg_num,
0136afa0 LS	189	GFP_KERNEL);
	190	if (!data->saved_reg)
	191	return -ENOMEM;
	192	}
	193
	194	ret = clk_prepare_enable(data->ipg_clk);
	195	if (ret) {
	196	dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
	197	return ret;
	198	}
	199
	200	/* steer all IRQs into configured channel */
	201	writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
	202
deb904e4	203	data->domain = irq_domain_add_linear(np, data->reg_num * 32,
0136afa0 LS	204	&imx_irqsteer_domain_ops, data);
	205	if (!data->domain) {
	206	dev_err(&pdev->dev, "failed to create IRQ domain\n");
28528fca AD	207	ret = -ENOMEM;
28528fca AD	208	goto out;
0136afa0 LS	209	}
0136afa0 LS	210
28528fca AD	211	if (!data->irq_count \|\| data->irq_count > CHAN_MAX_OUTPUT_INT) {
	212	ret = -EINVAL;
	213	goto out;
	214	}
	215
	216	for (i = 0; i < data->irq_count; i++) {
	217	data->irq[i] = irq_of_parse_and_map(np, i);
	218	if (!data->irq[i]) {
	219	ret = -EINVAL;
	220	goto out;
	221	}
	222
	223	irq_set_chained_handler_and_data(data->irq[i],
	224	imx_irqsteer_irq_handler,
	225	data);
	226	}
0136afa0 LS	227
	228	platform_set_drvdata(pdev, data);
	229
	230	return 0;
28528fca AD	231	out:
	232	clk_disable_unprepare(data->ipg_clk);
	233	return ret;
0136afa0 LS	234	}
	235
	236	static int imx_irqsteer_remove(struct platform_device *pdev)
	237	{
	238	struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev);
28528fca AD	239	int i;
	240
	241	for (i = 0; i < irqsteer_data->irq_count; i++)
	242	irq_set_chained_handler_and_data(irqsteer_data->irq[i],
	243	NULL, NULL);
0136afa0	244
0136afa0 LS	245	irq_domain_remove(irqsteer_data->domain);
	246
	247	clk_disable_unprepare(irqsteer_data->ipg_clk);
	248
	249	return 0;
	250	}
	251
	252	#ifdef CONFIG_PM_SLEEP
	253	static void imx_irqsteer_save_regs(struct irqsteer_data *data)
	254	{
	255	int i;
	256
deb904e4	257	for (i = 0; i < data->reg_num; i++)
0136afa0	258	data->saved_reg[i] = readl_relaxed(data->regs +
deb904e4	259	CHANMASK(i, data->reg_num));
0136afa0 LS	260	}
	261
	262	static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
	263	{
	264	int i;
	265
	266	writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
deb904e4	267	for (i = 0; i < data->reg_num; i++)
0136afa0	268	writel_relaxed(data->saved_reg[i],
deb904e4	269	data->regs + CHANMASK(i, data->reg_num));
0136afa0 LS	270	}
	271
	272	static int imx_irqsteer_suspend(struct device *dev)
	273	{
	274	struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
	275
	276	imx_irqsteer_save_regs(irqsteer_data);
	277	clk_disable_unprepare(irqsteer_data->ipg_clk);
	278
	279	return 0;
	280	}
	281
	282	static int imx_irqsteer_resume(struct device *dev)
	283	{
	284	struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
	285	int ret;
	286
	287	ret = clk_prepare_enable(irqsteer_data->ipg_clk);
	288	if (ret) {
	289	dev_err(dev, "failed to enable ipg clk: %d\n", ret);
	290	return ret;
	291	}
	292	imx_irqsteer_restore_regs(irqsteer_data);
	293
	294	return 0;
	295	}
	296	#endif
	297
	298	static const struct dev_pm_ops imx_irqsteer_pm_ops = {
	299	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_irqsteer_suspend, imx_irqsteer_resume)
	300	};
	301
	302	static const struct of_device_id imx_irqsteer_dt_ids[] = {
	303	{ .compatible = "fsl,imx-irqsteer", },
	304	{},
	305	};
	306
	307	static struct platform_driver imx_irqsteer_driver = {
	308	.driver = {
	309	.name = "imx-irqsteer",
	310	.of_match_table = imx_irqsteer_dt_ids,
	311	.pm = &imx_irqsteer_pm_ops,
	312	},
	313	.probe = imx_irqsteer_probe,
	314	.remove = imx_irqsteer_remove,
	315	};
	316	builtin_platform_driver(imx_irqsteer_driver);