[people/ms/linux.git] / drivers / irqchip / irq-renesas-intc-irqpin.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Renesas INTC External IRQ Pin Driver
 *
 *  Copyright (C) 2013 Magnus Damm
 */

#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>

#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */

#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
#define INTC_IRQPIN_REG_NR_MANDATORY 5
#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
#define INTC_IRQPIN_REG_NR 6

/* INTC external IRQ PIN hardware register access:
 *
 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
 *
 * (*) May be accessed by more than one driver instance - lock needed
 * (**) Read-modify-write access by one driver instance - lock needed
 * (***) Accessed by one driver instance only - no locking needed
 */

struct intc_irqpin_iomem {
	void __iomem *iomem;
	unsigned long (*read)(void __iomem *iomem);
	void (*write)(void __iomem *iomem, unsigned long data);
	int width;
};

struct intc_irqpin_irq {
	int hw_irq;
	int requested_irq;
	int domain_irq;
	struct intc_irqpin_priv *p;
};

struct intc_irqpin_priv {
	struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
	struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
	unsigned int sense_bitfield_width;
	struct platform_device *pdev;
	struct irq_chip irq_chip;
	struct irq_domain *irq_domain;
	atomic_t wakeup_path;
	unsigned shared_irqs:1;
	u8 shared_irq_mask;
};

struct intc_irqpin_config {
	int irlm_bit;		/* -1 if non-existent */
};

static unsigned long intc_irqpin_read32(void __iomem *iomem)
{
	return ioread32(iomem);
}

static unsigned long intc_irqpin_read8(void __iomem *iomem)
{
	return ioread8(iomem);
}

static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
{
	iowrite32(data, iomem);
}

static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
{
	iowrite8(data, iomem);
}

static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
					     int reg)
{
	struct intc_irqpin_iomem *i = &p->iomem[reg];

	return i->read(i->iomem);
}

static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
				     int reg, unsigned long data)
{
	struct intc_irqpin_iomem *i = &p->iomem[reg];

	i->write(i->iomem, data);
}

static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
						   int reg, int hw_irq)
{
	return BIT((p->iomem[reg].width - 1) - hw_irq);
}

static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
					       int reg, int hw_irq)
{
	intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
}

static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */

static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
					  int reg, int shift,
					  int width, int value)
{
	unsigned long flags;
	unsigned long tmp;

	raw_spin_lock_irqsave(&intc_irqpin_lock, flags);

	tmp = intc_irqpin_read(p, reg);
	tmp &= ~(((1 << width) - 1) << shift);
	tmp |= value << shift;
	intc_irqpin_write(p, reg, tmp);

	raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
}

static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
					 int irq, int do_mask)
{
	/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
	int bitfield_width = 4;
	int shift = 32 - (irq + 1) * bitfield_width;

	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
				      shift, bitfield_width,
				      do_mask ? 0 : (1 << bitfield_width) - 1);
}

static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
{
	/* The SENSE register is assumed to be 32-bit. */
	int bitfield_width = p->sense_bitfield_width;
	int shift = 32 - (irq + 1) * bitfield_width;

	dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);

	if (value >= (1 << bitfield_width))
		return -EINVAL;

	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
				      bitfield_width, value);
	return 0;
}

static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
{
	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
		str, i->requested_irq, i->hw_irq, i->domain_irq);
}

static void intc_irqpin_irq_enable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "enable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
}

static void intc_irqpin_irq_disable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "disable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
}

static void intc_irqpin_shared_irq_enable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);

	p->shared_irq_mask &= ~BIT(hw_irq);
}

static void intc_irqpin_shared_irq_disable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);

	p->shared_irq_mask |= BIT(hw_irq);
}

static void intc_irqpin_irq_enable_force(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;

	intc_irqpin_irq_enable(d);

	/* enable interrupt through parent interrupt controller,
	 * assumes non-shared interrupt with 1:1 mapping
	 * needed for busted IRQs on some SoCs like sh73a0
	 */
	irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
}

static void intc_irqpin_irq_disable_force(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;

	/* disable interrupt through parent interrupt controller,
	 * assumes non-shared interrupt with 1:1 mapping
	 * needed for busted IRQs on some SoCs like sh73a0
	 */
	irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
	intc_irqpin_irq_disable(d);
}

#define INTC_IRQ_SENSE_VALID 0x10
#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)

static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
	[IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
	[IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
	[IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
	[IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
};

static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
{
	unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);

	if (!(value & INTC_IRQ_SENSE_VALID))
		return -EINVAL;

	return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
				     value ^ INTC_IRQ_SENSE_VALID);
}

static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
	if (on)
		atomic_inc(&p->wakeup_path);
	else
		atomic_dec(&p->wakeup_path);

	return 0;
}

static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
{
	struct intc_irqpin_irq *i = dev_id;
	struct intc_irqpin_priv *p = i->p;
	unsigned long bit;

	intc_irqpin_dbg(i, "demux1");
	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);

	if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
		intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
		intc_irqpin_dbg(i, "demux2");
		generic_handle_irq(i->domain_irq);
		return IRQ_HANDLED;
	}
	return IRQ_NONE;
}

static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
{
	struct intc_irqpin_priv *p = dev_id;
	unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
	irqreturn_t status = IRQ_NONE;
	int k;

	for (k = 0; k < 8; k++) {
		if (reg_source & BIT(7 - k)) {
			if (BIT(k) & p->shared_irq_mask)
				continue;

			status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
		}
	}

	return status;
}

/*
 * This lock class tells lockdep that INTC External IRQ Pin irqs are in a
 * different category than their parents, so it won't report false recursion.
 */
static struct lock_class_key intc_irqpin_irq_lock_class;

/* And this is for the request mutex */
static struct lock_class_key intc_irqpin_irq_request_class;

static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
				      irq_hw_number_t hw)
{
	struct intc_irqpin_priv *p = h->host_data;

	p->irq[hw].domain_irq = virq;
	p->irq[hw].hw_irq = hw;

	intc_irqpin_dbg(&p->irq[hw], "map");
	irq_set_chip_data(virq, h->host_data);
	irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
			      &intc_irqpin_irq_request_class);
	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	return 0;
}

static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
	.map	= intc_irqpin_irq_domain_map,
	.xlate  = irq_domain_xlate_twocell,
};

static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
	.irlm_bit = 23, /* ICR0.IRLM0 */
};

static const struct intc_irqpin_config intc_irqpin_rmobile = {
	.irlm_bit = -1,
};

static const struct of_device_id intc_irqpin_dt_ids[] = {
	{ .compatible = "renesas,intc-irqpin", },
	{ .compatible = "renesas,intc-irqpin-r8a7778",
	  .data = &intc_irqpin_irlm_r8a777x },
	{ .compatible = "renesas,intc-irqpin-r8a7779",
	  .data = &intc_irqpin_irlm_r8a777x },
	{ .compatible = "renesas,intc-irqpin-r8a7740",
	  .data = &intc_irqpin_rmobile },
	{ .compatible = "renesas,intc-irqpin-sh73a0",
	  .data = &intc_irqpin_rmobile },
	{},
};
MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);

static int intc_irqpin_probe(struct platform_device *pdev)
{
	const struct intc_irqpin_config *config;
	struct device *dev = &pdev->dev;
	struct intc_irqpin_priv *p;
	struct intc_irqpin_iomem *i;
	struct resource *io[INTC_IRQPIN_REG_NR];
	struct irq_chip *irq_chip;
	void (*enable_fn)(struct irq_data *d);
	void (*disable_fn)(struct irq_data *d);
	const char *name = dev_name(dev);
	bool control_parent;
	unsigned int nirqs;
	int ref_irq;
	int ret;
	int k;

	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
	if (!p)
		return -ENOMEM;

	/* deal with driver instance configuration */
	of_property_read_u32(dev->of_node, "sense-bitfield-width",
			     &p->sense_bitfield_width);
	control_parent = of_property_read_bool(dev->of_node, "control-parent");
	if (!p->sense_bitfield_width)
		p->sense_bitfield_width = 4; /* default to 4 bits */

	p->pdev = pdev;
	platform_set_drvdata(pdev, p);

	config = of_device_get_match_data(dev);

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);

	/* get hold of register banks */
	memset(io, 0, sizeof(io));
	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
		io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
		if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
			dev_err(dev, "not enough IOMEM resources\n");
			ret = -EINVAL;
			goto err0;
		}
	}

	/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
	for (k = 0; k < INTC_IRQPIN_MAX; k++) {
		ret = platform_get_irq_optional(pdev, k);
		if (ret == -ENXIO)
			break;
		if (ret < 0)
			goto err0;

		p->irq[k].p = p;
		p->irq[k].requested_irq = ret;
	}

	nirqs = k;
	if (nirqs < 1) {
		dev_err(dev, "not enough IRQ resources\n");
		ret = -EINVAL;
		goto err0;
	}

	/* ioremap IOMEM and setup read/write callbacks */
	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
		i = &p->iomem[k];

		/* handle optional registers */
		if (!io[k])
			continue;

		switch (resource_size(io[k])) {
		case 1:
			i->width = 8;
			i->read = intc_irqpin_read8;
			i->write = intc_irqpin_write8;
			break;
		case 4:
			i->width = 32;
			i->read = intc_irqpin_read32;
			i->write = intc_irqpin_write32;
			break;
		default:
			dev_err(dev, "IOMEM size mismatch\n");
			ret = -EINVAL;
			goto err0;
		}

		i->iomem = devm_ioremap(dev, io[k]->start,
					resource_size(io[k]));
		if (!i->iomem) {
			dev_err(dev, "failed to remap IOMEM\n");
			ret = -ENXIO;
			goto err0;
		}
	}

	/* configure "individual IRQ mode" where needed */
	if (config && config->irlm_bit >= 0) {
		if (io[INTC_IRQPIN_REG_IRLM])
			intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
						      config->irlm_bit, 1, 1);
		else
			dev_warn(dev, "unable to select IRLM mode\n");
	}

	/* mask all interrupts using priority */
	for (k = 0; k < nirqs; k++)
		intc_irqpin_mask_unmask_prio(p, k, 1);

	/* clear all pending interrupts */
	intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);

	/* scan for shared interrupt lines */
	ref_irq = p->irq[0].requested_irq;
	p->shared_irqs = 1;
	for (k = 1; k < nirqs; k++) {
		if (ref_irq != p->irq[k].requested_irq) {
			p->shared_irqs = 0;
			break;
		}
	}

	/* use more severe masking method if requested */
	if (control_parent) {
		enable_fn = intc_irqpin_irq_enable_force;
		disable_fn = intc_irqpin_irq_disable_force;
	} else if (!p->shared_irqs) {
		enable_fn = intc_irqpin_irq_enable;
		disable_fn = intc_irqpin_irq_disable;
	} else {
		enable_fn = intc_irqpin_shared_irq_enable;
		disable_fn = intc_irqpin_shared_irq_disable;
	}

	irq_chip = &p->irq_chip;
	irq_chip->name = "intc-irqpin";
	irq_chip->irq_mask = disable_fn;
	irq_chip->irq_unmask = enable_fn;
	irq_chip->irq_set_type = intc_irqpin_irq_set_type;
	irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
	irq_chip->flags	= IRQCHIP_MASK_ON_SUSPEND;

	p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
					      &intc_irqpin_irq_domain_ops, p);
	if (!p->irq_domain) {
		ret = -ENXIO;
		dev_err(dev, "cannot initialize irq domain\n");
		goto err0;
	}

	irq_domain_set_pm_device(p->irq_domain, dev);

	if (p->shared_irqs) {
		/* request one shared interrupt */
		if (devm_request_irq(dev, p->irq[0].requested_irq,
				intc_irqpin_shared_irq_handler,
				IRQF_SHARED, name, p)) {
			dev_err(dev, "failed to request low IRQ\n");
			ret = -ENOENT;
			goto err1;
		}
	} else {
		/* request interrupts one by one */
		for (k = 0; k < nirqs; k++) {
			if (devm_request_irq(dev, p->irq[k].requested_irq,
					     intc_irqpin_irq_handler, 0, name,
					     &p->irq[k])) {
				dev_err(dev, "failed to request low IRQ\n");
				ret = -ENOENT;
				goto err1;
			}
		}
	}

	/* unmask all interrupts on prio level */
	for (k = 0; k < nirqs; k++)
		intc_irqpin_mask_unmask_prio(p, k, 0);

	dev_info(dev, "driving %d irqs\n", nirqs);

	return 0;

err1:
	irq_domain_remove(p->irq_domain);
err0:
	pm_runtime_put(dev);
	pm_runtime_disable(dev);
	return ret;
}

static int intc_irqpin_remove(struct platform_device *pdev)
{
	struct intc_irqpin_priv *p = platform_get_drvdata(pdev);

	irq_domain_remove(p->irq_domain);
	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	return 0;
}

static int __maybe_unused intc_irqpin_suspend(struct device *dev)
{
	struct intc_irqpin_priv *p = dev_get_drvdata(dev);

	if (atomic_read(&p->wakeup_path))
		device_set_wakeup_path(dev);

	return 0;
}

static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);

static struct platform_driver intc_irqpin_device_driver = {
	.probe		= intc_irqpin_probe,
	.remove		= intc_irqpin_remove,
	.driver		= {
		.name	= "renesas_intc_irqpin",
		.of_match_table = intc_irqpin_dt_ids,
		.pm	= &intc_irqpin_pm_ops,
	}
};

static int __init intc_irqpin_init(void)
{
	return platform_driver_register(&intc_irqpin_device_driver);
}
postcore_initcall(intc_irqpin_init);

static void __exit intc_irqpin_exit(void)
{
	platform_driver_unregister(&intc_irqpin_device_driver);
}
module_exit(intc_irqpin_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
bf973285	1	// SPDX-License-Identifier: GPL-2.0
44358048 MD	2	/*
	3	* Renesas INTC External IRQ Pin Driver
	4	*
	5	* Copyright (C) 2013 Magnus Damm
44358048 MD	6	*/
	7
	8	#include <linux/init.h>
894db164	9	#include <linux/of.h>
44358048 MD	10	#include <linux/platform_device.h>
	11	#include <linux/spinlock.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/ioport.h>
	14	#include <linux/io.h>
	15	#include <linux/irq.h>
	16	#include <linux/irqdomain.h>
	17	#include <linux/err.h>
	18	#include <linux/slab.h>
	19	#include <linux/module.h>
e03f9088	20	#include <linux/of_device.h>
705bc96c	21	#include <linux/pm_runtime.h>
44358048 MD	22
	23	#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
	24
	25	#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
	26	#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
	27	#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
	28	#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
	29	#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
e03f9088 MD	30	#define INTC_IRQPIN_REG_NR_MANDATORY 5
	31	#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
	32	#define INTC_IRQPIN_REG_NR 6
44358048 MD	33
	34	/* INTC external IRQ PIN hardware register access:
	35	*
	36	* SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
	37	* PRIO is read-write 32-bit with 4-bits per IRQ (**)
	38	* SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
	39	* MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
	40	* CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
	41	*
	42	* (*) May be accessed by more than one driver instance - lock needed
	43	* (**) Read-modify-write access by one driver instance - lock needed
	44	* (***) Accessed by one driver instance only - no locking needed
	45	*/
	46
	47	struct intc_irqpin_iomem {
	48	void __iomem *iomem;
	49	unsigned long (read)(void __iomem iomem);
	50	void (write)(void __iomem iomem, unsigned long data);
	51	int width;
862d3098	52	};
44358048 MD	53
	54	struct intc_irqpin_irq {
	55	int hw_irq;
33f958f2 MD	56	int requested_irq;
33f958f2 MD	57	int domain_irq;
44358048	58	struct intc_irqpin_priv *p;
862d3098	59	};
44358048 MD	60
	61	struct intc_irqpin_priv {
	62	struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
	63	struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
f9551a9c	64	unsigned int sense_bitfield_width;
44358048 MD	65	struct platform_device *pdev;
	66	struct irq_chip irq_chip;
	67	struct irq_domain *irq_domain;
66bf8252	68	atomic_t wakeup_path;
86e57ca7	69	unsigned shared_irqs:1;
427cc720	70	u8 shared_irq_mask;
44358048 MD	71	};
44358048 MD	72
86e57ca7	73	struct intc_irqpin_config {
b388bdf2	74	int irlm_bit; /* -1 if non-existent */
e03f9088 MD	75	};
e03f9088 MD	76
44358048 MD	77	static unsigned long intc_irqpin_read32(void __iomem *iomem)
	78	{
	79	return ioread32(iomem);
	80	}
	81
	82	static unsigned long intc_irqpin_read8(void __iomem *iomem)
	83	{
	84	return ioread8(iomem);
	85	}
	86
	87	static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
	88	{
	89	iowrite32(data, iomem);
	90	}
	91
	92	static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
	93	{
	94	iowrite8(data, iomem);
	95	}
	96
	97	static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
	98	int reg)
	99	{
	100	struct intc_irqpin_iomem *i = &p->iomem[reg];
862d3098	101
44358048 MD	102	return i->read(i->iomem);
	103	}
	104
	105	static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
	106	int reg, unsigned long data)
	107	{
	108	struct intc_irqpin_iomem *i = &p->iomem[reg];
862d3098	109
44358048 MD	110	i->write(i->iomem, data);
	111	}
	112
	113	static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
	114	int reg, int hw_irq)
	115	{
	116	return BIT((p->iomem[reg].width - 1) - hw_irq);
	117	}
	118
	119	static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
	120	int reg, int hw_irq)
	121	{
	122	intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
	123	}
	124
	125	static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
	126
	127	static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
	128	int reg, int shift,
	129	int width, int value)
	130	{
	131	unsigned long flags;
	132	unsigned long tmp;
	133
	134	raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
	135
	136	tmp = intc_irqpin_read(p, reg);
	137	tmp &= ~(((1 << width) - 1) << shift);
	138	tmp \|= value << shift;
	139	intc_irqpin_write(p, reg, tmp);
	140
	141	raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
	142	}
	143
	144	static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
	145	int irq, int do_mask)
	146	{
e55bc558 LP	147	/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
	148	int bitfield_width = 4;
	149	int shift = 32 - (irq + 1) * bitfield_width;
44358048 MD	150
	151	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
	152	shift, bitfield_width,
	153	do_mask ? 0 : (1 << bitfield_width) - 1);
	154	}
	155
	156	static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
	157	{
e55bc558	158	/* The SENSE register is assumed to be 32-bit. */
f9551a9c	159	int bitfield_width = p->sense_bitfield_width;
e55bc558	160	int shift = 32 - (irq + 1) * bitfield_width;
44358048 MD	161
	162	dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
	163
	164	if (value >= (1 << bitfield_width))
	165	return -EINVAL;
	166
	167	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
	168	bitfield_width, value);
	169	return 0;
	170	}
	171
	172	static void intc_irqpin_dbg(struct intc_irqpin_irq i, char str)
	173	{
	174	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
33f958f2	175	str, i->requested_irq, i->hw_irq, i->domain_irq);
44358048 MD	176	}
	177
	178	static void intc_irqpin_irq_enable(struct irq_data *d)
	179	{
	180	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	181	int hw_irq = irqd_to_hwirq(d);
	182
	183	intc_irqpin_dbg(&p->irq[hw_irq], "enable");
	184	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
	185	}
	186
	187	static void intc_irqpin_irq_disable(struct irq_data *d)
	188	{
	189	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	190	int hw_irq = irqd_to_hwirq(d);
	191
	192	intc_irqpin_dbg(&p->irq[hw_irq], "disable");
	193	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
	194	}
	195
427cc720 BH	196	static void intc_irqpin_shared_irq_enable(struct irq_data *d)
	197	{
	198	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	199	int hw_irq = irqd_to_hwirq(d);
	200
	201	intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
	202	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
	203
	204	p->shared_irq_mask &= ~BIT(hw_irq);
	205	}
	206
	207	static void intc_irqpin_shared_irq_disable(struct irq_data *d)
	208	{
	209	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	210	int hw_irq = irqd_to_hwirq(d);
	211
	212	intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
	213	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
	214
	215	p->shared_irq_mask \|= BIT(hw_irq);
	216	}
	217
44358048 MD	218	static void intc_irqpin_irq_enable_force(struct irq_data *d)
	219	{
	220	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
33f958f2	221	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
44358048 MD	222
44358048 MD	223	intc_irqpin_irq_enable(d);
d1b6aecd MD	224
	225	/* enable interrupt through parent interrupt controller,
	226	* assumes non-shared interrupt with 1:1 mapping
	227	* needed for busted IRQs on some SoCs like sh73a0
	228	*/
44358048 MD	229	irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
	230	}
	231
	232	static void intc_irqpin_irq_disable_force(struct irq_data *d)
	233	{
	234	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
33f958f2	235	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
44358048	236
d1b6aecd MD	237	/* disable interrupt through parent interrupt controller,
	238	* assumes non-shared interrupt with 1:1 mapping
	239	* needed for busted IRQs on some SoCs like sh73a0
	240	*/
44358048 MD	241	irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
	242	intc_irqpin_irq_disable(d);
	243	}
	244
	245	#define INTC_IRQ_SENSE_VALID 0x10
	246	#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
	247
	248	static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
	249	[IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
	250	[IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
	251	[IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
	252	[IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
	253	[IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
	254	};
	255
	256	static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
	257	{
	258	unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
	259	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	260
	261	if (!(value & INTC_IRQ_SENSE_VALID))
	262	return -EINVAL;
	263
	264	return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
	265	value ^ INTC_IRQ_SENSE_VALID);
	266	}
	267
705bc96c GU	268	static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
	269	{
	270	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
f4e209cd GU	271	int hw_irq = irqd_to_hwirq(d);
	272
	273	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
705bc96c	274	if (on)
66bf8252	275	atomic_inc(&p->wakeup_path);
705bc96c	276	else
66bf8252	277	atomic_dec(&p->wakeup_path);
705bc96c GU	278
	279	return 0;
	280	}
	281
44358048 MD	282	static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
	283	{
	284	struct intc_irqpin_irq *i = dev_id;
	285	struct intc_irqpin_priv *p = i->p;
	286	unsigned long bit;
	287
	288	intc_irqpin_dbg(i, "demux1");
	289	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
	290
	291	if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
	292	intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
	293	intc_irqpin_dbg(i, "demux2");
33f958f2	294	generic_handle_irq(i->domain_irq);
44358048 MD	295	return IRQ_HANDLED;
	296	}
	297	return IRQ_NONE;
	298	}
	299
427cc720 BH	300	static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
	301	{
	302	struct intc_irqpin_priv *p = dev_id;
	303	unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
	304	irqreturn_t status = IRQ_NONE;
	305	int k;
	306
	307	for (k = 0; k < 8; k++) {
	308	if (reg_source & BIT(7 - k)) {
	309	if (BIT(k) & p->shared_irq_mask)
	310	continue;
	311
	312	status \|= intc_irqpin_irq_handler(irq, &p->irq[k]);
	313	}
	314	}
	315
	316	return status;
	317	}
	318
769b5cf7 GU	319	/*
	320	* This lock class tells lockdep that INTC External IRQ Pin irqs are in a
	321	* different category than their parents, so it won't report false recursion.
	322	*/
	323	static struct lock_class_key intc_irqpin_irq_lock_class;
	324
39c3fd58 AL	325	/* And this is for the request mutex */
	326	static struct lock_class_key intc_irqpin_irq_request_class;
	327
44358048 MD	328	static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
	329	irq_hw_number_t hw)
	330	{
	331	struct intc_irqpin_priv *p = h->host_data;
	332
33f958f2 MD	333	p->irq[hw].domain_irq = virq;
	334	p->irq[hw].hw_irq = hw;
	335
44358048 MD	336	intc_irqpin_dbg(&p->irq[hw], "map");
44358048 MD	337	irq_set_chip_data(virq, h->host_data);
39c3fd58 AL	338	irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
39c3fd58 AL	339	&intc_irqpin_irq_request_class);
44358048	340	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
44358048 MD	341	return 0;
	342	}
	343
96009736	344	static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
44358048	345	.map = intc_irqpin_irq_domain_map,
9d833bbe	346	.xlate = irq_domain_xlate_twocell,
44358048 MD	347	};
44358048 MD	348
86e57ca7	349	static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
e03f9088	350	.irlm_bit = 23, /* ICR0.IRLM0 */
86e57ca7 GU	351	};
	352
	353	static const struct intc_irqpin_config intc_irqpin_rmobile = {
b388bdf2	354	.irlm_bit = -1,
e03f9088 MD	355	};
	356
	357	static const struct of_device_id intc_irqpin_dt_ids[] = {
	358	{ .compatible = "renesas,intc-irqpin", },
26c21dd9 UH	359	{ .compatible = "renesas,intc-irqpin-r8a7778",
26c21dd9 UH	360	.data = &intc_irqpin_irlm_r8a777x },
e03f9088	361	{ .compatible = "renesas,intc-irqpin-r8a7779",
26c21dd9	362	.data = &intc_irqpin_irlm_r8a777x },
86e57ca7 GU	363	{ .compatible = "renesas,intc-irqpin-r8a7740",
	364	.data = &intc_irqpin_rmobile },
	365	{ .compatible = "renesas,intc-irqpin-sh73a0",
	366	.data = &intc_irqpin_rmobile },
e03f9088 MD	367	{},
	368	};
	369	MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
	370
44358048 MD	371	static int intc_irqpin_probe(struct platform_device *pdev)
44358048 MD	372	{
42a5968c	373	const struct intc_irqpin_config *config;
36845f1b	374	struct device *dev = &pdev->dev;
44358048 MD	375	struct intc_irqpin_priv *p;
	376	struct intc_irqpin_iomem *i;
	377	struct resource *io[INTC_IRQPIN_REG_NR];
44358048 MD	378	struct irq_chip *irq_chip;
	379	void (enable_fn)(struct irq_data d);
	380	void (disable_fn)(struct irq_data d);
36845f1b	381	const char *name = dev_name(dev);
f9551a9c	382	bool control_parent;
1affe594	383	unsigned int nirqs;
427cc720	384	int ref_irq;
44358048 MD	385	int ret;
	386	int k;
	387
36845f1b	388	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
89626d4b	389	if (!p)
705bc96c	390	return -ENOMEM;
44358048 MD	391
44358048 MD	392	/* deal with driver instance configuration */
f9551a9c GU	393	of_property_read_u32(dev->of_node, "sense-bitfield-width",
	394	&p->sense_bitfield_width);
	395	control_parent = of_property_read_bool(dev->of_node, "control-parent");
	396	if (!p->sense_bitfield_width)
	397	p->sense_bitfield_width = 4; /* default to 4 bits */
44358048 MD	398
	399	p->pdev = pdev;
	400	platform_set_drvdata(pdev, p);
	401
42a5968c	402	config = of_device_get_match_data(dev);
705bc96c GU	403
	404	pm_runtime_enable(dev);
	405	pm_runtime_get_sync(dev);
	406
e03f9088 MD	407	/* get hold of register banks */
e03f9088 MD	408	memset(io, 0, sizeof(io));
44358048 MD	409	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
44358048 MD	410	io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
e03f9088	411	if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
36845f1b	412	dev_err(dev, "not enough IOMEM resources\n");
44358048	413	ret = -EINVAL;
08eba5ba	414	goto err0;
44358048 MD	415	}
	416	}
	417
	418	/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
	419	for (k = 0; k < INTC_IRQPIN_MAX; k++) {
31bd548f LP	420	ret = platform_get_irq_optional(pdev, k);
31bd548f LP	421	if (ret == -ENXIO)
44358048	422	break;
31bd548f LP	423	if (ret < 0)
31bd548f LP	424	goto err0;
44358048	425
44358048	426	p->irq[k].p = p;
31bd548f	427	p->irq[k].requested_irq = ret;
44358048 MD	428	}
44358048 MD	429
1affe594 GU	430	nirqs = k;
1affe594 GU	431	if (nirqs < 1) {
36845f1b	432	dev_err(dev, "not enough IRQ resources\n");
44358048	433	ret = -EINVAL;
08eba5ba	434	goto err0;
44358048 MD	435	}
	436
	437	/* ioremap IOMEM and setup read/write callbacks */
	438	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
	439	i = &p->iomem[k];
	440
e03f9088 MD	441	/* handle optional registers */
	442	if (!io[k])
	443	continue;
	444
44358048 MD	445	switch (resource_size(io[k])) {
	446	case 1:
	447	i->width = 8;
	448	i->read = intc_irqpin_read8;
	449	i->write = intc_irqpin_write8;
	450	break;
	451	case 4:
	452	i->width = 32;
	453	i->read = intc_irqpin_read32;
	454	i->write = intc_irqpin_write32;
	455	break;
	456	default:
36845f1b	457	dev_err(dev, "IOMEM size mismatch\n");
44358048	458	ret = -EINVAL;
08eba5ba	459	goto err0;
44358048 MD	460	}
44358048 MD	461
4bdc0d67	462	i->iomem = devm_ioremap(dev, io[k]->start,
bc714c8b	463	resource_size(io[k]));
44358048	464	if (!i->iomem) {
36845f1b	465	dev_err(dev, "failed to remap IOMEM\n");
44358048	466	ret = -ENXIO;
08eba5ba	467	goto err0;
44358048 MD	468	}
	469	}
	470
e03f9088	471	/* configure "individual IRQ mode" where needed */
b388bdf2	472	if (config && config->irlm_bit >= 0) {
e03f9088 MD	473	if (io[INTC_IRQPIN_REG_IRLM])
e03f9088 MD	474	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
86e57ca7	475	config->irlm_bit, 1, 1);
e03f9088 MD	476	else
	477	dev_warn(dev, "unable to select IRLM mode\n");
	478	}
	479
44358048	480	/* mask all interrupts using priority */
1affe594	481	for (k = 0; k < nirqs; k++)
44358048 MD	482	intc_irqpin_mask_unmask_prio(p, k, 1);
44358048 MD	483
427cc720 BH	484	/* clear all pending interrupts */
	485	intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
	486
	487	/* scan for shared interrupt lines */
	488	ref_irq = p->irq[0].requested_irq;
86e57ca7	489	p->shared_irqs = 1;
1affe594	490	for (k = 1; k < nirqs; k++) {
427cc720	491	if (ref_irq != p->irq[k].requested_irq) {
86e57ca7	492	p->shared_irqs = 0;
427cc720 BH	493	break;
	494	}
	495	}
	496
44358048	497	/* use more severe masking method if requested */
f9551a9c	498	if (control_parent) {
44358048 MD	499	enable_fn = intc_irqpin_irq_enable_force;
44358048 MD	500	disable_fn = intc_irqpin_irq_disable_force;
427cc720	501	} else if (!p->shared_irqs) {
44358048 MD	502	enable_fn = intc_irqpin_irq_enable;
44358048 MD	503	disable_fn = intc_irqpin_irq_disable;
427cc720 BH	504	} else {
	505	enable_fn = intc_irqpin_shared_irq_enable;
	506	disable_fn = intc_irqpin_shared_irq_disable;
44358048 MD	507	}
	508
	509	irq_chip = &p->irq_chip;
ec93b94a	510	irq_chip->name = "intc-irqpin";
44358048 MD	511	irq_chip->irq_mask = disable_fn;
44358048 MD	512	irq_chip->irq_unmask = enable_fn;
44358048	513	irq_chip->irq_set_type = intc_irqpin_irq_set_type;
705bc96c GU	514	irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
705bc96c GU	515	irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
44358048	516
1affe594 GU	517	p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
1affe594 GU	518	&intc_irqpin_irq_domain_ops, p);
44358048 MD	519	if (!p->irq_domain) {
44358048 MD	520	ret = -ENXIO;
36845f1b	521	dev_err(dev, "cannot initialize irq domain\n");
08eba5ba	522	goto err0;
44358048 MD	523	}
44358048 MD	524
c2ea6b9b MZ	525	irq_domain_set_pm_device(p->irq_domain, dev);
c2ea6b9b MZ	526
427cc720 BH	527	if (p->shared_irqs) {
427cc720 BH	528	/* request one shared interrupt */
36845f1b	529	if (devm_request_irq(dev, p->irq[0].requested_irq,
427cc720 BH	530	intc_irqpin_shared_irq_handler,
427cc720 BH	531	IRQF_SHARED, name, p)) {
36845f1b	532	dev_err(dev, "failed to request low IRQ\n");
44358048	533	ret = -ENOENT;
08eba5ba	534	goto err1;
44358048	535	}
427cc720 BH	536	} else {
427cc720 BH	537	/* request interrupts one by one */
1affe594	538	for (k = 0; k < nirqs; k++) {
36845f1b GU	539	if (devm_request_irq(dev, p->irq[k].requested_irq,
	540	intc_irqpin_irq_handler, 0, name,
	541	&p->irq[k])) {
	542	dev_err(dev, "failed to request low IRQ\n");
427cc720 BH	543	ret = -ENOENT;
	544	goto err1;
	545	}
	546	}
44358048 MD	547	}
44358048 MD	548
427cc720	549	/* unmask all interrupts on prio level */
1affe594	550	for (k = 0; k < nirqs; k++)
427cc720 BH	551	intc_irqpin_mask_unmask_prio(p, k, 0);
427cc720 BH	552
1affe594	553	dev_info(dev, "driving %d irqs\n", nirqs);
44358048	554
44358048 MD	555	return 0;
44358048 MD	556
44358048	557	err1:
08eba5ba	558	irq_domain_remove(p->irq_domain);
44358048	559	err0:
705bc96c GU	560	pm_runtime_put(dev);
705bc96c GU	561	pm_runtime_disable(dev);
44358048 MD	562	return ret;
	563	}
	564
	565	static int intc_irqpin_remove(struct platform_device *pdev)
	566	{
	567	struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
44358048 MD	568
44358048 MD	569	irq_domain_remove(p->irq_domain);
705bc96c GU	570	pm_runtime_put(&pdev->dev);
705bc96c GU	571	pm_runtime_disable(&pdev->dev);
44358048 MD	572	return 0;
	573	}
	574
66bf8252 GU	575	static int __maybe_unused intc_irqpin_suspend(struct device *dev)
	576	{
	577	struct intc_irqpin_priv *p = dev_get_drvdata(dev);
	578
	579	if (atomic_read(&p->wakeup_path))
	580	device_set_wakeup_path(dev);
	581
	582	return 0;
	583	}
	584
	585	static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
	586
44358048 MD	587	static struct platform_driver intc_irqpin_device_driver = {
	588	.probe = intc_irqpin_probe,
	589	.remove = intc_irqpin_remove,
	590	.driver = {
	591	.name = "renesas_intc_irqpin",
9d833bbe	592	.of_match_table = intc_irqpin_dt_ids,
66bf8252	593	.pm = &intc_irqpin_pm_ops,
44358048 MD	594	}
	595	};
	596
	597	static int __init intc_irqpin_init(void)
	598	{
	599	return platform_driver_register(&intc_irqpin_device_driver);
	600	}
	601	postcore_initcall(intc_irqpin_init);
	602
	603	static void __exit intc_irqpin_exit(void)
	604	{
	605	platform_driver_unregister(&intc_irqpin_device_driver);
	606	}
	607	module_exit(intc_irqpin_exit);
	608
	609	MODULE_AUTHOR("Magnus Damm");
	610	MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
	611	MODULE_LICENSE("GPL v2");