[thirdparty/kernel/stable.git] / drivers / irqchip / irq-sirfsoc.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * interrupt controller support for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/syscore_ops.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>

#define SIRFSOC_INT_RISC_MASK0		0x0018
#define SIRFSOC_INT_RISC_MASK1		0x001C
#define SIRFSOC_INT_RISC_LEVEL0		0x0020
#define SIRFSOC_INT_RISC_LEVEL1		0x0024
#define SIRFSOC_INIT_IRQ_ID		0x0038
#define SIRFSOC_INT_BASE_OFFSET		0x0004

#define SIRFSOC_NUM_IRQS		64
#define SIRFSOC_NUM_BANKS		(SIRFSOC_NUM_IRQS / 32)

static struct irq_domain *sirfsoc_irqdomain;

static void __iomem *sirfsoc_irq_get_regbase(void)
{
	return (void __iomem __force *)sirfsoc_irqdomain->host_data;
}

static __init void sirfsoc_alloc_gc(void __iomem *base)
{
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	unsigned int set = IRQ_LEVEL;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int i;

	irq_alloc_domain_generic_chips(sirfsoc_irqdomain, 32, 1, "irq_sirfsoc",
				       handle_level_irq, clr, set,
				       IRQ_GC_INIT_MASK_CACHE);

	for (i = 0; i < SIRFSOC_NUM_BANKS; i++) {
		gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, i * 32);
		gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET;
		ct = gc->chip_types;
		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;
		ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
	}
}

static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base = sirfsoc_irq_get_regbase();
	u32 irqstat;

	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
	handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
}

static int __init sirfsoc_irq_init(struct device_node *np,
	struct device_node *parent)
{
	void __iomem *base = of_iomap(np, 0);
	if (!base)
		panic("unable to map intc cpu registers\n");

	sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
						  &irq_generic_chip_ops, base);
	sirfsoc_alloc_gc(base);

	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);

	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);

	set_handle_irq(sirfsoc_handle_irq);

	return 0;
}
IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);

struct sirfsoc_irq_status {
	u32 mask0;
	u32 mask1;
	u32 level0;
	u32 level1;
};

static struct sirfsoc_irq_status sirfsoc_irq_st;

static int sirfsoc_irq_suspend(void)
{
	void __iomem *base = sirfsoc_irq_get_regbase();

	sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
	sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
	sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
	sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);

	return 0;
}

static void sirfsoc_irq_resume(void)
{
	void __iomem *base = sirfsoc_irq_get_regbase();

	writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
	writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
	writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
	writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
}

static struct syscore_ops sirfsoc_irq_syscore_ops = {
	.suspend	= sirfsoc_irq_suspend,
	.resume		= sirfsoc_irq_resume,
};

static int __init sirfsoc_irq_pm_init(void)
{
	if (!sirfsoc_irqdomain)
		return 0;

	register_syscore_ops(&sirfsoc_irq_syscore_ops);
	return 0;
}
device_initcall(sirfsoc_irq_pm_init);
Commit	Line	Data
a636cd6c	1	// SPDX-License-Identifier: GPL-2.0-or-later
60dbd768 AB	2	/*
	3	* interrupt controller support for CSR SiRFprimaII
	4	*
	5	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
60dbd768 AB	6	*/
	7
	8	#include <linux/init.h>
	9	#include <linux/io.h>
	10	#include <linux/irq.h>
	11	#include <linux/of.h>
	12	#include <linux/of_address.h>
41a83e06	13	#include <linux/irqchip.h>
60dbd768 AB	14	#include <linux/irqdomain.h>
	15	#include <linux/syscore_ops.h>
	16	#include <asm/mach/irq.h>
	17	#include <asm/exception.h>
60dbd768	18
d452bca8 TG	19	#define SIRFSOC_INT_RISC_MASK0 0x0018
	20	#define SIRFSOC_INT_RISC_MASK1 0x001C
	21	#define SIRFSOC_INT_RISC_LEVEL0 0x0020
	22	#define SIRFSOC_INT_RISC_LEVEL1 0x0024
60dbd768	23	#define SIRFSOC_INIT_IRQ_ID 0x0038
d452bca8	24	#define SIRFSOC_INT_BASE_OFFSET 0x0004
60dbd768	25
29eb51a7	26	#define SIRFSOC_NUM_IRQS 64
d452bca8	27	#define SIRFSOC_NUM_BANKS (SIRFSOC_NUM_IRQS / 32)
60dbd768 AB	28
	29	static struct irq_domain *sirfsoc_irqdomain;
	30
4a3691cc BD	31	static void __iomem *sirfsoc_irq_get_regbase(void)
	32	{
	33	return (void __iomem __force *)sirfsoc_irqdomain->host_data;
	34	}
	35
d452bca8	36	static __init void sirfsoc_alloc_gc(void __iomem *base)
60dbd768	37	{
29eb51a7	38	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
a87010ef	39	unsigned int set = IRQ_LEVEL;
d452bca8 TG	40	struct irq_chip_generic *gc;
	41	struct irq_chip_type *ct;
	42	int i;
	43
	44	irq_alloc_domain_generic_chips(sirfsoc_irqdomain, 32, 1, "irq_sirfsoc",
	45	handle_level_irq, clr, set,
	46	IRQ_GC_INIT_MASK_CACHE);
	47
	48	for (i = 0; i < SIRFSOC_NUM_BANKS; i++) {
	49	gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, i * 32);
	50	gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET;
	51	ct = gc->chip_types;
	52	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	53	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	54	ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
	55	}
60dbd768 AB	56	}
60dbd768 AB	57
8783dd3a	58	static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
60dbd768	59	{
4a3691cc	60	void __iomem *base = sirfsoc_irq_get_regbase();
c15018e9	61	u32 irqstat;
60dbd768 AB	62
60dbd768 AB	63	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
c15018e9	64	handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
60dbd768 AB	65	}
60dbd768 AB	66
7caf6852 BS	67	static int __init sirfsoc_irq_init(struct device_node *np,
7caf6852 BS	68	struct device_node *parent)
60dbd768 AB	69	{
	70	void __iomem *base = of_iomap(np, 0);
	71	if (!base)
	72	panic("unable to map intc cpu registers\n");
	73
29eb51a7	74	sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
d452bca8 TG	75	&irq_generic_chip_ops, base);
d452bca8 TG	76	sirfsoc_alloc_gc(base);
60dbd768 AB	77
	78	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
	79	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
	80
	81	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
	82	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
	83
	84	set_handle_irq(sirfsoc_handle_irq);
	85
	86	return 0;
	87	}
	88	IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
	89
	90	struct sirfsoc_irq_status {
	91	u32 mask0;
	92	u32 mask1;
	93	u32 level0;
	94	u32 level1;
	95	};
	96
	97	static struct sirfsoc_irq_status sirfsoc_irq_st;
	98
	99	static int sirfsoc_irq_suspend(void)
	100	{
4a3691cc	101	void __iomem *base = sirfsoc_irq_get_regbase();
60dbd768 AB	102
	103	sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
	104	sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
	105	sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
	106	sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
	107
	108	return 0;
	109	}
	110
	111	static void sirfsoc_irq_resume(void)
	112	{
4a3691cc	113	void __iomem *base = sirfsoc_irq_get_regbase();
60dbd768 AB	114
	115	writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
	116	writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
	117	writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
	118	writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
	119	}
	120
	121	static struct syscore_ops sirfsoc_irq_syscore_ops = {
	122	.suspend = sirfsoc_irq_suspend,
	123	.resume = sirfsoc_irq_resume,
	124	};
	125
	126	static int __init sirfsoc_irq_pm_init(void)
	127	{
	128	if (!sirfsoc_irqdomain)
	129	return 0;
	130
	131	register_syscore_ops(&sirfsoc_irq_syscore_ops);
	132	return 0;
	133	}
	134	device_initcall(sirfsoc_irq_pm_init);