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Commit | Line | Data |
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b79cb653 | 1 | /* |
ca06fa79 PB |
2 | * Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver |
3 | * | |
6d897616 | 4 | * Copyright (C) 2005 Steven Toth <stoth@linuxtv.org> |
ca06fa79 PB |
5 | * |
6 | * Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc> | |
7 | * | |
8 | * Support for CX24123/CX24113-NIM by Patrick Boettcher <pb@linuxtv.org> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
b79cb653 ST |
24 | |
25 | #include <linux/slab.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
b79cb653 ST |
28 | #include <linux/init.h> |
29 | ||
30 | #include "dvb_frontend.h" | |
31 | #include "cx24123.h" | |
32 | ||
a74b51fc VC |
33 | #define XTAL 10111000 |
34 | ||
70047f9c | 35 | static int force_band; |
93504abf ST |
36 | module_param(force_band, int, 0644); |
37 | MODULE_PARM_DESC(force_band, "Force a specific band select "\ | |
38 | "(1-9, default:off)."); | |
39 | ||
b79cb653 | 40 | static int debug; |
93504abf ST |
41 | module_param(debug, int, 0644); |
42 | MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); | |
ca06fa79 PB |
43 | |
44 | #define info(args...) do { printk(KERN_INFO "CX24123: " args); } while (0) | |
45 | #define err(args...) do { printk(KERN_ERR "CX24123: " args); } while (0) | |
46 | ||
b79cb653 ST |
47 | #define dprintk(args...) \ |
48 | do { \ | |
ca06fa79 PB |
49 | if (debug) { \ |
50 | printk(KERN_DEBUG "CX24123: %s: ", __func__); \ | |
51 | printk(args); \ | |
52 | } \ | |
b79cb653 ST |
53 | } while (0) |
54 | ||
93504abf ST |
55 | struct cx24123_state { |
56 | struct i2c_adapter *i2c; | |
57 | const struct cx24123_config *config; | |
b79cb653 ST |
58 | |
59 | struct dvb_frontend frontend; | |
60 | ||
b79cb653 ST |
61 | /* Some PLL specifics for tuning */ |
62 | u32 VCAarg; | |
63 | u32 VGAarg; | |
64 | u32 bandselectarg; | |
65 | u32 pllarg; | |
a74b51fc | 66 | u32 FILTune; |
b79cb653 | 67 | |
ca06fa79 PB |
68 | struct i2c_adapter tuner_i2c_adapter; |
69 | ||
70 | u8 demod_rev; | |
71 | ||
b79cb653 ST |
72 | /* The Demod/Tuner can't easily provide these, we cache them */ |
73 | u32 currentfreq; | |
74 | u32 currentsymbolrate; | |
75 | }; | |
76 | ||
e3b152bc | 77 | /* Various tuner defaults need to be established for a given symbol rate Sps */ |
93504abf | 78 | static struct cx24123_AGC_val { |
e3b152bc JS |
79 | u32 symbolrate_low; |
80 | u32 symbolrate_high; | |
e3b152bc JS |
81 | u32 VCAprogdata; |
82 | u32 VGAprogdata; | |
a74b51fc | 83 | u32 FILTune; |
e3b152bc JS |
84 | } cx24123_AGC_vals[] = |
85 | { | |
86 | { | |
87 | .symbolrate_low = 1000000, | |
88 | .symbolrate_high = 4999999, | |
a74b51fc VC |
89 | /* the specs recommend other values for VGA offsets, |
90 | but tests show they are wrong */ | |
0e4558ab YP |
91 | .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, |
92 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07, | |
93 | .FILTune = 0x27f /* 0.41 V */ | |
e3b152bc JS |
94 | }, |
95 | { | |
96 | .symbolrate_low = 5000000, | |
97 | .symbolrate_high = 14999999, | |
0e4558ab YP |
98 | .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, |
99 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f, | |
a74b51fc | 100 | .FILTune = 0x317 /* 0.90 V */ |
e3b152bc JS |
101 | }, |
102 | { | |
103 | .symbolrate_low = 15000000, | |
104 | .symbolrate_high = 45000000, | |
0e4558ab YP |
105 | .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180, |
106 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f, | |
107 | .FILTune = 0x145 /* 2.70 V */ | |
e3b152bc JS |
108 | }, |
109 | }; | |
110 | ||
111 | /* | |
112 | * Various tuner defaults need to be established for a given frequency kHz. | |
113 | * fixme: The bounds on the bands do not match the doc in real life. | |
114 | * fixme: Some of them have been moved, other might need adjustment. | |
115 | */ | |
93504abf | 116 | static struct cx24123_bandselect_val { |
e3b152bc JS |
117 | u32 freq_low; |
118 | u32 freq_high; | |
e3b152bc | 119 | u32 VCOdivider; |
e3b152bc JS |
120 | u32 progdata; |
121 | } cx24123_bandselect_vals[] = | |
122 | { | |
70047f9c | 123 | /* band 1 */ |
e3b152bc JS |
124 | { |
125 | .freq_low = 950000, | |
e3b152bc | 126 | .freq_high = 1074999, |
e3b152bc | 127 | .VCOdivider = 4, |
70047f9c | 128 | .progdata = (0 << 19) | (0 << 9) | 0x40, |
e3b152bc | 129 | }, |
70047f9c YP |
130 | |
131 | /* band 2 */ | |
e3b152bc JS |
132 | { |
133 | .freq_low = 1075000, | |
70047f9c YP |
134 | .freq_high = 1177999, |
135 | .VCOdivider = 4, | |
136 | .progdata = (0 << 19) | (0 << 9) | 0x80, | |
e3b152bc | 137 | }, |
70047f9c YP |
138 | |
139 | /* band 3 */ | |
e3b152bc | 140 | { |
70047f9c YP |
141 | .freq_low = 1178000, |
142 | .freq_high = 1295999, | |
e3b152bc | 143 | .VCOdivider = 2, |
70047f9c | 144 | .progdata = (0 << 19) | (1 << 9) | 0x01, |
e3b152bc | 145 | }, |
70047f9c YP |
146 | |
147 | /* band 4 */ | |
e3b152bc | 148 | { |
70047f9c YP |
149 | .freq_low = 1296000, |
150 | .freq_high = 1431999, | |
e3b152bc | 151 | .VCOdivider = 2, |
70047f9c | 152 | .progdata = (0 << 19) | (1 << 9) | 0x02, |
e3b152bc | 153 | }, |
70047f9c YP |
154 | |
155 | /* band 5 */ | |
e3b152bc | 156 | { |
70047f9c YP |
157 | .freq_low = 1432000, |
158 | .freq_high = 1575999, | |
e3b152bc | 159 | .VCOdivider = 2, |
70047f9c | 160 | .progdata = (0 << 19) | (1 << 9) | 0x04, |
e3b152bc | 161 | }, |
70047f9c YP |
162 | |
163 | /* band 6 */ | |
e3b152bc | 164 | { |
70047f9c | 165 | .freq_low = 1576000, |
e3b152bc | 166 | .freq_high = 1717999, |
e3b152bc | 167 | .VCOdivider = 2, |
70047f9c | 168 | .progdata = (0 << 19) | (1 << 9) | 0x08, |
e3b152bc | 169 | }, |
70047f9c YP |
170 | |
171 | /* band 7 */ | |
e3b152bc JS |
172 | { |
173 | .freq_low = 1718000, | |
174 | .freq_high = 1855999, | |
e3b152bc | 175 | .VCOdivider = 2, |
70047f9c | 176 | .progdata = (0 << 19) | (1 << 9) | 0x10, |
e3b152bc | 177 | }, |
70047f9c YP |
178 | |
179 | /* band 8 */ | |
e3b152bc JS |
180 | { |
181 | .freq_low = 1856000, | |
182 | .freq_high = 2035999, | |
e3b152bc | 183 | .VCOdivider = 2, |
70047f9c | 184 | .progdata = (0 << 19) | (1 << 9) | 0x20, |
e3b152bc | 185 | }, |
70047f9c YP |
186 | |
187 | /* band 9 */ | |
e3b152bc JS |
188 | { |
189 | .freq_low = 2036000, | |
70047f9c | 190 | .freq_high = 2150000, |
e3b152bc | 191 | .VCOdivider = 2, |
70047f9c | 192 | .progdata = (0 << 19) | (1 << 9) | 0x40, |
e3b152bc JS |
193 | }, |
194 | }; | |
195 | ||
b79cb653 ST |
196 | static struct { |
197 | u8 reg; | |
198 | u8 data; | |
199 | } cx24123_regdata[] = | |
200 | { | |
201 | {0x00, 0x03}, /* Reset system */ | |
202 | {0x00, 0x00}, /* Clear reset */ | |
0e4558ab YP |
203 | {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */ |
204 | {0x04, 0x10}, /* MPEG */ | |
205 | {0x05, 0x04}, /* MPEG */ | |
206 | {0x06, 0x31}, /* MPEG (default) */ | |
207 | {0x0b, 0x00}, /* Freq search start point (default) */ | |
208 | {0x0c, 0x00}, /* Demodulator sample gain (default) */ | |
d93f8860 | 209 | {0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */ |
0e4558ab YP |
210 | {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */ |
211 | {0x0f, 0xfe}, /* FEC search mask (all supported codes) */ | |
212 | {0x10, 0x01}, /* Default search inversion, no repeat (default) */ | |
213 | {0x16, 0x00}, /* Enable reading of frequency */ | |
214 | {0x17, 0x01}, /* Enable EsNO Ready Counter */ | |
215 | {0x1c, 0x80}, /* Enable error counter */ | |
216 | {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */ | |
217 | {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */ | |
218 | {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */ | |
219 | {0x29, 0x00}, /* DiSEqC LNB_DC off */ | |
220 | {0x2a, 0xb0}, /* DiSEqC Parameters (default) */ | |
221 | {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */ | |
222 | {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */ | |
b79cb653 ST |
223 | {0x2d, 0x00}, |
224 | {0x2e, 0x00}, | |
225 | {0x2f, 0x00}, | |
226 | {0x30, 0x00}, | |
227 | {0x31, 0x00}, | |
0e4558ab YP |
228 | {0x32, 0x8c}, /* DiSEqC Parameters (default) */ |
229 | {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */ | |
b79cb653 | 230 | {0x34, 0x00}, |
0e4558ab YP |
231 | {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */ |
232 | {0x36, 0x02}, /* DiSEqC Parameters (default) */ | |
233 | {0x37, 0x3a}, /* DiSEqC Parameters (default) */ | |
234 | {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */ | |
235 | {0x44, 0x00}, /* Constellation (default) */ | |
236 | {0x45, 0x00}, /* Symbol count (default) */ | |
237 | {0x46, 0x0d}, /* Symbol rate estimator on (default) */ | |
18c053b3 | 238 | {0x56, 0xc1}, /* Error Counter = Viterbi BER */ |
0e4558ab | 239 | {0x57, 0xff}, /* Error Counter Window (default) */ |
d93f8860 | 240 | {0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */ |
0e4558ab | 241 | {0x67, 0x83}, /* Non-DCII symbol clock */ |
b79cb653 ST |
242 | }; |
243 | ||
ca06fa79 PB |
244 | static int cx24123_i2c_writereg(struct cx24123_state *state, |
245 | u8 i2c_addr, int reg, int data) | |
b79cb653 ST |
246 | { |
247 | u8 buf[] = { reg, data }; | |
ca06fa79 PB |
248 | struct i2c_msg msg = { |
249 | .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 | |
250 | }; | |
b79cb653 ST |
251 | int err; |
252 | ||
ca06fa79 | 253 | /* printk(KERN_DEBUG "wr(%02x): %02x %02x\n", i2c_addr, reg, data); */ |
caf970e0 | 254 | |
93504abf ST |
255 | err = i2c_transfer(state->i2c, &msg, 1); |
256 | if (err != 1) { | |
b79cb653 | 257 | printk("%s: writereg error(err == %i, reg == 0x%02x," |
ca06fa79 PB |
258 | " data == 0x%02x)\n", __func__, err, reg, data); |
259 | return err; | |
b79cb653 ST |
260 | } |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
ca06fa79 | 265 | static int cx24123_i2c_readreg(struct cx24123_state *state, u8 i2c_addr, u8 reg) |
b79cb653 ST |
266 | { |
267 | int ret; | |
ca06fa79 | 268 | u8 b = 0; |
b79cb653 | 269 | struct i2c_msg msg[] = { |
ca06fa79 PB |
270 | { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, |
271 | { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &b, .len = 1 } | |
b79cb653 ST |
272 | }; |
273 | ||
274 | ret = i2c_transfer(state->i2c, msg, 2); | |
275 | ||
276 | if (ret != 2) { | |
ca06fa79 | 277 | err("%s: reg=0x%x (error=%d)\n", __func__, reg, ret); |
b79cb653 ST |
278 | return ret; |
279 | } | |
280 | ||
ca06fa79 | 281 | /* printk(KERN_DEBUG "rd(%02x): %02x %02x\n", i2c_addr, reg, b); */ |
caf970e0 | 282 | |
ca06fa79 | 283 | return b; |
b79cb653 ST |
284 | } |
285 | ||
ca06fa79 PB |
286 | #define cx24123_readreg(state, reg) \ |
287 | cx24123_i2c_readreg(state, state->config->demod_address, reg) | |
288 | #define cx24123_writereg(state, reg, val) \ | |
289 | cx24123_i2c_writereg(state, state->config->demod_address, reg, val) | |
290 | ||
93504abf ST |
291 | static int cx24123_set_inversion(struct cx24123_state *state, |
292 | fe_spectral_inversion_t inversion) | |
b79cb653 | 293 | { |
0e4558ab YP |
294 | u8 nom_reg = cx24123_readreg(state, 0x0e); |
295 | u8 auto_reg = cx24123_readreg(state, 0x10); | |
296 | ||
b79cb653 ST |
297 | switch (inversion) { |
298 | case INVERSION_OFF: | |
ca06fa79 | 299 | dprintk("inversion off\n"); |
0e4558ab YP |
300 | cx24123_writereg(state, 0x0e, nom_reg & ~0x80); |
301 | cx24123_writereg(state, 0x10, auto_reg | 0x80); | |
b79cb653 ST |
302 | break; |
303 | case INVERSION_ON: | |
ca06fa79 | 304 | dprintk("inversion on\n"); |
0e4558ab YP |
305 | cx24123_writereg(state, 0x0e, nom_reg | 0x80); |
306 | cx24123_writereg(state, 0x10, auto_reg | 0x80); | |
b79cb653 ST |
307 | break; |
308 | case INVERSION_AUTO: | |
ca06fa79 | 309 | dprintk("inversion auto\n"); |
0e4558ab | 310 | cx24123_writereg(state, 0x10, auto_reg & ~0x80); |
b79cb653 ST |
311 | break; |
312 | default: | |
313 | return -EINVAL; | |
314 | } | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
93504abf ST |
319 | static int cx24123_get_inversion(struct cx24123_state *state, |
320 | fe_spectral_inversion_t *inversion) | |
b79cb653 ST |
321 | { |
322 | u8 val; | |
323 | ||
324 | val = cx24123_readreg(state, 0x1b) >> 7; | |
325 | ||
caf970e0 | 326 | if (val == 0) { |
ca06fa79 | 327 | dprintk("read inversion off\n"); |
e3b152bc | 328 | *inversion = INVERSION_OFF; |
caf970e0 | 329 | } else { |
ca06fa79 | 330 | dprintk("read inversion on\n"); |
e3b152bc | 331 | *inversion = INVERSION_ON; |
caf970e0 | 332 | } |
b79cb653 ST |
333 | |
334 | return 0; | |
335 | } | |
336 | ||
93504abf | 337 | static int cx24123_set_fec(struct cx24123_state *state, fe_code_rate_t fec) |
b79cb653 | 338 | { |
0e4558ab YP |
339 | u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07; |
340 | ||
93504abf | 341 | if ((fec < FEC_NONE) || (fec > FEC_AUTO)) |
e3b152bc | 342 | fec = FEC_AUTO; |
b79cb653 | 343 | |
d12a9b91 | 344 | /* Set the soft decision threshold */ |
93504abf ST |
345 | if (fec == FEC_1_2) |
346 | cx24123_writereg(state, 0x43, | |
347 | cx24123_readreg(state, 0x43) | 0x01); | |
d12a9b91 | 348 | else |
93504abf ST |
349 | cx24123_writereg(state, 0x43, |
350 | cx24123_readreg(state, 0x43) & ~0x01); | |
d12a9b91 | 351 | |
b79cb653 | 352 | switch (fec) { |
b79cb653 | 353 | case FEC_1_2: |
ca06fa79 | 354 | dprintk("set FEC to 1/2\n"); |
0e4558ab YP |
355 | cx24123_writereg(state, 0x0e, nom_reg | 0x01); |
356 | cx24123_writereg(state, 0x0f, 0x02); | |
357 | break; | |
b79cb653 | 358 | case FEC_2_3: |
ca06fa79 | 359 | dprintk("set FEC to 2/3\n"); |
0e4558ab YP |
360 | cx24123_writereg(state, 0x0e, nom_reg | 0x02); |
361 | cx24123_writereg(state, 0x0f, 0x04); | |
362 | break; | |
b79cb653 | 363 | case FEC_3_4: |
ca06fa79 | 364 | dprintk("set FEC to 3/4\n"); |
0e4558ab YP |
365 | cx24123_writereg(state, 0x0e, nom_reg | 0x03); |
366 | cx24123_writereg(state, 0x0f, 0x08); | |
367 | break; | |
368 | case FEC_4_5: | |
ca06fa79 | 369 | dprintk("set FEC to 4/5\n"); |
0e4558ab YP |
370 | cx24123_writereg(state, 0x0e, nom_reg | 0x04); |
371 | cx24123_writereg(state, 0x0f, 0x10); | |
372 | break; | |
373 | case FEC_5_6: | |
ca06fa79 | 374 | dprintk("set FEC to 5/6\n"); |
0e4558ab YP |
375 | cx24123_writereg(state, 0x0e, nom_reg | 0x05); |
376 | cx24123_writereg(state, 0x0f, 0x20); | |
377 | break; | |
378 | case FEC_6_7: | |
ca06fa79 | 379 | dprintk("set FEC to 6/7\n"); |
0e4558ab YP |
380 | cx24123_writereg(state, 0x0e, nom_reg | 0x06); |
381 | cx24123_writereg(state, 0x0f, 0x40); | |
382 | break; | |
383 | case FEC_7_8: | |
ca06fa79 | 384 | dprintk("set FEC to 7/8\n"); |
0e4558ab YP |
385 | cx24123_writereg(state, 0x0e, nom_reg | 0x07); |
386 | cx24123_writereg(state, 0x0f, 0x80); | |
387 | break; | |
b79cb653 | 388 | case FEC_AUTO: |
ca06fa79 | 389 | dprintk("set FEC to auto\n"); |
0e4558ab YP |
390 | cx24123_writereg(state, 0x0f, 0xfe); |
391 | break; | |
b79cb653 ST |
392 | default: |
393 | return -EOPNOTSUPP; | |
394 | } | |
0e4558ab YP |
395 | |
396 | return 0; | |
b79cb653 ST |
397 | } |
398 | ||
93504abf | 399 | static int cx24123_get_fec(struct cx24123_state *state, fe_code_rate_t *fec) |
b79cb653 | 400 | { |
e3b152bc | 401 | int ret; |
b79cb653 | 402 | |
93504abf | 403 | ret = cx24123_readreg(state, 0x1b); |
e3b152bc JS |
404 | if (ret < 0) |
405 | return ret; | |
a74b51fc VC |
406 | ret = ret & 0x07; |
407 | ||
408 | switch (ret) { | |
b79cb653 | 409 | case 1: |
e3b152bc JS |
410 | *fec = FEC_1_2; |
411 | break; | |
a74b51fc | 412 | case 2: |
e3b152bc JS |
413 | *fec = FEC_2_3; |
414 | break; | |
a74b51fc | 415 | case 3: |
e3b152bc JS |
416 | *fec = FEC_3_4; |
417 | break; | |
a74b51fc | 418 | case 4: |
e3b152bc JS |
419 | *fec = FEC_4_5; |
420 | break; | |
a74b51fc | 421 | case 5: |
e3b152bc JS |
422 | *fec = FEC_5_6; |
423 | break; | |
a74b51fc VC |
424 | case 6: |
425 | *fec = FEC_6_7; | |
426 | break; | |
b79cb653 | 427 | case 7: |
e3b152bc JS |
428 | *fec = FEC_7_8; |
429 | break; | |
b79cb653 | 430 | default: |
0e4558ab YP |
431 | /* this can happen when there's no lock */ |
432 | *fec = FEC_NONE; | |
b79cb653 ST |
433 | } |
434 | ||
e3b152bc | 435 | return 0; |
b79cb653 ST |
436 | } |
437 | ||
0e4558ab YP |
438 | /* Approximation of closest integer of log2(a/b). It actually gives the |
439 | lowest integer i such that 2^i >= round(a/b) */ | |
440 | static u32 cx24123_int_log2(u32 a, u32 b) | |
441 | { | |
442 | u32 exp, nearest = 0; | |
443 | u32 div = a / b; | |
93504abf ST |
444 | if (a % b >= b / 2) |
445 | ++div; | |
446 | if (div < (1 << 31)) { | |
447 | for (exp = 1; div > exp; nearest++) | |
0e4558ab YP |
448 | exp += exp; |
449 | } | |
450 | return nearest; | |
451 | } | |
452 | ||
93504abf | 453 | static int cx24123_set_symbolrate(struct cx24123_state *state, u32 srate) |
b79cb653 | 454 | { |
0e4558ab | 455 | u32 tmp, sample_rate, ratio, sample_gain; |
a74b51fc VC |
456 | u8 pll_mult; |
457 | ||
458 | /* check if symbol rate is within limits */ | |
dea74869 PB |
459 | if ((srate > state->frontend.ops.info.symbol_rate_max) || |
460 | (srate < state->frontend.ops.info.symbol_rate_min)) | |
1ebcad77 | 461 | return -EOPNOTSUPP; |
a74b51fc VC |
462 | |
463 | /* choose the sampling rate high enough for the required operation, | |
464 | while optimizing the power consumed by the demodulator */ | |
465 | if (srate < (XTAL*2)/2) | |
466 | pll_mult = 2; | |
467 | else if (srate < (XTAL*3)/2) | |
468 | pll_mult = 3; | |
469 | else if (srate < (XTAL*4)/2) | |
470 | pll_mult = 4; | |
471 | else if (srate < (XTAL*5)/2) | |
472 | pll_mult = 5; | |
473 | else if (srate < (XTAL*6)/2) | |
474 | pll_mult = 6; | |
475 | else if (srate < (XTAL*7)/2) | |
476 | pll_mult = 7; | |
477 | else if (srate < (XTAL*8)/2) | |
478 | pll_mult = 8; | |
479 | else | |
480 | pll_mult = 9; | |
481 | ||
482 | ||
483 | sample_rate = pll_mult * XTAL; | |
b79cb653 | 484 | |
a74b51fc VC |
485 | /* |
486 | SYSSymbolRate[21:0] = (srate << 23) / sample_rate | |
b79cb653 | 487 | |
a74b51fc VC |
488 | We have to use 32 bit unsigned arithmetic without precision loss. |
489 | The maximum srate is 45000000 or 0x02AEA540. This number has | |
490 | only 6 clear bits on top, hence we can shift it left only 6 bits | |
491 | at a time. Borrowed from cx24110.c | |
492 | */ | |
b79cb653 | 493 | |
a74b51fc VC |
494 | tmp = srate << 6; |
495 | ratio = tmp / sample_rate; | |
496 | ||
497 | tmp = (tmp % sample_rate) << 6; | |
498 | ratio = (ratio << 6) + (tmp / sample_rate); | |
499 | ||
500 | tmp = (tmp % sample_rate) << 6; | |
501 | ratio = (ratio << 6) + (tmp / sample_rate); | |
502 | ||
503 | tmp = (tmp % sample_rate) << 5; | |
504 | ratio = (ratio << 5) + (tmp / sample_rate); | |
505 | ||
506 | ||
507 | cx24123_writereg(state, 0x01, pll_mult * 6); | |
508 | ||
93504abf ST |
509 | cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f); |
510 | cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff); | |
511 | cx24123_writereg(state, 0x0a, ratio & 0xff); | |
a74b51fc | 512 | |
0e4558ab YP |
513 | /* also set the demodulator sample gain */ |
514 | sample_gain = cx24123_int_log2(sample_rate, srate); | |
515 | tmp = cx24123_readreg(state, 0x0c) & ~0xe0; | |
516 | cx24123_writereg(state, 0x0c, tmp | sample_gain << 5); | |
517 | ||
ca06fa79 PB |
518 | dprintk("srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", |
519 | srate, ratio, sample_rate, sample_gain); | |
b79cb653 ST |
520 | |
521 | return 0; | |
522 | } | |
523 | ||
524 | /* | |
93504abf ST |
525 | * Based on the required frequency and symbolrate, the tuner AGC has |
526 | * to be configured and the correct band selected. | |
527 | * Calculate those values. | |
b79cb653 | 528 | */ |
93504abf ST |
529 | static int cx24123_pll_calculate(struct dvb_frontend *fe, |
530 | struct dvb_frontend_parameters *p) | |
b79cb653 ST |
531 | { |
532 | struct cx24123_state *state = fe->demodulator_priv; | |
e3b152bc JS |
533 | u32 ndiv = 0, adiv = 0, vco_div = 0; |
534 | int i = 0; | |
a74b51fc | 535 | int pump = 2; |
70047f9c | 536 | int band = 0; |
0496daa7 | 537 | int num_bands = ARRAY_SIZE(cx24123_bandselect_vals); |
93504abf ST |
538 | struct cx24123_bandselect_val *bsv = NULL; |
539 | struct cx24123_AGC_val *agcv = NULL; | |
b79cb653 ST |
540 | |
541 | /* Defaults for low freq, low rate */ | |
542 | state->VCAarg = cx24123_AGC_vals[0].VCAprogdata; | |
543 | state->VGAarg = cx24123_AGC_vals[0].VGAprogdata; | |
544 | state->bandselectarg = cx24123_bandselect_vals[0].progdata; | |
545 | vco_div = cx24123_bandselect_vals[0].VCOdivider; | |
546 | ||
93504abf ST |
547 | /* For the given symbol rate, determine the VCA, VGA and |
548 | * FILTUNE programming bits */ | |
549 | for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) { | |
550 | agcv = &cx24123_AGC_vals[i]; | |
551 | if ((agcv->symbolrate_low <= p->u.qpsk.symbol_rate) && | |
552 | (agcv->symbolrate_high >= p->u.qpsk.symbol_rate)) { | |
553 | state->VCAarg = agcv->VCAprogdata; | |
554 | state->VGAarg = agcv->VGAprogdata; | |
555 | state->FILTune = agcv->FILTune; | |
b79cb653 ST |
556 | } |
557 | } | |
558 | ||
70047f9c | 559 | /* determine the band to use */ |
93504abf ST |
560 | if (force_band < 1 || force_band > num_bands) { |
561 | for (i = 0; i < num_bands; i++) { | |
562 | bsv = &cx24123_bandselect_vals[i]; | |
563 | if ((bsv->freq_low <= p->frequency) && | |
564 | (bsv->freq_high >= p->frequency)) | |
70047f9c | 565 | band = i; |
b79cb653 | 566 | } |
93504abf | 567 | } else |
70047f9c YP |
568 | band = force_band - 1; |
569 | ||
570 | state->bandselectarg = cx24123_bandselect_vals[band].progdata; | |
571 | vco_div = cx24123_bandselect_vals[band].VCOdivider; | |
572 | ||
573 | /* determine the charge pump current */ | |
93504abf ST |
574 | if (p->frequency < (cx24123_bandselect_vals[band].freq_low + |
575 | cx24123_bandselect_vals[band].freq_high) / 2) | |
70047f9c YP |
576 | pump = 0x01; |
577 | else | |
578 | pump = 0x02; | |
b79cb653 ST |
579 | |
580 | /* Determine the N/A dividers for the requested lband freq (in kHz). */ | |
93504abf ST |
581 | /* Note: the reference divider R=10, frequency is in KHz, |
582 | * XTAL is in Hz */ | |
583 | ndiv = (((p->frequency * vco_div * 10) / | |
584 | (2 * XTAL / 1000)) / 32) & 0x1ff; | |
585 | adiv = (((p->frequency * vco_div * 10) / | |
586 | (2 * XTAL / 1000)) % 32) & 0x1f; | |
b79cb653 | 587 | |
9b5a4a67 ST |
588 | if (adiv == 0 && ndiv > 0) |
589 | ndiv--; | |
b79cb653 | 590 | |
93504abf ST |
591 | /* control bits 11, refdiv 11, charge pump polarity 1, |
592 | * charge pump current, ndiv, adiv */ | |
593 | state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | | |
594 | (pump << 14) | (ndiv << 5) | adiv; | |
b79cb653 ST |
595 | |
596 | return 0; | |
597 | } | |
598 | ||
599 | /* | |
600 | * Tuner data is 21 bits long, must be left-aligned in data. | |
93504abf ST |
601 | * Tuner cx24109 is written through a dedicated 3wire interface |
602 | * on the demod chip. | |
b79cb653 | 603 | */ |
93504abf ST |
604 | static int cx24123_pll_writereg(struct dvb_frontend *fe, |
605 | struct dvb_frontend_parameters *p, u32 data) | |
b79cb653 ST |
606 | { |
607 | struct cx24123_state *state = fe->demodulator_priv; | |
0144f314 | 608 | unsigned long timeout; |
b79cb653 | 609 | |
ca06fa79 | 610 | dprintk("pll writereg called, data=0x%08x\n", data); |
caf970e0 | 611 | |
b79cb653 ST |
612 | /* align the 21 bytes into to bit23 boundary */ |
613 | data = data << 3; | |
614 | ||
615 | /* Reset the demod pll word length to 0x15 bits */ | |
616 | cx24123_writereg(state, 0x21, 0x15); | |
617 | ||
b79cb653 | 618 | /* write the msb 8 bits, wait for the send to be completed */ |
0144f314 | 619 | timeout = jiffies + msecs_to_jiffies(40); |
e3b152bc | 620 | cx24123_writereg(state, 0x22, (data >> 16) & 0xff); |
0144f314 ST |
621 | while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { |
622 | if (time_after(jiffies, timeout)) { | |
ca06fa79 PB |
623 | err("%s: demodulator is not responding, "\ |
624 | "possibly hung, aborting.\n", __func__); | |
b79cb653 ST |
625 | return -EREMOTEIO; |
626 | } | |
0144f314 | 627 | msleep(10); |
b79cb653 ST |
628 | } |
629 | ||
b79cb653 | 630 | /* send another 8 bytes, wait for the send to be completed */ |
0144f314 | 631 | timeout = jiffies + msecs_to_jiffies(40); |
93504abf | 632 | cx24123_writereg(state, 0x22, (data >> 8) & 0xff); |
0144f314 ST |
633 | while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { |
634 | if (time_after(jiffies, timeout)) { | |
ca06fa79 PB |
635 | err("%s: demodulator is not responding, "\ |
636 | "possibly hung, aborting.\n", __func__); | |
b79cb653 ST |
637 | return -EREMOTEIO; |
638 | } | |
0144f314 | 639 | msleep(10); |
b79cb653 ST |
640 | } |
641 | ||
93504abf ST |
642 | /* send the lower 5 bits of this byte, padded with 3 LBB, |
643 | * wait for the send to be completed */ | |
0144f314 | 644 | timeout = jiffies + msecs_to_jiffies(40); |
93504abf | 645 | cx24123_writereg(state, 0x22, (data) & 0xff); |
0144f314 ST |
646 | while ((cx24123_readreg(state, 0x20) & 0x80)) { |
647 | if (time_after(jiffies, timeout)) { | |
ca06fa79 PB |
648 | err("%s: demodulator is not responding," \ |
649 | "possibly hung, aborting.\n", __func__); | |
b79cb653 ST |
650 | return -EREMOTEIO; |
651 | } | |
0144f314 | 652 | msleep(10); |
b79cb653 ST |
653 | } |
654 | ||
655 | /* Trigger the demod to configure the tuner */ | |
656 | cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2); | |
657 | cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd); | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
93504abf ST |
662 | static int cx24123_pll_tune(struct dvb_frontend *fe, |
663 | struct dvb_frontend_parameters *p) | |
b79cb653 ST |
664 | { |
665 | struct cx24123_state *state = fe->demodulator_priv; | |
a74b51fc VC |
666 | u8 val; |
667 | ||
668 | dprintk("frequency=%i\n", p->frequency); | |
b79cb653 | 669 | |
e3b152bc | 670 | if (cx24123_pll_calculate(fe, p) != 0) { |
ca06fa79 | 671 | err("%s: cx24123_pll_calcutate failed\n", __func__); |
b79cb653 ST |
672 | return -EINVAL; |
673 | } | |
674 | ||
675 | /* Write the new VCO/VGA */ | |
676 | cx24123_pll_writereg(fe, p, state->VCAarg); | |
677 | cx24123_pll_writereg(fe, p, state->VGAarg); | |
678 | ||
679 | /* Write the new bandselect and pll args */ | |
680 | cx24123_pll_writereg(fe, p, state->bandselectarg); | |
681 | cx24123_pll_writereg(fe, p, state->pllarg); | |
682 | ||
a74b51fc VC |
683 | /* set the FILTUNE voltage */ |
684 | val = cx24123_readreg(state, 0x28) & ~0x3; | |
685 | cx24123_writereg(state, 0x27, state->FILTune >> 2); | |
686 | cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3)); | |
687 | ||
ca06fa79 PB |
688 | dprintk("pll tune VCA=%d, band=%d, pll=%d\n", state->VCAarg, |
689 | state->bandselectarg, state->pllarg); | |
caf970e0 | 690 | |
b79cb653 ST |
691 | return 0; |
692 | } | |
693 | ||
ca06fa79 PB |
694 | |
695 | /* | |
696 | * 0x23: | |
697 | * [7:7] = BTI enabled | |
698 | * [6:6] = I2C repeater enabled | |
699 | * [5:5] = I2C repeater start | |
700 | * [0:0] = BTI start | |
701 | */ | |
702 | ||
703 | /* mode == 1 -> i2c-repeater, 0 -> bti */ | |
704 | static int cx24123_repeater_mode(struct cx24123_state *state, u8 mode, u8 start) | |
705 | { | |
706 | u8 r = cx24123_readreg(state, 0x23) & 0x1e; | |
707 | if (mode) | |
708 | r |= (1 << 6) | (start << 5); | |
709 | else | |
710 | r |= (1 << 7) | (start); | |
711 | return cx24123_writereg(state, 0x23, r); | |
712 | } | |
713 | ||
93504abf | 714 | static int cx24123_initfe(struct dvb_frontend *fe) |
b79cb653 ST |
715 | { |
716 | struct cx24123_state *state = fe->demodulator_priv; | |
717 | int i; | |
718 | ||
ca06fa79 | 719 | dprintk("init frontend\n"); |
caf970e0 | 720 | |
b79cb653 | 721 | /* Configure the demod to a good set of defaults */ |
0496daa7 | 722 | for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++) |
93504abf ST |
723 | cx24123_writereg(state, cx24123_regdata[i].reg, |
724 | cx24123_regdata[i].data); | |
b79cb653 | 725 | |
ef76856d | 726 | /* Set the LNB polarity */ |
93504abf ST |
727 | if (state->config->lnb_polarity) |
728 | cx24123_writereg(state, 0x32, | |
729 | cx24123_readreg(state, 0x32) | 0x02); | |
ef76856d | 730 | |
ca06fa79 | 731 | if (state->config->dont_use_pll) |
93504abf | 732 | cx24123_repeater_mode(state, 1, 0); |
ca06fa79 | 733 | |
b79cb653 ST |
734 | return 0; |
735 | } | |
736 | ||
93504abf ST |
737 | static int cx24123_set_voltage(struct dvb_frontend *fe, |
738 | fe_sec_voltage_t voltage) | |
b79cb653 ST |
739 | { |
740 | struct cx24123_state *state = fe->demodulator_priv; | |
741 | u8 val; | |
742 | ||
cd20ca9f | 743 | val = cx24123_readreg(state, 0x29) & ~0x40; |
1c956a3a | 744 | |
cd20ca9f AQ |
745 | switch (voltage) { |
746 | case SEC_VOLTAGE_13: | |
ca06fa79 | 747 | dprintk("setting voltage 13V\n"); |
ccd214b2 | 748 | return cx24123_writereg(state, 0x29, val & 0x7f); |
cd20ca9f | 749 | case SEC_VOLTAGE_18: |
ca06fa79 | 750 | dprintk("setting voltage 18V\n"); |
ccd214b2 | 751 | return cx24123_writereg(state, 0x29, val | 0x80); |
ef76856d YP |
752 | case SEC_VOLTAGE_OFF: |
753 | /* already handled in cx88-dvb */ | |
754 | return 0; | |
cd20ca9f AQ |
755 | default: |
756 | return -EINVAL; | |
757 | }; | |
1c956a3a VC |
758 | |
759 | return 0; | |
b79cb653 ST |
760 | } |
761 | ||
dce1dfc2 YP |
762 | /* wait for diseqc queue to become ready (or timeout) */ |
763 | static void cx24123_wait_for_diseqc(struct cx24123_state *state) | |
764 | { | |
765 | unsigned long timeout = jiffies + msecs_to_jiffies(200); | |
766 | while (!(cx24123_readreg(state, 0x29) & 0x40)) { | |
93504abf | 767 | if (time_after(jiffies, timeout)) { |
ca06fa79 PB |
768 | err("%s: diseqc queue not ready, " \ |
769 | "command may be lost.\n", __func__); | |
dce1dfc2 YP |
770 | break; |
771 | } | |
772 | msleep(10); | |
773 | } | |
774 | } | |
775 | ||
93504abf ST |
776 | static int cx24123_send_diseqc_msg(struct dvb_frontend *fe, |
777 | struct dvb_diseqc_master_cmd *cmd) | |
b79cb653 | 778 | { |
a74b51fc | 779 | struct cx24123_state *state = fe->demodulator_priv; |
cd20ca9f | 780 | int i, val, tone; |
a74b51fc | 781 | |
ca06fa79 | 782 | dprintk("\n"); |
b79cb653 | 783 | |
cd20ca9f AQ |
784 | /* stop continuous tone if enabled */ |
785 | tone = cx24123_readreg(state, 0x29); | |
786 | if (tone & 0x10) | |
787 | cx24123_writereg(state, 0x29, tone & ~0x50); | |
a74b51fc | 788 | |
dce1dfc2 YP |
789 | /* wait for diseqc queue ready */ |
790 | cx24123_wait_for_diseqc(state); | |
791 | ||
a74b51fc | 792 | /* select tone mode */ |
cd20ca9f | 793 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); |
a74b51fc VC |
794 | |
795 | for (i = 0; i < cmd->msg_len; i++) | |
796 | cx24123_writereg(state, 0x2C + i, cmd->msg[i]); | |
797 | ||
798 | val = cx24123_readreg(state, 0x29); | |
93504abf ST |
799 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | |
800 | ((cmd->msg_len-3) & 3)); | |
a74b51fc | 801 | |
dce1dfc2 YP |
802 | /* wait for diseqc message to finish sending */ |
803 | cx24123_wait_for_diseqc(state); | |
a74b51fc | 804 | |
cd20ca9f | 805 | /* restart continuous tone if enabled */ |
93504abf | 806 | if (tone & 0x10) |
cd20ca9f | 807 | cx24123_writereg(state, 0x29, tone & ~0x40); |
cd20ca9f | 808 | |
a74b51fc VC |
809 | return 0; |
810 | } | |
811 | ||
93504abf ST |
812 | static int cx24123_diseqc_send_burst(struct dvb_frontend *fe, |
813 | fe_sec_mini_cmd_t burst) | |
a74b51fc VC |
814 | { |
815 | struct cx24123_state *state = fe->demodulator_priv; | |
cd20ca9f | 816 | int val, tone; |
a74b51fc | 817 | |
ca06fa79 | 818 | dprintk("\n"); |
a74b51fc | 819 | |
cd20ca9f AQ |
820 | /* stop continuous tone if enabled */ |
821 | tone = cx24123_readreg(state, 0x29); | |
822 | if (tone & 0x10) | |
823 | cx24123_writereg(state, 0x29, tone & ~0x50); | |
a74b51fc | 824 | |
cd20ca9f | 825 | /* wait for diseqc queue ready */ |
dce1dfc2 YP |
826 | cx24123_wait_for_diseqc(state); |
827 | ||
a74b51fc | 828 | /* select tone mode */ |
cd20ca9f AQ |
829 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4); |
830 | msleep(30); | |
a74b51fc | 831 | val = cx24123_readreg(state, 0x29); |
a74b51fc VC |
832 | if (burst == SEC_MINI_A) |
833 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00)); | |
834 | else if (burst == SEC_MINI_B) | |
835 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08)); | |
836 | else | |
837 | return -EINVAL; | |
838 | ||
dce1dfc2 | 839 | cx24123_wait_for_diseqc(state); |
cd20ca9f | 840 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); |
a74b51fc | 841 | |
cd20ca9f | 842 | /* restart continuous tone if enabled */ |
93504abf | 843 | if (tone & 0x10) |
cd20ca9f | 844 | cx24123_writereg(state, 0x29, tone & ~0x40); |
93504abf | 845 | |
a74b51fc | 846 | return 0; |
b79cb653 ST |
847 | } |
848 | ||
93504abf | 849 | static int cx24123_read_status(struct dvb_frontend *fe, fe_status_t *status) |
b79cb653 ST |
850 | { |
851 | struct cx24123_state *state = fe->demodulator_priv; | |
b79cb653 | 852 | int sync = cx24123_readreg(state, 0x14); |
b79cb653 ST |
853 | |
854 | *status = 0; | |
ca06fa79 PB |
855 | if (state->config->dont_use_pll) { |
856 | u32 tun_status = 0; | |
857 | if (fe->ops.tuner_ops.get_status) | |
858 | fe->ops.tuner_ops.get_status(fe, &tun_status); | |
859 | if (tun_status & TUNER_STATUS_LOCKED) | |
860 | *status |= FE_HAS_SIGNAL; | |
861 | } else { | |
862 | int lock = cx24123_readreg(state, 0x20); | |
863 | if (lock & 0x01) | |
864 | *status |= FE_HAS_SIGNAL; | |
865 | } | |
866 | ||
a74b51fc | 867 | if (sync & 0x02) |
d93f8860 | 868 | *status |= FE_HAS_CARRIER; /* Phase locked */ |
b79cb653 ST |
869 | if (sync & 0x04) |
870 | *status |= FE_HAS_VITERBI; | |
d93f8860 MCC |
871 | |
872 | /* Reed-Solomon Status */ | |
b79cb653 | 873 | if (sync & 0x08) |
a74b51fc | 874 | *status |= FE_HAS_SYNC; |
b79cb653 | 875 | if (sync & 0x80) |
d93f8860 | 876 | *status |= FE_HAS_LOCK; /*Full Sync */ |
b79cb653 ST |
877 | |
878 | return 0; | |
879 | } | |
880 | ||
881 | /* | |
93504abf ST |
882 | * Configured to return the measurement of errors in blocks, |
883 | * because no UCBLOCKS value is available, so this value doubles up | |
884 | * to satisfy both measurements. | |
b79cb653 | 885 | */ |
ca06fa79 | 886 | static int cx24123_read_ber(struct dvb_frontend *fe, u32 *ber) |
b79cb653 ST |
887 | { |
888 | struct cx24123_state *state = fe->demodulator_priv; | |
889 | ||
18c053b3 YP |
890 | /* The true bit error rate is this value divided by |
891 | the window size (set as 256 * 255) */ | |
892 | *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) | | |
b79cb653 | 893 | (cx24123_readreg(state, 0x1d) << 8 | |
18c053b3 | 894 | cx24123_readreg(state, 0x1e)); |
caf970e0 | 895 | |
ca06fa79 | 896 | dprintk("BER = %d\n", *ber); |
b79cb653 ST |
897 | |
898 | return 0; | |
899 | } | |
900 | ||
ca06fa79 PB |
901 | static int cx24123_read_signal_strength(struct dvb_frontend *fe, |
902 | u16 *signal_strength) | |
b79cb653 ST |
903 | { |
904 | struct cx24123_state *state = fe->demodulator_priv; | |
d93f8860 | 905 | |
93504abf ST |
906 | /* larger = better */ |
907 | *signal_strength = cx24123_readreg(state, 0x3b) << 8; | |
b79cb653 | 908 | |
ca06fa79 | 909 | dprintk("Signal strength = %d\n", *signal_strength); |
caf970e0 | 910 | |
b79cb653 ST |
911 | return 0; |
912 | } | |
913 | ||
ca06fa79 | 914 | static int cx24123_read_snr(struct dvb_frontend *fe, u16 *snr) |
b79cb653 ST |
915 | { |
916 | struct cx24123_state *state = fe->demodulator_priv; | |
b79cb653 | 917 | |
18c053b3 YP |
918 | /* Inverted raw Es/N0 count, totally bogus but better than the |
919 | BER threshold. */ | |
920 | *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) | | |
921 | (u16)cx24123_readreg(state, 0x19)); | |
caf970e0 | 922 | |
ca06fa79 | 923 | dprintk("read S/N index = %d\n", *snr); |
caf970e0 | 924 | |
b79cb653 ST |
925 | return 0; |
926 | } | |
927 | ||
ca06fa79 PB |
928 | static int cx24123_set_frontend(struct dvb_frontend *fe, |
929 | struct dvb_frontend_parameters *p) | |
b79cb653 ST |
930 | { |
931 | struct cx24123_state *state = fe->demodulator_priv; | |
932 | ||
ca06fa79 | 933 | dprintk("\n"); |
caf970e0 | 934 | |
b79cb653 ST |
935 | if (state->config->set_ts_params) |
936 | state->config->set_ts_params(fe, 0); | |
937 | ||
93504abf | 938 | state->currentfreq = p->frequency; |
e3b152bc | 939 | state->currentsymbolrate = p->u.qpsk.symbol_rate; |
b79cb653 ST |
940 | |
941 | cx24123_set_inversion(state, p->inversion); | |
942 | cx24123_set_fec(state, p->u.qpsk.fec_inner); | |
943 | cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate); | |
ca06fa79 PB |
944 | |
945 | if (!state->config->dont_use_pll) | |
946 | cx24123_pll_tune(fe, p); | |
947 | else if (fe->ops.tuner_ops.set_params) | |
948 | fe->ops.tuner_ops.set_params(fe, p); | |
949 | else | |
950 | err("it seems I don't have a tuner..."); | |
b79cb653 | 951 | |
25985edc | 952 | /* Enable automatic acquisition and reset cycle */ |
e3b152bc | 953 | cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07)); |
b79cb653 ST |
954 | cx24123_writereg(state, 0x00, 0x10); |
955 | cx24123_writereg(state, 0x00, 0); | |
956 | ||
ca06fa79 PB |
957 | if (state->config->agc_callback) |
958 | state->config->agc_callback(fe); | |
959 | ||
b79cb653 ST |
960 | return 0; |
961 | } | |
962 | ||
93504abf ST |
963 | static int cx24123_get_frontend(struct dvb_frontend *fe, |
964 | struct dvb_frontend_parameters *p) | |
b79cb653 ST |
965 | { |
966 | struct cx24123_state *state = fe->demodulator_priv; | |
967 | ||
ca06fa79 | 968 | dprintk("\n"); |
caf970e0 | 969 | |
b79cb653 | 970 | if (cx24123_get_inversion(state, &p->inversion) != 0) { |
ca06fa79 | 971 | err("%s: Failed to get inversion status\n", __func__); |
b79cb653 ST |
972 | return -EREMOTEIO; |
973 | } | |
974 | if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) { | |
ca06fa79 | 975 | err("%s: Failed to get fec status\n", __func__); |
b79cb653 ST |
976 | return -EREMOTEIO; |
977 | } | |
978 | p->frequency = state->currentfreq; | |
979 | p->u.qpsk.symbol_rate = state->currentsymbolrate; | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
93504abf | 984 | static int cx24123_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) |
b79cb653 ST |
985 | { |
986 | struct cx24123_state *state = fe->demodulator_priv; | |
987 | u8 val; | |
988 | ||
cd20ca9f AQ |
989 | /* wait for diseqc queue ready */ |
990 | cx24123_wait_for_diseqc(state); | |
1c956a3a | 991 | |
cd20ca9f | 992 | val = cx24123_readreg(state, 0x29) & ~0x40; |
1c956a3a | 993 | |
cd20ca9f AQ |
994 | switch (tone) { |
995 | case SEC_TONE_ON: | |
ca06fa79 | 996 | dprintk("setting tone on\n"); |
cd20ca9f AQ |
997 | return cx24123_writereg(state, 0x29, val | 0x10); |
998 | case SEC_TONE_OFF: | |
ca06fa79 | 999 | dprintk("setting tone off\n"); |
cd20ca9f AQ |
1000 | return cx24123_writereg(state, 0x29, val & 0xef); |
1001 | default: | |
ca06fa79 | 1002 | err("CASE reached default with tone=%d\n", tone); |
cd20ca9f | 1003 | return -EINVAL; |
b79cb653 | 1004 | } |
1c956a3a VC |
1005 | |
1006 | return 0; | |
b79cb653 ST |
1007 | } |
1008 | ||
93504abf ST |
1009 | static int cx24123_tune(struct dvb_frontend *fe, |
1010 | struct dvb_frontend_parameters *params, | |
174ff219 | 1011 | unsigned int mode_flags, |
3ea96615 | 1012 | unsigned int *delay, |
174ff219 YP |
1013 | fe_status_t *status) |
1014 | { | |
1015 | int retval = 0; | |
1016 | ||
1017 | if (params != NULL) | |
1018 | retval = cx24123_set_frontend(fe, params); | |
1019 | ||
1020 | if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) | |
1021 | cx24123_read_status(fe, status); | |
1022 | *delay = HZ/10; | |
1023 | ||
1024 | return retval; | |
1025 | } | |
1026 | ||
1027 | static int cx24123_get_algo(struct dvb_frontend *fe) | |
1028 | { | |
93504abf | 1029 | return 1; /* FE_ALGO_HW */ |
174ff219 YP |
1030 | } |
1031 | ||
93504abf | 1032 | static void cx24123_release(struct dvb_frontend *fe) |
b79cb653 | 1033 | { |
93504abf | 1034 | struct cx24123_state *state = fe->demodulator_priv; |
ca06fa79 PB |
1035 | dprintk("\n"); |
1036 | i2c_del_adapter(&state->tuner_i2c_adapter); | |
b79cb653 ST |
1037 | kfree(state); |
1038 | } | |
1039 | ||
ca06fa79 PB |
1040 | static int cx24123_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, |
1041 | struct i2c_msg msg[], int num) | |
1042 | { | |
1043 | struct cx24123_state *state = i2c_get_adapdata(i2c_adap); | |
1044 | /* this repeater closes after the first stop */ | |
93504abf | 1045 | cx24123_repeater_mode(state, 1, 1); |
ca06fa79 PB |
1046 | return i2c_transfer(state->i2c, msg, num); |
1047 | } | |
1048 | ||
1049 | static u32 cx24123_tuner_i2c_func(struct i2c_adapter *adapter) | |
1050 | { | |
1051 | return I2C_FUNC_I2C; | |
1052 | } | |
1053 | ||
1054 | static struct i2c_algorithm cx24123_tuner_i2c_algo = { | |
1055 | .master_xfer = cx24123_tuner_i2c_tuner_xfer, | |
1056 | .functionality = cx24123_tuner_i2c_func, | |
1057 | }; | |
1058 | ||
1059 | struct i2c_adapter * | |
1060 | cx24123_get_tuner_i2c_adapter(struct dvb_frontend *fe) | |
1061 | { | |
1062 | struct cx24123_state *state = fe->demodulator_priv; | |
1063 | return &state->tuner_i2c_adapter; | |
1064 | } | |
1065 | EXPORT_SYMBOL(cx24123_get_tuner_i2c_adapter); | |
1066 | ||
b79cb653 ST |
1067 | static struct dvb_frontend_ops cx24123_ops; |
1068 | ||
93504abf ST |
1069 | struct dvb_frontend *cx24123_attach(const struct cx24123_config *config, |
1070 | struct i2c_adapter *i2c) | |
b79cb653 | 1071 | { |
8420fa7e | 1072 | /* allocate memory for the internal state */ |
ca06fa79 PB |
1073 | struct cx24123_state *state = |
1074 | kzalloc(sizeof(struct cx24123_state), GFP_KERNEL); | |
b79cb653 | 1075 | |
ca06fa79 | 1076 | dprintk("\n"); |
b79cb653 | 1077 | if (state == NULL) { |
8420fa7e | 1078 | err("Unable to kzalloc\n"); |
b79cb653 ST |
1079 | goto error; |
1080 | } | |
1081 | ||
1082 | /* setup the state */ | |
1083 | state->config = config; | |
1084 | state->i2c = i2c; | |
b79cb653 ST |
1085 | |
1086 | /* check if the demod is there */ | |
ca06fa79 PB |
1087 | state->demod_rev = cx24123_readreg(state, 0x00); |
1088 | switch (state->demod_rev) { | |
93504abf ST |
1089 | case 0xe1: |
1090 | info("detected CX24123C\n"); | |
1091 | break; | |
1092 | case 0xd1: | |
1093 | info("detected CX24123\n"); | |
1094 | break; | |
ca06fa79 PB |
1095 | default: |
1096 | err("wrong demod revision: %x\n", state->demod_rev); | |
b79cb653 ST |
1097 | goto error; |
1098 | } | |
1099 | ||
1100 | /* create dvb_frontend */ | |
93504abf ST |
1101 | memcpy(&state->frontend.ops, &cx24123_ops, |
1102 | sizeof(struct dvb_frontend_ops)); | |
b79cb653 | 1103 | state->frontend.demodulator_priv = state; |
ca06fa79 | 1104 | |
93504abf ST |
1105 | /* create tuner i2c adapter */ |
1106 | if (config->dont_use_pll) | |
1107 | cx24123_repeater_mode(state, 1, 0); | |
ca06fa79 | 1108 | |
1d434012 JD |
1109 | strlcpy(state->tuner_i2c_adapter.name, "CX24123 tuner I2C bus", |
1110 | sizeof(state->tuner_i2c_adapter.name)); | |
ca06fa79 PB |
1111 | state->tuner_i2c_adapter.algo = &cx24123_tuner_i2c_algo; |
1112 | state->tuner_i2c_adapter.algo_data = NULL; | |
1113 | i2c_set_adapdata(&state->tuner_i2c_adapter, state); | |
1114 | if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) { | |
93504abf | 1115 | err("tuner i2c bus could not be initialized\n"); |
ca06fa79 PB |
1116 | goto error; |
1117 | } | |
1118 | ||
b79cb653 ST |
1119 | return &state->frontend; |
1120 | ||
1121 | error: | |
1122 | kfree(state); | |
1123 | ||
1124 | return NULL; | |
1125 | } | |
93504abf | 1126 | EXPORT_SYMBOL(cx24123_attach); |
b79cb653 ST |
1127 | |
1128 | static struct dvb_frontend_ops cx24123_ops = { | |
1129 | ||
1130 | .info = { | |
1131 | .name = "Conexant CX24123/CX24109", | |
1132 | .type = FE_QPSK, | |
1133 | .frequency_min = 950000, | |
1134 | .frequency_max = 2150000, | |
1135 | .frequency_stepsize = 1011, /* kHz for QPSK frontends */ | |
0e4558ab | 1136 | .frequency_tolerance = 5000, |
b79cb653 ST |
1137 | .symbol_rate_min = 1000000, |
1138 | .symbol_rate_max = 45000000, | |
1139 | .caps = FE_CAN_INVERSION_AUTO | | |
1140 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
0e4558ab YP |
1141 | FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | |
1142 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
b79cb653 ST |
1143 | FE_CAN_QPSK | FE_CAN_RECOVER |
1144 | }, | |
1145 | ||
1146 | .release = cx24123_release, | |
1147 | ||
1148 | .init = cx24123_initfe, | |
1149 | .set_frontend = cx24123_set_frontend, | |
1150 | .get_frontend = cx24123_get_frontend, | |
1151 | .read_status = cx24123_read_status, | |
1152 | .read_ber = cx24123_read_ber, | |
1153 | .read_signal_strength = cx24123_read_signal_strength, | |
1154 | .read_snr = cx24123_read_snr, | |
b79cb653 | 1155 | .diseqc_send_master_cmd = cx24123_send_diseqc_msg, |
a74b51fc | 1156 | .diseqc_send_burst = cx24123_diseqc_send_burst, |
b79cb653 ST |
1157 | .set_tone = cx24123_set_tone, |
1158 | .set_voltage = cx24123_set_voltage, | |
174ff219 YP |
1159 | .tune = cx24123_tune, |
1160 | .get_frontend_algo = cx24123_get_algo, | |
b79cb653 ST |
1161 | }; |
1162 | ||
ca06fa79 PB |
1163 | MODULE_DESCRIPTION("DVB Frontend module for Conexant " \ |
1164 | "CX24123/CX24109/CX24113 hardware"); | |
b79cb653 ST |
1165 | MODULE_AUTHOR("Steven Toth"); |
1166 | MODULE_LICENSE("GPL"); | |
1167 |