[thirdparty/kernel/stable.git] / drivers / media / pci / cx18 / cx18-queue.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  cx18 buffer queues
 *
 *  Derived from ivtv-queue.c
 *
 *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
 *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
 */

#include "cx18-driver.h"
#include "cx18-queue.h"
#include "cx18-streams.h"
#include "cx18-scb.h"
#include "cx18-io.h"

void cx18_buf_swap(struct cx18_buffer *buf)
{
	int i;

	for (i = 0; i < buf->bytesused; i += 4)
		swab32s((u32 *)(buf->buf + i));
}

void _cx18_mdl_swap(struct cx18_mdl *mdl)
{
	struct cx18_buffer *buf;

	list_for_each_entry(buf, &mdl->buf_list, list) {
		if (buf->bytesused == 0)
			break;
		cx18_buf_swap(buf);
	}
}

void cx18_queue_init(struct cx18_queue *q)
{
	INIT_LIST_HEAD(&q->list);
	atomic_set(&q->depth, 0);
	q->bytesused = 0;
}

struct cx18_queue *_cx18_enqueue(struct cx18_stream *s, struct cx18_mdl *mdl,
				 struct cx18_queue *q, int to_front)
{
	/* clear the mdl if it is not to be enqueued to the full queue */
	if (q != &s->q_full) {
		mdl->bytesused = 0;
		mdl->readpos = 0;
		mdl->m_flags = 0;
		mdl->skipped = 0;
		mdl->curr_buf = NULL;
	}

	/* q_busy is restricted to a max buffer count imposed by firmware */
	if (q == &s->q_busy &&
	    atomic_read(&q->depth) >= CX18_MAX_FW_MDLS_PER_STREAM)
		q = &s->q_free;

	spin_lock(&q->lock);

	if (to_front)
		list_add(&mdl->list, &q->list); /* LIFO */
	else
		list_add_tail(&mdl->list, &q->list); /* FIFO */
	q->bytesused += mdl->bytesused - mdl->readpos;
	atomic_inc(&q->depth);

	spin_unlock(&q->lock);
	return q;
}

struct cx18_mdl *cx18_dequeue(struct cx18_stream *s, struct cx18_queue *q)
{
	struct cx18_mdl *mdl = NULL;

	spin_lock(&q->lock);
	if (!list_empty(&q->list)) {
		mdl = list_first_entry(&q->list, struct cx18_mdl, list);
		list_del_init(&mdl->list);
		q->bytesused -= mdl->bytesused - mdl->readpos;
		mdl->skipped = 0;
		atomic_dec(&q->depth);
	}
	spin_unlock(&q->lock);
	return mdl;
}

static void _cx18_mdl_update_bufs_for_cpu(struct cx18_stream *s,
					  struct cx18_mdl *mdl)
{
	struct cx18_buffer *buf;
	u32 buf_size = s->buf_size;
	u32 bytesused = mdl->bytesused;

	list_for_each_entry(buf, &mdl->buf_list, list) {
		buf->readpos = 0;
		if (bytesused >= buf_size) {
			buf->bytesused = buf_size;
			bytesused -= buf_size;
		} else {
			buf->bytesused = bytesused;
			bytesused = 0;
		}
		cx18_buf_sync_for_cpu(s, buf);
	}
}

static inline void cx18_mdl_update_bufs_for_cpu(struct cx18_stream *s,
						struct cx18_mdl *mdl)
{
	struct cx18_buffer *buf;

	if (list_is_singular(&mdl->buf_list)) {
		buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
				       list);
		buf->bytesused = mdl->bytesused;
		buf->readpos = 0;
		cx18_buf_sync_for_cpu(s, buf);
	} else {
		_cx18_mdl_update_bufs_for_cpu(s, mdl);
	}
}

struct cx18_mdl *cx18_queue_get_mdl(struct cx18_stream *s, u32 id,
	u32 bytesused)
{
	struct cx18 *cx = s->cx;
	struct cx18_mdl *mdl;
	struct cx18_mdl *tmp;
	struct cx18_mdl *ret = NULL;
	LIST_HEAD(sweep_up);

	/*
	 * We don't have to acquire multiple q locks here, because we are
	 * serialized by the single threaded work handler.
	 * MDLs from the firmware will thus remain in order as
	 * they are moved from q_busy to q_full or to the dvb ring buffer.
	 */
	spin_lock(&s->q_busy.lock);
	list_for_each_entry_safe(mdl, tmp, &s->q_busy.list, list) {
		/*
		 * We should find what the firmware told us is done,
		 * right at the front of the queue.  If we don't, we likely have
		 * missed an mdl done message from the firmware.
		 * Once we skip an mdl repeatedly, relative to the size of
		 * q_busy, we have high confidence we've missed it.
		 */
		if (mdl->id != id) {
			mdl->skipped++;
			if (mdl->skipped >= atomic_read(&s->q_busy.depth)-1) {
				/* mdl must have fallen out of rotation */
				CX18_WARN("Skipped %s, MDL %d, %d times - it must have dropped out of rotation\n",
					  s->name, mdl->id,
					  mdl->skipped);
				/* Sweep it up to put it back into rotation */
				list_move_tail(&mdl->list, &sweep_up);
				atomic_dec(&s->q_busy.depth);
			}
			continue;
		}
		/*
		 * We pull the desired mdl off of the queue here.  Something
		 * will have to put it back on a queue later.
		 */
		list_del_init(&mdl->list);
		atomic_dec(&s->q_busy.depth);
		ret = mdl;
		break;
	}
	spin_unlock(&s->q_busy.lock);

	/*
	 * We found the mdl for which we were looking.  Get it ready for
	 * the caller to put on q_full or in the dvb ring buffer.
	 */
	if (ret != NULL) {
		ret->bytesused = bytesused;
		ret->skipped = 0;
		/* 0'ed readpos, m_flags & curr_buf when mdl went on q_busy */
		cx18_mdl_update_bufs_for_cpu(s, ret);
		if (s->type != CX18_ENC_STREAM_TYPE_TS)
			set_bit(CX18_F_M_NEED_SWAP, &ret->m_flags);
	}

	/* Put any mdls the firmware is ignoring back into normal rotation */
	list_for_each_entry_safe(mdl, tmp, &sweep_up, list) {
		list_del_init(&mdl->list);
		cx18_enqueue(s, mdl, &s->q_free);
	}
	return ret;
}

/* Move all mdls of a queue, while flushing the mdl */
static void cx18_queue_flush(struct cx18_stream *s,
			     struct cx18_queue *q_src, struct cx18_queue *q_dst)
{
	struct cx18_mdl *mdl;

	/* It only makes sense to flush to q_free or q_idle */
	if (q_src == q_dst || q_dst == &s->q_full || q_dst == &s->q_busy)
		return;

	spin_lock(&q_src->lock);
	spin_lock(&q_dst->lock);
	while (!list_empty(&q_src->list)) {
		mdl = list_first_entry(&q_src->list, struct cx18_mdl, list);
		list_move_tail(&mdl->list, &q_dst->list);
		mdl->bytesused = 0;
		mdl->readpos = 0;
		mdl->m_flags = 0;
		mdl->skipped = 0;
		mdl->curr_buf = NULL;
		atomic_inc(&q_dst->depth);
	}
	cx18_queue_init(q_src);
	spin_unlock(&q_src->lock);
	spin_unlock(&q_dst->lock);
}

void cx18_flush_queues(struct cx18_stream *s)
{
	cx18_queue_flush(s, &s->q_busy, &s->q_free);
	cx18_queue_flush(s, &s->q_full, &s->q_free);
}

/*
 * Note, s->buf_pool is not protected by a lock,
 * the stream better not have *anything* going on when calling this
 */
void cx18_unload_queues(struct cx18_stream *s)
{
	struct cx18_queue *q_idle = &s->q_idle;
	struct cx18_mdl *mdl;
	struct cx18_buffer *buf;

	/* Move all MDLS to q_idle */
	cx18_queue_flush(s, &s->q_busy, q_idle);
	cx18_queue_flush(s, &s->q_full, q_idle);
	cx18_queue_flush(s, &s->q_free, q_idle);

	/* Reset MDL id's and move all buffers back to the stream's buf_pool */
	spin_lock(&q_idle->lock);
	list_for_each_entry(mdl, &q_idle->list, list) {
		while (!list_empty(&mdl->buf_list)) {
			buf = list_first_entry(&mdl->buf_list,
					       struct cx18_buffer, list);
			list_move_tail(&buf->list, &s->buf_pool);
			buf->bytesused = 0;
			buf->readpos = 0;
		}
		mdl->id = s->mdl_base_idx; /* reset id to a "safe" value */
		/* all other mdl fields were cleared by cx18_queue_flush() */
	}
	spin_unlock(&q_idle->lock);
}

/*
 * Note, s->buf_pool is not protected by a lock,
 * the stream better not have *anything* going on when calling this
 */
void cx18_load_queues(struct cx18_stream *s)
{
	struct cx18 *cx = s->cx;
	struct cx18_mdl *mdl;
	struct cx18_buffer *buf;
	int mdl_id;
	int i;
	u32 partial_buf_size;

	/*
	 * Attach buffers to MDLs, give the MDLs ids, and add MDLs to q_free
	 * Excess MDLs are left on q_idle
	 * Excess buffers are left in buf_pool and/or on an MDL in q_idle
	 */
	mdl_id = s->mdl_base_idx;
	for (mdl = cx18_dequeue(s, &s->q_idle), i = s->bufs_per_mdl;
	     mdl != NULL && i == s->bufs_per_mdl;
	     mdl = cx18_dequeue(s, &s->q_idle)) {

		mdl->id = mdl_id;

		for (i = 0; i < s->bufs_per_mdl; i++) {
			if (list_empty(&s->buf_pool))
				break;

			buf = list_first_entry(&s->buf_pool, struct cx18_buffer,
					       list);
			list_move_tail(&buf->list, &mdl->buf_list);

			/* update the firmware's MDL array with this buffer */
			cx18_writel(cx, buf->dma_handle,
				    &cx->scb->cpu_mdl[mdl_id + i].paddr);
			cx18_writel(cx, s->buf_size,
				    &cx->scb->cpu_mdl[mdl_id + i].length);
		}

		if (i == s->bufs_per_mdl) {
			/*
			 * The encoder doesn't honor s->mdl_size.  So in the
			 * case of a non-integral number of buffers to meet
			 * mdl_size, we lie about the size of the last buffer
			 * in the MDL to get the encoder to really only send
			 * us mdl_size bytes per MDL transfer.
			 */
			partial_buf_size = s->mdl_size % s->buf_size;
			if (partial_buf_size) {
				cx18_writel(cx, partial_buf_size,
				      &cx->scb->cpu_mdl[mdl_id + i - 1].length);
			}
			cx18_enqueue(s, mdl, &s->q_free);
		} else {
			/* Not enough buffers for this MDL; we won't use it */
			cx18_push(s, mdl, &s->q_idle);
		}
		mdl_id += i;
	}
}

void _cx18_mdl_sync_for_device(struct cx18_stream *s, struct cx18_mdl *mdl)
{
	int dma = s->dma;
	u32 buf_size = s->buf_size;
	struct pci_dev *pci_dev = s->cx->pci_dev;
	struct cx18_buffer *buf;

	list_for_each_entry(buf, &mdl->buf_list, list)
		pci_dma_sync_single_for_device(pci_dev, buf->dma_handle,
					       buf_size, dma);
}

int cx18_stream_alloc(struct cx18_stream *s)
{
	struct cx18 *cx = s->cx;
	int i;

	if (s->buffers == 0)
		return 0;

	CX18_DEBUG_INFO("Allocate %s stream: %d x %d buffers (%d.%02d kB total)\n",
		s->name, s->buffers, s->buf_size,
		s->buffers * s->buf_size / 1024,
		(s->buffers * s->buf_size * 100 / 1024) % 100);

	if (((char __iomem *)&cx->scb->cpu_mdl[cx->free_mdl_idx + s->buffers] -
				(char __iomem *)cx->scb) > SCB_RESERVED_SIZE) {
		unsigned bufsz = (((char __iomem *)cx->scb) + SCB_RESERVED_SIZE -
					((char __iomem *)cx->scb->cpu_mdl));

		CX18_ERR("Too many buffers, cannot fit in SCB area\n");
		CX18_ERR("Max buffers = %zu\n",
			bufsz / sizeof(struct cx18_mdl_ent));
		return -ENOMEM;
	}

	s->mdl_base_idx = cx->free_mdl_idx;

	/* allocate stream buffers and MDLs */
	for (i = 0; i < s->buffers; i++) {
		struct cx18_mdl *mdl;
		struct cx18_buffer *buf;

		/* 1 MDL per buffer to handle the worst & also default case */
		mdl = kzalloc(sizeof(struct cx18_mdl), GFP_KERNEL|__GFP_NOWARN);
		if (mdl == NULL)
			break;

		buf = kzalloc(sizeof(struct cx18_buffer),
				GFP_KERNEL|__GFP_NOWARN);
		if (buf == NULL) {
			kfree(mdl);
			break;
		}

		buf->buf = kmalloc(s->buf_size, GFP_KERNEL|__GFP_NOWARN);
		if (buf->buf == NULL) {
			kfree(mdl);
			kfree(buf);
			break;
		}

		INIT_LIST_HEAD(&mdl->list);
		INIT_LIST_HEAD(&mdl->buf_list);
		mdl->id = s->mdl_base_idx; /* a somewhat safe value */
		cx18_enqueue(s, mdl, &s->q_idle);

		INIT_LIST_HEAD(&buf->list);
		buf->dma_handle = pci_map_single(s->cx->pci_dev,
				buf->buf, s->buf_size, s->dma);
		cx18_buf_sync_for_cpu(s, buf);
		list_add_tail(&buf->list, &s->buf_pool);
	}
	if (i == s->buffers) {
		cx->free_mdl_idx += s->buffers;
		return 0;
	}
	CX18_ERR("Couldn't allocate buffers for %s stream\n", s->name);
	cx18_stream_free(s);
	return -ENOMEM;
}

void cx18_stream_free(struct cx18_stream *s)
{
	struct cx18_mdl *mdl;
	struct cx18_buffer *buf;
	struct cx18 *cx = s->cx;

	CX18_DEBUG_INFO("Deallocating buffers for %s stream\n", s->name);

	/* move all buffers to buf_pool and all MDLs to q_idle */
	cx18_unload_queues(s);

	/* empty q_idle */
	while ((mdl = cx18_dequeue(s, &s->q_idle)))
		kfree(mdl);

	/* empty buf_pool */
	while (!list_empty(&s->buf_pool)) {
		buf = list_first_entry(&s->buf_pool, struct cx18_buffer, list);
		list_del_init(&buf->list);

		pci_unmap_single(s->cx->pci_dev, buf->dma_handle,
				s->buf_size, s->dma);
		kfree(buf->buf);
		kfree(buf);
	}
}
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
1c1e45d1 HV	2	/*
	3	* cx18 buffer queues
	4	*
	5	* Derived from ivtv-queue.c
	6	*
	7	* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
6afdeaf8	8	* Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
1c1e45d1 HV	9	*/
	10
	11	#include "cx18-driver.h"
1c1e45d1	12	#include "cx18-queue.h"
21a278b8	13	#include "cx18-streams.h"
1c1e45d1	14	#include "cx18-scb.h"
52fcb3ec	15	#include "cx18-io.h"
1c1e45d1	16
1c1e45d1 HV	17	void cx18_buf_swap(struct cx18_buffer *buf)
	18	{
	19	int i;
	20
	21	for (i = 0; i < buf->bytesused; i += 4)
	22	swab32s((u32 *)(buf->buf + i));
	23	}
	24
52fcb3ec AW	25	void _cx18_mdl_swap(struct cx18_mdl *mdl)
	26	{
	27	struct cx18_buffer *buf;
	28
	29	list_for_each_entry(buf, &mdl->buf_list, list) {
	30	if (buf->bytesused == 0)
	31	break;
	32	cx18_buf_swap(buf);
	33	}
	34	}
	35
1c1e45d1 HV	36	void cx18_queue_init(struct cx18_queue *q)
	37	{
	38	INIT_LIST_HEAD(&q->list);
c37b11bf	39	atomic_set(&q->depth, 0);
1c1e45d1 HV	40	q->bytesused = 0;
	41	}
	42
52fcb3ec	43	struct cx18_queue _cx18_enqueue(struct cx18_stream s, struct cx18_mdl *mdl,
66c2a6b0	44	struct cx18_queue *q, int to_front)
1c1e45d1	45	{
52fcb3ec	46	/* clear the mdl if it is not to be enqueued to the full queue */
66c2a6b0	47	if (q != &s->q_full) {
52fcb3ec AW	48	mdl->bytesused = 0;
	49	mdl->readpos = 0;
	50	mdl->m_flags = 0;
	51	mdl->skipped = 0;
	52	mdl->curr_buf = NULL;
1c1e45d1	53	}
66c2a6b0	54
0ef02892 AW	55	/* q_busy is restricted to a max buffer count imposed by firmware */
0ef02892 AW	56	if (q == &s->q_busy &&
c37b11bf	57	atomic_read(&q->depth) >= CX18_MAX_FW_MDLS_PER_STREAM)
66c2a6b0 AW	58	q = &s->q_free;
66c2a6b0 AW	59
40c5520f AW	60	spin_lock(&q->lock);
40c5520f AW	61
b80e1074	62	if (to_front)
52fcb3ec	63	list_add(&mdl->list, &q->list); /* LIFO */
b80e1074	64	else
52fcb3ec AW	65	list_add_tail(&mdl->list, &q->list); /* FIFO */
52fcb3ec AW	66	q->bytesused += mdl->bytesused - mdl->readpos;
c37b11bf	67	atomic_inc(&q->depth);
66c2a6b0	68
40c5520f	69	spin_unlock(&q->lock);
66c2a6b0	70	return q;
1c1e45d1 HV	71	}
1c1e45d1 HV	72
52fcb3ec	73	struct cx18_mdl cx18_dequeue(struct cx18_stream s, struct cx18_queue *q)
1c1e45d1	74	{
52fcb3ec	75	struct cx18_mdl *mdl = NULL;
1c1e45d1	76
40c5520f	77	spin_lock(&q->lock);
1c1e45d1	78	if (!list_empty(&q->list)) {
52fcb3ec AW	79	mdl = list_first_entry(&q->list, struct cx18_mdl, list);
	80	list_del_init(&mdl->list);
	81	q->bytesused -= mdl->bytesused - mdl->readpos;
	82	mdl->skipped = 0;
c37b11bf	83	atomic_dec(&q->depth);
1c1e45d1	84	}
40c5520f	85	spin_unlock(&q->lock);
52fcb3ec AW	86	return mdl;
	87	}
	88
ad689d54 AW	89	static void _cx18_mdl_update_bufs_for_cpu(struct cx18_stream *s,
ad689d54 AW	90	struct cx18_mdl *mdl)
52fcb3ec AW	91	{
	92	struct cx18_buffer *buf;
	93	u32 buf_size = s->buf_size;
	94	u32 bytesused = mdl->bytesused;
	95
	96	list_for_each_entry(buf, &mdl->buf_list, list) {
	97	buf->readpos = 0;
	98	if (bytesused >= buf_size) {
	99	buf->bytesused = buf_size;
	100	bytesused -= buf_size;
	101	} else {
	102	buf->bytesused = bytesused;
	103	bytesused = 0;
	104	}
ad689d54	105	cx18_buf_sync_for_cpu(s, buf);
52fcb3ec	106	}
1c1e45d1 HV	107	}
1c1e45d1 HV	108
ad689d54 AW	109	static inline void cx18_mdl_update_bufs_for_cpu(struct cx18_stream *s,
ad689d54 AW	110	struct cx18_mdl *mdl)
52fcb3ec AW	111	{
	112	struct cx18_buffer *buf;
	113
	114	if (list_is_singular(&mdl->buf_list)) {
	115	buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
	116	list);
	117	buf->bytesused = mdl->bytesused;
	118	buf->readpos = 0;
ad689d54	119	cx18_buf_sync_for_cpu(s, buf);
52fcb3ec	120	} else {
ad689d54	121	_cx18_mdl_update_bufs_for_cpu(s, mdl);
52fcb3ec AW	122	}
	123	}
	124
	125	struct cx18_mdl cx18_queue_get_mdl(struct cx18_stream s, u32 id,
1c1e45d1 HV	126	u32 bytesused)
	127	{
	128	struct cx18 *cx = s->cx;
52fcb3ec AW	129	struct cx18_mdl *mdl;
	130	struct cx18_mdl *tmp;
	131	struct cx18_mdl *ret = NULL;
40c5520f AW	132	LIST_HEAD(sweep_up);
	133
	134	/*
	135	* We don't have to acquire multiple q locks here, because we are
	136	* serialized by the single threaded work handler.
52fcb3ec	137	* MDLs from the firmware will thus remain in order as
40c5520f AW	138	* they are moved from q_busy to q_full or to the dvb ring buffer.
	139	*/
	140	spin_lock(&s->q_busy.lock);
52fcb3ec	141	list_for_each_entry_safe(mdl, tmp, &s->q_busy.list, list) {
40c5520f AW	142	/*
	143	* We should find what the firmware told us is done,
	144	* right at the front of the queue. If we don't, we likely have
52fcb3ec AW	145	* missed an mdl done message from the firmware.
52fcb3ec AW	146	* Once we skip an mdl repeatedly, relative to the size of
40c5520f AW	147	* q_busy, we have high confidence we've missed it.
40c5520f AW	148	*/
52fcb3ec AW	149	if (mdl->id != id) {
	150	mdl->skipped++;
	151	if (mdl->skipped >= atomic_read(&s->q_busy.depth)-1) {
	152	/* mdl must have fallen out of rotation */
6beb1388 MCC	153	CX18_WARN("Skipped %s, MDL %d, %d times - it must have dropped out of rotation\n",
6beb1388 MCC	154	s->name, mdl->id,
52fcb3ec	155	mdl->skipped);
40c5520f	156	/* Sweep it up to put it back into rotation */
52fcb3ec	157	list_move_tail(&mdl->list, &sweep_up);
c37b11bf	158	atomic_dec(&s->q_busy.depth);
bca11a57	159	}
1c1e45d1	160	continue;
ee2d64f5	161	}
40c5520f	162	/*
52fcb3ec	163	* We pull the desired mdl off of the queue here. Something
40c5520f AW	164	* will have to put it back on a queue later.
40c5520f AW	165	*/
52fcb3ec	166	list_del_init(&mdl->list);
c37b11bf	167	atomic_dec(&s->q_busy.depth);
52fcb3ec	168	ret = mdl;
bca11a57	169	break;
1c1e45d1	170	}
40c5520f AW	171	spin_unlock(&s->q_busy.lock);
	172
	173	/*
52fcb3ec	174	* We found the mdl for which we were looking. Get it ready for
40c5520f AW	175	* the caller to put on q_full or in the dvb ring buffer.
	176	*/
	177	if (ret != NULL) {
	178	ret->bytesused = bytesused;
	179	ret->skipped = 0;
52fcb3ec	180	/* 0'ed readpos, m_flags & curr_buf when mdl went on q_busy */
ad689d54	181	cx18_mdl_update_bufs_for_cpu(s, ret);
40c5520f	182	if (s->type != CX18_ENC_STREAM_TYPE_TS)
52fcb3ec	183	set_bit(CX18_F_M_NEED_SWAP, &ret->m_flags);
40c5520f AW	184	}
40c5520f AW	185
52fcb3ec AW	186	/* Put any mdls the firmware is ignoring back into normal rotation */
	187	list_for_each_entry_safe(mdl, tmp, &sweep_up, list) {
	188	list_del_init(&mdl->list);
	189	cx18_enqueue(s, mdl, &s->q_free);
40c5520f	190	}
bca11a57	191	return ret;
1c1e45d1 HV	192	}
1c1e45d1 HV	193
52fcb3ec AW	194	/* Move all mdls of a queue, while flushing the mdl */
	195	static void cx18_queue_flush(struct cx18_stream *s,
	196	struct cx18_queue q_src, struct cx18_queue q_dst)
1c1e45d1	197	{
52fcb3ec	198	struct cx18_mdl *mdl;
1c1e45d1	199
52fcb3ec AW	200	/* It only makes sense to flush to q_free or q_idle */
52fcb3ec AW	201	if (q_src == q_dst \|\| q_dst == &s->q_full \|\| q_dst == &s->q_busy)
6c9de528	202	return;
1c1e45d1	203
52fcb3ec AW	204	spin_lock(&q_src->lock);
	205	spin_lock(&q_dst->lock);
	206	while (!list_empty(&q_src->list)) {
	207	mdl = list_first_entry(&q_src->list, struct cx18_mdl, list);
	208	list_move_tail(&mdl->list, &q_dst->list);
	209	mdl->bytesused = 0;
	210	mdl->readpos = 0;
	211	mdl->m_flags = 0;
	212	mdl->skipped = 0;
	213	mdl->curr_buf = NULL;
	214	atomic_inc(&q_dst->depth);
1c1e45d1	215	}
52fcb3ec AW	216	cx18_queue_init(q_src);
	217	spin_unlock(&q_src->lock);
	218	spin_unlock(&q_dst->lock);
1c1e45d1 HV	219	}
	220
	221	void cx18_flush_queues(struct cx18_stream *s)
	222	{
52fcb3ec AW	223	cx18_queue_flush(s, &s->q_busy, &s->q_free);
	224	cx18_queue_flush(s, &s->q_full, &s->q_free);
	225	}
	226
	227	/*
	228	* Note, s->buf_pool is not protected by a lock,
	229	* the stream better not have anything going on when calling this
	230	*/
	231	void cx18_unload_queues(struct cx18_stream *s)
	232	{
	233	struct cx18_queue *q_idle = &s->q_idle;
	234	struct cx18_mdl *mdl;
	235	struct cx18_buffer *buf;
	236
	237	/* Move all MDLS to q_idle */
	238	cx18_queue_flush(s, &s->q_busy, q_idle);
	239	cx18_queue_flush(s, &s->q_full, q_idle);
	240	cx18_queue_flush(s, &s->q_free, q_idle);
	241
	242	/* Reset MDL id's and move all buffers back to the stream's buf_pool */
	243	spin_lock(&q_idle->lock);
	244	list_for_each_entry(mdl, &q_idle->list, list) {
	245	while (!list_empty(&mdl->buf_list)) {
	246	buf = list_first_entry(&mdl->buf_list,
	247	struct cx18_buffer, list);
	248	list_move_tail(&buf->list, &s->buf_pool);
	249	buf->bytesused = 0;
	250	buf->readpos = 0;
	251	}
	252	mdl->id = s->mdl_base_idx; /* reset id to a "safe" value */
	253	/* all other mdl fields were cleared by cx18_queue_flush() */
	254	}
	255	spin_unlock(&q_idle->lock);
	256	}
	257
	258	/*
	259	* Note, s->buf_pool is not protected by a lock,
	260	* the stream better not have anything going on when calling this
	261	*/
	262	void cx18_load_queues(struct cx18_stream *s)
	263	{
	264	struct cx18 *cx = s->cx;
	265	struct cx18_mdl *mdl;
	266	struct cx18_buffer *buf;
	267	int mdl_id;
	268	int i;
1047a838	269	u32 partial_buf_size;
52fcb3ec AW	270
	271	/*
	272	* Attach buffers to MDLs, give the MDLs ids, and add MDLs to q_free
	273	* Excess MDLs are left on q_idle
	274	* Excess buffers are left in buf_pool and/or on an MDL in q_idle
	275	*/
	276	mdl_id = s->mdl_base_idx;
	277	for (mdl = cx18_dequeue(s, &s->q_idle), i = s->bufs_per_mdl;
	278	mdl != NULL && i == s->bufs_per_mdl;
	279	mdl = cx18_dequeue(s, &s->q_idle)) {
	280
	281	mdl->id = mdl_id;
	282
	283	for (i = 0; i < s->bufs_per_mdl; i++) {
	284	if (list_empty(&s->buf_pool))
	285	break;
	286
	287	buf = list_first_entry(&s->buf_pool, struct cx18_buffer,
	288	list);
	289	list_move_tail(&buf->list, &mdl->buf_list);
	290
	291	/* update the firmware's MDL array with this buffer */
	292	cx18_writel(cx, buf->dma_handle,
	293	&cx->scb->cpu_mdl[mdl_id + i].paddr);
	294	cx18_writel(cx, s->buf_size,
	295	&cx->scb->cpu_mdl[mdl_id + i].length);
	296	}
	297
1047a838 AW	298	if (i == s->bufs_per_mdl) {
	299	/*
	300	* The encoder doesn't honor s->mdl_size. So in the
	301	* case of a non-integral number of buffers to meet
	302	* mdl_size, we lie about the size of the last buffer
	303	* in the MDL to get the encoder to really only send
	304	* us mdl_size bytes per MDL transfer.
	305	*/
	306	partial_buf_size = s->mdl_size % s->buf_size;
	307	if (partial_buf_size) {
	308	cx18_writel(cx, partial_buf_size,
	309	&cx->scb->cpu_mdl[mdl_id + i - 1].length);
	310	}
52fcb3ec	311	cx18_enqueue(s, mdl, &s->q_free);
1047a838 AW	312	} else {
	313	/* Not enough buffers for this MDL; we won't use it */
	314	cx18_push(s, mdl, &s->q_idle);
	315	}
52fcb3ec AW	316	mdl_id += i;
	317	}
	318	}
	319
52fcb3ec AW	320	void _cx18_mdl_sync_for_device(struct cx18_stream s, struct cx18_mdl mdl)
	321	{
	322	int dma = s->dma;
	323	u32 buf_size = s->buf_size;
	324	struct pci_dev *pci_dev = s->cx->pci_dev;
	325	struct cx18_buffer *buf;
	326
	327	list_for_each_entry(buf, &mdl->buf_list, list)
	328	pci_dma_sync_single_for_device(pci_dev, buf->dma_handle,
	329	buf_size, dma);
1c1e45d1 HV	330	}
	331
	332	int cx18_stream_alloc(struct cx18_stream *s)
	333	{
	334	struct cx18 *cx = s->cx;
	335	int i;
	336
	337	if (s->buffers == 0)
	338	return 0;
	339
6beb1388	340	CX18_DEBUG_INFO("Allocate %s stream: %d x %d buffers (%d.%02d kB total)\n",
1c1e45d1	341	s->name, s->buffers, s->buf_size,
22dce188 AW	342	s->buffers * s->buf_size / 1024,
22dce188 AW	343	(s->buffers * s->buf_size * 100 / 1024) % 100);
1c1e45d1	344
fa655dda	345	if (((char __iomem *)&cx->scb->cpu_mdl[cx->free_mdl_idx + s->buffers] -
c6eb8eaf HV	346	(char __iomem *)cx->scb) > SCB_RESERVED_SIZE) {
	347	unsigned bufsz = (((char __iomem *)cx->scb) + SCB_RESERVED_SIZE -
	348	((char __iomem *)cx->scb->cpu_mdl));
1c1e45d1 HV	349
1c1e45d1 HV	350	CX18_ERR("Too many buffers, cannot fit in SCB area\n");
339f06c5	351	CX18_ERR("Max buffers = %zu\n",
f0076e60	352	bufsz / sizeof(struct cx18_mdl_ent));
1c1e45d1 HV	353	return -ENOMEM;
	354	}
	355
fa655dda	356	s->mdl_base_idx = cx->free_mdl_idx;
1c1e45d1	357
52fcb3ec	358	/* allocate stream buffers and MDLs */
1c1e45d1	359	for (i = 0; i < s->buffers; i++) {
52fcb3ec AW	360	struct cx18_mdl *mdl;
52fcb3ec AW	361	struct cx18_buffer *buf;
1c1e45d1	362
52fcb3ec AW	363	/* 1 MDL per buffer to handle the worst & also default case */
	364	mdl = kzalloc(sizeof(struct cx18_mdl), GFP_KERNEL\|__GFP_NOWARN);
	365	if (mdl == NULL)
1c1e45d1	366	break;
52fcb3ec AW	367
	368	buf = kzalloc(sizeof(struct cx18_buffer),
	369	GFP_KERNEL\|__GFP_NOWARN);
	370	if (buf == NULL) {
	371	kfree(mdl);
	372	break;
	373	}
	374
3f98387e	375	buf->buf = kmalloc(s->buf_size, GFP_KERNEL\|__GFP_NOWARN);
1c1e45d1	376	if (buf->buf == NULL) {
52fcb3ec	377	kfree(mdl);
1c1e45d1 HV	378	kfree(buf);
	379	break;
	380	}
52fcb3ec AW	381
	382	INIT_LIST_HEAD(&mdl->list);
	383	INIT_LIST_HEAD(&mdl->buf_list);
	384	mdl->id = s->mdl_base_idx; /* a somewhat safe value */
	385	cx18_enqueue(s, mdl, &s->q_idle);
	386
1c1e45d1	387	INIT_LIST_HEAD(&buf->list);
3d05913d	388	buf->dma_handle = pci_map_single(s->cx->pci_dev,
1c1e45d1 HV	389	buf->buf, s->buf_size, s->dma);
1c1e45d1 HV	390	cx18_buf_sync_for_cpu(s, buf);
52fcb3ec	391	list_add_tail(&buf->list, &s->buf_pool);
1c1e45d1 HV	392	}
1c1e45d1 HV	393	if (i == s->buffers) {
fa655dda	394	cx->free_mdl_idx += s->buffers;
1c1e45d1 HV	395	return 0;
	396	}
	397	CX18_ERR("Couldn't allocate buffers for %s stream\n", s->name);
	398	cx18_stream_free(s);
	399	return -ENOMEM;
	400	}
	401
	402	void cx18_stream_free(struct cx18_stream *s)
	403	{
52fcb3ec	404	struct cx18_mdl *mdl;
1c1e45d1	405	struct cx18_buffer *buf;
7b1dde03 AW	406	struct cx18 *cx = s->cx;
	407
	408	CX18_DEBUG_INFO("Deallocating buffers for %s stream\n", s->name);
1c1e45d1	409
52fcb3ec AW	410	/* move all buffers to buf_pool and all MDLs to q_idle */
	411	cx18_unload_queues(s);
	412
	413	/* empty q_idle */
	414	while ((mdl = cx18_dequeue(s, &s->q_idle)))
	415	kfree(mdl);
	416
	417	/* empty buf_pool */
	418	while (!list_empty(&s->buf_pool)) {
	419	buf = list_first_entry(&s->buf_pool, struct cx18_buffer, list);
	420	list_del_init(&buf->list);
1c1e45d1	421
3d05913d	422	pci_unmap_single(s->cx->pci_dev, buf->dma_handle,
1c1e45d1 HV	423	s->buf_size, s->dma);
	424	kfree(buf->buf);
	425	kfree(buf);
	426	}
	427	}