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Commit | Line | Data |
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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
02b20b0b MCC |
2 | /* |
3 | * Driver for the Conexant CX25821 PCIe bridge | |
4 | * | |
bb4c9a74 | 5 | * Copyright (C) 2009 Conexant Systems Inc. |
02b20b0b | 6 | * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> |
b671ae6b | 7 | * Based on Steven Toth <stoth@linuxtv.org> cx25821 driver |
6d8c2ba1 PB |
8 | * Parts adapted/taken from Eduardo Moscoso Rubino |
9 | * Copyright (C) 2009 Eduardo Moscoso Rubino <moscoso@TopoLogica.com> | |
02b20b0b MCC |
10 | */ |
11 | ||
36d89f7d JP |
12 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
13 | ||
02b20b0b MCC |
14 | #include "cx25821-video.h" |
15 | ||
16 | MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards"); | |
6d8c2ba1 | 17 | MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>"); |
02b20b0b MCC |
18 | MODULE_LICENSE("GPL"); |
19 | ||
53e712d0 | 20 | static unsigned int video_nr[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET }; |
02b20b0b MCC |
21 | |
22 | module_param_array(video_nr, int, NULL, 0444); | |
02b20b0b MCC |
23 | |
24 | MODULE_PARM_DESC(video_nr, "video device numbers"); | |
02b20b0b | 25 | |
1a9fc855 | 26 | static unsigned int video_debug = VIDEO_DEBUG; |
02b20b0b MCC |
27 | module_param(video_debug, int, 0644); |
28 | MODULE_PARM_DESC(video_debug, "enable debug messages [video]"); | |
29 | ||
30 | static unsigned int irq_debug; | |
31 | module_param(irq_debug, int, 0644); | |
32 | MODULE_PARM_DESC(irq_debug, "enable debug messages [IRQ handler]"); | |
33 | ||
02b20b0b MCC |
34 | #define FORMAT_FLAGS_PACKED 0x01 |
35 | ||
95c232a2 | 36 | static const struct cx25821_fmt formats[] = { |
1a9fc855 | 37 | { |
d7d93387 MCC |
38 | .name = "4:1:1, packed, Y41P", |
39 | .fourcc = V4L2_PIX_FMT_Y41P, | |
40 | .depth = 12, | |
41 | .flags = FORMAT_FLAGS_PACKED, | |
42 | }, { | |
43 | .name = "4:2:2, packed, YUYV", | |
44 | .fourcc = V4L2_PIX_FMT_YUYV, | |
45 | .depth = 16, | |
46 | .flags = FORMAT_FLAGS_PACKED, | |
d7d93387 | 47 | }, |
02b20b0b MCC |
48 | }; |
49 | ||
95c232a2 | 50 | static const struct cx25821_fmt *cx25821_format_by_fourcc(unsigned int fourcc) |
02b20b0b | 51 | { |
1a9fc855 | 52 | unsigned int i; |
02b20b0b | 53 | |
1a9fc855 MCC |
54 | for (i = 0; i < ARRAY_SIZE(formats); i++) |
55 | if (formats[i].fourcc == fourcc) | |
56 | return formats + i; | |
1a9fc855 | 57 | return NULL; |
02b20b0b MCC |
58 | } |
59 | ||
02b20b0b | 60 | int cx25821_start_video_dma(struct cx25821_dev *dev, |
1a9fc855 MCC |
61 | struct cx25821_dmaqueue *q, |
62 | struct cx25821_buffer *buf, | |
bfef0d35 | 63 | const struct sram_channel *channel) |
02b20b0b | 64 | { |
1a9fc855 | 65 | int tmp = 0; |
02b20b0b | 66 | |
1a9fc855 MCC |
67 | /* setup fifo + format */ |
68 | cx25821_sram_channel_setup(dev, channel, buf->bpl, buf->risc.dma); | |
02b20b0b | 69 | |
1a9fc855 MCC |
70 | /* reset counter */ |
71 | cx_write(channel->gpcnt_ctl, 3); | |
02b20b0b | 72 | |
1a9fc855 MCC |
73 | /* enable irq */ |
74 | cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << channel->i)); | |
75 | cx_set(channel->int_msk, 0x11); | |
02b20b0b | 76 | |
1a9fc855 MCC |
77 | /* start dma */ |
78 | cx_write(channel->dma_ctl, 0x11); /* FIFO and RISC enable */ | |
02b20b0b | 79 | |
1a9fc855 MCC |
80 | /* make sure upstream setting if any is reversed */ |
81 | tmp = cx_read(VID_CH_MODE_SEL); | |
82 | cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00); | |
02b20b0b | 83 | |
1a9fc855 | 84 | return 0; |
02b20b0b MCC |
85 | } |
86 | ||
02b20b0b MCC |
87 | int cx25821_video_irq(struct cx25821_dev *dev, int chan_num, u32 status) |
88 | { | |
1a9fc855 MCC |
89 | int handled = 0; |
90 | u32 mask; | |
bfef0d35 | 91 | const struct sram_channel *channel = dev->channels[chan_num].sram_channels; |
1a9fc855 MCC |
92 | |
93 | mask = cx_read(channel->int_msk); | |
94 | if (0 == (status & mask)) | |
95 | return handled; | |
96 | ||
97 | cx_write(channel->int_stat, status); | |
98 | ||
99 | /* risc op code error */ | |
100 | if (status & (1 << 16)) { | |
36d89f7d JP |
101 | pr_warn("%s, %s: video risc op code error\n", |
102 | dev->name, channel->name); | |
1a9fc855 MCC |
103 | cx_clear(channel->dma_ctl, 0x11); |
104 | cx25821_sram_channel_dump(dev, channel); | |
105 | } | |
02b20b0b | 106 | |
1a9fc855 MCC |
107 | /* risc1 y */ |
108 | if (status & FLD_VID_DST_RISC1) { | |
b671ae6b HV |
109 | struct cx25821_dmaqueue *dmaq = |
110 | &dev->channels[channel->i].dma_vidq; | |
111 | struct cx25821_buffer *buf; | |
02b20b0b | 112 | |
1a9fc855 | 113 | spin_lock(&dev->slock); |
b671ae6b HV |
114 | if (!list_empty(&dmaq->active)) { |
115 | buf = list_entry(dmaq->active.next, | |
116 | struct cx25821_buffer, queue); | |
117 | ||
d6dd645e | 118 | buf->vb.vb2_buf.timestamp = ktime_get_ns(); |
2d700715 | 119 | buf->vb.sequence = dmaq->count++; |
b671ae6b | 120 | list_del(&buf->queue); |
2d700715 | 121 | vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); |
b671ae6b | 122 | } |
1a9fc855 MCC |
123 | spin_unlock(&dev->slock); |
124 | handled++; | |
125 | } | |
126 | return handled; | |
02b20b0b MCC |
127 | } |
128 | ||
df9ecb0c | 129 | static int cx25821_queue_setup(struct vb2_queue *q, |
b671ae6b | 130 | unsigned int *num_buffers, unsigned int *num_planes, |
36c0f8b3 | 131 | unsigned int sizes[], struct device *alloc_devs[]) |
02b20b0b | 132 | { |
b671ae6b | 133 | struct cx25821_channel *chan = q->drv_priv; |
11c8a2df HV |
134 | unsigned size = (chan->fmt->depth * chan->width * chan->height) >> 3; |
135 | ||
df9ecb0c HV |
136 | if (*num_planes) |
137 | return sizes[0] < size ? -EINVAL : 0; | |
02b20b0b | 138 | |
b671ae6b | 139 | *num_planes = 1; |
df9ecb0c | 140 | sizes[0] = size; |
1a9fc855 | 141 | return 0; |
02b20b0b MCC |
142 | } |
143 | ||
b671ae6b | 144 | static int cx25821_buffer_prepare(struct vb2_buffer *vb) |
02b20b0b | 145 | { |
2d700715 | 146 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
b671ae6b | 147 | struct cx25821_channel *chan = vb->vb2_queue->drv_priv; |
2efe2cc4 | 148 | struct cx25821_dev *dev = chan->dev; |
1a9fc855 | 149 | struct cx25821_buffer *buf = |
2d700715 | 150 | container_of(vbuf, struct cx25821_buffer, vb); |
b671ae6b | 151 | struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0); |
30fdf035 | 152 | u32 line0_offset; |
1a9fc855 | 153 | int bpl_local = LINE_SIZE_D1; |
b671ae6b | 154 | int ret; |
1a9fc855 | 155 | |
b671ae6b HV |
156 | if (chan->pixel_formats == PIXEL_FRMT_411) |
157 | buf->bpl = (chan->fmt->depth * chan->width) >> 3; | |
158 | else | |
159 | buf->bpl = (chan->fmt->depth >> 3) * chan->width; | |
bb4c9a74 | 160 | |
b671ae6b | 161 | if (vb2_plane_size(vb, 0) < chan->height * buf->bpl) |
1a9fc855 | 162 | return -EINVAL; |
b671ae6b | 163 | vb2_set_plane_payload(vb, 0, chan->height * buf->bpl); |
2d700715 | 164 | buf->vb.field = chan->field; |
bb4c9a74 | 165 | |
b671ae6b HV |
166 | if (chan->pixel_formats == PIXEL_FRMT_411) { |
167 | bpl_local = buf->bpl; | |
168 | } else { | |
169 | bpl_local = buf->bpl; /* Default */ | |
1a9fc855 | 170 | |
b671ae6b HV |
171 | if (chan->use_cif_resolution) { |
172 | if (dev->tvnorm & V4L2_STD_625_50) | |
173 | bpl_local = 352 << 1; | |
174 | else | |
175 | bpl_local = chan->cif_width << 1; | |
bb4c9a74 | 176 | } |
bb4c9a74 MCC |
177 | } |
178 | ||
b671ae6b HV |
179 | switch (chan->field) { |
180 | case V4L2_FIELD_TOP: | |
181 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
182 | sgt->sgl, 0, UNSET, | |
183 | buf->bpl, 0, chan->height); | |
184 | break; | |
185 | case V4L2_FIELD_BOTTOM: | |
186 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
187 | sgt->sgl, UNSET, 0, | |
188 | buf->bpl, 0, chan->height); | |
189 | break; | |
190 | case V4L2_FIELD_INTERLACED: | |
191 | /* All other formats are top field first */ | |
192 | line0_offset = 0; | |
193 | dprintk(1, "top field first\n"); | |
194 | ||
195 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
196 | sgt->sgl, line0_offset, | |
197 | bpl_local, bpl_local, bpl_local, | |
198 | chan->height >> 1); | |
199 | break; | |
200 | case V4L2_FIELD_SEQ_TB: | |
201 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
202 | sgt->sgl, | |
203 | 0, buf->bpl * (chan->height >> 1), | |
204 | buf->bpl, 0, chan->height >> 1); | |
205 | break; | |
206 | case V4L2_FIELD_SEQ_BT: | |
207 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
208 | sgt->sgl, | |
209 | buf->bpl * (chan->height >> 1), 0, | |
210 | buf->bpl, 0, chan->height >> 1); | |
211 | break; | |
212 | default: | |
213 | WARN_ON(1); | |
214 | ret = -EINVAL; | |
215 | break; | |
bb4c9a74 | 216 | } |
02b20b0b | 217 | |
1a9fc855 | 218 | dprintk(2, "[%p/%d] buffer_prep - %dx%d %dbpp \"%s\" - dma=0x%08lx\n", |
2d700715 | 219 | buf, buf->vb.vb2_buf.index, chan->width, chan->height, |
b671ae6b HV |
220 | chan->fmt->depth, chan->fmt->name, |
221 | (unsigned long)buf->risc.dma); | |
02b20b0b | 222 | |
b671ae6b | 223 | return ret; |
02b20b0b MCC |
224 | } |
225 | ||
b671ae6b | 226 | static void cx25821_buffer_finish(struct vb2_buffer *vb) |
02b20b0b | 227 | { |
2d700715 | 228 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
1a9fc855 | 229 | struct cx25821_buffer *buf = |
2d700715 | 230 | container_of(vbuf, struct cx25821_buffer, vb); |
b671ae6b HV |
231 | struct cx25821_channel *chan = vb->vb2_queue->drv_priv; |
232 | struct cx25821_dev *dev = chan->dev; | |
02b20b0b | 233 | |
b671ae6b | 234 | cx25821_free_buffer(dev, buf); |
02b20b0b MCC |
235 | } |
236 | ||
b671ae6b | 237 | static void cx25821_buffer_queue(struct vb2_buffer *vb) |
6d8c2ba1 | 238 | { |
2d700715 | 239 | struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); |
8e4ac074 | 240 | struct cx25821_buffer *buf = |
2d700715 | 241 | container_of(vbuf, struct cx25821_buffer, vb); |
b671ae6b | 242 | struct cx25821_channel *chan = vb->vb2_queue->drv_priv; |
2efe2cc4 | 243 | struct cx25821_dev *dev = chan->dev; |
b671ae6b | 244 | struct cx25821_buffer *prev; |
2efe2cc4 | 245 | struct cx25821_dmaqueue *q = &dev->channels[chan->id].dma_vidq; |
e6cf66c1 | 246 | |
b671ae6b HV |
247 | buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12); |
248 | buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); | |
249 | buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12); | |
250 | buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ | |
251 | ||
252 | if (list_empty(&q->active)) { | |
253 | list_add_tail(&buf->queue, &q->active); | |
e6cf66c1 | 254 | } else { |
b671ae6b | 255 | buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1); |
e6cf66c1 | 256 | prev = list_entry(q->active.prev, struct cx25821_buffer, |
b671ae6b HV |
257 | queue); |
258 | list_add_tail(&buf->queue, &q->active); | |
259 | prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); | |
8ebbda49 | 260 | } |
6d8c2ba1 PB |
261 | } |
262 | ||
b671ae6b | 263 | static int cx25821_start_streaming(struct vb2_queue *q, unsigned int count) |
6d8c2ba1 | 264 | { |
b671ae6b | 265 | struct cx25821_channel *chan = q->drv_priv; |
8d125c50 | 266 | struct cx25821_dev *dev = chan->dev; |
b671ae6b HV |
267 | struct cx25821_dmaqueue *dmaq = &dev->channels[chan->id].dma_vidq; |
268 | struct cx25821_buffer *buf = list_entry(dmaq->active.next, | |
269 | struct cx25821_buffer, queue); | |
84293f08 | 270 | |
b671ae6b HV |
271 | dmaq->count = 0; |
272 | cx25821_start_video_dma(dev, dmaq, buf, chan->sram_channels); | |
273 | return 0; | |
6d8c2ba1 PB |
274 | } |
275 | ||
b671ae6b | 276 | static void cx25821_stop_streaming(struct vb2_queue *q) |
6d8c2ba1 | 277 | { |
b671ae6b | 278 | struct cx25821_channel *chan = q->drv_priv; |
2efe2cc4 | 279 | struct cx25821_dev *dev = chan->dev; |
b671ae6b HV |
280 | struct cx25821_dmaqueue *dmaq = &dev->channels[chan->id].dma_vidq; |
281 | unsigned long flags; | |
6d8c2ba1 | 282 | |
b671ae6b HV |
283 | cx_write(chan->sram_channels->dma_ctl, 0); /* FIFO and RISC disable */ |
284 | spin_lock_irqsave(&dev->slock, flags); | |
285 | while (!list_empty(&dmaq->active)) { | |
286 | struct cx25821_buffer *buf = list_entry(dmaq->active.next, | |
287 | struct cx25821_buffer, queue); | |
6d8c2ba1 | 288 | |
b671ae6b | 289 | list_del(&buf->queue); |
2d700715 | 290 | vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); |
21377cdd | 291 | } |
b671ae6b | 292 | spin_unlock_irqrestore(&dev->slock, flags); |
6d8c2ba1 PB |
293 | } |
294 | ||
10accd2e | 295 | static const struct vb2_ops cx25821_video_qops = { |
b671ae6b HV |
296 | .queue_setup = cx25821_queue_setup, |
297 | .buf_prepare = cx25821_buffer_prepare, | |
298 | .buf_finish = cx25821_buffer_finish, | |
299 | .buf_queue = cx25821_buffer_queue, | |
300 | .wait_prepare = vb2_ops_wait_prepare, | |
301 | .wait_finish = vb2_ops_wait_finish, | |
302 | .start_streaming = cx25821_start_streaming, | |
303 | .stop_streaming = cx25821_stop_streaming, | |
304 | }; | |
305 | ||
95c232a2 | 306 | /* VIDEO IOCTLS */ |
4c1d0f73 HV |
307 | |
308 | static int cx25821_vidioc_enum_fmt_vid_cap(struct file *file, void *priv, | |
309 | struct v4l2_fmtdesc *f) | |
310 | { | |
311 | if (unlikely(f->index >= ARRAY_SIZE(formats))) | |
312 | return -EINVAL; | |
313 | ||
c0decac1 | 314 | strscpy(f->description, formats[f->index].name, sizeof(f->description)); |
4c1d0f73 HV |
315 | f->pixelformat = formats[f->index].fourcc; |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
95c232a2 HV |
320 | static int cx25821_vidioc_g_fmt_vid_cap(struct file *file, void *priv, |
321 | struct v4l2_format *f) | |
322 | { | |
2efe2cc4 | 323 | struct cx25821_channel *chan = video_drvdata(file); |
95c232a2 | 324 | |
2efe2cc4 HV |
325 | f->fmt.pix.width = chan->width; |
326 | f->fmt.pix.height = chan->height; | |
b671ae6b | 327 | f->fmt.pix.field = chan->field; |
2efe2cc4 | 328 | f->fmt.pix.pixelformat = chan->fmt->fourcc; |
988f7b80 HV |
329 | f->fmt.pix.bytesperline = (chan->width * chan->fmt->depth) >> 3; |
330 | f->fmt.pix.sizeimage = chan->height * f->fmt.pix.bytesperline; | |
331 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; | |
95c232a2 HV |
332 | |
333 | return 0; | |
334 | } | |
335 | ||
336 | static int cx25821_vidioc_try_fmt_vid_cap(struct file *file, void *priv, | |
337 | struct v4l2_format *f) | |
338 | { | |
988f7b80 HV |
339 | struct cx25821_channel *chan = video_drvdata(file); |
340 | struct cx25821_dev *dev = chan->dev; | |
95c232a2 | 341 | const struct cx25821_fmt *fmt; |
988f7b80 | 342 | enum v4l2_field field = f->fmt.pix.field; |
66f93178 | 343 | unsigned int maxh; |
988f7b80 | 344 | unsigned w; |
95c232a2 HV |
345 | |
346 | fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat); | |
347 | if (NULL == fmt) | |
348 | return -EINVAL; | |
988f7b80 HV |
349 | maxh = (dev->tvnorm & V4L2_STD_625_50) ? 576 : 480; |
350 | ||
351 | w = f->fmt.pix.width; | |
352 | if (field != V4L2_FIELD_BOTTOM) | |
353 | field = V4L2_FIELD_TOP; | |
354 | if (w < 352) { | |
355 | w = 176; | |
356 | f->fmt.pix.height = maxh / 4; | |
357 | } else if (w < 720) { | |
358 | w = 352; | |
359 | f->fmt.pix.height = maxh / 2; | |
360 | } else { | |
361 | w = 720; | |
362 | f->fmt.pix.height = maxh; | |
363 | field = V4L2_FIELD_INTERLACED; | |
95c232a2 | 364 | } |
95c232a2 | 365 | f->fmt.pix.field = field; |
988f7b80 | 366 | f->fmt.pix.width = w; |
95c232a2 HV |
367 | f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; |
368 | f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; | |
988f7b80 | 369 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; |
95c232a2 HV |
370 | |
371 | return 0; | |
372 | } | |
6d8c2ba1 PB |
373 | |
374 | static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, | |
c1e6e241 | 375 | struct v4l2_format *f) |
6d8c2ba1 | 376 | { |
2efe2cc4 | 377 | struct cx25821_channel *chan = video_drvdata(file); |
8d125c50 | 378 | struct cx25821_dev *dev = chan->dev; |
a39bea3a | 379 | int pix_format = PIXEL_FRMT_422; |
a6aa0dc4 | 380 | int err; |
a39bea3a | 381 | |
255c040a | 382 | err = cx25821_vidioc_try_fmt_vid_cap(file, priv, f); |
6d8c2ba1 | 383 | |
255c040a LF |
384 | if (0 != err) |
385 | return err; | |
6d8c2ba1 | 386 | |
2efe2cc4 | 387 | chan->fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat); |
b671ae6b | 388 | chan->field = f->fmt.pix.field; |
988f7b80 HV |
389 | chan->width = f->fmt.pix.width; |
390 | chan->height = f->fmt.pix.height; | |
6d8c2ba1 | 391 | |
6678762a LF |
392 | if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) |
393 | pix_format = PIXEL_FRMT_411; | |
6678762a | 394 | else |
988f7b80 | 395 | pix_format = PIXEL_FRMT_422; |
6d8c2ba1 | 396 | |
6678762a | 397 | cx25821_set_pixel_format(dev, SRAM_CH00, pix_format); |
6d8c2ba1 | 398 | |
6678762a | 399 | /* check if cif resolution */ |
2efe2cc4 HV |
400 | if (chan->width == 320 || chan->width == 352) |
401 | chan->use_cif_resolution = 1; | |
6678762a | 402 | else |
2efe2cc4 | 403 | chan->use_cif_resolution = 0; |
6d8c2ba1 | 404 | |
2efe2cc4 HV |
405 | chan->cif_width = chan->width; |
406 | medusa_set_resolution(dev, chan->width, SRAM_CH00); | |
6678762a | 407 | return 0; |
6d8c2ba1 PB |
408 | } |
409 | ||
6d8c2ba1 PB |
410 | static int vidioc_log_status(struct file *file, void *priv) |
411 | { | |
8d125c50 HV |
412 | struct cx25821_channel *chan = video_drvdata(file); |
413 | struct cx25821_dev *dev = chan->dev; | |
414 | const struct sram_channel *sram_ch = chan->sram_channels; | |
02859b61 | 415 | u32 tmp = 0; |
6d8c2ba1 | 416 | |
02859b61 | 417 | tmp = cx_read(sram_ch->dma_ctl); |
36d89f7d JP |
418 | pr_info("Video input 0 is %s\n", |
419 | (tmp & 0x11) ? "streaming" : "stopped"); | |
02859b61 | 420 | return 0; |
6d8c2ba1 PB |
421 | } |
422 | ||
02b20b0b | 423 | |
95c232a2 | 424 | static int cx25821_vidioc_querycap(struct file *file, void *priv, |
c1e6e241 | 425 | struct v4l2_capability *cap) |
02b20b0b | 426 | { |
8d125c50 HV |
427 | struct cx25821_channel *chan = video_drvdata(file); |
428 | struct cx25821_dev *dev = chan->dev; | |
3dd473ca HV |
429 | const u32 cap_input = V4L2_CAP_VIDEO_CAPTURE | |
430 | V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; | |
0df13d99 | 431 | const u32 cap_output = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_READWRITE; |
1a9fc855 | 432 | |
cc1e6315 | 433 | strscpy(cap->driver, "cx25821", sizeof(cap->driver)); |
c0decac1 | 434 | strscpy(cap->card, cx25821_boards[dev->board].name, sizeof(cap->card)); |
1a9fc855 | 435 | sprintf(cap->bus_info, "PCIe:%s", pci_name(dev->pci)); |
8d125c50 | 436 | if (chan->id >= VID_CHANNEL_NUM) |
3dd473ca HV |
437 | cap->device_caps = cap_output; |
438 | else | |
439 | cap->device_caps = cap_input; | |
0df13d99 | 440 | cap->capabilities = cap_input | cap_output | V4L2_CAP_DEVICE_CAPS; |
1a9fc855 | 441 | return 0; |
02b20b0b MCC |
442 | } |
443 | ||
95c232a2 | 444 | static int cx25821_vidioc_g_std(struct file *file, void *priv, v4l2_std_id *tvnorms) |
18c73af6 | 445 | { |
8d125c50 | 446 | struct cx25821_channel *chan = video_drvdata(file); |
18c73af6 | 447 | |
8d125c50 | 448 | *tvnorms = chan->dev->tvnorm; |
18c73af6 HV |
449 | return 0; |
450 | } | |
451 | ||
a3f17af2 MCC |
452 | static int cx25821_vidioc_s_std(struct file *file, void *priv, |
453 | v4l2_std_id tvnorms) | |
02b20b0b | 454 | { |
8d125c50 HV |
455 | struct cx25821_channel *chan = video_drvdata(file); |
456 | struct cx25821_dev *dev = chan->dev; | |
02b20b0b | 457 | |
314527ac | 458 | if (dev->tvnorm == tvnorms) |
1a9fc855 | 459 | return 0; |
02b20b0b | 460 | |
a6aa0dc4 | 461 | dev->tvnorm = tvnorms; |
988f7b80 HV |
462 | chan->width = 720; |
463 | chan->height = (dev->tvnorm & V4L2_STD_625_50) ? 576 : 480; | |
02b20b0b | 464 | |
1a9fc855 | 465 | medusa_set_videostandard(dev); |
02b20b0b | 466 | |
1a9fc855 | 467 | return 0; |
02b20b0b | 468 | } |
02b20b0b | 469 | |
95c232a2 HV |
470 | static int cx25821_vidioc_enum_input(struct file *file, void *priv, |
471 | struct v4l2_input *i) | |
02b20b0b | 472 | { |
a6aa0dc4 | 473 | if (i->index) |
1a9fc855 | 474 | return -EINVAL; |
02b20b0b | 475 | |
1a9fc855 | 476 | i->type = V4L2_INPUT_TYPE_CAMERA; |
1a9fc855 | 477 | i->std = CX25821_NORMS; |
cc1e6315 | 478 | strscpy(i->name, "Composite", sizeof(i->name)); |
1a9fc855 | 479 | return 0; |
02b20b0b MCC |
480 | } |
481 | ||
95c232a2 | 482 | static int cx25821_vidioc_g_input(struct file *file, void *priv, unsigned int *i) |
bb4c9a74 | 483 | { |
a6aa0dc4 | 484 | *i = 0; |
1a9fc855 | 485 | return 0; |
02b20b0b MCC |
486 | } |
487 | ||
95c232a2 | 488 | static int cx25821_vidioc_s_input(struct file *file, void *priv, unsigned int i) |
02b20b0b | 489 | { |
a6aa0dc4 | 490 | return i ? -EINVAL : 0; |
02b20b0b MCC |
491 | } |
492 | ||
f8d7ee70 | 493 | static int cx25821_s_ctrl(struct v4l2_ctrl *ctrl) |
02b20b0b | 494 | { |
f8d7ee70 HV |
495 | struct cx25821_channel *chan = |
496 | container_of(ctrl->handler, struct cx25821_channel, hdl); | |
497 | struct cx25821_dev *dev = chan->dev; | |
02b20b0b | 498 | |
f8d7ee70 | 499 | switch (ctrl->id) { |
1a9fc855 | 500 | case V4L2_CID_BRIGHTNESS: |
f8d7ee70 | 501 | medusa_set_brightness(dev, ctrl->val, chan->id); |
02b20b0b | 502 | break; |
1a9fc855 | 503 | case V4L2_CID_HUE: |
f8d7ee70 | 504 | medusa_set_hue(dev, ctrl->val, chan->id); |
02b20b0b | 505 | break; |
1a9fc855 | 506 | case V4L2_CID_CONTRAST: |
f8d7ee70 | 507 | medusa_set_contrast(dev, ctrl->val, chan->id); |
02b20b0b | 508 | break; |
1a9fc855 | 509 | case V4L2_CID_SATURATION: |
f8d7ee70 | 510 | medusa_set_saturation(dev, ctrl->val, chan->id); |
02b20b0b | 511 | break; |
1a9fc855 | 512 | default: |
f8d7ee70 | 513 | return -EINVAL; |
02b20b0b | 514 | } |
f8d7ee70 | 515 | return 0; |
02b20b0b MCC |
516 | } |
517 | ||
1f198870 HV |
518 | static int cx25821_vidioc_enum_output(struct file *file, void *priv, |
519 | struct v4l2_output *o) | |
6d8c2ba1 | 520 | { |
1f198870 HV |
521 | if (o->index) |
522 | return -EINVAL; | |
6d8c2ba1 | 523 | |
1f198870 HV |
524 | o->type = V4L2_INPUT_TYPE_CAMERA; |
525 | o->std = CX25821_NORMS; | |
cc1e6315 | 526 | strscpy(o->name, "Composite", sizeof(o->name)); |
6f87cc6c | 527 | return 0; |
6d8c2ba1 PB |
528 | } |
529 | ||
1f198870 | 530 | static int cx25821_vidioc_g_output(struct file *file, void *priv, unsigned int *o) |
6d8c2ba1 | 531 | { |
1f198870 | 532 | *o = 0; |
f9ef6be3 | 533 | return 0; |
6d8c2ba1 PB |
534 | } |
535 | ||
1f198870 | 536 | static int cx25821_vidioc_s_output(struct file *file, void *priv, unsigned int o) |
6d8c2ba1 | 537 | { |
1f198870 | 538 | return o ? -EINVAL : 0; |
6d8c2ba1 PB |
539 | } |
540 | ||
e90878ab HV |
541 | static int cx25821_vidioc_try_fmt_vid_out(struct file *file, void *priv, |
542 | struct v4l2_format *f) | |
543 | { | |
544 | struct cx25821_channel *chan = video_drvdata(file); | |
545 | struct cx25821_dev *dev = chan->dev; | |
546 | const struct cx25821_fmt *fmt; | |
547 | ||
548 | fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat); | |
549 | if (NULL == fmt) | |
550 | return -EINVAL; | |
551 | f->fmt.pix.width = 720; | |
552 | f->fmt.pix.height = (dev->tvnorm & V4L2_STD_625_50) ? 576 : 480; | |
553 | f->fmt.pix.field = V4L2_FIELD_INTERLACED; | |
554 | f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; | |
555 | f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; | |
556 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; | |
e90878ab HV |
557 | return 0; |
558 | } | |
559 | ||
560 | static int vidioc_s_fmt_vid_out(struct file *file, void *priv, | |
561 | struct v4l2_format *f) | |
562 | { | |
563 | struct cx25821_channel *chan = video_drvdata(file); | |
564 | int err; | |
565 | ||
566 | err = cx25821_vidioc_try_fmt_vid_out(file, priv, f); | |
567 | ||
568 | if (0 != err) | |
569 | return err; | |
570 | ||
571 | chan->fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat); | |
b671ae6b | 572 | chan->field = f->fmt.pix.field; |
e90878ab HV |
573 | chan->width = f->fmt.pix.width; |
574 | chan->height = f->fmt.pix.height; | |
575 | if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) | |
576 | chan->pixel_formats = PIXEL_FRMT_411; | |
577 | else | |
578 | chan->pixel_formats = PIXEL_FRMT_422; | |
579 | return 0; | |
580 | } | |
581 | ||
f8d7ee70 HV |
582 | static const struct v4l2_ctrl_ops cx25821_ctrl_ops = { |
583 | .s_ctrl = cx25821_s_ctrl, | |
584 | }; | |
585 | ||
6d8c2ba1 | 586 | static const struct v4l2_file_operations video_fops = { |
fa7ce1f4 | 587 | .owner = THIS_MODULE, |
8d125c50 | 588 | .open = v4l2_fh_open, |
b671ae6b HV |
589 | .release = vb2_fop_release, |
590 | .read = vb2_fop_read, | |
591 | .poll = vb2_fop_poll, | |
1f198870 | 592 | .unlocked_ioctl = video_ioctl2, |
b671ae6b | 593 | .mmap = vb2_fop_mmap, |
6d8c2ba1 PB |
594 | }; |
595 | ||
596 | static const struct v4l2_ioctl_ops video_ioctl_ops = { | |
fa7ce1f4 LF |
597 | .vidioc_querycap = cx25821_vidioc_querycap, |
598 | .vidioc_enum_fmt_vid_cap = cx25821_vidioc_enum_fmt_vid_cap, | |
599 | .vidioc_g_fmt_vid_cap = cx25821_vidioc_g_fmt_vid_cap, | |
600 | .vidioc_try_fmt_vid_cap = cx25821_vidioc_try_fmt_vid_cap, | |
601 | .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, | |
b671ae6b HV |
602 | .vidioc_reqbufs = vb2_ioctl_reqbufs, |
603 | .vidioc_prepare_buf = vb2_ioctl_prepare_buf, | |
11c8a2df | 604 | .vidioc_create_bufs = vb2_ioctl_create_bufs, |
b671ae6b HV |
605 | .vidioc_querybuf = vb2_ioctl_querybuf, |
606 | .vidioc_qbuf = vb2_ioctl_qbuf, | |
607 | .vidioc_dqbuf = vb2_ioctl_dqbuf, | |
608 | .vidioc_streamon = vb2_ioctl_streamon, | |
609 | .vidioc_streamoff = vb2_ioctl_streamoff, | |
18c73af6 | 610 | .vidioc_g_std = cx25821_vidioc_g_std, |
fa7ce1f4 | 611 | .vidioc_s_std = cx25821_vidioc_s_std, |
fa7ce1f4 LF |
612 | .vidioc_enum_input = cx25821_vidioc_enum_input, |
613 | .vidioc_g_input = cx25821_vidioc_g_input, | |
614 | .vidioc_s_input = cx25821_vidioc_s_input, | |
fa7ce1f4 | 615 | .vidioc_log_status = vidioc_log_status, |
8d125c50 HV |
616 | .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, |
617 | .vidioc_unsubscribe_event = v4l2_event_unsubscribe, | |
6d8c2ba1 PB |
618 | }; |
619 | ||
ffd3c233 HV |
620 | static const struct video_device cx25821_video_device = { |
621 | .name = "cx25821-video", | |
527db49d | 622 | .fops = &video_fops, |
467870ca | 623 | .release = video_device_release_empty, |
ffd3c233 | 624 | .minor = -1, |
527db49d LF |
625 | .ioctl_ops = &video_ioctl_ops, |
626 | .tvnorms = CX25821_NORMS, | |
6d8c2ba1 | 627 | }; |
ffd3c233 | 628 | |
1f198870 HV |
629 | static const struct v4l2_file_operations video_out_fops = { |
630 | .owner = THIS_MODULE, | |
631 | .open = v4l2_fh_open, | |
b671ae6b HV |
632 | .release = vb2_fop_release, |
633 | .write = vb2_fop_write, | |
634 | .poll = vb2_fop_poll, | |
1f198870 | 635 | .unlocked_ioctl = video_ioctl2, |
b671ae6b | 636 | .mmap = vb2_fop_mmap, |
1f198870 HV |
637 | }; |
638 | ||
639 | static const struct v4l2_ioctl_ops video_out_ioctl_ops = { | |
640 | .vidioc_querycap = cx25821_vidioc_querycap, | |
e90878ab HV |
641 | .vidioc_enum_fmt_vid_out = cx25821_vidioc_enum_fmt_vid_cap, |
642 | .vidioc_g_fmt_vid_out = cx25821_vidioc_g_fmt_vid_cap, | |
643 | .vidioc_try_fmt_vid_out = cx25821_vidioc_try_fmt_vid_out, | |
644 | .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out, | |
1f198870 HV |
645 | .vidioc_g_std = cx25821_vidioc_g_std, |
646 | .vidioc_s_std = cx25821_vidioc_s_std, | |
647 | .vidioc_enum_output = cx25821_vidioc_enum_output, | |
648 | .vidioc_g_output = cx25821_vidioc_g_output, | |
649 | .vidioc_s_output = cx25821_vidioc_s_output, | |
650 | .vidioc_log_status = vidioc_log_status, | |
651 | }; | |
652 | ||
653 | static const struct video_device cx25821_video_out_device = { | |
654 | .name = "cx25821-video", | |
655 | .fops = &video_out_fops, | |
656 | .release = video_device_release_empty, | |
657 | .minor = -1, | |
658 | .ioctl_ops = &video_out_ioctl_ops, | |
659 | .tvnorms = CX25821_NORMS, | |
660 | }; | |
661 | ||
ffd3c233 HV |
662 | void cx25821_video_unregister(struct cx25821_dev *dev, int chan_num) |
663 | { | |
664 | cx_clear(PCI_INT_MSK, 1); | |
665 | ||
467870ca HV |
666 | if (video_is_registered(&dev->channels[chan_num].vdev)) { |
667 | video_unregister_device(&dev->channels[chan_num].vdev); | |
f8d7ee70 | 668 | v4l2_ctrl_handler_free(&dev->channels[chan_num].hdl); |
ffd3c233 | 669 | } |
ffd3c233 HV |
670 | } |
671 | ||
672 | int cx25821_video_register(struct cx25821_dev *dev) | |
673 | { | |
674 | int err; | |
675 | int i; | |
676 | ||
be178cb4 | 677 | /* initial device configuration */ |
a6aa0dc4 | 678 | dev->tvnorm = V4L2_STD_NTSC_M; |
be178cb4 | 679 | |
ffd3c233 HV |
680 | spin_lock_init(&dev->slock); |
681 | ||
b6f21dc3 | 682 | for (i = 0; i < MAX_VID_CAP_CHANNEL_NUM - 1; ++i) { |
2efe2cc4 HV |
683 | struct cx25821_channel *chan = &dev->channels[i]; |
684 | struct video_device *vdev = &chan->vdev; | |
685 | struct v4l2_ctrl_handler *hdl = &chan->hdl; | |
b671ae6b | 686 | struct vb2_queue *q; |
1f198870 | 687 | bool is_output = i > SRAM_CH08; |
467870ca | 688 | |
ffd3c233 HV |
689 | if (i == SRAM_CH08) /* audio channel */ |
690 | continue; | |
691 | ||
1f198870 HV |
692 | if (!is_output) { |
693 | v4l2_ctrl_handler_init(hdl, 4); | |
694 | v4l2_ctrl_new_std(hdl, &cx25821_ctrl_ops, | |
695 | V4L2_CID_BRIGHTNESS, 0, 10000, 1, 6200); | |
696 | v4l2_ctrl_new_std(hdl, &cx25821_ctrl_ops, | |
697 | V4L2_CID_CONTRAST, 0, 10000, 1, 5000); | |
698 | v4l2_ctrl_new_std(hdl, &cx25821_ctrl_ops, | |
699 | V4L2_CID_SATURATION, 0, 10000, 1, 5000); | |
700 | v4l2_ctrl_new_std(hdl, &cx25821_ctrl_ops, | |
701 | V4L2_CID_HUE, 0, 10000, 1, 5000); | |
702 | if (hdl->error) { | |
703 | err = hdl->error; | |
704 | goto fail_unreg; | |
705 | } | |
706 | err = v4l2_ctrl_handler_setup(hdl); | |
707 | if (err) | |
708 | goto fail_unreg; | |
7087d31b HV |
709 | } else { |
710 | chan->out = &dev->vid_out_data[i - SRAM_CH09]; | |
711 | chan->out->chan = chan; | |
f8d7ee70 | 712 | } |
ffd3c233 | 713 | |
2efe2cc4 | 714 | chan->sram_channels = &cx25821_sram_channels[i]; |
2efe2cc4 | 715 | chan->width = 720; |
b671ae6b | 716 | chan->field = V4L2_FIELD_INTERLACED; |
2efe2cc4 HV |
717 | if (dev->tvnorm & V4L2_STD_625_50) |
718 | chan->height = 576; | |
719 | else | |
720 | chan->height = 480; | |
ffd3c233 | 721 | |
2efe2cc4 HV |
722 | if (chan->pixel_formats == PIXEL_FRMT_411) |
723 | chan->fmt = cx25821_format_by_fourcc(V4L2_PIX_FMT_Y41P); | |
724 | else | |
725 | chan->fmt = cx25821_format_by_fourcc(V4L2_PIX_FMT_YUYV); | |
ffd3c233 | 726 | |
2efe2cc4 | 727 | cx_write(chan->sram_channels->int_stat, 0xffffffff); |
ffd3c233 | 728 | |
2efe2cc4 | 729 | INIT_LIST_HEAD(&chan->dma_vidq.active); |
2efe2cc4 | 730 | |
b671ae6b HV |
731 | q = &chan->vidq; |
732 | ||
733 | q->type = is_output ? V4L2_BUF_TYPE_VIDEO_OUTPUT : | |
734 | V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
735 | q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; | |
736 | q->io_modes |= is_output ? VB2_WRITE : VB2_READ; | |
737 | q->gfp_flags = GFP_DMA32; | |
738 | q->min_buffers_needed = 2; | |
739 | q->drv_priv = chan; | |
740 | q->buf_struct_size = sizeof(struct cx25821_buffer); | |
741 | q->ops = &cx25821_video_qops; | |
742 | q->mem_ops = &vb2_dma_sg_memops; | |
743 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; | |
744 | q->lock = &dev->lock; | |
2bc46b3a | 745 | q->dev = &dev->pci->dev; |
2efe2cc4 | 746 | |
b671ae6b HV |
747 | if (!is_output) { |
748 | err = vb2_queue_init(q); | |
749 | if (err < 0) | |
750 | goto fail_unreg; | |
751 | } | |
ffd3c233 HV |
752 | |
753 | /* register v4l devices */ | |
1f198870 | 754 | *vdev = is_output ? cx25821_video_out_device : cx25821_video_device; |
467870ca | 755 | vdev->v4l2_dev = &dev->v4l2_dev; |
1f198870 HV |
756 | if (!is_output) |
757 | vdev->ctrl_handler = hdl; | |
758 | else | |
759 | vdev->vfl_dir = VFL_DIR_TX; | |
be178cb4 | 760 | vdev->lock = &dev->lock; |
b671ae6b | 761 | vdev->queue = q; |
467870ca | 762 | snprintf(vdev->name, sizeof(vdev->name), "%s #%d", dev->name, i); |
2efe2cc4 | 763 | video_set_drvdata(vdev, chan); |
ffd3c233 | 764 | |
467870ca HV |
765 | err = video_register_device(vdev, VFL_TYPE_GRABBER, |
766 | video_nr[dev->nr]); | |
ffd3c233 HV |
767 | |
768 | if (err < 0) | |
769 | goto fail_unreg; | |
ffd3c233 HV |
770 | } |
771 | ||
772 | /* set PCI interrupt */ | |
773 | cx_set(PCI_INT_MSK, 0xff); | |
774 | ||
ffd3c233 HV |
775 | return 0; |
776 | ||
777 | fail_unreg: | |
467870ca HV |
778 | while (i >= 0) |
779 | cx25821_video_unregister(dev, i--); | |
ffd3c233 HV |
780 | return err; |
781 | } |