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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
[thirdparty/kernel/stable.git] / drivers / media / pci / cx88 / cx88-dvb.c
CommitLineData
c942fddf 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 2/*
1da177e4
LT		 3 * device driver for Conexant 2388x based TV cards
4 * MPEG Transport Stream (DVB) routines
5 *
fc40b261 6 * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
1da177e4 7 * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
1da177e4
LT		 8 */
9
65bc2fe8
MCC		 10#include "cx88.h"
11#include "dvb-pll.h"
12
1da177e4
LT		 13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/device.h>
16#include <linux/fs.h>
17#include <linux/kthread.h>
18#include <linux/file.h>
19#include <linux/suspend.h>
20
5e453dc7 21#include <media/v4l2-common.h>
41ef7c1e 22
1f10c7af
AQ		 23#include "mt352.h"
24#include "mt352_priv.h"
ecf854df 25#include "cx88-vp3054-i2c.h"
1f10c7af
AQ		 26#include "zl10353.h"
27#include "cx22702.h"
28#include "or51132.h"
29#include "lgdt330x.h"
60464da8 30#include "s5h1409.h"
c21973e8 31#include "xc4000.h"
60464da8 32#include "xc5000.h"
1f10c7af
AQ		 33#include "nxt200x.h"
34#include "cx24123.h"
cd20ca9f 35#include "isl6421.h"
0df31f83 36#include "tuner-simple.h"
827855d3 37#include "tda9887.h"
d893d5dc 38#include "s5h1411.h"
e4aab64c
IL		 39#include "stv0299.h"
40#include "z0194a.h"
41#include "stv0288.h"
42#include "stb6000.h"
5bd1b663 43#include "cx24116.h"
b699c271
IL		 44#include "stv0900.h"
45#include "stb6100.h"
46#include "stb6100_proc.h"
111ac84a 47#include "mb86a16.h"
73f0af44 48#include "ts2020.h"
0cb73639 49#include "ds3000.h"
1da177e4
LT		 50
51MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
52MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
53MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
54MODULE_LICENSE("GPL");
1990d50b 55MODULE_VERSION(CX88_VERSION);
1da177e4 56
ff699e6b 57static unsigned int debug;
1da177e4 58module_param(debug, int, 0644);
7b61ba8f 59MODULE_PARM_DESC(debug, "enable debug messages [dvb]");
1da177e4 60
44c6e2a7
AWC		 61static unsigned int dvb_buf_tscnt = 32;
62module_param(dvb_buf_tscnt, int, 0644);
63MODULE_PARM_DESC(dvb_buf_tscnt, "DVB Buffer TS count [dvb]");
64
78e92006
JG		 65DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
66
65bc2fe8
MCC		 67#define dprintk(level, fmt, arg...) do { \
68 if (debug >= level) \
69 printk(KERN_DEBUG pr_fmt("%s: dvb:" fmt), \
70 __func__, ##arg); \
71} while (0)
1da177e4
LT		 72
73/* ------------------------------------------------------------------ */
74
df9ecb0c 75static int queue_setup(struct vb2_queue *q,
399426ca
MCC		 76 unsigned int *num_buffers, unsigned int *num_planes,
77 unsigned int sizes[], struct device *alloc_devs[])
1da177e4 78{
0b6b6302 79 struct cx8802_dev *dev = q->drv_priv;
1da177e4 80
0b6b6302 81 *num_planes = 1;
1da177e4 82 dev->ts_packet_size = 188 * 4;
44c6e2a7 83 dev->ts_packet_count = dvb_buf_tscnt;
0b6b6302
HV		 84 sizes[0] = dev->ts_packet_size * dev->ts_packet_count;
85 *num_buffers = dvb_buf_tscnt;
1da177e4
LT		 86 return 0;
87}
88
0b6b6302
HV		 89static int buffer_prepare(struct vb2_buffer *vb)
90{
2d700715 91 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
0b6b6302 92 struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
2d700715 93 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
0b6b6302 94
ccd6f1d4 95 return cx8802_buf_prepare(vb->vb2_queue, dev, buf);
0b6b6302
HV		 96}
97
98static void buffer_finish(struct vb2_buffer *vb)
99{
2d700715 100 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
0b6b6302 101 struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
2d700715 102 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
5e7045e3 103 struct cx88_riscmem *risc = &buf->risc;
0b6b6302 104
5e7045e3
HV		 105 if (risc->cpu)
106 pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma);
107 memset(risc, 0, sizeof(*risc));
0b6b6302
HV		 108}
109
110static void buffer_queue(struct vb2_buffer *vb)
1da177e4 111{
2d700715 112 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
0b6b6302 113 struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
2d700715 114 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
0b6b6302
HV		 115
116 cx8802_buf_queue(dev, buf);
1da177e4
LT		 117}
118
0b6b6302 119static int start_streaming(struct vb2_queue *q, unsigned int count)
1da177e4 120{
0b6b6302
HV		 121 struct cx8802_dev *dev = q->drv_priv;
122 struct cx88_dmaqueue *dmaq = &dev->mpegq;
123 struct cx88_buffer *buf;
124
125 buf = list_entry(dmaq->active.next, struct cx88_buffer, list);
126 cx8802_start_dma(dev, dmaq, buf);
127 return 0;
1da177e4
LT		 128}
129
0b6b6302 130static void stop_streaming(struct vb2_queue *q)
1da177e4 131{
0b6b6302
HV		 132 struct cx8802_dev *dev = q->drv_priv;
133 struct cx88_dmaqueue *dmaq = &dev->mpegq;
134 unsigned long flags;
135
136 cx8802_cancel_buffers(dev);
137
138 spin_lock_irqsave(&dev->slock, flags);
139 while (!list_empty(&dmaq->active)) {
140 struct cx88_buffer *buf = list_entry(dmaq->active.next,
141 struct cx88_buffer, list);
142
143 list_del(&buf->list);
2d700715 144 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
0b6b6302
HV		 145 }
146 spin_unlock_irqrestore(&dev->slock, flags);
1da177e4
LT		 147}
148
10accd2e 149static const struct vb2_ops dvb_qops = {
0b6b6302
HV		 150 .queue_setup = queue_setup,
151 .buf_prepare = buffer_prepare,
152 .buf_finish = buffer_finish,
153 .buf_queue = buffer_queue,
154 .wait_prepare = vb2_ops_wait_prepare,
155 .wait_finish = vb2_ops_wait_finish,
156 .start_streaming = start_streaming,
157 .stop_streaming = stop_streaming,
1da177e4
LT		 158};
159
160/* ------------------------------------------------------------------ */
22f3f17d 161
7b61ba8f 162static int cx88_dvb_bus_ctrl(struct dvb_frontend *fe, int acquire)
22f3f17d 163{
7b61ba8f 164 struct cx8802_dev *dev = fe->dvb->priv;
22f3f17d
MK		 165 struct cx8802_driver *drv = NULL;
166 int ret = 0;
363c35fc
ST		 167 int fe_id;
168
0b6b6302 169 fe_id = vb2_dvb_find_frontend(&dev->frontends, fe);
363c35fc 170 if (!fe_id) {
65bc2fe8 171 pr_err("%s() No frontend found\n", __func__);
363c35fc
ST		 172 return -EINVAL;
173 }
174
8a317a87 175 mutex_lock(&dev->core->lock);
22f3f17d
MK		 176 drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
177 if (drv) {
7b61ba8f 178 if (acquire) {
363c35fc 179 dev->frontends.active_fe_id = fe_id;
22f3f17d 180 ret = drv->request_acquire(drv);
363c35fc 181 } else {
22f3f17d 182 ret = drv->request_release(drv);
363c35fc
ST		 183 dev->frontends.active_fe_id = 0;
184 }
22f3f17d 185 }
1fe70e96 186 mutex_unlock(&dev->core->lock);
22f3f17d
MK		 187
188 return ret;
189}
190
e32fadc4
MCC		 191static void cx88_dvb_gate_ctrl(struct cx88_core *core, int open)
192{
0b6b6302
HV		 193 struct vb2_dvb_frontends *f;
194 struct vb2_dvb_frontend *fe;
e32fadc4
MCC		 195
196 if (!core->dvbdev)
197 return;
198
199 f = &core->dvbdev->frontends;
200
201 if (!f)
202 return;
203
204 if (f->gate <= 1) /* undefined or fe0 */
0b6b6302 205 fe = vb2_dvb_get_frontend(f, 1);
e32fadc4 206 else
0b6b6302 207 fe = vb2_dvb_get_frontend(f, f->gate);
e32fadc4
MCC		 208
209 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
210 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
211}
212
22f3f17d
MK		 213/* ------------------------------------------------------------------ */
214
7b61ba8f 215static int dvico_fusionhdtv_demod_init(struct dvb_frontend *fe)
1da177e4 216{
7b61ba8f
MCC		 217 static const u8 clock_config[] = { CLOCK_CTL, 0x38, 0x39 };
218 static const u8 reset[] = { RESET, 0x80 };
219 static const u8 adc_ctl_1_cfg[] = { ADC_CTL_1, 0x40 };
220 static const u8 agc_cfg[] = { AGC_TARGET, 0x24, 0x20 };
221 static const u8 gpp_ctl_cfg[] = { GPP_CTL, 0x33 };
2e4e98e7 222 static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
1da177e4
LT		 223
224 mt352_write(fe, clock_config, sizeof(clock_config));
225 udelay(200);
226 mt352_write(fe, reset, sizeof(reset));
227 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
228
229 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
230 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
231 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
232 return 0;
233}
234
43eabb4e
CP		 235static int dvico_dual_demod_init(struct dvb_frontend *fe)
236{
7b61ba8f
MCC		 237 static const u8 clock_config[] = { CLOCK_CTL, 0x38, 0x38 };
238 static const u8 reset[] = { RESET, 0x80 };
239 static const u8 adc_ctl_1_cfg[] = { ADC_CTL_1, 0x40 };
240 static const u8 agc_cfg[] = { AGC_TARGET, 0x28, 0x20 };
241 static const u8 gpp_ctl_cfg[] = { GPP_CTL, 0x33 };
2e4e98e7 242 static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
43eabb4e
CP		 243
244 mt352_write(fe, clock_config, sizeof(clock_config));
245 udelay(200);
246 mt352_write(fe, reset, sizeof(reset));
247 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
248
249 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
250 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
251 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
252
253 return 0;
254}
255
7b61ba8f 256static int dntv_live_dvbt_demod_init(struct dvb_frontend *fe)
1da177e4 257{
7b61ba8f
MCC		 258 static const u8 clock_config[] = { 0x89, 0x38, 0x39 };
259 static const u8 reset[] = { 0x50, 0x80 };
260 static const u8 adc_ctl_1_cfg[] = { 0x8E, 0x40 };
261 static const u8 agc_cfg[] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
f2421ca3 262 0x00, 0xFF, 0x00, 0x40, 0x40 };
2e4e98e7 263 static const u8 dntv_extra[] = { 0xB5, 0x7A };
264 static const u8 capt_range_cfg[] = { 0x75, 0x32 };
1da177e4
LT		 265
266 mt352_write(fe, clock_config, sizeof(clock_config));
267 udelay(2000);
268 mt352_write(fe, reset, sizeof(reset));
269 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
270
271 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
272 udelay(2000);
273 mt352_write(fe, dntv_extra, sizeof(dntv_extra));
274 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
275
276 return 0;
277}
278
2e4e98e7 279static const struct mt352_config dvico_fusionhdtv = {
f7b54b10 280 .demod_address = 0x0f,
3d7d027a 281 .demod_init = dvico_fusionhdtv_demod_init,
1da177e4
LT		 282};
283
2e4e98e7 284static const struct mt352_config dntv_live_dvbt_config = {
1da177e4
LT		 285 .demod_address = 0x0f,
286 .demod_init = dntv_live_dvbt_demod_init,
1da177e4 287};
fc40b261 288
2e4e98e7 289static const struct mt352_config dvico_fusionhdtv_dual = {
f7b54b10 290 .demod_address = 0x0f,
43eabb4e 291 .demod_init = dvico_dual_demod_init,
43eabb4e
CP		 292};
293
2e4e98e7 294static const struct zl10353_config cx88_terratec_cinergy_ht_pci_mkii_config = {
70101a27
SW		 295 .demod_address = (0x1e >> 1),
296 .no_tuner = 1,
297 .if2 = 45600,
298};
299
0244fd78 300static const struct mb86a16_config twinhan_vp1027 = {
111ac84a
SI		 301 .demod_address = 0x08,
302};
303
7b34be71 304#if IS_ENABLED(CONFIG_VIDEO_CX88_VP3054)
7b61ba8f 305static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend *fe)
3d7d027a 306{
7b61ba8f
MCC		 307 static const u8 clock_config[] = { 0x89, 0x38, 0x38 };
308 static const u8 reset[] = { 0x50, 0x80 };
309 static const u8 adc_ctl_1_cfg[] = { 0x8E, 0x40 };
310 static const u8 agc_cfg[] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
3d7d027a 311 0x00, 0xFF, 0x00, 0x40, 0x40 };
2e4e98e7 312 static const u8 dntv_extra[] = { 0xB5, 0x7A };
313 static const u8 capt_range_cfg[] = { 0x75, 0x32 };
3d7d027a
CP		 314
315 mt352_write(fe, clock_config, sizeof(clock_config));
316 udelay(2000);
317 mt352_write(fe, reset, sizeof(reset));
318 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
319
320 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
321 udelay(2000);
322 mt352_write(fe, dntv_extra, sizeof(dntv_extra));
323 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
324
325 return 0;
326}
327
2e4e98e7 328static const struct mt352_config dntv_live_dvbt_pro_config = {
fc40b261
CP		 329 .demod_address = 0x0f,
330 .no_tuner = 1,
3d7d027a 331 .demod_init = dntv_live_dvbt_pro_demod_init,
fc40b261
CP		 332};
333#endif
1da177e4 334
2e4e98e7 335static const struct zl10353_config dvico_fusionhdtv_hybrid = {
f7b54b10 336 .demod_address = 0x0f,
f54376e2 337 .no_tuner = 1,
780dfef3
CP		 338};
339
2e4e98e7 340static const struct zl10353_config dvico_fusionhdtv_xc3028 = {
b3fb91d2
CP		 341 .demod_address = 0x0f,
342 .if2 = 45600,
343 .no_tuner = 1,
344};
345
2e4e98e7 346static const struct mt352_config dvico_fusionhdtv_mt352_xc3028 = {
b3fb91d2
CP		 347 .demod_address = 0x0f,
348 .if2 = 4560,
349 .no_tuner = 1,
350 .demod_init = dvico_fusionhdtv_demod_init,
351};
352
2e4e98e7 353static const struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
f7b54b10 354 .demod_address = 0x0f,
780dfef3 355};
780dfef3 356
2e4e98e7 357static const struct cx22702_config connexant_refboard_config = {
1da177e4 358 .demod_address = 0x43,
38d84c3b 359 .output_mode = CX22702_SERIAL_OUTPUT,
1da177e4
LT		 360};
361
2e4e98e7 362static const struct cx22702_config hauppauge_hvr_config = {
aa481a65
ST		 363 .demod_address = 0x63,
364 .output_mode = CX22702_SERIAL_OUTPUT,
365};
1da177e4 366
7b61ba8f 367static int or51132_set_ts_param(struct dvb_frontend *fe, int is_punctured)
1da177e4 368{
7b61ba8f
MCC		 369 struct cx8802_dev *dev = fe->dvb->priv;
370
1da177e4
LT		 371 dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
372 return 0;
373}
374
2e4e98e7 375static const struct or51132_config pchdtv_hd3000 = {
f7b54b10
MK		 376 .demod_address = 0x15,
377 .set_ts_params = or51132_set_ts_param,
1da177e4 378};
1da177e4 379
7b61ba8f 380static int lgdt330x_pll_rf_set(struct dvb_frontend *fe, int index)
0ccef6db 381{
7b61ba8f 382 struct cx8802_dev *dev = fe->dvb->priv;
0ccef6db
MK		 383 struct cx88_core *core = dev->core;
384
32d83efc 385 dprintk(1, "%s: index = %d\n", __func__, index);
0ccef6db
MK		 386 if (index == 0)
387 cx_clear(MO_GP0_IO, 8);
388 else
389 cx_set(MO_GP0_IO, 8);
390 return 0;
391}
392
7b61ba8f 393static int lgdt330x_set_ts_param(struct dvb_frontend *fe, int is_punctured)
f1798495 394{
7b61ba8f
MCC		 395 struct cx8802_dev *dev = fe->dvb->priv;
396
f1798495
MK		 397 if (is_punctured)
398 dev->ts_gen_cntrl |= 0x04;
399 else
400 dev->ts_gen_cntrl &= ~0x04;
401 return 0;
402}
403
6ddcc919 404static struct lgdt330x_config fusionhdtv_3_gold = {
f7b54b10
MK		 405 .demod_chip = LGDT3302,
406 .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
407 .set_ts_params = lgdt330x_set_ts_param,
0d723c09 408};
e52e98a7 409
2e4e98e7 410static const struct lgdt330x_config fusionhdtv_5_gold = {
f7b54b10
MK		 411 .demod_chip = LGDT3303,
412 .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
413 .set_ts_params = lgdt330x_set_ts_param,
e52e98a7 414};
da215d22 415
2e4e98e7 416static const struct lgdt330x_config pchdtv_hd5500 = {
f7b54b10
MK		 417 .demod_chip = LGDT3303,
418 .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
419 .set_ts_params = lgdt330x_set_ts_param,
da215d22 420};
f1798495 421
7b61ba8f 422static int nxt200x_set_ts_param(struct dvb_frontend *fe, int is_punctured)
fde6d31e 423{
7b61ba8f
MCC		 424 struct cx8802_dev *dev = fe->dvb->priv;
425
fde6d31e
KL		 426 dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
427 return 0;
428}
429
2e4e98e7 430static const struct nxt200x_config ati_hdtvwonder = {
f7b54b10 431 .demod_address = 0x0a,
f7b54b10 432 .set_ts_params = nxt200x_set_ts_param,
fde6d31e 433};
fde6d31e 434
7b61ba8f 435static int cx24123_set_ts_param(struct dvb_frontend *fe,
399426ca 436 int is_punctured)
0fa14aa6 437{
7b61ba8f
MCC		 438 struct cx8802_dev *dev = fe->dvb->priv;
439
f7b54b10 440 dev->ts_gen_cntrl = 0x02;
0fa14aa6
ST		 441 return 0;
442}
443
7b61ba8f 444static int kworld_dvbs_100_set_voltage(struct dvb_frontend *fe,
0df289a2 445 enum fe_sec_voltage voltage)
0e0351e3 446{
7b61ba8f 447 struct cx8802_dev *dev = fe->dvb->priv;
0e0351e3
VC		 448 struct cx88_core *core = dev->core;
449
4a390558 450 if (voltage == SEC_VOLTAGE_OFF)
f7b54b10 451 cx_write(MO_GP0_IO, 0x000006fb);
4a390558 452 else
cd20ca9f 453 cx_write(MO_GP0_IO, 0x000006f9);
cd20ca9f
AQ		 454
455 if (core->prev_set_voltage)
456 return core->prev_set_voltage(fe, voltage);
457 return 0;
0e0351e3
VC		 458}
459
f7b54b10 460static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
0df289a2 461 enum fe_sec_voltage voltage)
c02a34f4 462{
7b61ba8f 463 struct cx8802_dev *dev = fe->dvb->priv;
c02a34f4
SA		 464 struct cx88_core *core = dev->core;
465
466 if (voltage == SEC_VOLTAGE_OFF) {
7b61ba8f 467 dprintk(1, "LNB Voltage OFF\n");
c02a34f4
SA		 468 cx_write(MO_GP0_IO, 0x0000efff);
469 }
470
471 if (core->prev_set_voltage)
472 return core->prev_set_voltage(fe, voltage);
473 return 0;
474}
475
af832623 476static int tevii_dvbs_set_voltage(struct dvb_frontend *fe,
0df289a2 477 enum fe_sec_voltage voltage)
af832623 478{
7b61ba8f 479 struct cx8802_dev *dev = fe->dvb->priv;
af832623
IL		 480 struct cx88_core *core = dev->core;
481
ad5f74c0 482 cx_set(MO_GP0_IO, 0x6040);
af832623 483 switch (voltage) {
111ac84a
SI		 484 case SEC_VOLTAGE_13:
485 cx_clear(MO_GP0_IO, 0x20);
486 break;
487 case SEC_VOLTAGE_18:
488 cx_set(MO_GP0_IO, 0x20);
489 break;
490 case SEC_VOLTAGE_OFF:
491 cx_clear(MO_GP0_IO, 0x20);
492 break;
493 }
494
495 if (core->prev_set_voltage)
496 return core->prev_set_voltage(fe, voltage);
497 return 0;
498}
499
500static int vp1027_set_voltage(struct dvb_frontend *fe,
0df289a2 501 enum fe_sec_voltage voltage)
111ac84a
SI		 502{
503 struct cx8802_dev *dev = fe->dvb->priv;
504 struct cx88_core *core = dev->core;
505
506 switch (voltage) {
507 case SEC_VOLTAGE_13:
508 dprintk(1, "LNB SEC Voltage=13\n");
509 cx_write(MO_GP0_IO, 0x00001220);
510 break;
511 case SEC_VOLTAGE_18:
512 dprintk(1, "LNB SEC Voltage=18\n");
513 cx_write(MO_GP0_IO, 0x00001222);
514 break;
515 case SEC_VOLTAGE_OFF:
516 dprintk(1, "LNB Voltage OFF\n");
517 cx_write(MO_GP0_IO, 0x00001230);
518 break;
af832623
IL		 519 }
520
521 if (core->prev_set_voltage)
522 return core->prev_set_voltage(fe, voltage);
523 return 0;
524}
525
2e4e98e7 526static const struct cx24123_config geniatech_dvbs_config = {
f7b54b10
MK		 527 .demod_address = 0x55,
528 .set_ts_params = cx24123_set_ts_param,
c02a34f4
SA		 529};
530
2e4e98e7 531static const struct cx24123_config hauppauge_novas_config = {
f7b54b10
MK		 532 .demod_address = 0x55,
533 .set_ts_params = cx24123_set_ts_param,
0e0351e3
VC		 534};
535
2e4e98e7 536static const struct cx24123_config kworld_dvbs_100_config = {
f7b54b10
MK		 537 .demod_address = 0x15,
538 .set_ts_params = cx24123_set_ts_param,
ef76856d 539 .lnb_polarity = 1,
0fa14aa6 540};
0fa14aa6 541
2e4e98e7 542static const struct s5h1409_config pinnacle_pctv_hd_800i_config = {
60464da8
ST		 543 .demod_address = 0x32 >> 1,
544 .output_mode = S5H1409_PARALLEL_OUTPUT,
545 .gpio = S5H1409_GPIO_ON,
546 .qam_if = 44000,
547 .inversion = S5H1409_INVERSION_OFF,
548 .status_mode = S5H1409_DEMODLOCKING,
ad05ff09 549 .mpeg_timing = S5H1409_MPEGTIMING_NONCONTINUOUS_NONINVERTING_CLOCK,
60464da8
ST		 550};
551
2e4e98e7 552static const struct s5h1409_config dvico_hdtv5_pci_nano_config = {
5c00fac0
ST		 553 .demod_address = 0x32 >> 1,
554 .output_mode = S5H1409_SERIAL_OUTPUT,
555 .gpio = S5H1409_GPIO_OFF,
556 .inversion = S5H1409_INVERSION_OFF,
557 .status_mode = S5H1409_DEMODLOCKING,
ad05ff09 558 .mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
5c00fac0
ST		 559};
560
2e4e98e7 561static const struct s5h1409_config kworld_atsc_120_config = {
99e09eac 562 .demod_address = 0x32 >> 1,
99e09eac
MCC		 563 .output_mode = S5H1409_SERIAL_OUTPUT,
564 .gpio = S5H1409_GPIO_OFF,
565 .inversion = S5H1409_INVERSION_OFF,
566 .status_mode = S5H1409_DEMODLOCKING,
ad05ff09 567 .mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
99e09eac
MCC		 568};
569
2e4e98e7 570static const struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = {
60464da8
ST		 571 .i2c_address = 0x64,
572 .if_khz = 5380,
60464da8
ST		 573};
574
2e4e98e7 575static const struct zl10353_config cx88_pinnacle_hybrid_pctv = {
3f6014fc
SV		 576 .demod_address = (0x1e >> 1),
577 .no_tuner = 1,
578 .if2 = 45600,
579};
580
2e4e98e7 581static const struct zl10353_config cx88_geniatech_x8000_mt = {
57069349
MCC		 582 .demod_address = (0x1e >> 1),
583 .no_tuner = 1,
584 .disable_i2c_gate_ctrl = 1,
9507901e
MCC		 585};
586
2e4e98e7 587static const struct s5h1411_config dvico_fusionhdtv7_config = {
d893d5dc
ST		 588 .output_mode = S5H1411_SERIAL_OUTPUT,
589 .gpio = S5H1411_GPIO_ON,
ad05ff09 590 .mpeg_timing = S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
d893d5dc
ST		 591 .qam_if = S5H1411_IF_44000,
592 .vsb_if = S5H1411_IF_44000,
593 .inversion = S5H1411_INVERSION_OFF,
594 .status_mode = S5H1411_DEMODLOCKING
595};
596
2e4e98e7 597static const struct xc5000_config dvico_fusionhdtv7_tuner_config = {
d893d5dc
ST		 598 .i2c_address = 0xc2 >> 1,
599 .if_khz = 5380,
d893d5dc
ST		 600};
601
23fb348d
MCC		 602static int attach_xc3028(u8 addr, struct cx8802_dev *dev)
603{
604 struct dvb_frontend *fe;
0b6b6302 605 struct vb2_dvb_frontend *fe0 = NULL;
99e09eac 606 struct xc2028_ctrl ctl;
23fb348d
MCC		 607 struct xc2028_config cfg = {
608 .i2c_adap = &dev->core->i2c_adap,
609 .i2c_addr = addr,
99e09eac 610 .ctrl = &ctl,
23fb348d
MCC		 611 };
612
92abe9ee 613 /* Get the first frontend */
0b6b6302 614 fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
363c35fc
ST		 615 if (!fe0)
616 return -EINVAL;
617
618 if (!fe0->dvb.frontend) {
65bc2fe8 619 pr_err("dvb frontend not attached. Can't attach xc3028\n");
ddd5441d
MCC		 620 return -EINVAL;
621 }
622
99e09eac
MCC		 623 /*
624 * Some xc3028 devices may be hidden by an I2C gate. This is known
625 * to happen with some s5h1409-based devices.
626 * Now that I2C gate is open, sets up xc3028 configuration
627 */
628 cx88_setup_xc3028(dev->core, &ctl);
629
363c35fc 630 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, &cfg);
23fb348d 631 if (!fe) {
65bc2fe8 632 pr_err("xc3028 attach failed\n");
363c35fc
ST		 633 dvb_frontend_detach(fe0->dvb.frontend);
634 dvb_unregister_frontend(fe0->dvb.frontend);
635 fe0->dvb.frontend = NULL;
23fb348d
MCC		 636 return -EINVAL;
637 }
638
65bc2fe8 639 pr_info("xc3028 attached\n");
23fb348d
MCC		 640
641 return 0;
642}
9507901e 643
c21973e8 644static int attach_xc4000(struct cx8802_dev *dev, struct xc4000_config *cfg)
645{
646 struct dvb_frontend *fe;
0b6b6302 647 struct vb2_dvb_frontend *fe0 = NULL;
c21973e8 648
649 /* Get the first frontend */
0b6b6302 650 fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
c21973e8 651 if (!fe0)
652 return -EINVAL;
653
654 if (!fe0->dvb.frontend) {
65bc2fe8 655 pr_err("dvb frontend not attached. Can't attach xc4000\n");
c21973e8 656 return -EINVAL;
657 }
658
659 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend, &dev->core->i2c_adap,
660 cfg);
661 if (!fe) {
65bc2fe8 662 pr_err("xc4000 attach failed\n");
c21973e8 663 dvb_frontend_detach(fe0->dvb.frontend);
664 dvb_unregister_frontend(fe0->dvb.frontend);
665 fe0->dvb.frontend = NULL;
666 return -EINVAL;
667 }
668
65bc2fe8 669 pr_info("xc4000 attached\n");
c21973e8 670
671 return 0;
672}
673
5bd1b663 674static int cx24116_set_ts_param(struct dvb_frontend *fe,
399426ca 675 int is_punctured)
5bd1b663
ST		 676{
677 struct cx8802_dev *dev = fe->dvb->priv;
7b61ba8f 678
5bd1b663
ST		 679 dev->ts_gen_cntrl = 0x2;
680
681 return 0;
682}
683
b699c271 684static int stv0900_set_ts_param(struct dvb_frontend *fe,
399426ca 685 int is_punctured)
b699c271
IL		 686{
687 struct cx8802_dev *dev = fe->dvb->priv;
7b61ba8f 688
b699c271
IL		 689 dev->ts_gen_cntrl = 0;
690
691 return 0;
692}
693
5bd1b663
ST		 694static int cx24116_reset_device(struct dvb_frontend *fe)
695{
696 struct cx8802_dev *dev = fe->dvb->priv;
697 struct cx88_core *core = dev->core;
698
699 /* Reset the part */
363c35fc 700 /* Put the cx24116 into reset */
5bd1b663 701 cx_write(MO_SRST_IO, 0);
399426ca 702 usleep_range(10000, 20000);
363c35fc 703 /* Take the cx24116 out of reset */
5bd1b663 704 cx_write(MO_SRST_IO, 1);
399426ca 705 usleep_range(10000, 20000);
5bd1b663
ST		 706
707 return 0;
708}
709
2e4e98e7 710static const struct cx24116_config hauppauge_hvr4000_config = {
5bd1b663
ST		 711 .demod_address = 0x05,
712 .set_ts_params = cx24116_set_ts_param,
713 .reset_device = cx24116_reset_device,
714};
715
2e4e98e7 716static const struct cx24116_config tevii_s460_config = {
af832623
IL		 717 .demod_address = 0x55,
718 .set_ts_params = cx24116_set_ts_param,
719 .reset_device = cx24116_reset_device,
720};
721
0cb73639 722static int ds3000_set_ts_param(struct dvb_frontend *fe,
399426ca 723 int is_punctured)
0cb73639
IL		 724{
725 struct cx8802_dev *dev = fe->dvb->priv;
7b61ba8f 726
0cb73639
IL		 727 dev->ts_gen_cntrl = 4;
728
729 return 0;
730}
731
732static struct ds3000_config tevii_ds3000_config = {
733 .demod_address = 0x68,
734 .set_ts_params = ds3000_set_ts_param,
735};
736
73f0af44
KD		 737static struct ts2020_config tevii_ts2020_config = {
738 .tuner_address = 0x60,
b858c331 739 .clk_out_div = 1,
73f0af44
KD		 740};
741
2e4e98e7 742static const struct stv0900_config prof_7301_stv0900_config = {
b699c271
IL		 743 .demod_address = 0x6a,
744/* demod_mode = 0,*/
745 .xtal = 27000000,
746 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
747 .diseqc_mode = 2,/* 2/3 PWM */
748 .tun1_maddress = 0,/* 0x60 */
749 .tun1_adc = 0,/* 2 Vpp */
750 .path1_mode = 3,
751 .set_ts_params = stv0900_set_ts_param,
752};
753
2e4e98e7 754static const struct stb6100_config prof_7301_stb6100_config = {
b699c271
IL		 755 .tuner_address = 0x60,
756 .refclock = 27000000,
757};
758
2e4e98e7 759static const struct stv0299_config tevii_tuner_sharp_config = {
e4aab64c 760 .demod_address = 0x68,
d4305c68 761 .inittab = sharp_z0194a_inittab,
e4aab64c
IL		 762 .mclk = 88000000UL,
763 .invert = 1,
764 .skip_reinit = 0,
765 .lock_output = 1,
766 .volt13_op0_op1 = STV0299_VOLT13_OP1,
767 .min_delay_ms = 100,
d4305c68 768 .set_symbol_rate = sharp_z0194a_set_symbol_rate,
e4aab64c
IL		 769 .set_ts_params = cx24116_set_ts_param,
770};
771
2e4e98e7 772static const struct stv0288_config tevii_tuner_earda_config = {
e4aab64c
IL		 773 .demod_address = 0x68,
774 .min_delay_ms = 100,
775 .set_ts_params = cx24116_set_ts_param,
776};
777
6e0e12f1 778static int cx8802_alloc_frontends(struct cx8802_dev *dev)
1da177e4 779{
0590d91c 780 struct cx88_core *core = dev->core;
0b6b6302 781 struct vb2_dvb_frontend *fe = NULL;
e32fadc4 782 int i;
0590d91c 783
e32fadc4
MCC		 784 mutex_init(&dev->frontends.lock);
785 INIT_LIST_HEAD(&dev->frontends.felist);
786
6e0e12f1
AW		 787 if (!core->board.num_frontends)
788 return -ENODEV;
789
65bc2fe8
MCC		 790 pr_info("%s: allocating %d frontend(s)\n", __func__,
791 core->board.num_frontends);
e32fadc4 792 for (i = 1; i <= core->board.num_frontends; i++) {
0b6b6302 793 fe = vb2_dvb_alloc_frontend(&dev->frontends, i);
6e0e12f1 794 if (!fe) {
65bc2fe8 795 pr_err("%s() failed to alloc\n", __func__);
0b6b6302 796 vb2_dvb_dealloc_frontends(&dev->frontends);
6e0e12f1 797 return -ENOMEM;
e32fadc4
MCC		 798 }
799 }
6e0e12f1
AW		 800 return 0;
801}
802
2e4e98e7 803static const u8 samsung_smt_7020_inittab[] = {
4f3ca2f1
DH		 804 0x01, 0x15,
805 0x02, 0x00,
806 0x03, 0x00,
807 0x04, 0x7D,
808 0x05, 0x0F,
809 0x06, 0x02,
810 0x07, 0x00,
811 0x08, 0x60,
812
813 0x0A, 0xC2,
814 0x0B, 0x00,
815 0x0C, 0x01,
816 0x0D, 0x81,
817 0x0E, 0x44,
818 0x0F, 0x09,
819 0x10, 0x3C,
820 0x11, 0x84,
821 0x12, 0xDA,
822 0x13, 0x99,
823 0x14, 0x8D,
824 0x15, 0xCE,
825 0x16, 0xE8,
826 0x17, 0x43,
827 0x18, 0x1C,
828 0x19, 0x1B,
829 0x1A, 0x1D,
830
831 0x1C, 0x12,
832 0x1D, 0x00,
833 0x1E, 0x00,
834 0x1F, 0x00,
835 0x20, 0x00,
836 0x21, 0x00,
837 0x22, 0x00,
838 0x23, 0x00,
839
840 0x28, 0x02,
841 0x29, 0x28,
842 0x2A, 0x14,
843 0x2B, 0x0F,
844 0x2C, 0x09,
845 0x2D, 0x05,
846
847 0x31, 0x1F,
848 0x32, 0x19,
849 0x33, 0xFC,
850 0x34, 0x13,
851 0xff, 0xff,
852};
853
14d24d14 854static int samsung_smt_7020_tuner_set_params(struct dvb_frontend *fe)
4f3ca2f1 855{
b738ae16 856 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
4f3ca2f1
DH		 857 struct cx8802_dev *dev = fe->dvb->priv;
858 u8 buf[4];
859 u32 div;
860 struct i2c_msg msg = {
861 .addr = 0x61,
862 .flags = 0,
863 .buf = buf,
864 .len = sizeof(buf) };
865
b738ae16 866 div = c->frequency / 125;
4f3ca2f1
DH		 867
868 buf[0] = (div >> 8) & 0x7f;
869 buf[1] = div & 0xff;
870 buf[2] = 0x84; /* 0xC4 */
871 buf[3] = 0x00;
872
b738ae16 873 if (c->frequency < 1500000)
4f3ca2f1
DH		 874 buf[3] |= 0x10;
875
876 if (fe->ops.i2c_gate_ctrl)
877 fe->ops.i2c_gate_ctrl(fe, 1);
878
879 if (i2c_transfer(&dev->core->i2c_adap, &msg, 1) != 1)
880 return -EIO;
881
882 return 0;
883}
884
885static int samsung_smt_7020_set_tone(struct dvb_frontend *fe,
399426ca 886 enum fe_sec_tone_mode tone)
4f3ca2f1
DH		 887{
888 struct cx8802_dev *dev = fe->dvb->priv;
889 struct cx88_core *core = dev->core;
890
891 cx_set(MO_GP0_IO, 0x0800);
892
893 switch (tone) {
894 case SEC_TONE_ON:
895 cx_set(MO_GP0_IO, 0x08);
896 break;
897 case SEC_TONE_OFF:
898 cx_clear(MO_GP0_IO, 0x08);
899 break;
900 default:
901 return -EINVAL;
902 }
903
904 return 0;
905}
906
907static int samsung_smt_7020_set_voltage(struct dvb_frontend *fe,
0df289a2 908 enum fe_sec_voltage voltage)
4f3ca2f1
DH		 909{
910 struct cx8802_dev *dev = fe->dvb->priv;
911 struct cx88_core *core = dev->core;
912
913 u8 data;
914 struct i2c_msg msg = {
915 .addr = 8,
916 .flags = 0,
917 .buf = &data,
918 .len = sizeof(data) };
919
920 cx_set(MO_GP0_IO, 0x8000);
921
922 switch (voltage) {
923 case SEC_VOLTAGE_OFF:
924 break;
925 case SEC_VOLTAGE_13:
926 data = ISL6421_EN1 | ISL6421_LLC1;
927 cx_clear(MO_GP0_IO, 0x80);
928 break;
929 case SEC_VOLTAGE_18:
930 data = ISL6421_EN1 | ISL6421_LLC1 | ISL6421_VSEL1;
931 cx_clear(MO_GP0_IO, 0x80);
932 break;
933 default:
934 return -EINVAL;
c2c1b415 935 }
4f3ca2f1
DH		 936
937 return (i2c_transfer(&dev->core->i2c_adap, &msg, 1) == 1) ? 0 : -EIO;
938}
939
940static int samsung_smt_7020_stv0299_set_symbol_rate(struct dvb_frontend *fe,
399426ca 941 u32 srate, u32 ratio)
4f3ca2f1
DH		 942{
943 u8 aclk = 0;
944 u8 bclk = 0;
945
946 if (srate < 1500000) {
947 aclk = 0xb7;
948 bclk = 0x47;
949 } else if (srate < 3000000) {
950 aclk = 0xb7;
951 bclk = 0x4b;
952 } else if (srate < 7000000) {
953 aclk = 0xb7;
954 bclk = 0x4f;
955 } else if (srate < 14000000) {
956 aclk = 0xb7;
957 bclk = 0x53;
958 } else if (srate < 30000000) {
959 aclk = 0xb6;
960 bclk = 0x53;
961 } else if (srate < 45000000) {
962 aclk = 0xb4;
963 bclk = 0x51;
964 }
965
966 stv0299_writereg(fe, 0x13, aclk);
967 stv0299_writereg(fe, 0x14, bclk);
968 stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
969 stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
970 stv0299_writereg(fe, 0x21, ratio & 0xf0);
971
972 return 0;
973}
974
2e4e98e7 975static const struct stv0299_config samsung_stv0299_config = {
4f3ca2f1
DH		 976 .demod_address = 0x68,
977 .inittab = samsung_smt_7020_inittab,
978 .mclk = 88000000UL,
979 .invert = 0,
980 .skip_reinit = 0,
981 .lock_output = STV0299_LOCKOUTPUT_LK,
982 .volt13_op0_op1 = STV0299_VOLT13_OP1,
983 .min_delay_ms = 100,
984 .set_symbol_rate = samsung_smt_7020_stv0299_set_symbol_rate,
985};
986
6e0e12f1
AW		 987static int dvb_register(struct cx8802_dev *dev)
988{
989 struct cx88_core *core = dev->core;
0b6b6302 990 struct vb2_dvb_frontend *fe0, *fe1 = NULL;
6e0e12f1 991 int mfe_shared = 0; /* bus not shared by default */
7b0962d3 992 int res = -EINVAL;
6e0e12f1 993
7b61ba8f 994 if (core->i2c_rc != 0) {
65bc2fe8 995 pr_err("no i2c-bus available, cannot attach dvb drivers\n");
6e0e12f1
AW		 996 goto frontend_detach;
997 }
e32fadc4 998
363c35fc 999 /* Get the first frontend */
0b6b6302 1000 fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
363c35fc 1001 if (!fe0)
60a5a927 1002 goto frontend_detach;
1da177e4 1003
8e739090
DB		 1004 /* multi-frontend gate control is undefined or defaults to fe0 */
1005 dev->frontends.gate = 0;
1006
e32fadc4
MCC		 1007 /* Sets the gate control callback to be used by i2c command calls */
1008 core->gate_ctrl = cx88_dvb_gate_ctrl;
1009
8e739090 1010 /* init frontend(s) */
0590d91c 1011 switch (core->boardnr) {
1da177e4 1012 case CX88_BOARD_HAUPPAUGE_DVB_T1:
363c35fc 1013 fe0->dvb.frontend = dvb_attach(cx22702_attach,
ed355260 1014 &connexant_refboard_config,
0590d91c 1015 &core->i2c_adap);
399426ca 1016 if (fe0->dvb.frontend) {
363c35fc 1017 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1018 0x61, &core->i2c_adap,
1019 DVB_PLL_THOMSON_DTT759X))
1020 goto frontend_detach;
f54376e2 1021 }
1da177e4 1022 break;
e057ee11 1023 case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
1da177e4 1024 case CX88_BOARD_CONEXANT_DVB_T1:
f39624fd 1025 case CX88_BOARD_KWORLD_DVB_T_CX22702:
2b5200a7 1026 case CX88_BOARD_WINFAST_DTV1000:
363c35fc 1027 fe0->dvb.frontend = dvb_attach(cx22702_attach,
f7b54b10 1028 &connexant_refboard_config,
0590d91c 1029 &core->i2c_adap);
399426ca 1030 if (fe0->dvb.frontend) {
363c35fc 1031 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1032 0x60, &core->i2c_adap,
1033 DVB_PLL_THOMSON_DTT7579))
1034 goto frontend_detach;
f54376e2 1035 }
1da177e4 1036 break;
4bd6e9d9 1037 case CX88_BOARD_WINFAST_DTV2000H:
611900c1
ST		 1038 case CX88_BOARD_HAUPPAUGE_HVR1100:
1039 case CX88_BOARD_HAUPPAUGE_HVR1100LP:
a5a2ecfc 1040 case CX88_BOARD_HAUPPAUGE_HVR1300:
363c35fc 1041 fe0->dvb.frontend = dvb_attach(cx22702_attach,
ed355260 1042 &hauppauge_hvr_config,
0590d91c 1043 &core->i2c_adap);
399426ca 1044 if (fe0->dvb.frontend) {
363c35fc 1045 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
399426ca
MCC		 1046 &core->i2c_adap, 0x61,
1047 TUNER_PHILIPS_FMD1216ME_MK3))
0590d91c 1048 goto frontend_detach;
f54376e2 1049 }
611900c1 1050 break;
27b93d8a
MS		 1051 case CX88_BOARD_WINFAST_DTV2000H_J:
1052 fe0->dvb.frontend = dvb_attach(cx22702_attach,
1053 &hauppauge_hvr_config,
1054 &core->i2c_adap);
399426ca 1055 if (fe0->dvb.frontend) {
27b93d8a 1056 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
399426ca
MCC		 1057 &core->i2c_adap, 0x61,
1058 TUNER_PHILIPS_FMD1216MEX_MK3))
27b93d8a
MS		 1059 goto frontend_detach;
1060 }
1061 break;
363c35fc 1062 case CX88_BOARD_HAUPPAUGE_HVR3000:
60a5a927
DB		 1063 /* MFE frontend 1 */
1064 mfe_shared = 1;
1065 dev->frontends.gate = 2;
363c35fc
ST		 1066 /* DVB-S init */
1067 fe0->dvb.frontend = dvb_attach(cx24123_attach,
399426ca
MCC		 1068 &hauppauge_novas_config,
1069 &dev->core->i2c_adap);
363c35fc 1070 if (fe0->dvb.frontend) {
60a5a927
DB		 1071 if (!dvb_attach(isl6421_attach,
1072 fe0->dvb.frontend,
1073 &dev->core->i2c_adap,
48a8a03b 1074 0x08, ISL6421_DCL, 0x00, false))
60a5a927 1075 goto frontend_detach;
363c35fc 1076 }
60a5a927 1077 /* MFE frontend 2 */
0b6b6302 1078 fe1 = vb2_dvb_get_frontend(&dev->frontends, 2);
60a5a927
DB		 1079 if (!fe1)
1080 goto frontend_detach;
1081 /* DVB-T init */
1082 fe1->dvb.frontend = dvb_attach(cx22702_attach,
399426ca
MCC		 1083 &hauppauge_hvr_config,
1084 &dev->core->i2c_adap);
60a5a927
DB		 1085 if (fe1->dvb.frontend) {
1086 fe1->dvb.frontend->id = 1;
1087 if (!dvb_attach(simple_tuner_attach,
1088 fe1->dvb.frontend,
1089 &dev->core->i2c_adap,
1090 0x61, TUNER_PHILIPS_FMD1216ME_MK3))
1091 goto frontend_detach;
363c35fc
ST		 1092 }
1093 break;
780dfef3 1094 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
363c35fc 1095 fe0->dvb.frontend = dvb_attach(mt352_attach,
f7b54b10 1096 &dvico_fusionhdtv,
0590d91c 1097 &core->i2c_adap);
399426ca 1098 if (fe0->dvb.frontend) {
363c35fc 1099 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1100 0x60, NULL, DVB_PLL_THOMSON_DTT7579))
1101 goto frontend_detach;
780dfef3 1102 break;
f54376e2 1103 }
780dfef3 1104 /* ZL10353 replaces MT352 on later cards */
363c35fc 1105 fe0->dvb.frontend = dvb_attach(zl10353_attach,
f7b54b10 1106 &dvico_fusionhdtv_plus_v1_1,
0590d91c 1107 &core->i2c_adap);
399426ca 1108 if (fe0->dvb.frontend) {
363c35fc 1109 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1110 0x60, NULL, DVB_PLL_THOMSON_DTT7579))
1111 goto frontend_detach;
f54376e2 1112 }
c2af3cd6
MK		 1113 break;
1114 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
399426ca
MCC		 1115 /*
1116 * The tin box says DEE1601, but it seems to be DTT7579
1117 * compatible, with a slightly different MT352 AGC gain.
1118 */
363c35fc 1119 fe0->dvb.frontend = dvb_attach(mt352_attach,
f7b54b10 1120 &dvico_fusionhdtv_dual,
0590d91c 1121 &core->i2c_adap);
399426ca 1122 if (fe0->dvb.frontend) {
363c35fc 1123 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1124 0x61, NULL, DVB_PLL_THOMSON_DTT7579))
1125 goto frontend_detach;
c2af3cd6
MK		 1126 break;
1127 }
c2af3cd6 1128 /* ZL10353 replaces MT352 on later cards */
363c35fc 1129 fe0->dvb.frontend = dvb_attach(zl10353_attach,
f7b54b10 1130 &dvico_fusionhdtv_plus_v1_1,
0590d91c 1131 &core->i2c_adap);
399426ca 1132 if (fe0->dvb.frontend) {
363c35fc 1133 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1134 0x61, NULL, DVB_PLL_THOMSON_DTT7579))
1135 goto frontend_detach;
c2af3cd6 1136 }
1da177e4 1137 break;
780dfef3 1138 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
363c35fc 1139 fe0->dvb.frontend = dvb_attach(mt352_attach,
f7b54b10 1140 &dvico_fusionhdtv,
0590d91c 1141 &core->i2c_adap);
399426ca 1142 if (fe0->dvb.frontend) {
363c35fc 1143 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1144 0x61, NULL, DVB_PLL_LG_Z201))
1145 goto frontend_detach;
f54376e2 1146 }
1da177e4
LT		 1147 break;
1148 case CX88_BOARD_KWORLD_DVB_T:
1149 case CX88_BOARD_DNTV_LIVE_DVB_T:
a82decf6 1150 case CX88_BOARD_ADSTECH_DVB_T_PCI:
363c35fc 1151 fe0->dvb.frontend = dvb_attach(mt352_attach,
f7b54b10 1152 &dntv_live_dvbt_config,
0590d91c 1153 &core->i2c_adap);
399426ca 1154 if (fe0->dvb.frontend) {
363c35fc 1155 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1156 0x61, NULL, DVB_PLL_UNKNOWN_1))
1157 goto frontend_detach;
f54376e2 1158 }
1da177e4 1159 break;
fc40b261 1160 case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
7b34be71 1161#if IS_ENABLED(CONFIG_VIDEO_CX88_VP3054)
f0ad9097 1162 /* MT352 is on a secondary I2C bus made from some GPIO lines */
399426ca
MCC		 1163 fe0->dvb.frontend = dvb_attach(mt352_attach,
1164 &dntv_live_dvbt_pro_config,
f0ad9097 1165 &dev->vp3054->adap);
399426ca 1166 if (fe0->dvb.frontend) {
363c35fc 1167 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1168 &core->i2c_adap, 0x61,
1169 TUNER_PHILIPS_FMD1216ME_MK3))
1170 goto frontend_detach;
f54376e2 1171 }
fc40b261 1172#else
65bc2fe8 1173 pr_err("built without vp3054 support\n");
fc40b261
CP		 1174#endif
1175 break;
780dfef3 1176 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
363c35fc 1177 fe0->dvb.frontend = dvb_attach(zl10353_attach,
f7b54b10 1178 &dvico_fusionhdtv_hybrid,
0590d91c 1179 &core->i2c_adap);
399426ca 1180 if (fe0->dvb.frontend) {
363c35fc 1181 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
399426ca
MCC		 1182 &core->i2c_adap, 0x61,
1183 TUNER_THOMSON_FE6600))
0590d91c 1184 goto frontend_detach;
f54376e2 1185 }
780dfef3 1186 break;
b3fb91d2 1187 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
363c35fc 1188 fe0->dvb.frontend = dvb_attach(zl10353_attach,
b3fb91d2 1189 &dvico_fusionhdtv_xc3028,
0590d91c 1190 &core->i2c_adap);
399426ca 1191 if (!fe0->dvb.frontend)
363c35fc 1192 fe0->dvb.frontend = dvb_attach(mt352_attach,
b3fb91d2 1193 &dvico_fusionhdtv_mt352_xc3028,
0590d91c 1194 &core->i2c_adap);
8765561f
CP		 1195 /*
1196 * On this board, the demod provides the I2C bus pullup.
1197 * We must not permit gate_ctrl to be performed, or
1198 * the xc3028 cannot communicate on the bus.
1199 */
363c35fc
ST		 1200 if (fe0->dvb.frontend)
1201 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
23fb348d 1202 if (attach_xc3028(0x61, dev) < 0)
becd4305 1203 goto frontend_detach;
b3fb91d2 1204 break;
1da177e4 1205 case CX88_BOARD_PCHDTV_HD3000:
363c35fc 1206 fe0->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
0590d91c 1207 &core->i2c_adap);
399426ca 1208 if (fe0->dvb.frontend) {
363c35fc 1209 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1210 &core->i2c_adap, 0x61,
1211 TUNER_THOMSON_DTT761X))
1212 goto frontend_detach;
f54376e2 1213 }
1da177e4 1214 break;
f1798495
MK		 1215 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
1216 dev->ts_gen_cntrl = 0x08;
f1798495 1217
0590d91c 1218 /* Do a hardware reset of chip before using it. */
f1798495 1219 cx_clear(MO_GP0_IO, 1);
9d08ba6d 1220 msleep(100);
0ccef6db 1221 cx_set(MO_GP0_IO, 1);
9d08ba6d 1222 msleep(200);
0ccef6db
MK		 1223
1224 /* Select RF connector callback */
6ddcc919 1225 fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
363c35fc 1226 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
f7b54b10 1227 &fusionhdtv_3_gold,
23ba635d 1228 0x0e,
0590d91c 1229 &core->i2c_adap);
399426ca 1230 if (fe0->dvb.frontend) {
363c35fc 1231 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1232 &core->i2c_adap, 0x61,
1233 TUNER_MICROTUNE_4042FI5))
1234 goto frontend_detach;
f1798495
MK		 1235 }
1236 break;
0d723c09
MK		 1237 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
1238 dev->ts_gen_cntrl = 0x08;
0d723c09 1239
0590d91c 1240 /* Do a hardware reset of chip before using it. */
0d723c09 1241 cx_clear(MO_GP0_IO, 1);
9d08ba6d 1242 msleep(100);
d975872c 1243 cx_set(MO_GP0_IO, 9);
9d08ba6d 1244 msleep(200);
363c35fc 1245 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
f7b54b10 1246 &fusionhdtv_3_gold,
23ba635d 1247 0x0e,
0590d91c 1248 &core->i2c_adap);
399426ca 1249 if (fe0->dvb.frontend) {
363c35fc 1250 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1251 &core->i2c_adap, 0x61,
1252 TUNER_THOMSON_DTT761X))
1253 goto frontend_detach;
0d723c09
MK		 1254 }
1255 break;
e52e98a7
MCC		 1256 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
1257 dev->ts_gen_cntrl = 0x08;
e52e98a7 1258
0590d91c 1259 /* Do a hardware reset of chip before using it. */
e52e98a7 1260 cx_clear(MO_GP0_IO, 1);
9d08ba6d 1261 msleep(100);
e52e98a7 1262 cx_set(MO_GP0_IO, 1);
9d08ba6d 1263 msleep(200);
363c35fc 1264 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
f7b54b10 1265 &fusionhdtv_5_gold,
23ba635d 1266 0x0e,
0590d91c 1267 &core->i2c_adap);
399426ca 1268 if (fe0->dvb.frontend) {
363c35fc 1269 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1270 &core->i2c_adap, 0x61,
1271 TUNER_LG_TDVS_H06XF))
1272 goto frontend_detach;
363c35fc 1273 if (!dvb_attach(tda9887_attach, fe0->dvb.frontend,
399426ca 1274 &core->i2c_adap, 0x43))
0590d91c 1275 goto frontend_detach;
e52e98a7
MCC		 1276 }
1277 break;
da215d22
RS		 1278 case CX88_BOARD_PCHDTV_HD5500:
1279 dev->ts_gen_cntrl = 0x08;
da215d22 1280
0590d91c 1281 /* Do a hardware reset of chip before using it. */
da215d22 1282 cx_clear(MO_GP0_IO, 1);
9d08ba6d 1283 msleep(100);
da215d22 1284 cx_set(MO_GP0_IO, 1);
9d08ba6d 1285 msleep(200);
363c35fc 1286 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
f7b54b10 1287 &pchdtv_hd5500,
23ba635d 1288 0x59,
0590d91c 1289 &core->i2c_adap);
399426ca 1290 if (fe0->dvb.frontend) {
363c35fc 1291 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1292 &core->i2c_adap, 0x61,
1293 TUNER_LG_TDVS_H06XF))
1294 goto frontend_detach;
363c35fc 1295 if (!dvb_attach(tda9887_attach, fe0->dvb.frontend,
399426ca 1296 &core->i2c_adap, 0x43))
0590d91c 1297 goto frontend_detach;
da215d22
RS		 1298 }
1299 break;
fde6d31e 1300 case CX88_BOARD_ATI_HDTVWONDER:
363c35fc 1301 fe0->dvb.frontend = dvb_attach(nxt200x_attach,
f7b54b10 1302 &ati_hdtvwonder,
0590d91c 1303 &core->i2c_adap);
399426ca 1304 if (fe0->dvb.frontend) {
363c35fc 1305 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1306 &core->i2c_adap, 0x61,
1307 TUNER_PHILIPS_TUV1236D))
1308 goto frontend_detach;
f54376e2 1309 }
0fa14aa6 1310 break;
0fa14aa6
ST		 1311 case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
1312 case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
363c35fc 1313 fe0->dvb.frontend = dvb_attach(cx24123_attach,
f7b54b10 1314 &hauppauge_novas_config,
0590d91c 1315 &core->i2c_adap);
363c35fc 1316 if (fe0->dvb.frontend) {
48a8a03b
MCC		 1317 bool override_tone;
1318
1319 if (core->model == 92001)
1320 override_tone = true;
1321 else
1322 override_tone = false;
1323
363c35fc 1324 if (!dvb_attach(isl6421_attach, fe0->dvb.frontend,
399426ca
MCC		 1325 &core->i2c_adap, 0x08, ISL6421_DCL,
1326 0x00, override_tone))
0590d91c 1327 goto frontend_detach;
cd20ca9f 1328 }
0e0351e3
VC		 1329 break;
1330 case CX88_BOARD_KWORLD_DVBS_100:
363c35fc 1331 fe0->dvb.frontend = dvb_attach(cx24123_attach,
f7b54b10 1332 &kworld_dvbs_100_config,
0590d91c 1333 &core->i2c_adap);
363c35fc
ST		 1334 if (fe0->dvb.frontend) {
1335 core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
1336 fe0->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
cd20ca9f 1337 }
fde6d31e 1338 break;
c02a34f4 1339 case CX88_BOARD_GENIATECH_DVBS:
363c35fc 1340 fe0->dvb.frontend = dvb_attach(cx24123_attach,
f7b54b10 1341 &geniatech_dvbs_config,
0590d91c 1342 &core->i2c_adap);
363c35fc
ST		 1343 if (fe0->dvb.frontend) {
1344 core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
1345 fe0->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
c02a34f4
SA		 1346 }
1347 break;
60464da8 1348 case CX88_BOARD_PINNACLE_PCTV_HD_800i:
363c35fc 1349 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
60464da8 1350 &pinnacle_pctv_hd_800i_config,
0590d91c 1351 &core->i2c_adap);
399426ca 1352 if (fe0->dvb.frontend) {
363c35fc 1353 if (!dvb_attach(xc5000_attach, fe0->dvb.frontend,
0590d91c 1354 &core->i2c_adap,
30650961 1355 &pinnacle_pctv_hd_800i_tuner_config))
0590d91c 1356 goto frontend_detach;
60464da8
ST		 1357 }
1358 break;
5c00fac0 1359 case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
363c35fc 1360 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
399426ca
MCC		 1361 &dvico_hdtv5_pci_nano_config,
1362 &core->i2c_adap);
1363 if (fe0->dvb.frontend) {
5c00fac0
ST		 1364 struct dvb_frontend *fe;
1365 struct xc2028_config cfg = {
0590d91c 1366 .i2c_adap = &core->i2c_adap,
5c00fac0 1367 .i2c_addr = 0x61,
5c00fac0
ST		 1368 };
1369 static struct xc2028_ctrl ctl = {
ef80bfeb 1370 .fname = XC2028_DEFAULT_FIRMWARE,
5c00fac0 1371 .max_len = 64,
33e53161 1372 .scode_table = XC3028_FE_OREN538,
5c00fac0
ST		 1373 };
1374
1375 fe = dvb_attach(xc2028_attach,
363c35fc 1376 fe0->dvb.frontend, &cfg);
399426ca 1377 if (fe && fe->ops.tuner_ops.set_config)
5c00fac0
ST		 1378 fe->ops.tuner_ops.set_config(fe, &ctl);
1379 }
1380 break;
d49f7a24 1381 case CX88_BOARD_PINNACLE_HYBRID_PCTV:
3047a176 1382 case CX88_BOARD_WINFAST_DTV1800H:
363c35fc 1383 fe0->dvb.frontend = dvb_attach(zl10353_attach,
3f6014fc 1384 &cx88_pinnacle_hybrid_pctv,
0590d91c 1385 &core->i2c_adap);
363c35fc
ST		 1386 if (fe0->dvb.frontend) {
1387 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
3f6014fc
SV		 1388 if (attach_xc3028(0x61, dev) < 0)
1389 goto frontend_detach;
1390 }
9507901e 1391 break;
8eb79c0b 1392 case CX88_BOARD_WINFAST_DTV1800H_XC4000:
f271a3af 1393 case CX88_BOARD_WINFAST_DTV2000H_PLUS:
1394 fe0->dvb.frontend = dvb_attach(zl10353_attach,
1395 &cx88_pinnacle_hybrid_pctv,
1396 &core->i2c_adap);
1397 if (fe0->dvb.frontend) {
1398 struct xc4000_config cfg = {
1399 .i2c_address = 0x61,
1400 .default_pm = 0,
1401 .dvb_amplitude = 134,
1402 .set_smoothedcvbs = 1,
1403 .if_khz = 4560
1404 };
1405 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
1406 if (attach_xc4000(dev, &cfg) < 0)
1407 goto frontend_detach;
1408 }
1409 break;
1410 case CX88_BOARD_GENIATECH_X8000_MT:
99e09eac 1411 dev->ts_gen_cntrl = 0x00;
9507901e 1412
363c35fc 1413 fe0->dvb.frontend = dvb_attach(zl10353_attach,
9507901e 1414 &cx88_geniatech_x8000_mt,
0590d91c 1415 &core->i2c_adap);
23fb348d 1416 if (attach_xc3028(0x61, dev) < 0)
0590d91c 1417 goto frontend_detach;
9507901e 1418 break;
7b61ba8f 1419 case CX88_BOARD_KWORLD_ATSC_120:
363c35fc 1420 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
99e09eac 1421 &kworld_atsc_120_config,
0590d91c 1422 &core->i2c_adap);
99e09eac 1423 if (attach_xc3028(0x61, dev) < 0)
0590d91c 1424 goto frontend_detach;
99e09eac 1425 break;
d893d5dc 1426 case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD:
363c35fc 1427 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
d893d5dc 1428 &dvico_fusionhdtv7_config,
0590d91c 1429 &core->i2c_adap);
399426ca 1430 if (fe0->dvb.frontend) {
363c35fc 1431 if (!dvb_attach(xc5000_attach, fe0->dvb.frontend,
0590d91c 1432 &core->i2c_adap,
30650961 1433 &dvico_fusionhdtv7_tuner_config))
0590d91c 1434 goto frontend_detach;
d893d5dc
ST		 1435 }
1436 break;
5bd1b663 1437 case CX88_BOARD_HAUPPAUGE_HVR4000:
60a5a927
DB		 1438 /* MFE frontend 1 */
1439 mfe_shared = 1;
1440 dev->frontends.gate = 2;
363c35fc
ST		 1441 /* DVB-S/S2 Init */
1442 fe0->dvb.frontend = dvb_attach(cx24116_attach,
399426ca
MCC		 1443 &hauppauge_hvr4000_config,
1444 &dev->core->i2c_adap);
363c35fc 1445 if (fe0->dvb.frontend) {
60a5a927
DB		 1446 if (!dvb_attach(isl6421_attach,
1447 fe0->dvb.frontend,
1448 &dev->core->i2c_adap,
48a8a03b 1449 0x08, ISL6421_DCL, 0x00, false))
60a5a927 1450 goto frontend_detach;
363c35fc 1451 }
60a5a927 1452 /* MFE frontend 2 */
0b6b6302 1453 fe1 = vb2_dvb_get_frontend(&dev->frontends, 2);
60a5a927
DB		 1454 if (!fe1)
1455 goto frontend_detach;
1456 /* DVB-T Init */
1457 fe1->dvb.frontend = dvb_attach(cx22702_attach,
399426ca
MCC		 1458 &hauppauge_hvr_config,
1459 &dev->core->i2c_adap);
60a5a927
DB		 1460 if (fe1->dvb.frontend) {
1461 fe1->dvb.frontend->id = 1;
1462 if (!dvb_attach(simple_tuner_attach,
1463 fe1->dvb.frontend,
1464 &dev->core->i2c_adap,
1465 0x61, TUNER_PHILIPS_FMD1216ME_MK3))
1466 goto frontend_detach;
363c35fc
ST		 1467 }
1468 break;
5bd1b663 1469 case CX88_BOARD_HAUPPAUGE_HVR4000LITE:
363c35fc 1470 fe0->dvb.frontend = dvb_attach(cx24116_attach,
399426ca
MCC		 1471 &hauppauge_hvr4000_config,
1472 &dev->core->i2c_adap);
363c35fc 1473 if (fe0->dvb.frontend) {
60a5a927
DB		 1474 if (!dvb_attach(isl6421_attach,
1475 fe0->dvb.frontend,
1476 &dev->core->i2c_adap,
48a8a03b 1477 0x08, ISL6421_DCL, 0x00, false))
60a5a927 1478 goto frontend_detach;
5bd1b663
ST		 1479 }
1480 break;
cd3cde12 1481 case CX88_BOARD_PROF_6200:
4b29631d 1482 case CX88_BOARD_TBS_8910:
e4aab64c 1483 case CX88_BOARD_TEVII_S420:
363c35fc 1484 fe0->dvb.frontend = dvb_attach(stv0299_attach,
e4aab64c
IL		 1485 &tevii_tuner_sharp_config,
1486 &core->i2c_adap);
399426ca 1487 if (fe0->dvb.frontend) {
363c35fc 1488 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, 0x60,
e4aab64c
IL		 1489 &core->i2c_adap, DVB_PLL_OPERA1))
1490 goto frontend_detach;
363c35fc
ST		 1491 core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
1492 fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
e4aab64c
IL		 1493
1494 } else {
363c35fc 1495 fe0->dvb.frontend = dvb_attach(stv0288_attach,
e4aab64c
IL		 1496 &tevii_tuner_earda_config,
1497 &core->i2c_adap);
399426ca
MCC		 1498 if (fe0->dvb.frontend) {
1499 if (!dvb_attach(stb6000_attach,
1500 fe0->dvb.frontend, 0x61,
e4aab64c
IL		 1501 &core->i2c_adap))
1502 goto frontend_detach;
363c35fc
ST		 1503 core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
1504 fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
e4aab64c
IL		 1505 }
1506 }
1507 break;
af832623 1508 case CX88_BOARD_TEVII_S460:
363c35fc 1509 fe0->dvb.frontend = dvb_attach(cx24116_attach,
af832623
IL		 1510 &tevii_s460_config,
1511 &core->i2c_adap);
399426ca 1512 if (fe0->dvb.frontend)
363c35fc 1513 fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
4cd7fb87 1514 break;
0cb73639
IL		 1515 case CX88_BOARD_TEVII_S464:
1516 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1517 &tevii_ds3000_config,
1518 &core->i2c_adap);
399426ca 1519 if (fe0->dvb.frontend) {
73f0af44 1520 dvb_attach(ts2020_attach, fe0->dvb.frontend,
399426ca 1521 &tevii_ts2020_config, &core->i2c_adap);
0cb73639
IL		 1522 fe0->dvb.frontend->ops.set_voltage =
1523 tevii_dvbs_set_voltage;
73f0af44 1524 }
0cb73639 1525 break;
4cd7fb87 1526 case CX88_BOARD_OMICOM_SS4_PCI:
ee73042c 1527 case CX88_BOARD_TBS_8920:
57f51dbc 1528 case CX88_BOARD_PROF_7300:
4b29631d 1529 case CX88_BOARD_SATTRADE_ST4200:
363c35fc 1530 fe0->dvb.frontend = dvb_attach(cx24116_attach,
ee73042c
OR		 1531 &hauppauge_hvr4000_config,
1532 &core->i2c_adap);
399426ca 1533 if (fe0->dvb.frontend)
363c35fc 1534 fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
af832623 1535 break;
70101a27
SW		 1536 case CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII:
1537 fe0->dvb.frontend = dvb_attach(zl10353_attach,
1538 &cx88_terratec_cinergy_ht_pci_mkii_config,
1539 &core->i2c_adap);
1540 if (fe0->dvb.frontend) {
1541 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
1542 if (attach_xc3028(0x61, dev) < 0)
1543 goto frontend_detach;
1544 }
1545 break;
b699c271
IL		 1546 case CX88_BOARD_PROF_7301:{
1547 struct dvb_tuner_ops *tuner_ops = NULL;
1548
1549 fe0->dvb.frontend = dvb_attach(stv0900_attach,
399426ca
MCC		 1550 &prof_7301_stv0900_config,
1551 &core->i2c_adap, 0);
1552 if (fe0->dvb.frontend) {
b699c271
IL		 1553 if (!dvb_attach(stb6100_attach, fe0->dvb.frontend,
1554 &prof_7301_stb6100_config,
1555 &core->i2c_adap))
1556 goto frontend_detach;
1557
1558 tuner_ops = &fe0->dvb.frontend->ops.tuner_ops;
1559 tuner_ops->set_frequency = stb6100_set_freq;
1560 tuner_ops->get_frequency = stb6100_get_freq;
1561 tuner_ops->set_bandwidth = stb6100_set_bandw;
1562 tuner_ops->get_bandwidth = stb6100_get_bandw;
1563
1564 core->prev_set_voltage =
1565 fe0->dvb.frontend->ops.set_voltage;
1566 fe0->dvb.frontend->ops.set_voltage =
1567 tevii_dvbs_set_voltage;
1568 }
1569 break;
1570 }
4f3ca2f1
DH		 1571 case CX88_BOARD_SAMSUNG_SMT_7020:
1572 dev->ts_gen_cntrl = 0x08;
1573
4f3ca2f1
DH		 1574 cx_set(MO_GP0_IO, 0x0101);
1575
1576 cx_clear(MO_GP0_IO, 0x01);
9d08ba6d 1577 msleep(100);
4f3ca2f1 1578 cx_set(MO_GP0_IO, 0x01);
9d08ba6d 1579 msleep(200);
4f3ca2f1
DH		 1580
1581 fe0->dvb.frontend = dvb_attach(stv0299_attach,
399426ca
MCC		 1582 &samsung_stv0299_config,
1583 &dev->core->i2c_adap);
4f3ca2f1
DH		 1584 if (fe0->dvb.frontend) {
1585 fe0->dvb.frontend->ops.tuner_ops.set_params =
1586 samsung_smt_7020_tuner_set_params;
1587 fe0->dvb.frontend->tuner_priv =
1588 &dev->core->i2c_adap;
1589 fe0->dvb.frontend->ops.set_voltage =
1590 samsung_smt_7020_set_voltage;
1591 fe0->dvb.frontend->ops.set_tone =
1592 samsung_smt_7020_set_tone;
1593 }
1594
1595 break;
111ac84a
SI		 1596 case CX88_BOARD_TWINHAN_VP1027_DVBS:
1597 dev->ts_gen_cntrl = 0x00;
1598 fe0->dvb.frontend = dvb_attach(mb86a16_attach,
399426ca
MCC		 1599 &twinhan_vp1027,
1600 &core->i2c_adap);
111ac84a
SI		 1601 if (fe0->dvb.frontend) {
1602 core->prev_set_voltage =
1603 fe0->dvb.frontend->ops.set_voltage;
1604 fe0->dvb.frontend->ops.set_voltage =
1605 vp1027_set_voltage;
1606 }
1607 break;
4f3ca2f1 1608
1da177e4 1609 default:
65bc2fe8 1610 pr_err("The frontend of your DVB/ATSC card isn't supported yet\n");
1da177e4
LT		 1611 break;
1612 }
363c35fc 1613
7b61ba8f 1614 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
65bc2fe8 1615 pr_err("frontend initialization failed\n");
60a5a927 1616 goto frontend_detach;
9507901e 1617 }
d7cba043 1618 /* define general-purpose callback pointer */
363c35fc 1619 fe0->dvb.frontend->callback = cx88_tuner_callback;
9507901e 1620
6c5be74c 1621 /* Ensure all frontends negotiate bus access */
363c35fc
ST		 1622 fe0->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
1623 if (fe1)
1624 fe1->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
1da177e4 1625
3aab15af
HV		 1626 /* Put the tuner in standby to keep it quiet */
1627 call_all(core, tuner, standby);
93352f5c 1628
1da177e4 1629 /* register everything */
0b6b6302 1630 res = vb2_dvb_register_bus(&dev->frontends, THIS_MODULE, dev,
2773b0e9
MCC		 1631 &dev->pci->dev, NULL, adapter_nr,
1632 mfe_shared);
7b0962d3
DF		 1633 if (res)
1634 goto frontend_detach;
1635 return res;
0590d91c
MCC		 1636
1637frontend_detach:
e32fadc4 1638 core->gate_ctrl = NULL;
0b6b6302 1639 vb2_dvb_dealloc_frontends(&dev->frontends);
7b0962d3 1640 return res;
1da177e4
LT		 1641}
1642
1643/* ----------------------------------------------------------- */
1644
6c5be74c
ST		 1645/* CX8802 MPEG -> mini driver - We have been given the hardware */
1646static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
1da177e4 1647{
6c5be74c
ST		 1648 struct cx88_core *core = drv->core;
1649 int err = 0;
7b61ba8f
MCC		 1650
1651 dprintk(1, "%s\n", __func__);
6c5be74c 1652
6a59d64c 1653 switch (core->boardnr) {
6c5be74c
ST		 1654 case CX88_BOARD_HAUPPAUGE_HVR1300:
1655 /* We arrive here with either the cx23416 or the cx22702
1656 * on the bus. Take the bus from the cx23416 and enable the
1657 * cx22702 demod
1658 */
79392737
DB		 1659 /* Toggle reset on cx22702 leaving i2c active */
1660 cx_set(MO_GP0_IO, 0x00000080);
1661 udelay(1000);
1662 cx_clear(MO_GP0_IO, 0x00000080);
1663 udelay(50);
1664 cx_set(MO_GP0_IO, 0x00000080);
1665 udelay(1000);
1666 /* enable the cx22702 pins */
6c5be74c
ST		 1667 cx_clear(MO_GP0_IO, 0x00000004);
1668 udelay(1000);
1669 break;
363c35fc 1670
92abe9ee 1671 case CX88_BOARD_HAUPPAUGE_HVR3000:
363c35fc 1672 case CX88_BOARD_HAUPPAUGE_HVR4000:
79392737
DB		 1673 /* Toggle reset on cx22702 leaving i2c active */
1674 cx_set(MO_GP0_IO, 0x00000080);
1675 udelay(1000);
1676 cx_clear(MO_GP0_IO, 0x00000080);
1677 udelay(50);
1678 cx_set(MO_GP0_IO, 0x00000080);
1679 udelay(1000);
1680 switch (core->dvbdev->frontends.active_fe_id) {
1681 case 1: /* DVB-S/S2 Enabled */
1682 /* tri-state the cx22702 pins */
1683 cx_set(MO_GP0_IO, 0x00000004);
1684 /* Take the cx24116/cx24123 out of reset */
1685 cx_write(MO_SRST_IO, 1);
363c35fc 1686 core->dvbdev->ts_gen_cntrl = 0x02; /* Parallel IO */
79392737
DB		 1687 break;
1688 case 2: /* DVB-T Enabled */
363c35fc
ST		 1689 /* Put the cx24116/cx24123 into reset */
1690 cx_write(MO_SRST_IO, 0);
79392737 1691 /* enable the cx22702 pins */
363c35fc
ST		 1692 cx_clear(MO_GP0_IO, 0x00000004);
1693 core->dvbdev->ts_gen_cntrl = 0x0c; /* Serial IO */
79392737 1694 break;
363c35fc 1695 }
79392737 1696 udelay(1000);
363c35fc
ST		 1697 break;
1698
f271a3af 1699 case CX88_BOARD_WINFAST_DTV2000H_PLUS:
1700 /* set RF input to AIR for DVB-T (GPIO 16) */
1701 cx_write(MO_GP2_IO, 0x0101);
1702 break;
1703
6c5be74c
ST		 1704 default:
1705 err = -ENODEV;
1706 }
1707 return err;
1708}
1709
1710/* CX8802 MPEG -> mini driver - We no longer have the hardware */
1711static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
1712{
1713 struct cx88_core *core = drv->core;
1714 int err = 0;
7b61ba8f
MCC		 1715
1716 dprintk(1, "%s\n", __func__);
6c5be74c 1717
6a59d64c 1718 switch (core->boardnr) {
6c5be74c
ST		 1719 case CX88_BOARD_HAUPPAUGE_HVR1300:
1720 /* Do Nothing, leave the cx22702 on the bus. */
1721 break;
363c35fc
ST		 1722 case CX88_BOARD_HAUPPAUGE_HVR3000:
1723 case CX88_BOARD_HAUPPAUGE_HVR4000:
1724 break;
6c5be74c
ST		 1725 default:
1726 err = -ENODEV;
1727 }
1728 return err;
1729}
1730
1731static int cx8802_dvb_probe(struct cx8802_driver *drv)
1732{
1733 struct cx88_core *core = drv->core;
1734 struct cx8802_dev *dev = drv->core->dvbdev;
cbd82441 1735 int err;
0b6b6302 1736 struct vb2_dvb_frontend *fe;
6e0e12f1 1737 int i;
1da177e4 1738
7b61ba8f
MCC		 1739 dprintk(1, "%s\n", __func__);
1740 dprintk(1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
6a59d64c 1741 core->boardnr,
6c5be74c
ST		 1742 core->name,
1743 core->pci_bus,
1744 core->pci_slot);
1da177e4
LT		 1745
1746 err = -ENODEV;
6a59d64c 1747 if (!(core->board.mpeg & CX88_MPEG_DVB))
1da177e4
LT		 1748 goto fail_core;
1749
ecf854df 1750 /* If vp3054 isn't enabled, a stub will just return 0 */
fc40b261 1751 err = vp3054_i2c_probe(dev);
7b61ba8f 1752 if (err != 0)
6e0e12f1 1753 goto fail_core;
fc40b261 1754
1da177e4 1755 /* dvb stuff */
65bc2fe8 1756 pr_info("cx2388x based DVB/ATSC card\n");
363c35fc
ST		 1757 dev->ts_gen_cntrl = 0x0c;
1758
6e0e12f1
AW		 1759 err = cx8802_alloc_frontends(dev);
1760 if (err)
1761 goto fail_core;
1762
6e0e12f1 1763 for (i = 1; i <= core->board.num_frontends; i++) {
0b6b6302
HV		 1764 struct vb2_queue *q;
1765
1766 fe = vb2_dvb_get_frontend(&core->dvbdev->frontends, i);
399426ca 1767 if (!fe) {
65bc2fe8
MCC		 1768 pr_err("%s() failed to get frontend(%d)\n",
1769 __func__, i);
e546b1ef 1770 err = -ENODEV;
6e0e12f1
AW		 1771 goto fail_probe;
1772 }
0b6b6302
HV		 1773 q = &fe->dvb.dvbq;
1774 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1775 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
1776 q->gfp_flags = GFP_DMA32;
1777 q->min_buffers_needed = 2;
1778 q->drv_priv = dev;
1779 q->buf_struct_size = sizeof(struct cx88_buffer);
1780 q->ops = &dvb_qops;
1781 q->mem_ops = &vb2_dma_sg_memops;
1782 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1783 q->lock = &core->lock;
2bc46b3a 1784 q->dev = &dev->pci->dev;
0b6b6302
HV		 1785
1786 err = vb2_queue_init(q);
1787 if (err < 0)
1788 goto fail_probe;
1789
1790 /* init struct vb2_dvb */
6e0e12f1 1791 fe->dvb.name = dev->core->name;
363c35fc 1792 }
6e0e12f1 1793
1da177e4 1794 err = dvb_register(dev);
cbd82441
DB		 1795 if (err)
1796 /* frontends/adapter de-allocated in dvb_register */
65bc2fe8 1797 pr_err("dvb_register failed (err = %d)\n", err);
cbd82441
DB		 1798 return err;
1799fail_probe:
0b6b6302 1800 vb2_dvb_dealloc_frontends(&core->dvbdev->frontends);
92abe9ee 1801fail_core:
1da177e4
LT		 1802 return err;
1803}
1804
6c5be74c 1805static int cx8802_dvb_remove(struct cx8802_driver *drv)
1da177e4 1806{
0fcd488d 1807 struct cx88_core *core = drv->core;
6c5be74c 1808 struct cx8802_dev *dev = drv->core->dvbdev;
611900c1 1809
7b61ba8f 1810 dprintk(1, "%s\n", __func__);
0fcd488d 1811
0b6b6302 1812 vb2_dvb_unregister_bus(&dev->frontends);
1da177e4 1813
fc40b261 1814 vp3054_i2c_remove(dev);
fc40b261 1815
e32fadc4
MCC		 1816 core->gate_ctrl = NULL;
1817
6c5be74c 1818 return 0;
1da177e4
LT		 1819}
1820
6c5be74c
ST		 1821static struct cx8802_driver cx8802_dvb_driver = {
1822 .type_id = CX88_MPEG_DVB,
1823 .hw_access = CX8802_DRVCTL_SHARED,
1824 .probe = cx8802_dvb_probe,
1825 .remove = cx8802_dvb_remove,
1826 .advise_acquire = cx8802_dvb_advise_acquire,
1827 .advise_release = cx8802_dvb_advise_release,
1da177e4
LT		 1828};
1829
31d0f845 1830static int __init dvb_init(void)
1da177e4 1831{
65bc2fe8 1832 pr_info("cx2388x dvb driver version %s loaded\n", CX88_VERSION);
6c5be74c 1833 return cx8802_register_driver(&cx8802_dvb_driver);
1da177e4
LT		 1834}
1835
31d0f845 1836static void __exit dvb_fini(void)
1da177e4 1837{
6c5be74c 1838 cx8802_unregister_driver(&cx8802_dvb_driver);
1da177e4
LT		 1839}
1840
1841module_init(dvb_init);
1842module_exit(dvb_fini);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git