[thirdparty/kernel/stable.git] / drivers / media / pci / solo6x10 / solo6x10-p2m.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
 *
 * Original author:
 * Ben Collins <bcollins@ubuntu.com>
 *
 * Additional work by:
 * John Brooks <john.brooks@bluecherry.net>
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>

#include "solo6x10.h"

static int multi_p2m;
module_param(multi_p2m, uint, 0644);
MODULE_PARM_DESC(multi_p2m,
		 "Use multiple P2M DMA channels (default: no, 6010-only)");

static int desc_mode;
module_param(desc_mode, uint, 0644);
MODULE_PARM_DESC(desc_mode,
		 "Allow use of descriptor mode DMA (default: no, 6010-only)");

int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
		 void *sys_addr, u32 ext_addr, u32 size,
		 int repeat, u32 ext_size)
{
	dma_addr_t dma_addr;
	int ret;

	if (WARN_ON_ONCE((unsigned long)sys_addr & 0x03))
		return -EINVAL;
	if (WARN_ON_ONCE(!size))
		return -EINVAL;

	dma_addr = pci_map_single(solo_dev->pdev, sys_addr, size,
				  wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
	if (pci_dma_mapping_error(solo_dev->pdev, dma_addr))
		return -ENOMEM;

	ret = solo_p2m_dma_t(solo_dev, wr, dma_addr, ext_addr, size,
			     repeat, ext_size);

	pci_unmap_single(solo_dev->pdev, dma_addr, size,
			 wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);

	return ret;
}

/* Mutex must be held for p2m_id before calling this!! */
int solo_p2m_dma_desc(struct solo_dev *solo_dev,
		      struct solo_p2m_desc *desc, dma_addr_t desc_dma,
		      int desc_cnt)
{
	struct solo_p2m_dev *p2m_dev;
	unsigned int timeout;
	unsigned int config = 0;
	int ret = 0;
	unsigned int p2m_id = 0;

	/* Get next ID. According to Softlogic, 6110 has problems on !=0 P2M */
	if (solo_dev->type != SOLO_DEV_6110 && multi_p2m)
		p2m_id = atomic_inc_return(&solo_dev->p2m_count) % SOLO_NR_P2M;

	p2m_dev = &solo_dev->p2m_dev[p2m_id];

	if (mutex_lock_interruptible(&p2m_dev->mutex))
		return -EINTR;

	reinit_completion(&p2m_dev->completion);
	p2m_dev->error = 0;

	if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && desc_mode) {
		/* For 6010 with more than one desc, we can do a one-shot */
		p2m_dev->desc_count = p2m_dev->desc_idx = 0;
		config = solo_reg_read(solo_dev, SOLO_P2M_CONFIG(p2m_id));

		solo_reg_write(solo_dev, SOLO_P2M_DES_ADR(p2m_id), desc_dma);
		solo_reg_write(solo_dev, SOLO_P2M_DESC_ID(p2m_id), desc_cnt);
		solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config |
			       SOLO_P2M_DESC_MODE);
	} else {
		/* For single descriptors and 6110, we need to run each desc */
		p2m_dev->desc_count = desc_cnt;
		p2m_dev->desc_idx = 1;
		p2m_dev->descs = desc;

		solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(p2m_id),
			       desc[1].dma_addr);
		solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(p2m_id),
			       desc[1].ext_addr);
		solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(p2m_id),
			       desc[1].cfg);
		solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id),
			       desc[1].ctrl);
	}

	timeout = wait_for_completion_timeout(&p2m_dev->completion,
					      solo_dev->p2m_jiffies);

	if (WARN_ON_ONCE(p2m_dev->error))
		ret = -EIO;
	else if (timeout == 0) {
		solo_dev->p2m_timeouts++;
		ret = -EAGAIN;
	}

	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id), 0);

	/* Don't write here for the no_desc_mode case, because config is 0.
	 * We can't test no_desc_mode again, it might race. */
	if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && config)
		solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config);

	mutex_unlock(&p2m_dev->mutex);

	return ret;
}

void solo_p2m_fill_desc(struct solo_p2m_desc *desc, int wr,
			dma_addr_t dma_addr, u32 ext_addr, u32 size,
			int repeat, u32 ext_size)
{
	WARN_ON_ONCE(dma_addr & 0x03);
	WARN_ON_ONCE(!size);

	desc->cfg = SOLO_P2M_COPY_SIZE(size >> 2);
	desc->ctrl = SOLO_P2M_BURST_SIZE(SOLO_P2M_BURST_256) |
		(wr ? SOLO_P2M_WRITE : 0) | SOLO_P2M_TRANS_ON;

	if (repeat) {
		desc->cfg |= SOLO_P2M_EXT_INC(ext_size >> 2);
		desc->ctrl |=  SOLO_P2M_PCI_INC(size >> 2) |
			 SOLO_P2M_REPEAT(repeat);
	}

	desc->dma_addr = dma_addr;
	desc->ext_addr = ext_addr;
}

int solo_p2m_dma_t(struct solo_dev *solo_dev, int wr,
		   dma_addr_t dma_addr, u32 ext_addr, u32 size,
		   int repeat, u32 ext_size)
{
	struct solo_p2m_desc desc[2];

	solo_p2m_fill_desc(&desc[1], wr, dma_addr, ext_addr, size, repeat,
			   ext_size);

	/* No need for desc_dma since we know it is a single-shot */
	return solo_p2m_dma_desc(solo_dev, desc, 0, 1);
}

void solo_p2m_isr(struct solo_dev *solo_dev, int id)
{
	struct solo_p2m_dev *p2m_dev = &solo_dev->p2m_dev[id];
	struct solo_p2m_desc *desc;

	if (p2m_dev->desc_count <= p2m_dev->desc_idx) {
		complete(&p2m_dev->completion);
		return;
	}

	/* Setup next descriptor */
	p2m_dev->desc_idx++;
	desc = &p2m_dev->descs[p2m_dev->desc_idx];

	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), 0);
	solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(id), desc->dma_addr);
	solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(id), desc->ext_addr);
	solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(id), desc->cfg);
	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), desc->ctrl);
}

void solo_p2m_error_isr(struct solo_dev *solo_dev)
{
	unsigned int err = solo_reg_read(solo_dev, SOLO_PCI_ERR);
	struct solo_p2m_dev *p2m_dev;
	int i;

	if (!(err & (SOLO_PCI_ERR_P2M | SOLO_PCI_ERR_P2M_DESC)))
		return;

	for (i = 0; i < SOLO_NR_P2M; i++) {
		p2m_dev = &solo_dev->p2m_dev[i];
		p2m_dev->error = 1;
		solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
		complete(&p2m_dev->completion);
	}
}

void solo_p2m_exit(struct solo_dev *solo_dev)
{
	int i;

	for (i = 0; i < SOLO_NR_P2M; i++)
		solo_irq_off(solo_dev, SOLO_IRQ_P2M(i));
}

static int solo_p2m_test(struct solo_dev *solo_dev, int base, int size)
{
	u32 *wr_buf;
	u32 *rd_buf;
	int i;
	int ret = -EIO;
	int order = get_order(size);

	wr_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
	if (wr_buf == NULL)
		return -1;

	rd_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
	if (rd_buf == NULL) {
		free_pages((unsigned long)wr_buf, order);
		return -1;
	}

	for (i = 0; i < (size >> 3); i++)
		*(wr_buf + i) = (i << 16) | (i + 1);

	for (i = (size >> 3); i < (size >> 2); i++)
		*(wr_buf + i) = ~((i << 16) | (i + 1));

	memset(rd_buf, 0x55, size);

	if (solo_p2m_dma(solo_dev, 1, wr_buf, base, size, 0, 0))
		goto test_fail;

	if (solo_p2m_dma(solo_dev, 0, rd_buf, base, size, 0, 0))
		goto test_fail;

	for (i = 0; i < (size >> 2); i++) {
		if (*(wr_buf + i) != *(rd_buf + i))
			goto test_fail;
	}

	ret = 0;

test_fail:
	free_pages((unsigned long)wr_buf, order);
	free_pages((unsigned long)rd_buf, order);

	return ret;
}

int solo_p2m_init(struct solo_dev *solo_dev)
{
	struct solo_p2m_dev *p2m_dev;
	int i;

	for (i = 0; i < SOLO_NR_P2M; i++) {
		p2m_dev = &solo_dev->p2m_dev[i];

		mutex_init(&p2m_dev->mutex);
		init_completion(&p2m_dev->completion);

		solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
		solo_reg_write(solo_dev, SOLO_P2M_CONFIG(i),
			       SOLO_P2M_CSC_16BIT_565 |
			       SOLO_P2M_DESC_INTR_OPT |
			       SOLO_P2M_DMA_INTERVAL(0) |
			       SOLO_P2M_PCI_MASTER_MODE);
		solo_irq_on(solo_dev, SOLO_IRQ_P2M(i));
	}

	/* Find correct SDRAM size */
	for (solo_dev->sdram_size = 0, i = 2; i >= 0; i--) {
		solo_reg_write(solo_dev, SOLO_DMA_CTRL,
			       SOLO_DMA_CTRL_REFRESH_CYCLE(1) |
			       SOLO_DMA_CTRL_SDRAM_SIZE(i) |
			       SOLO_DMA_CTRL_SDRAM_CLK_INVERT |
			       SOLO_DMA_CTRL_READ_CLK_SELECT |
			       SOLO_DMA_CTRL_LATENCY(1));

		solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config |
			       SOLO_SYS_CFG_RESET);
		solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config);

		switch (i) {
		case 2:
			if (solo_p2m_test(solo_dev, 0x07ff0000, 0x00010000) ||
			    solo_p2m_test(solo_dev, 0x05ff0000, 0x00010000))
				continue;
			break;

		case 1:
			if (solo_p2m_test(solo_dev, 0x03ff0000, 0x00010000))
				continue;
			break;

		default:
			if (solo_p2m_test(solo_dev, 0x01ff0000, 0x00010000))
				continue;
		}

		solo_dev->sdram_size = (32 << 20) << i;
		break;
	}

	if (!solo_dev->sdram_size) {
		dev_err(&solo_dev->pdev->dev, "Error detecting SDRAM size\n");
		return -EIO;
	}

	if (SOLO_SDRAM_END(solo_dev) > solo_dev->sdram_size) {
		dev_err(&solo_dev->pdev->dev,
			"SDRAM is not large enough (%u < %u)\n",
			solo_dev->sdram_size, SOLO_SDRAM_END(solo_dev));
		return -EIO;
	}

	return 0;
}
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
faa4fd2a	2	/*
dcae5dac HV	3	* Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
	4	*
	5	* Original author:
	6	* Ben Collins <bcollins@ubuntu.com>
	7	*
	8	* Additional work by:
	9	* John Brooks <john.brooks@bluecherry.net>
faa4fd2a BC	10	*/
	11
	12	#include <linux/kernel.h>
dcae5dac	13	#include <linux/module.h>
7b4785f4	14	#include <linux/slab.h>
dcae5dac	15
ae69b22c	16	#include "solo6x10.h"
faa4fd2a	17
dcae5dac HV	18	static int multi_p2m;
	19	module_param(multi_p2m, uint, 0644);
	20	MODULE_PARM_DESC(multi_p2m,
	21	"Use multiple P2M DMA channels (default: no, 6010-only)");
faa4fd2a	22
dcae5dac HV	23	static int desc_mode;
	24	module_param(desc_mode, uint, 0644);
	25	MODULE_PARM_DESC(desc_mode,
	26	"Allow use of descriptor mode DMA (default: no, 6010-only)");
	27
	28	int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
	29	void *sys_addr, u32 ext_addr, u32 size,
	30	int repeat, u32 ext_size)
faa4fd2a BC	31	{
	32	dma_addr_t dma_addr;
	33	int ret;
	34
dcae5dac HV	35	if (WARN_ON_ONCE((unsigned long)sys_addr & 0x03))
	36	return -EINVAL;
	37	if (WARN_ON_ONCE(!size))
faa4fd2a BC	38	return -EINVAL;
	39
	40	dma_addr = pci_map_single(solo_dev->pdev, sys_addr, size,
	41	wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
f43afb1e HV	42	if (pci_dma_mapping_error(solo_dev->pdev, dma_addr))
f43afb1e HV	43	return -ENOMEM;
faa4fd2a	44
dcae5dac HV	45	ret = solo_p2m_dma_t(solo_dev, wr, dma_addr, ext_addr, size,
dcae5dac HV	46	repeat, ext_size);
faa4fd2a BC	47
	48	pci_unmap_single(solo_dev->pdev, dma_addr, size,
	49	wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
	50
	51	return ret;
	52	}
	53
dcae5dac HV	54	/* Mutex must be held for p2m_id before calling this!! */
	55	int solo_p2m_dma_desc(struct solo_dev *solo_dev,
	56	struct solo_p2m_desc *desc, dma_addr_t desc_dma,
	57	int desc_cnt)
faa4fd2a BC	58	{
faa4fd2a BC	59	struct solo_p2m_dev *p2m_dev;
f62de9be	60	unsigned int timeout;
dcae5dac	61	unsigned int config = 0;
f62de9be	62	int ret = 0;
0df305eb	63	unsigned int p2m_id = 0;
faa4fd2a	64
dcae5dac	65	/* Get next ID. According to Softlogic, 6110 has problems on !=0 P2M */
0df305eb	66	if (solo_dev->type != SOLO_DEV_6110 && multi_p2m)
dcae5dac	67	p2m_id = atomic_inc_return(&solo_dev->p2m_count) % SOLO_NR_P2M;
faa4fd2a	68
dcae5dac	69	p2m_dev = &solo_dev->p2m_dev[p2m_id];
faa4fd2a	70
dcae5dac HV	71	if (mutex_lock_interruptible(&p2m_dev->mutex))
dcae5dac HV	72	return -EINTR;
0e4de059	73
16735d02	74	reinit_completion(&p2m_dev->completion);
faa4fd2a	75	p2m_dev->error = 0;
faa4fd2a	76
dcae5dac HV	77	if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && desc_mode) {
	78	/* For 6010 with more than one desc, we can do a one-shot */
	79	p2m_dev->desc_count = p2m_dev->desc_idx = 0;
	80	config = solo_reg_read(solo_dev, SOLO_P2M_CONFIG(p2m_id));
	81
	82	solo_reg_write(solo_dev, SOLO_P2M_DES_ADR(p2m_id), desc_dma);
	83	solo_reg_write(solo_dev, SOLO_P2M_DESC_ID(p2m_id), desc_cnt);
	84	solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config \|
	85	SOLO_P2M_DESC_MODE);
	86	} else {
	87	/* For single descriptors and 6110, we need to run each desc */
	88	p2m_dev->desc_count = desc_cnt;
	89	p2m_dev->desc_idx = 1;
	90	p2m_dev->descs = desc;
	91
	92	solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(p2m_id),
	93	desc[1].dma_addr);
	94	solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(p2m_id),
	95	desc[1].ext_addr);
	96	solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(p2m_id),
	97	desc[1].cfg);
	98	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id),
	99	desc[1].ctrl);
	100	}
faa4fd2a	101
dcae5dac HV	102	timeout = wait_for_completion_timeout(&p2m_dev->completion,
dcae5dac HV	103	solo_dev->p2m_jiffies);
0e4de059	104
dcae5dac	105	if (WARN_ON_ONCE(p2m_dev->error))
f62de9be	106	ret = -EIO;
dcae5dac HV	107	else if (timeout == 0) {
dcae5dac HV	108	solo_dev->p2m_timeouts++;
f62de9be	109	ret = -EAGAIN;
f62de9be BC	110	}
f62de9be BC	111
dcae5dac	112	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id), 0);
f62de9be	113
dcae5dac HV	114	/* Don't write here for the no_desc_mode case, because config is 0.
	115	* We can't test no_desc_mode again, it might race. */
	116	if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && config)
	117	solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config);
faa4fd2a	118
dcae5dac	119	mutex_unlock(&p2m_dev->mutex);
faa4fd2a	120
dcae5dac HV	121	return ret;
dcae5dac HV	122	}
faa4fd2a	123
dcae5dac HV	124	void solo_p2m_fill_desc(struct solo_p2m_desc *desc, int wr,
	125	dma_addr_t dma_addr, u32 ext_addr, u32 size,
	126	int repeat, u32 ext_size)
faa4fd2a	127	{
dcae5dac HV	128	WARN_ON_ONCE(dma_addr & 0x03);
dcae5dac HV	129	WARN_ON_ONCE(!size);
faa4fd2a	130
dcae5dac HV	131	desc->cfg = SOLO_P2M_COPY_SIZE(size >> 2);
	132	desc->ctrl = SOLO_P2M_BURST_SIZE(SOLO_P2M_BURST_256) \|
	133	(wr ? SOLO_P2M_WRITE : 0) \| SOLO_P2M_TRANS_ON;
faa4fd2a	134
dcae5dac HV	135	if (repeat) {
	136	desc->cfg \|= SOLO_P2M_EXT_INC(ext_size >> 2);
	137	desc->ctrl \|= SOLO_P2M_PCI_INC(size >> 2) \|
	138	SOLO_P2M_REPEAT(repeat);
faa4fd2a BC	139	}
faa4fd2a BC	140
dcae5dac HV	141	desc->dma_addr = dma_addr;
dcae5dac HV	142	desc->ext_addr = ext_addr;
faa4fd2a BC	143	}
faa4fd2a BC	144
dcae5dac HV	145	int solo_p2m_dma_t(struct solo_dev *solo_dev, int wr,
	146	dma_addr_t dma_addr, u32 ext_addr, u32 size,
	147	int repeat, u32 ext_size)
faa4fd2a	148	{
dcae5dac	149	struct solo_p2m_desc desc[2];
faa4fd2a	150
dcae5dac HV	151	solo_p2m_fill_desc(&desc[1], wr, dma_addr, ext_addr, size, repeat,
dcae5dac HV	152	ext_size);
faa4fd2a	153
dcae5dac HV	154	/* No need for desc_dma since we know it is a single-shot */
dcae5dac HV	155	return solo_p2m_dma_desc(solo_dev, desc, 0, 1);
faa4fd2a	156	}
faa4fd2a	157
decebabf	158	void solo_p2m_isr(struct solo_dev *solo_dev, int id)
faa4fd2a	159	{
f62de9be	160	struct solo_p2m_dev *p2m_dev = &solo_dev->p2m_dev[id];
dcae5dac HV	161	struct solo_p2m_desc *desc;
	162
	163	if (p2m_dev->desc_count <= p2m_dev->desc_idx) {
	164	complete(&p2m_dev->completion);
	165	return;
	166	}
f62de9be	167
dcae5dac HV	168	/* Setup next descriptor */
	169	p2m_dev->desc_idx++;
	170	desc = &p2m_dev->descs[p2m_dev->desc_idx];
f62de9be	171
dcae5dac HV	172	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), 0);
	173	solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(id), desc->dma_addr);
	174	solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(id), desc->ext_addr);
	175	solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(id), desc->cfg);
	176	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), desc->ctrl);
faa4fd2a BC	177	}
faa4fd2a BC	178
dcae5dac	179	void solo_p2m_error_isr(struct solo_dev *solo_dev)
faa4fd2a	180	{
dcae5dac	181	unsigned int err = solo_reg_read(solo_dev, SOLO_PCI_ERR);
faa4fd2a BC	182	struct solo_p2m_dev *p2m_dev;
	183	int i;
	184
4718892f	185	if (!(err & (SOLO_PCI_ERR_P2M \| SOLO_PCI_ERR_P2M_DESC)))
faa4fd2a BC	186	return;
	187
	188	for (i = 0; i < SOLO_NR_P2M; i++) {
	189	p2m_dev = &solo_dev->p2m_dev[i];
	190	p2m_dev->error = 1;
	191	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
	192	complete(&p2m_dev->completion);
	193	}
	194	}
	195
decebabf	196	void solo_p2m_exit(struct solo_dev *solo_dev)
faa4fd2a BC	197	{
	198	int i;
	199
	200	for (i = 0; i < SOLO_NR_P2M; i++)
decebabf	201	solo_irq_off(solo_dev, SOLO_IRQ_P2M(i));
faa4fd2a BC	202	}
faa4fd2a BC	203
dcae5dac HV	204	static int solo_p2m_test(struct solo_dev *solo_dev, int base, int size)
	205	{
	206	u32 *wr_buf;
	207	u32 *rd_buf;
	208	int i;
	209	int ret = -EIO;
	210	int order = get_order(size);
	211
	212	wr_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
	213	if (wr_buf == NULL)
	214	return -1;
	215
	216	rd_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
	217	if (rd_buf == NULL) {
	218	free_pages((unsigned long)wr_buf, order);
	219	return -1;
	220	}
	221
	222	for (i = 0; i < (size >> 3); i++)
	223	*(wr_buf + i) = (i << 16) \| (i + 1);
	224
	225	for (i = (size >> 3); i < (size >> 2); i++)
	226	*(wr_buf + i) = ~((i << 16) \| (i + 1));
	227
	228	memset(rd_buf, 0x55, size);
	229
	230	if (solo_p2m_dma(solo_dev, 1, wr_buf, base, size, 0, 0))
	231	goto test_fail;
	232
	233	if (solo_p2m_dma(solo_dev, 0, rd_buf, base, size, 0, 0))
	234	goto test_fail;
	235
	236	for (i = 0; i < (size >> 2); i++) {
	237	if ((wr_buf + i) != (rd_buf + i))
	238	goto test_fail;
	239	}
	240
	241	ret = 0;
	242
	243	test_fail:
	244	free_pages((unsigned long)wr_buf, order);
	245	free_pages((unsigned long)rd_buf, order);
	246
	247	return ret;
	248	}
	249
decebabf	250	int solo_p2m_init(struct solo_dev *solo_dev)
faa4fd2a BC	251	{
	252	struct solo_p2m_dev *p2m_dev;
	253	int i;
	254
	255	for (i = 0; i < SOLO_NR_P2M; i++) {
	256	p2m_dev = &solo_dev->p2m_dev[i];
	257
f62de9be	258	mutex_init(&p2m_dev->mutex);
faa4fd2a BC	259	init_completion(&p2m_dev->completion);
faa4fd2a BC	260
faa4fd2a BC	261	solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
	262	solo_reg_write(solo_dev, SOLO_P2M_CONFIG(i),
	263	SOLO_P2M_CSC_16BIT_565 \|
0e4de059	264	SOLO_P2M_DESC_INTR_OPT \|
dcae5dac	265	SOLO_P2M_DMA_INTERVAL(0) \|
faa4fd2a	266	SOLO_P2M_PCI_MASTER_MODE);
decebabf	267	solo_irq_on(solo_dev, SOLO_IRQ_P2M(i));
faa4fd2a BC	268	}
faa4fd2a BC	269
dcae5dac HV	270	/* Find correct SDRAM size */
	271	for (solo_dev->sdram_size = 0, i = 2; i >= 0; i--) {
	272	solo_reg_write(solo_dev, SOLO_DMA_CTRL,
	273	SOLO_DMA_CTRL_REFRESH_CYCLE(1) \|
	274	SOLO_DMA_CTRL_SDRAM_SIZE(i) \|
	275	SOLO_DMA_CTRL_SDRAM_CLK_INVERT \|
	276	SOLO_DMA_CTRL_READ_CLK_SELECT \|
	277	SOLO_DMA_CTRL_LATENCY(1));
	278
	279	solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config \|
	280	SOLO_SYS_CFG_RESET);
	281	solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config);
	282
	283	switch (i) {
	284	case 2:
	285	if (solo_p2m_test(solo_dev, 0x07ff0000, 0x00010000) \|\|
	286	solo_p2m_test(solo_dev, 0x05ff0000, 0x00010000))
	287	continue;
	288	break;
	289
	290	case 1:
	291	if (solo_p2m_test(solo_dev, 0x03ff0000, 0x00010000))
	292	continue;
	293	break;
	294
	295	default:
	296	if (solo_p2m_test(solo_dev, 0x01ff0000, 0x00010000))
	297	continue;
	298	}
	299
	300	solo_dev->sdram_size = (32 << 20) << i;
	301	break;
	302	}
	303
	304	if (!solo_dev->sdram_size) {
	305	dev_err(&solo_dev->pdev->dev, "Error detecting SDRAM size\n");
	306	return -EIO;
	307	}
	308
	309	if (SOLO_SDRAM_END(solo_dev) > solo_dev->sdram_size) {
	310	dev_err(&solo_dev->pdev->dev,
	311	"SDRAM is not large enough (%u < %u)\n",
	312	solo_dev->sdram_size, SOLO_SDRAM_END(solo_dev));
	313	return -EIO;
	314	}
faa4fd2a BC	315
	316	return 0;
	317	}