[thirdparty/kernel/stable.git] / drivers / media / platform / exynos-gsc / gsc-core.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * header file for Samsung EXYNOS5 SoC series G-Scaler driver

 */

#ifndef GSC_CORE_H_
#define GSC_CORE_H_

#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/videodev2.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <media/videobuf2-v4l2.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-mem2mem.h>
#include <media/v4l2-mediabus.h>
#include <media/videobuf2-dma-contig.h>

#include "gsc-regs.h"

#define CONFIG_VB2_GSC_DMA_CONTIG	1
#define GSC_MODULE_NAME			"exynos-gsc"

#define GSC_SHUTDOWN_TIMEOUT		((100*HZ)/1000)
#define GSC_MAX_DEVS			4
#define GSC_MAX_CLOCKS			4
#define GSC_M2M_BUF_NUM			0
#define GSC_MAX_CTRL_NUM		10
#define GSC_SC_ALIGN_4			4
#define GSC_SC_ALIGN_2			2
#define DEFAULT_CSC_EQ			1
#define DEFAULT_CSC_RANGE		1

#define GSC_PARAMS			(1 << 0)
#define GSC_SRC_FMT			(1 << 1)
#define GSC_DST_FMT			(1 << 2)
#define GSC_CTX_M2M			(1 << 3)
#define GSC_CTX_STOP_REQ		(1 << 6)
#define	GSC_CTX_ABORT			(1 << 7)

enum gsc_dev_flags {
	/* for m2m node */
	ST_M2M_OPEN,
	ST_M2M_RUN,
	ST_M2M_PEND,
	ST_M2M_SUSPENDED,
	ST_M2M_SUSPENDING,
};

enum gsc_irq {
	GSC_IRQ_DONE,
	GSC_IRQ_OVERRUN
};

/**
 * enum gsc_datapath - the path of data used for G-Scaler
 * @GSC_CAMERA: from camera
 * @GSC_DMA: from/to DMA
 * @GSC_LOCAL: to local path
 * @GSC_WRITEBACK: from FIMD
 */
enum gsc_datapath {
	GSC_CAMERA = 0x1,
	GSC_DMA,
	GSC_MIXER,
	GSC_FIMD,
	GSC_WRITEBACK,
};

enum gsc_color_fmt {
	GSC_RGB = 0x1,
	GSC_YUV420 = 0x2,
	GSC_YUV422 = 0x4,
	GSC_YUV444 = 0x8,
};

enum gsc_yuv_fmt {
	GSC_LSB_Y = 0x10,
	GSC_LSB_C,
	GSC_CBCR = 0x20,
	GSC_CRCB,
};

#define fh_to_ctx(__fh) container_of(__fh, struct gsc_ctx, fh)
#define is_rgb(x) (!!((x) & 0x1))
#define is_yuv420(x) (!!((x) & 0x2))
#define is_yuv422(x) (!!((x) & 0x4))

#define gsc_m2m_active(dev)	test_bit(ST_M2M_RUN, &(dev)->state)
#define gsc_m2m_pending(dev)	test_bit(ST_M2M_PEND, &(dev)->state)
#define gsc_m2m_opened(dev)	test_bit(ST_M2M_OPEN, &(dev)->state)

#define ctrl_to_ctx(__ctrl) \
	container_of((__ctrl)->handler, struct gsc_ctx, ctrl_handler)
/**
 * struct gsc_fmt - the driver's internal color format data
 * @mbus_code: Media Bus pixel code, -1 if not applicable
 * @name: format description
 * @pixelformat: the fourcc code for this format, 0 if not applicable
 * @yorder: Y/C order
 * @corder: Chrominance order control
 * @num_planes: number of physically non-contiguous data planes
 * @nr_comp: number of physically contiguous data planes
 * @depth: per plane driver's private 'number of bits per pixel'
 * @flags: flags indicating which operation mode format applies to
 */
struct gsc_fmt {
	u32 mbus_code;
	char	*name;
	u32	pixelformat;
	u32	color;
	u32	yorder;
	u32	corder;
	u16	num_planes;
	u16	num_comp;
	u8	depth[VIDEO_MAX_PLANES];
	u32	flags;
};

/**
 * struct gsc_input_buf - the driver's video buffer
 * @vb:	videobuf2 buffer
 * @list : linked list structure for buffer queue
 * @idx : index of G-Scaler input buffer
 */
struct gsc_input_buf {
	struct vb2_v4l2_buffer vb;
	struct list_head	list;
	int			idx;
};

/**
 * struct gsc_addr - the G-Scaler physical address set
 * @y:	 luminance plane address
 * @cb:	 Cb plane address
 * @cr:	 Cr plane address
 */
struct gsc_addr {
	dma_addr_t y;
	dma_addr_t cb;
	dma_addr_t cr;
};

/* struct gsc_ctrls - the G-Scaler control set
 * @rotate: rotation degree
 * @hflip: horizontal flip
 * @vflip: vertical flip
 * @global_alpha: the alpha value of current frame
 */
struct gsc_ctrls {
	struct v4l2_ctrl *rotate;
	struct v4l2_ctrl *hflip;
	struct v4l2_ctrl *vflip;
	struct v4l2_ctrl *global_alpha;
};

/**
 * struct gsc_scaler - the configuration data for G-Scaler inetrnal scaler
 * @pre_shfactor:	pre sclaer shift factor
 * @pre_hratio:		horizontal ratio of the prescaler
 * @pre_vratio:		vertical ratio of the prescaler
 * @main_hratio:	the main scaler's horizontal ratio
 * @main_vratio:	the main scaler's vertical ratio
 */
struct gsc_scaler {
	u32 pre_shfactor;
	u32 pre_hratio;
	u32 pre_vratio;
	u32 main_hratio;
	u32 main_vratio;
};

struct gsc_dev;

struct gsc_ctx;

/**
 * struct gsc_frame - source/target frame properties
 * @f_width:	SRC : SRCIMG_WIDTH, DST : OUTPUTDMA_WHOLE_IMG_WIDTH
 * @f_height:	SRC : SRCIMG_HEIGHT, DST : OUTPUTDMA_WHOLE_IMG_HEIGHT
 * @crop:	cropped(source)/scaled(destination) size
 * @payload:	image size in bytes (w x h x bpp)
 * @addr:	image frame buffer physical addresses
 * @fmt:	G-Scaler color format pointer
 * @colorspace: value indicating v4l2_colorspace
 * @alpha:	frame's alpha value
 */
struct gsc_frame {
	u32 f_width;
	u32 f_height;
	struct v4l2_rect crop;
	unsigned long payload[VIDEO_MAX_PLANES];
	struct gsc_addr	addr;
	const struct gsc_fmt *fmt;
	u32 colorspace;
	u8 alpha;
};

/**
 * struct gsc_m2m_device - v4l2 memory-to-memory device data
 * @vfd: the video device node for v4l2 m2m mode
 * @m2m_dev: v4l2 memory-to-memory device data
 * @ctx: hardware context data
 * @refcnt: the reference counter
 */
struct gsc_m2m_device {
	struct video_device	*vfd;
	struct v4l2_m2m_dev	*m2m_dev;
	struct gsc_ctx		*ctx;
	int			refcnt;
};

/**
 *  struct gsc_pix_max - image pixel size limits in various IP configurations
 *
 *  @org_scaler_bypass_w: max pixel width when the scaler is disabled
 *  @org_scaler_bypass_h: max pixel height when the scaler is disabled
 *  @org_scaler_input_w: max pixel width when the scaler is enabled
 *  @org_scaler_input_h: max pixel height when the scaler is enabled
 *  @real_rot_dis_w: max pixel src cropped height with the rotator is off
 *  @real_rot_dis_h: max pixel src croppped width with the rotator is off
 *  @real_rot_en_w: max pixel src cropped width with the rotator is on
 *  @real_rot_en_h: max pixel src cropped height with the rotator is on
 *  @target_rot_dis_w: max pixel dst scaled width with the rotator is off
 *  @target_rot_dis_h: max pixel dst scaled height with the rotator is off
 *  @target_rot_en_w: max pixel dst scaled width with the rotator is on
 *  @target_rot_en_h: max pixel dst scaled height with the rotator is on
 */
struct gsc_pix_max {
	u16 org_scaler_bypass_w;
	u16 org_scaler_bypass_h;
	u16 org_scaler_input_w;
	u16 org_scaler_input_h;
	u16 real_rot_dis_w;
	u16 real_rot_dis_h;
	u16 real_rot_en_w;
	u16 real_rot_en_h;
	u16 target_rot_dis_w;
	u16 target_rot_dis_h;
	u16 target_rot_en_w;
	u16 target_rot_en_h;
};

/**
 *  struct gsc_pix_min - image pixel size limits in various IP configurations
 *
 *  @org_w: minimum source pixel width
 *  @org_h: minimum source pixel height
 *  @real_w: minimum input crop pixel width
 *  @real_h: minimum input crop pixel height
 *  @target_rot_dis_w: minimum output scaled pixel height when rotator is off
 *  @target_rot_dis_h: minimum output scaled pixel height when rotator is off
 *  @target_rot_en_w: minimum output scaled pixel height when rotator is on
 *  @target_rot_en_h: minimum output scaled pixel height when rotator is on
 */
struct gsc_pix_min {
	u16 org_w;
	u16 org_h;
	u16 real_w;
	u16 real_h;
	u16 target_rot_dis_w;
	u16 target_rot_dis_h;
	u16 target_rot_en_w;
	u16 target_rot_en_h;
};

struct gsc_pix_align {
	u16 org_h;
	u16 org_w;
	u16 offset_h;
	u16 real_w;
	u16 real_h;
	u16 target_w;
	u16 target_h;
};

/**
 * struct gsc_variant - G-Scaler variant information
 */
struct gsc_variant {
	struct gsc_pix_max *pix_max;
	struct gsc_pix_min *pix_min;
	struct gsc_pix_align *pix_align;
	u16		in_buf_cnt;
	u16		out_buf_cnt;
	u16		sc_up_max;
	u16		sc_down_max;
	u16		poly_sc_down_max;
	u16		pre_sc_down_max;
	u16		local_sc_down;
};

/**
 * struct gsc_driverdata - per device type driver data for init time.
 *
 * @variant: the variant information for this driver.
 * @num_entities: the number of g-scalers
 */
struct gsc_driverdata {
	struct gsc_variant *variant[GSC_MAX_DEVS];
	const char	*clk_names[GSC_MAX_CLOCKS];
	int		num_clocks;
	int		num_entities;
};

/**
 * struct gsc_dev - abstraction for G-Scaler entity
 * @slock:	the spinlock protecting this data structure
 * @lock:	the mutex protecting this data structure
 * @pdev:	pointer to the G-Scaler platform device
 * @variant:	the IP variant information
 * @id:		G-Scaler device index (0..GSC_MAX_DEVS)
 * @clock:	clocks required for G-Scaler operation
 * @regs:	the mapped hardware registers
 * @irq_queue:	interrupt handler waitqueue
 * @m2m:	memory-to-memory V4L2 device information
 * @state:	flags used to synchronize m2m and capture mode operation
 * @vdev:	video device for G-Scaler instance
 */
struct gsc_dev {
	spinlock_t			slock;
	struct mutex			lock;
	struct platform_device		*pdev;
	struct gsc_variant		*variant;
	u16				id;
	int				num_clocks;
	struct clk			*clock[GSC_MAX_CLOCKS];
	void __iomem			*regs;
	wait_queue_head_t		irq_queue;
	struct gsc_m2m_device		m2m;
	unsigned long			state;
	struct video_device		vdev;
	struct v4l2_device		v4l2_dev;
};

/**
 * gsc_ctx - the device context data
 * @s_frame:		source frame properties
 * @d_frame:		destination frame properties
 * @in_path:		input mode (DMA or camera)
 * @out_path:		output mode (DMA or FIFO)
 * @scaler:		image scaler properties
 * @flags:		additional flags for image conversion
 * @state:		flags to keep track of user configuration
 * @gsc_dev:		the G-Scaler device this context applies to
 * @m2m_ctx:		memory-to-memory device context
 * @fh:                 v4l2 file handle
 * @ctrl_handler:       v4l2 controls handler
 * @gsc_ctrls		G-Scaler control set
 * @ctrls_rdy:          true if the control handler is initialized
 */
struct gsc_ctx {
	struct gsc_frame	s_frame;
	struct gsc_frame	d_frame;
	enum gsc_datapath	in_path;
	enum gsc_datapath	out_path;
	struct gsc_scaler	scaler;
	u32			flags;
	u32			state;
	int			rotation;
	unsigned int		hflip:1;
	unsigned int		vflip:1;
	struct gsc_dev		*gsc_dev;
	struct v4l2_m2m_ctx	*m2m_ctx;
	struct v4l2_fh		fh;
	struct v4l2_ctrl_handler ctrl_handler;
	struct gsc_ctrls	gsc_ctrls;
	bool			ctrls_rdy;
	enum v4l2_colorspace out_colorspace;
};

void gsc_set_prefbuf(struct gsc_dev *gsc, struct gsc_frame *frm);
int gsc_register_m2m_device(struct gsc_dev *gsc);
void gsc_unregister_m2m_device(struct gsc_dev *gsc);
void gsc_m2m_job_finish(struct gsc_ctx *ctx, int vb_state);

u32 get_plane_size(struct gsc_frame *fr, unsigned int plane);
const struct gsc_fmt *get_format(int index);
const struct gsc_fmt *find_fmt(u32 *pixelformat, u32 *mbus_code, u32 index);
int gsc_enum_fmt_mplane(struct v4l2_fmtdesc *f);
int gsc_try_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f);
void gsc_set_frame_size(struct gsc_frame *frame, int width, int height);
int gsc_g_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f);
void gsc_check_crop_change(u32 tmp_w, u32 tmp_h, u32 *w, u32 *h);
int gsc_try_selection(struct gsc_ctx *ctx, struct v4l2_selection *s);
int gsc_cal_prescaler_ratio(struct gsc_variant *var, u32 src, u32 dst,
							u32 *ratio);
void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *sh);
void gsc_check_src_scale_info(struct gsc_variant *var,
				struct gsc_frame *s_frame,
				u32 *wratio, u32 tx, u32 ty, u32 *hratio);
int gsc_check_scaler_ratio(struct gsc_variant *var, int sw, int sh, int dw,
			   int dh, int rot, int out_path);
int gsc_set_scaler_info(struct gsc_ctx *ctx);
int gsc_ctrls_create(struct gsc_ctx *ctx);
void gsc_ctrls_delete(struct gsc_ctx *ctx);
int gsc_prepare_addr(struct gsc_ctx *ctx, struct vb2_buffer *vb,
		     struct gsc_frame *frame, struct gsc_addr *addr);

static inline void gsc_ctx_state_lock_set(u32 state, struct gsc_ctx *ctx)
{
	unsigned long flags;

	spin_lock_irqsave(&ctx->gsc_dev->slock, flags);
	ctx->state |= state;
	spin_unlock_irqrestore(&ctx->gsc_dev->slock, flags);
}

static inline void gsc_ctx_state_lock_clear(u32 state, struct gsc_ctx *ctx)
{
	unsigned long flags;

	spin_lock_irqsave(&ctx->gsc_dev->slock, flags);
	ctx->state &= ~state;
	spin_unlock_irqrestore(&ctx->gsc_dev->slock, flags);
}

static inline int is_tiled(const struct gsc_fmt *fmt)
{
	return fmt->pixelformat == V4L2_PIX_FMT_NV12MT_16X16;
}

static inline void gsc_hw_enable_control(struct gsc_dev *dev, bool on)
{
	u32 cfg = readl(dev->regs + GSC_ENABLE);

	if (on)
		cfg |= GSC_ENABLE_ON;
	else
		cfg &= ~GSC_ENABLE_ON;

	writel(cfg, dev->regs + GSC_ENABLE);
}

static inline int gsc_hw_get_irq_status(struct gsc_dev *dev)
{
	u32 cfg = readl(dev->regs + GSC_IRQ);
	if (cfg & GSC_IRQ_STATUS_OR_IRQ)
		return GSC_IRQ_OVERRUN;
	else
		return GSC_IRQ_DONE;

}

static inline void gsc_hw_clear_irq(struct gsc_dev *dev, int irq)
{
	u32 cfg = readl(dev->regs + GSC_IRQ);
	if (irq == GSC_IRQ_OVERRUN)
		cfg |= GSC_IRQ_STATUS_OR_IRQ;
	else if (irq == GSC_IRQ_DONE)
		cfg |= GSC_IRQ_STATUS_FRM_DONE_IRQ;
	writel(cfg, dev->regs + GSC_IRQ);
}

static inline bool gsc_ctx_state_is_set(u32 mask, struct gsc_ctx *ctx)
{
	unsigned long flags;
	bool ret;

	spin_lock_irqsave(&ctx->gsc_dev->slock, flags);
	ret = (ctx->state & mask) == mask;
	spin_unlock_irqrestore(&ctx->gsc_dev->slock, flags);
	return ret;
}

static inline struct gsc_frame *ctx_get_frame(struct gsc_ctx *ctx,
					      enum v4l2_buf_type type)
{
	struct gsc_frame *frame;

	if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
		frame = &ctx->s_frame;
	} else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
		frame = &ctx->d_frame;
	} else {
		pr_err("Wrong buffer/video queue type (%d)", type);
		return ERR_PTR(-EINVAL);
	}

	return frame;
}

void gsc_hw_set_sw_reset(struct gsc_dev *dev);
int gsc_wait_reset(struct gsc_dev *dev);

void gsc_hw_set_frm_done_irq_mask(struct gsc_dev *dev, bool mask);
void gsc_hw_set_gsc_irq_enable(struct gsc_dev *dev, bool mask);
void gsc_hw_set_input_buf_masking(struct gsc_dev *dev, u32 shift, bool enable);
void gsc_hw_set_output_buf_masking(struct gsc_dev *dev, u32 shift, bool enable);
void gsc_hw_set_input_addr(struct gsc_dev *dev, struct gsc_addr *addr,
							int index);
void gsc_hw_set_output_addr(struct gsc_dev *dev, struct gsc_addr *addr,
							int index);
void gsc_hw_set_input_path(struct gsc_ctx *ctx);
void gsc_hw_set_in_size(struct gsc_ctx *ctx);
void gsc_hw_set_in_image_rgb(struct gsc_ctx *ctx);
void gsc_hw_set_in_image_format(struct gsc_ctx *ctx);
void gsc_hw_set_output_path(struct gsc_ctx *ctx);
void gsc_hw_set_out_size(struct gsc_ctx *ctx);
void gsc_hw_set_out_image_rgb(struct gsc_ctx *ctx);
void gsc_hw_set_out_image_format(struct gsc_ctx *ctx);
void gsc_hw_set_prescaler(struct gsc_ctx *ctx);
void gsc_hw_set_mainscaler(struct gsc_ctx *ctx);
void gsc_hw_set_rotation(struct gsc_ctx *ctx);
void gsc_hw_set_global_alpha(struct gsc_ctx *ctx);
void gsc_hw_set_sfr_update(struct gsc_ctx *ctx);

#endif /* GSC_CORE_H_ */
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
89069699 SK	2	/*
	3	* Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* header file for Samsung EXYNOS5 SoC series G-Scaler driver
	7
89069699 SK	8	*/
	9
	10	#ifndef GSC_CORE_H_
	11	#define GSC_CORE_H_
	12
	13	#include <linux/delay.h>
	14	#include <linux/sched.h>
	15	#include <linux/spinlock.h>
	16	#include <linux/types.h>
	17	#include <linux/videodev2.h>
	18	#include <linux/io.h>
	19	#include <linux/pm_runtime.h>
c139990e	20	#include <media/videobuf2-v4l2.h>
89069699 SK	21	#include <media/v4l2-ctrls.h>
	22	#include <media/v4l2-device.h>
	23	#include <media/v4l2-mem2mem.h>
	24	#include <media/v4l2-mediabus.h>
	25	#include <media/videobuf2-dma-contig.h>
	26
	27	#include "gsc-regs.h"
	28
	29	#define CONFIG_VB2_GSC_DMA_CONTIG 1
	30	#define GSC_MODULE_NAME "exynos-gsc"
	31
	32	#define GSC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
	33	#define GSC_MAX_DEVS 4
92955ea0	34	#define GSC_MAX_CLOCKS 4
89069699 SK	35	#define GSC_M2M_BUF_NUM 0
	36	#define GSC_MAX_CTRL_NUM 10
	37	#define GSC_SC_ALIGN_4 4
	38	#define GSC_SC_ALIGN_2 2
	39	#define DEFAULT_CSC_EQ 1
	40	#define DEFAULT_CSC_RANGE 1
	41
	42	#define GSC_PARAMS (1 << 0)
	43	#define GSC_SRC_FMT (1 << 1)
	44	#define GSC_DST_FMT (1 << 2)
	45	#define GSC_CTX_M2M (1 << 3)
	46	#define GSC_CTX_STOP_REQ (1 << 6)
d9315160	47	#define GSC_CTX_ABORT (1 << 7)
89069699 SK	48
89069699 SK	49	enum gsc_dev_flags {
89069699 SK	50	/* for m2m node */
	51	ST_M2M_OPEN,
	52	ST_M2M_RUN,
	53	ST_M2M_PEND,
	54	ST_M2M_SUSPENDED,
	55	ST_M2M_SUSPENDING,
	56	};
	57
	58	enum gsc_irq {
	59	GSC_IRQ_DONE,
	60	GSC_IRQ_OVERRUN
	61	};
	62
	63	/**
	64	* enum gsc_datapath - the path of data used for G-Scaler
	65	* @GSC_CAMERA: from camera
	66	* @GSC_DMA: from/to DMA
	67	* @GSC_LOCAL: to local path
	68	* @GSC_WRITEBACK: from FIMD
	69	*/
	70	enum gsc_datapath {
	71	GSC_CAMERA = 0x1,
	72	GSC_DMA,
	73	GSC_MIXER,
	74	GSC_FIMD,
	75	GSC_WRITEBACK,
	76	};
	77
	78	enum gsc_color_fmt {
	79	GSC_RGB = 0x1,
	80	GSC_YUV420 = 0x2,
	81	GSC_YUV422 = 0x4,
	82	GSC_YUV444 = 0x8,
	83	};
	84
	85	enum gsc_yuv_fmt {
	86	GSC_LSB_Y = 0x10,
	87	GSC_LSB_C,
	88	GSC_CBCR = 0x20,
	89	GSC_CRCB,
	90	};
	91
	92	#define fh_to_ctx(__fh) container_of(__fh, struct gsc_ctx, fh)
	93	#define is_rgb(x) (!!((x) & 0x1))
	94	#define is_yuv420(x) (!!((x) & 0x2))
	95	#define is_yuv422(x) (!!((x) & 0x4))
	96
	97	#define gsc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
	98	#define gsc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
	99	#define gsc_m2m_opened(dev) test_bit(ST_M2M_OPEN, &(dev)->state)
	100
	101	#define ctrl_to_ctx(__ctrl) \
	102	container_of((__ctrl)->handler, struct gsc_ctx, ctrl_handler)
	103	/**
	104	* struct gsc_fmt - the driver's internal color format data
	105	* @mbus_code: Media Bus pixel code, -1 if not applicable
	106	* @name: format description
	107	* @pixelformat: the fourcc code for this format, 0 if not applicable
	108	* @yorder: Y/C order
	109	* @corder: Chrominance order control
	110	* @num_planes: number of physically non-contiguous data planes
	111	* @nr_comp: number of physically contiguous data planes
	112	* @depth: per plane driver's private 'number of bits per pixel'
	113	* @flags: flags indicating which operation mode format applies to
114	*/
115	struct gsc_fmt {
27ffaeb0	116	u32 mbus_code;
89069699 SK	117	char *name;
	118	u32 pixelformat;
	119	u32 color;
	120	u32 yorder;
	121	u32 corder;
	122	u16 num_planes;
	123	u16 num_comp;
	124	u8 depth[VIDEO_MAX_PLANES];
	125	u32 flags;
	126	};
	127
	128	/**
	129	* struct gsc_input_buf - the driver's video buffer
	130	* @vb: videobuf2 buffer
	131	* @list : linked list structure for buffer queue
	132	* @idx : index of G-Scaler input buffer
	133	*/
	134	struct gsc_input_buf {
2d700715	135	struct vb2_v4l2_buffer vb;
89069699 SK	136	struct list_head list;
	137	int idx;
	138	};
	139
	140	/**
	141	* struct gsc_addr - the G-Scaler physical address set
	142	* @y: luminance plane address
	143	* @cb: Cb plane address
	144	* @cr: Cr plane address
	145	*/
	146	struct gsc_addr {
	147	dma_addr_t y;
	148	dma_addr_t cb;
	149	dma_addr_t cr;
	150	};
	151
	152	/* struct gsc_ctrls - the G-Scaler control set
	153	* @rotate: rotation degree
	154	* @hflip: horizontal flip
	155	* @vflip: vertical flip
	156	* @global_alpha: the alpha value of current frame
	157	*/
	158	struct gsc_ctrls {
	159	struct v4l2_ctrl *rotate;
	160	struct v4l2_ctrl *hflip;
	161	struct v4l2_ctrl *vflip;
	162	struct v4l2_ctrl *global_alpha;
	163	};
	164
	165	/**
	166	* struct gsc_scaler - the configuration data for G-Scaler inetrnal scaler
	167	* @pre_shfactor: pre sclaer shift factor
	168	* @pre_hratio: horizontal ratio of the prescaler
	169	* @pre_vratio: vertical ratio of the prescaler
	170	* @main_hratio: the main scaler's horizontal ratio
	171	* @main_vratio: the main scaler's vertical ratio
	172	*/
	173	struct gsc_scaler {
	174	u32 pre_shfactor;
	175	u32 pre_hratio;
	176	u32 pre_vratio;
	177	u32 main_hratio;
	178	u32 main_vratio;
	179	};
	180
	181	struct gsc_dev;
	182
	183	struct gsc_ctx;
	184
	185	/**
	186	* struct gsc_frame - source/target frame properties
	187	* @f_width: SRC : SRCIMG_WIDTH, DST : OUTPUTDMA_WHOLE_IMG_WIDTH
	188	* @f_height: SRC : SRCIMG_HEIGHT, DST : OUTPUTDMA_WHOLE_IMG_HEIGHT
	189	* @crop: cropped(source)/scaled(destination) size
	190	* @payload: image size in bytes (w x h x bpp)
	191	* @addr: image frame buffer physical addresses
	192	* @fmt: G-Scaler color format pointer
	193	* @colorspace: value indicating v4l2_colorspace
	194	* @alpha: frame's alpha value
	195	*/
	196	struct gsc_frame {
	197	u32 f_width;
	198	u32 f_height;
	199	struct v4l2_rect crop;
200	unsigned long payload[VIDEO_MAX_PLANES];
201	struct gsc_addr addr;
202	const struct gsc_fmt *fmt;
203	u32 colorspace;
204	u8 alpha;
205	};
206
207	/**
208	* struct gsc_m2m_device - v4l2 memory-to-memory device data
209	* @vfd: the video device node for v4l2 m2m mode
210	* @m2m_dev: v4l2 memory-to-memory device data
211	* @ctx: hardware context data
212	* @refcnt: the reference counter
213	*/
214	struct gsc_m2m_device {
215	struct video_device *vfd;
216	struct v4l2_m2m_dev *m2m_dev;
217	struct gsc_ctx *ctx;
218	int refcnt;
219	};
220
221	/**
222	* struct gsc_pix_max - image pixel size limits in various IP configurations
223	*
224	* @org_scaler_bypass_w: max pixel width when the scaler is disabled
225	* @org_scaler_bypass_h: max pixel height when the scaler is disabled
226	* @org_scaler_input_w: max pixel width when the scaler is enabled
227	* @org_scaler_input_h: max pixel height when the scaler is enabled
228	* @real_rot_dis_w: max pixel src cropped height with the rotator is off
229	* @real_rot_dis_h: max pixel src croppped width with the rotator is off
230	* @real_rot_en_w: max pixel src cropped width with the rotator is on
231	* @real_rot_en_h: max pixel src cropped height with the rotator is on
232	* @target_rot_dis_w: max pixel dst scaled width with the rotator is off
233	* @target_rot_dis_h: max pixel dst scaled height with the rotator is off
234	* @target_rot_en_w: max pixel dst scaled width with the rotator is on
235	* @target_rot_en_h: max pixel dst scaled height with the rotator is on
236	*/
237	struct gsc_pix_max {
238	u16 org_scaler_bypass_w;
239	u16 org_scaler_bypass_h;
240	u16 org_scaler_input_w;
241	u16 org_scaler_input_h;
242	u16 real_rot_dis_w;
243	u16 real_rot_dis_h;
244	u16 real_rot_en_w;
245	u16 real_rot_en_h;
246	u16 target_rot_dis_w;
247	u16 target_rot_dis_h;
248	u16 target_rot_en_w;
249	u16 target_rot_en_h;
250	};
251
252	/**
253	* struct gsc_pix_min - image pixel size limits in various IP configurations
254	*
255	* @org_w: minimum source pixel width
256	* @org_h: minimum source pixel height
257	* @real_w: minimum input crop pixel width
258	* @real_h: minimum input crop pixel height
259	* @target_rot_dis_w: minimum output scaled pixel height when rotator is off
260	* @target_rot_dis_h: minimum output scaled pixel height when rotator is off
261	* @target_rot_en_w: minimum output scaled pixel height when rotator is on
262	* @target_rot_en_h: minimum output scaled pixel height when rotator is on
263	*/
264	struct gsc_pix_min {
265	u16 org_w;
266	u16 org_h;
267	u16 real_w;
268	u16 real_h;
269	u16 target_rot_dis_w;
270	u16 target_rot_dis_h;
271	u16 target_rot_en_w;
272	u16 target_rot_en_h;
273	};
274
275	struct gsc_pix_align {
276	u16 org_h;
277	u16 org_w;
278	u16 offset_h;
279	u16 real_w;
280	u16 real_h;
281	u16 target_w;
282	u16 target_h;
283	};
284
285	/**
286	* struct gsc_variant - G-Scaler variant information
287	*/
288	struct gsc_variant {
289	struct gsc_pix_max *pix_max;
290	struct gsc_pix_min *pix_min;
291	struct gsc_pix_align *pix_align;
292	u16 in_buf_cnt;
293	u16 out_buf_cnt;
294	u16 sc_up_max;
295	u16 sc_down_max;
296	u16 poly_sc_down_max;
297	u16 pre_sc_down_max;
298	u16 local_sc_down;
299	};
300
301	/**
302	* struct gsc_driverdata - per device type driver data for init time.
303	*
304	* @variant: the variant information for this driver.
89069699 SK	305	* @num_entities: the number of g-scalers
	306	*/
	307	struct gsc_driverdata {
	308	struct gsc_variant *variant[GSC_MAX_DEVS];
92955ea0 MS	309	const char *clk_names[GSC_MAX_CLOCKS];
92955ea0 MS	310	int num_clocks;
89069699 SK	311	int num_entities;
	312	};
	313
	314	/**
	315	* struct gsc_dev - abstraction for G-Scaler entity
	316	* @slock: the spinlock protecting this data structure
	317	* @lock: the mutex protecting this data structure
	318	* @pdev: pointer to the G-Scaler platform device
	319	* @variant: the IP variant information
	320	* @id: G-Scaler device index (0..GSC_MAX_DEVS)
	321	* @clock: clocks required for G-Scaler operation
	322	* @regs: the mapped hardware registers
	323	* @irq_queue: interrupt handler waitqueue
	324	* @m2m: memory-to-memory V4L2 device information
	325	* @state: flags used to synchronize m2m and capture mode operation
89069699 SK	326	* @vdev: video device for G-Scaler instance
	327	*/
	328	struct gsc_dev {
	329	spinlock_t slock;
	330	struct mutex lock;
	331	struct platform_device *pdev;
	332	struct gsc_variant *variant;
	333	u16 id;
92955ea0 MS	334	int num_clocks;
92955ea0 MS	335	struct clk *clock[GSC_MAX_CLOCKS];
89069699 SK	336	void __iomem *regs;
	337	wait_queue_head_t irq_queue;
	338	struct gsc_m2m_device m2m;
89069699	339	unsigned long state;
89069699	340	struct video_device vdev;
d0b1c313	341	struct v4l2_device v4l2_dev;
89069699 SK	342	};
	343
	344	/**
	345	* gsc_ctx - the device context data
	346	* @s_frame: source frame properties
	347	* @d_frame: destination frame properties
	348	* @in_path: input mode (DMA or camera)
	349	* @out_path: output mode (DMA or FIFO)
	350	* @scaler: image scaler properties
	351	* @flags: additional flags for image conversion
	352	* @state: flags to keep track of user configuration
	353	* @gsc_dev: the G-Scaler device this context applies to
	354	* @m2m_ctx: memory-to-memory device context
	355	* @fh: v4l2 file handle
	356	* @ctrl_handler: v4l2 controls handler
	357	* @gsc_ctrls G-Scaler control set
	358	* @ctrls_rdy: true if the control handler is initialized
	359	*/
	360	struct gsc_ctx {
	361	struct gsc_frame s_frame;
	362	struct gsc_frame d_frame;
	363	enum gsc_datapath in_path;
	364	enum gsc_datapath out_path;
	365	struct gsc_scaler scaler;
	366	u32 flags;
	367	u32 state;
	368	int rotation;
	369	unsigned int hflip:1;
	370	unsigned int vflip:1;
	371	struct gsc_dev *gsc_dev;
	372	struct v4l2_m2m_ctx *m2m_ctx;
	373	struct v4l2_fh fh;
	374	struct v4l2_ctrl_handler ctrl_handler;
	375	struct gsc_ctrls gsc_ctrls;
	376	bool ctrls_rdy;
57612890	377	enum v4l2_colorspace out_colorspace;
89069699 SK	378	};
	379
	380	void gsc_set_prefbuf(struct gsc_dev gsc, struct gsc_frame frm);
	381	int gsc_register_m2m_device(struct gsc_dev *gsc);
	382	void gsc_unregister_m2m_device(struct gsc_dev *gsc);
	383	void gsc_m2m_job_finish(struct gsc_ctx *ctx, int vb_state);
	384
	385	u32 get_plane_size(struct gsc_frame *fr, unsigned int plane);
	386	const struct gsc_fmt *get_format(int index);
	387	const struct gsc_fmt find_fmt(u32 pixelformat, u32 *mbus_code, u32 index);
	388	int gsc_enum_fmt_mplane(struct v4l2_fmtdesc *f);
	389	int gsc_try_fmt_mplane(struct gsc_ctx ctx, struct v4l2_format f);
	390	void gsc_set_frame_size(struct gsc_frame *frame, int width, int height);
	391	int gsc_g_fmt_mplane(struct gsc_ctx ctx, struct v4l2_format f);
	392	void gsc_check_crop_change(u32 tmp_w, u32 tmp_h, u32 w, u32 h);
9ad763d0	393	int gsc_try_selection(struct gsc_ctx ctx, struct v4l2_selection s);
89069699 SK	394	int gsc_cal_prescaler_ratio(struct gsc_variant *var, u32 src, u32 dst,
	395	u32 *ratio);
	396	void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *sh);
	397	void gsc_check_src_scale_info(struct gsc_variant *var,
	398	struct gsc_frame *s_frame,
	399	u32 wratio, u32 tx, u32 ty, u32 hratio);
	400	int gsc_check_scaler_ratio(struct gsc_variant *var, int sw, int sh, int dw,
	401	int dh, int rot, int out_path);
	402	int gsc_set_scaler_info(struct gsc_ctx *ctx);
	403	int gsc_ctrls_create(struct gsc_ctx *ctx);
	404	void gsc_ctrls_delete(struct gsc_ctx *ctx);
	405	int gsc_prepare_addr(struct gsc_ctx ctx, struct vb2_buffer vb,
	406	struct gsc_frame frame, struct gsc_addr addr);
	407
	408	static inline void gsc_ctx_state_lock_set(u32 state, struct gsc_ctx *ctx)
	409	{
	410	unsigned long flags;
	411
	412	spin_lock_irqsave(&ctx->gsc_dev->slock, flags);
	413	ctx->state \|= state;
	414	spin_unlock_irqrestore(&ctx->gsc_dev->slock, flags);
	415	}
	416
	417	static inline void gsc_ctx_state_lock_clear(u32 state, struct gsc_ctx *ctx)
	418	{
	419	unsigned long flags;
	420
	421	spin_lock_irqsave(&ctx->gsc_dev->slock, flags);
	422	ctx->state &= ~state;
	423	spin_unlock_irqrestore(&ctx->gsc_dev->slock, flags);
	424	}
	425
aecede4c SAB	426	static inline int is_tiled(const struct gsc_fmt *fmt)
	427	{
	428	return fmt->pixelformat == V4L2_PIX_FMT_NV12MT_16X16;
	429	}
	430
89069699 SK	431	static inline void gsc_hw_enable_control(struct gsc_dev *dev, bool on)
	432	{
	433	u32 cfg = readl(dev->regs + GSC_ENABLE);
	434
	435	if (on)
	436	cfg \|= GSC_ENABLE_ON;
	437	else
	438	cfg &= ~GSC_ENABLE_ON;
	439
	440	writel(cfg, dev->regs + GSC_ENABLE);
	441	}
	442
	443	static inline int gsc_hw_get_irq_status(struct gsc_dev *dev)
	444	{
	445	u32 cfg = readl(dev->regs + GSC_IRQ);
	446	if (cfg & GSC_IRQ_STATUS_OR_IRQ)
	447	return GSC_IRQ_OVERRUN;
	448	else
	449	return GSC_IRQ_DONE;
	450
	451	}
	452
	453	static inline void gsc_hw_clear_irq(struct gsc_dev *dev, int irq)
	454	{
	455	u32 cfg = readl(dev->regs + GSC_IRQ);
	456	if (irq == GSC_IRQ_OVERRUN)
	457	cfg \|= GSC_IRQ_STATUS_OR_IRQ;
	458	else if (irq == GSC_IRQ_DONE)
	459	cfg \|= GSC_IRQ_STATUS_FRM_DONE_IRQ;
	460	writel(cfg, dev->regs + GSC_IRQ);
	461	}
	462
89069699 SK	463	static inline bool gsc_ctx_state_is_set(u32 mask, struct gsc_ctx *ctx)
	464	{
	465	unsigned long flags;
	466	bool ret;
	467
	468	spin_lock_irqsave(&ctx->gsc_dev->slock, flags);
	469	ret = (ctx->state & mask) == mask;
	470	spin_unlock_irqrestore(&ctx->gsc_dev->slock, flags);
	471	return ret;
	472	}
	473
	474	static inline struct gsc_frame ctx_get_frame(struct gsc_ctx ctx,
	475	enum v4l2_buf_type type)
	476	{
	477	struct gsc_frame *frame;
	478
	479	if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
	480	frame = &ctx->s_frame;
	481	} else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
	482	frame = &ctx->d_frame;
	483	} else {
	484	pr_err("Wrong buffer/video queue type (%d)", type);
	485	return ERR_PTR(-EINVAL);
	486	}
	487
	488	return frame;
	489	}
	490
	491	void gsc_hw_set_sw_reset(struct gsc_dev *dev);
	492	int gsc_wait_reset(struct gsc_dev *dev);
	493
	494	void gsc_hw_set_frm_done_irq_mask(struct gsc_dev *dev, bool mask);
	495	void gsc_hw_set_gsc_irq_enable(struct gsc_dev *dev, bool mask);
	496	void gsc_hw_set_input_buf_masking(struct gsc_dev *dev, u32 shift, bool enable);
	497	void gsc_hw_set_output_buf_masking(struct gsc_dev *dev, u32 shift, bool enable);
	498	void gsc_hw_set_input_addr(struct gsc_dev dev, struct gsc_addr addr,
	499	int index);
	500	void gsc_hw_set_output_addr(struct gsc_dev dev, struct gsc_addr addr,
	501	int index);
	502	void gsc_hw_set_input_path(struct gsc_ctx *ctx);
	503	void gsc_hw_set_in_size(struct gsc_ctx *ctx);
	504	void gsc_hw_set_in_image_rgb(struct gsc_ctx *ctx);
	505	void gsc_hw_set_in_image_format(struct gsc_ctx *ctx);
	506	void gsc_hw_set_output_path(struct gsc_ctx *ctx);
	507	void gsc_hw_set_out_size(struct gsc_ctx *ctx);
	508	void gsc_hw_set_out_image_rgb(struct gsc_ctx *ctx);
	509	void gsc_hw_set_out_image_format(struct gsc_ctx *ctx);
	510	void gsc_hw_set_prescaler(struct gsc_ctx *ctx);
	511	void gsc_hw_set_mainscaler(struct gsc_ctx *ctx);
	512	void gsc_hw_set_rotation(struct gsc_ctx *ctx);
	513	void gsc_hw_set_global_alpha(struct gsc_ctx *ctx);
	514	void gsc_hw_set_sfr_update(struct gsc_ctx *ctx);
	515
	516	#endif /* GSC_CORE_H_ */