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[thirdparty/kernel/stable.git] / drivers / media / platform / omap3isp / isp.c
CommitLineData
448de7e7
SA		 1/*
2 * isp.c
3 *
4 * TI OMAP3 ISP - Core
5 *
6 * Copyright (C) 2006-2010 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * Contributors:
13 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 * Sakari Ailus <sakari.ailus@iki.fi>
15 * David Cohen <dacohen@gmail.com>
16 * Stanimir Varbanov <svarbanov@mm-sol.com>
17 * Vimarsh Zutshi <vimarsh.zutshi@gmail.com>
18 * Tuukka Toivonen <tuukkat76@gmail.com>
19 * Sergio Aguirre <saaguirre@ti.com>
20 * Antti Koskipaa <akoskipa@gmail.com>
21 * Ivan T. Ivanov <iivanov@mm-sol.com>
22 * RaniSuneela <r-m@ti.com>
23 * Atanas Filipov <afilipov@mm-sol.com>
24 * Gjorgji Rosikopulos <grosikopulos@mm-sol.com>
25 * Hiroshi DOYU <hiroshi.doyu@nokia.com>
26 * Nayden Kanchev <nkanchev@mm-sol.com>
27 * Phil Carmody <ext-phil.2.carmody@nokia.com>
28 * Artem Bityutskiy <artem.bityutskiy@nokia.com>
29 * Dominic Curran <dcurran@ti.com>
30 * Ilkka Myllyperkio <ilkka.myllyperkio@sofica.fi>
31 * Pallavi Kulkarni <p-kulkarni@ti.com>
32 * Vaibhav Hiremath <hvaibhav@ti.com>
33 * Mohit Jalori <mjalori@ti.com>
34 * Sameer Venkatraman <sameerv@ti.com>
35 * Senthilvadivu Guruswamy <svadivu@ti.com>
36 * Thara Gopinath <thara@ti.com>
37 * Toni Leinonen <toni.leinonen@nokia.com>
38 * Troy Laramy <t-laramy@ti.com>
39 *
40 * This program is free software; you can redistribute it and/or modify
41 * it under the terms of the GNU General Public License version 2 as
42 * published by the Free Software Foundation.
448de7e7
SA		 43 */
44
45#include <asm/cacheflush.h>
46
47#include <linux/clk.h>
9b28ee3c 48#include <linux/clkdev.h>
448de7e7
SA		 49#include <linux/delay.h>
50#include <linux/device.h>
51#include <linux/dma-mapping.h>
52#include <linux/i2c.h>
53#include <linux/interrupt.h>
503596a1 54#include <linux/mfd/syscon.h>
448de7e7 55#include <linux/module.h>
c8d35c84 56#include <linux/omap-iommu.h>
448de7e7 57#include <linux/platform_device.h>
859969b3 58#include <linux/property.h>
448de7e7
SA		 59#include <linux/regulator/consumer.h>
60#include <linux/slab.h>
61#include <linux/sched.h>
62#include <linux/vmalloc.h>
63
2a0a5472
LP		 64#include <asm/dma-iommu.h>
65
448de7e7 66#include <media/v4l2-common.h>
859969b3 67#include <media/v4l2-fwnode.h>
448de7e7 68#include <media/v4l2-device.h>
506a47eb 69#include <media/v4l2-mc.h>
448de7e7
SA		 70
71#include "isp.h"
72#include "ispreg.h"
73#include "ispccdc.h"
74#include "isppreview.h"
75#include "ispresizer.h"
76#include "ispcsi2.h"
77#include "ispccp2.h"
78#include "isph3a.h"
79#include "isphist.h"
80
81static unsigned int autoidle;
82module_param(autoidle, int, 0444);
83MODULE_PARM_DESC(autoidle, "Enable OMAP3ISP AUTOIDLE support");
84
85static void isp_save_ctx(struct isp_device *isp);
86
87static void isp_restore_ctx(struct isp_device *isp);
88
89static const struct isp_res_mapping isp_res_maps[] = {
90 {
91 .isp_rev = ISP_REVISION_2_0,
8644cdf9
SA		 92 .offset = {
93 /* first MMIO area */
94 0x0000, /* base, len 0x0070 */
95 0x0400, /* ccp2, len 0x01f0 */
96 0x0600, /* ccdc, len 0x00a8 */
97 0x0a00, /* hist, len 0x0048 */
98 0x0c00, /* h3a, len 0x0060 */
99 0x0e00, /* preview, len 0x00a0 */
100 0x1000, /* resizer, len 0x00ac */
101 0x1200, /* sbl, len 0x00fc */
102 /* second MMIO area */
103 0x0000, /* csi2a, len 0x0170 */
104 0x0170, /* csiphy2, len 0x000c */
105 },
503596a1 106 .phy_type = ISP_PHY_TYPE_3430,
448de7e7
SA		 107 },
108 {
109 .isp_rev = ISP_REVISION_15_0,
8644cdf9
SA		 110 .offset = {
111 /* first MMIO area */
112 0x0000, /* base, len 0x0070 */
113 0x0400, /* ccp2, len 0x01f0 */
114 0x0600, /* ccdc, len 0x00a8 */
115 0x0a00, /* hist, len 0x0048 */
116 0x0c00, /* h3a, len 0x0060 */
117 0x0e00, /* preview, len 0x00a0 */
118 0x1000, /* resizer, len 0x00ac */
119 0x1200, /* sbl, len 0x00fc */
120 /* second MMIO area */
121 0x0000, /* csi2a, len 0x0170 (1st area) */
122 0x0170, /* csiphy2, len 0x000c */
123 0x01c0, /* csi2a, len 0x0040 (2nd area) */
124 0x0400, /* csi2c, len 0x0170 (1st area) */
125 0x0570, /* csiphy1, len 0x000c */
126 0x05c0, /* csi2c, len 0x0040 (2nd area) */
127 },
503596a1 128 .phy_type = ISP_PHY_TYPE_3630,
448de7e7
SA		 129 },
130};
131
132/* Structure for saving/restoring ISP module registers */
133static struct isp_reg isp_reg_list[] = {
134 {OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0},
135 {OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0},
136 {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0},
137 {0, ISP_TOK_TERM, 0}
138};
139
140/*
141 * omap3isp_flush - Post pending L3 bus writes by doing a register readback
142 * @isp: OMAP3 ISP device
143 *
144 * In order to force posting of pending writes, we need to write and
145 * readback the same register, in this case the revision register.
146 *
147 * See this link for reference:
148 * http://www.mail-archive.com/linux-omap@vger.kernel.org/msg08149.html
149 */
150void omap3isp_flush(struct isp_device *isp)
151{
152 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
153 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
154}
155
9b28ee3c
LP		 156/* -----------------------------------------------------------------------------
157 * XCLK
158 */
159
160#define to_isp_xclk(_hw) container_of(_hw, struct isp_xclk, hw)
161
162static void isp_xclk_update(struct isp_xclk *xclk, u32 divider)
163{
164 switch (xclk->id) {
165 case ISP_XCLK_A:
166 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
167 ISPTCTRL_CTRL_DIVA_MASK,
168 divider << ISPTCTRL_CTRL_DIVA_SHIFT);
169 break;
170 case ISP_XCLK_B:
171 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
172 ISPTCTRL_CTRL_DIVB_MASK,
173 divider << ISPTCTRL_CTRL_DIVB_SHIFT);
174 break;
175 }
176}
177
178static int isp_xclk_prepare(struct clk_hw *hw)
179{
180 struct isp_xclk *xclk = to_isp_xclk(hw);
181
182 omap3isp_get(xclk->isp);
183
184 return 0;
185}
186
187static void isp_xclk_unprepare(struct clk_hw *hw)
188{
189 struct isp_xclk *xclk = to_isp_xclk(hw);
190
191 omap3isp_put(xclk->isp);
192}
193
194static int isp_xclk_enable(struct clk_hw *hw)
195{
196 struct isp_xclk *xclk = to_isp_xclk(hw);
197 unsigned long flags;
198
199 spin_lock_irqsave(&xclk->lock, flags);
200 isp_xclk_update(xclk, xclk->divider);
201 xclk->enabled = true;
202 spin_unlock_irqrestore(&xclk->lock, flags);
203
204 return 0;
205}
206
207static void isp_xclk_disable(struct clk_hw *hw)
208{
209 struct isp_xclk *xclk = to_isp_xclk(hw);
210 unsigned long flags;
211
212 spin_lock_irqsave(&xclk->lock, flags);
213 isp_xclk_update(xclk, 0);
214 xclk->enabled = false;
215 spin_unlock_irqrestore(&xclk->lock, flags);
216}
217
218static unsigned long isp_xclk_recalc_rate(struct clk_hw *hw,
219 unsigned long parent_rate)
220{
221 struct isp_xclk *xclk = to_isp_xclk(hw);
222
223 return parent_rate / xclk->divider;
224}
225
226static u32 isp_xclk_calc_divider(unsigned long *rate, unsigned long parent_rate)
227{
228 u32 divider;
229
230 if (*rate >= parent_rate) {
231 *rate = parent_rate;
232 return ISPTCTRL_CTRL_DIV_BYPASS;
233 }
234
aadec012
LP		 235 if (*rate == 0)
236 *rate = 1;
237
9b28ee3c
LP		 238 divider = DIV_ROUND_CLOSEST(parent_rate, *rate);
239 if (divider >= ISPTCTRL_CTRL_DIV_BYPASS)
240 divider = ISPTCTRL_CTRL_DIV_BYPASS - 1;
241
242 *rate = parent_rate / divider;
243 return divider;
244}
245
246static long isp_xclk_round_rate(struct clk_hw *hw, unsigned long rate,
247 unsigned long *parent_rate)
248{
249 isp_xclk_calc_divider(&rate, *parent_rate);
250 return rate;
251}
252
253static int isp_xclk_set_rate(struct clk_hw *hw, unsigned long rate,
254 unsigned long parent_rate)
255{
256 struct isp_xclk *xclk = to_isp_xclk(hw);
257 unsigned long flags;
258 u32 divider;
259
260 divider = isp_xclk_calc_divider(&rate, parent_rate);
261
262 spin_lock_irqsave(&xclk->lock, flags);
263
264 xclk->divider = divider;
265 if (xclk->enabled)
266 isp_xclk_update(xclk, divider);
267
268 spin_unlock_irqrestore(&xclk->lock, flags);
269
270 dev_dbg(xclk->isp->dev, "%s: cam_xclk%c set to %lu Hz (div %u)\n",
271 __func__, xclk->id == ISP_XCLK_A ? 'a' : 'b', rate, divider);
272 return 0;
273}
274
275static const struct clk_ops isp_xclk_ops = {
276 .prepare = isp_xclk_prepare,
277 .unprepare = isp_xclk_unprepare,
278 .enable = isp_xclk_enable,
279 .disable = isp_xclk_disable,
280 .recalc_rate = isp_xclk_recalc_rate,
281 .round_rate = isp_xclk_round_rate,
282 .set_rate = isp_xclk_set_rate,
283};
284
285static const char *isp_xclk_parent_name = "cam_mclk";
286
64904b57
LP		 287static struct clk *isp_xclk_src_get(struct of_phandle_args *clkspec, void *data)
288{
289 unsigned int idx = clkspec->args[0];
290 struct isp_device *isp = data;
291
292 if (idx >= ARRAY_SIZE(isp->xclks))
293 return ERR_PTR(-ENOENT);
294
295 return isp->xclks[idx].clk;
296}
297
9b28ee3c
LP		 298static int isp_xclk_init(struct isp_device *isp)
299{
64904b57 300 struct device_node *np = isp->dev->of_node;
9b28ee3c
LP		 301 struct clk_init_data init;
302 unsigned int i;
303
f8e2ff26
SN		 304 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i)
305 isp->xclks[i].clk = ERR_PTR(-EINVAL);
306
9b28ee3c
LP		 307 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
308 struct isp_xclk *xclk = &isp->xclks[i];
9b28ee3c
LP		 309
310 xclk->isp = isp;
311 xclk->id = i == 0 ? ISP_XCLK_A : ISP_XCLK_B;
312 xclk->divider = 1;
313 spin_lock_init(&xclk->lock);
314
315 init.name = i == 0 ? "cam_xclka" : "cam_xclkb";
316 init.ops = &isp_xclk_ops;
317 init.parent_names = &isp_xclk_parent_name;
318 init.num_parents = 1;
319
320 xclk->hw.init = &init;
f8e2ff26
SN		 321 /*
322 * The first argument is NULL in order to avoid circular
323 * reference, as this driver takes reference on the
324 * sensor subdevice modules and the sensors would take
325 * reference on this module through clk_get().
326 */
327 xclk->clk = clk_register(NULL, &xclk->hw);
328 if (IS_ERR(xclk->clk))
329 return PTR_ERR(xclk->clk);
9b28ee3c
LP		 330 }
331
64904b57
LP		 332 if (np)
333 of_clk_add_provider(np, isp_xclk_src_get, isp);
334
9b28ee3c
LP		 335 return 0;
336}
337
338static void isp_xclk_cleanup(struct isp_device *isp)
339{
64904b57 340 struct device_node *np = isp->dev->of_node;
9b28ee3c
LP		 341 unsigned int i;
342
64904b57
LP		 343 if (np)
344 of_clk_del_provider(np);
345
9b28ee3c
LP		 346 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
347 struct isp_xclk *xclk = &isp->xclks[i];
348
f8e2ff26
SN		 349 if (!IS_ERR(xclk->clk))
350 clk_unregister(xclk->clk);
9b28ee3c
LP		 351 }
352}
353
354/* -----------------------------------------------------------------------------
355 * Interrupts
356 */
357
448de7e7
SA		 358/*
359 * isp_enable_interrupts - Enable ISP interrupts.
360 * @isp: OMAP3 ISP device
361 */
362static void isp_enable_interrupts(struct isp_device *isp)
363{
364 static const u32 irq = IRQ0ENABLE_CSIA_IRQ
365 | IRQ0ENABLE_CSIB_IRQ
366 | IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ
367 | IRQ0ENABLE_CCDC_LSC_DONE_IRQ
368 | IRQ0ENABLE_CCDC_VD0_IRQ
369 | IRQ0ENABLE_CCDC_VD1_IRQ
370 | IRQ0ENABLE_HS_VS_IRQ
371 | IRQ0ENABLE_HIST_DONE_IRQ
372 | IRQ0ENABLE_H3A_AWB_DONE_IRQ
373 | IRQ0ENABLE_H3A_AF_DONE_IRQ
374 | IRQ0ENABLE_PRV_DONE_IRQ
375 | IRQ0ENABLE_RSZ_DONE_IRQ;
376
377 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
378 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
379}
380
381/*
382 * isp_disable_interrupts - Disable ISP interrupts.
383 * @isp: OMAP3 ISP device
384 */
385static void isp_disable_interrupts(struct isp_device *isp)
386{
387 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
388}
389
448de7e7 390/*
96d62ae2 391 * isp_core_init - ISP core settings
448de7e7
SA		 392 * @isp: OMAP3 ISP device
393 * @idle: Consider idle state.
394 *
25aeb418 395 * Set the power settings for the ISP and SBL bus and configure the HS/VS
96d62ae2
LP		 396 * interrupt source.
397 *
398 * We need to configure the HS/VS interrupt source before interrupts get
399 * enabled, as the sensor might be free-running and the ISP default setting
400 * (HS edge) would put an unnecessary burden on the CPU.
448de7e7 401 */
96d62ae2 402static void isp_core_init(struct isp_device *isp, int idle)
448de7e7
SA		 403{
404 isp_reg_writel(isp,
405 ((idle ? ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY :
406 ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY) <<
407 ISP_SYSCONFIG_MIDLEMODE_SHIFT) |
408 ((isp->revision == ISP_REVISION_15_0) ?
409 ISP_SYSCONFIG_AUTOIDLE : 0),
410 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
411
96d62ae2
LP		 412 isp_reg_writel(isp,
413 (isp->autoidle ? ISPCTRL_SBL_AUTOIDLE : 0) |
414 ISPCTRL_SYNC_DETECT_VSRISE,
415 OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
448de7e7
SA		 416}
417
418/*
419 * Configure the bridge and lane shifter. Valid inputs are
420 *
421 * CCDC_INPUT_PARALLEL: Parallel interface
422 * CCDC_INPUT_CSI2A: CSI2a receiver
423 * CCDC_INPUT_CCP2B: CCP2b receiver
424 * CCDC_INPUT_CSI2C: CSI2c receiver
425 *
426 * The bridge and lane shifter are configured according to the selected input
427 * and the ISP platform data.
428 */
429void omap3isp_configure_bridge(struct isp_device *isp,
430 enum ccdc_input_entity input,
68908747 431 const struct isp_parallel_cfg *parcfg,
c51364ca 432 unsigned int shift, unsigned int bridge)
448de7e7
SA		 433{
434 u32 ispctrl_val;
435
436 ispctrl_val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
437 ispctrl_val &= ~ISPCTRL_SHIFT_MASK;
438 ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
439 ispctrl_val &= ~ISPCTRL_PAR_SER_CLK_SEL_MASK;
440 ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_MASK;
c51364ca 441 ispctrl_val |= bridge;
448de7e7
SA		 442
443 switch (input) {
444 case CCDC_INPUT_PARALLEL:
445 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
68908747 446 ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
74d1e7c0 447 shift += parcfg->data_lane_shift;
448de7e7
SA		 448 break;
449
450 case CCDC_INPUT_CSI2A:
451 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA;
452 break;
453
454 case CCDC_INPUT_CCP2B:
455 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB;
456 break;
457
458 case CCDC_INPUT_CSI2C:
459 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIC;
460 break;
461
462 default:
463 return;
464 }
465
c09af044
MJ		 466 ispctrl_val |= ((shift/2) << ISPCTRL_SHIFT_SHIFT) & ISPCTRL_SHIFT_MASK;
467
448de7e7
SA		 468 isp_reg_writel(isp, ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
469}
470
448de7e7
SA		 471void omap3isp_hist_dma_done(struct isp_device *isp)
472{
473 if (omap3isp_ccdc_busy(&isp->isp_ccdc) ||
474 omap3isp_stat_pcr_busy(&isp->isp_hist)) {
475 /* Histogram cannot be enabled in this frame anymore */
476 atomic_set(&isp->isp_hist.buf_err, 1);
d26da990
MCC		 477 dev_dbg(isp->dev,
478 "hist: Out of synchronization with CCDC. Ignoring next buffer.\n");
448de7e7
SA		 479 }
480}
481
482static inline void isp_isr_dbg(struct isp_device *isp, u32 irqstatus)
483{
484 static const char *name[] = {
485 "CSIA_IRQ",
486 "res1",
487 "res2",
488 "CSIB_LCM_IRQ",
489 "CSIB_IRQ",
490 "res5",
491 "res6",
492 "res7",
493 "CCDC_VD0_IRQ",
494 "CCDC_VD1_IRQ",
495 "CCDC_VD2_IRQ",
496 "CCDC_ERR_IRQ",
497 "H3A_AF_DONE_IRQ",
498 "H3A_AWB_DONE_IRQ",
499 "res14",
500 "res15",
501 "HIST_DONE_IRQ",
502 "CCDC_LSC_DONE",
503 "CCDC_LSC_PREFETCH_COMPLETED",
504 "CCDC_LSC_PREFETCH_ERROR",
505 "PRV_DONE_IRQ",
506 "CBUFF_IRQ",
507 "res22",
508 "res23",
509 "RSZ_DONE_IRQ",
510 "OVF_IRQ",
511 "res26",
512 "res27",
513 "MMU_ERR_IRQ",
514 "OCP_ERR_IRQ",
515 "SEC_ERR_IRQ",
516 "HS_VS_IRQ",
517 };
518 int i;
519
6c20c635 520 dev_dbg(isp->dev, "ISP IRQ: ");
448de7e7
SA		 521
522 for (i = 0; i < ARRAY_SIZE(name); i++) {
523 if ((1 << i) & irqstatus)
524 printk(KERN_CONT "%s ", name[i]);
525 }
526 printk(KERN_CONT "\n");
527}
528
529static void isp_isr_sbl(struct isp_device *isp)
530{
531 struct device *dev = isp->dev;
875e2e3e 532 struct isp_pipeline *pipe;
448de7e7
SA		 533 u32 sbl_pcr;
534
535 /*
536 * Handle shared buffer logic overflows for video buffers.
537 * ISPSBL_PCR_CCDCPRV_2_RSZ_OVF can be safely ignored.
538 */
539 sbl_pcr = isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
540 isp_reg_writel(isp, sbl_pcr, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
541 sbl_pcr &= ~ISPSBL_PCR_CCDCPRV_2_RSZ_OVF;
542
543 if (sbl_pcr)
544 dev_dbg(dev, "SBL overflow (PCR = 0x%08x)\n", sbl_pcr);
545
875e2e3e
LP		 546 if (sbl_pcr & ISPSBL_PCR_CSIB_WBL_OVF) {
547 pipe = to_isp_pipeline(&isp->isp_ccp2.subdev.entity);
548 if (pipe != NULL)
549 pipe->error = true;
550 }
551
552 if (sbl_pcr & ISPSBL_PCR_CSIA_WBL_OVF) {
553 pipe = to_isp_pipeline(&isp->isp_csi2a.subdev.entity);
554 if (pipe != NULL)
555 pipe->error = true;
556 }
557
558 if (sbl_pcr & ISPSBL_PCR_CCDC_WBL_OVF) {
559 pipe = to_isp_pipeline(&isp->isp_ccdc.subdev.entity);
560 if (pipe != NULL)
561 pipe->error = true;
448de7e7
SA		 562 }
563
564 if (sbl_pcr & ISPSBL_PCR_PRV_WBL_OVF) {
875e2e3e
LP		 565 pipe = to_isp_pipeline(&isp->isp_prev.subdev.entity);
566 if (pipe != NULL)
567 pipe->error = true;
448de7e7
SA		 568 }
569
570 if (sbl_pcr & (ISPSBL_PCR_RSZ1_WBL_OVF
571 | ISPSBL_PCR_RSZ2_WBL_OVF
572 | ISPSBL_PCR_RSZ3_WBL_OVF
875e2e3e
LP		 573 | ISPSBL_PCR_RSZ4_WBL_OVF)) {
574 pipe = to_isp_pipeline(&isp->isp_res.subdev.entity);
575 if (pipe != NULL)
576 pipe->error = true;
577 }
448de7e7
SA		 578
579 if (sbl_pcr & ISPSBL_PCR_H3A_AF_WBL_OVF)
580 omap3isp_stat_sbl_overflow(&isp->isp_af);
581
582 if (sbl_pcr & ISPSBL_PCR_H3A_AEAWB_WBL_OVF)
583 omap3isp_stat_sbl_overflow(&isp->isp_aewb);
584}
585
586/*
587 * isp_isr - Interrupt Service Routine for Camera ISP module.
588 * @irq: Not used currently.
589 * @_isp: Pointer to the OMAP3 ISP device
590 *
591 * Handles the corresponding callback if plugged in.
448de7e7
SA		 592 */
593static irqreturn_t isp_isr(int irq, void *_isp)
594{
595 static const u32 ccdc_events = IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ |
596 IRQ0STATUS_CCDC_LSC_DONE_IRQ |
597 IRQ0STATUS_CCDC_VD0_IRQ |
598 IRQ0STATUS_CCDC_VD1_IRQ |
599 IRQ0STATUS_HS_VS_IRQ;
600 struct isp_device *isp = _isp;
601 u32 irqstatus;
448de7e7
SA		 602
603 irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
604 isp_reg_writel(isp, irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
605
606 isp_isr_sbl(isp);
607
875e2e3e
LP		 608 if (irqstatus & IRQ0STATUS_CSIA_IRQ)
609 omap3isp_csi2_isr(&isp->isp_csi2a);
448de7e7 610
875e2e3e
LP		 611 if (irqstatus & IRQ0STATUS_CSIB_IRQ)
612 omap3isp_ccp2_isr(&isp->isp_ccp2);
448de7e7
SA		 613
614 if (irqstatus & IRQ0STATUS_CCDC_VD0_IRQ) {
615 if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW)
616 omap3isp_preview_isr_frame_sync(&isp->isp_prev);
617 if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER)
618 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
619 omap3isp_stat_isr_frame_sync(&isp->isp_aewb);
620 omap3isp_stat_isr_frame_sync(&isp->isp_af);
621 omap3isp_stat_isr_frame_sync(&isp->isp_hist);
622 }
623
624 if (irqstatus & ccdc_events)
625 omap3isp_ccdc_isr(&isp->isp_ccdc, irqstatus & ccdc_events);
626
627 if (irqstatus & IRQ0STATUS_PRV_DONE_IRQ) {
628 if (isp->isp_prev.output & PREVIEW_OUTPUT_RESIZER)
629 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
630 omap3isp_preview_isr(&isp->isp_prev);
631 }
632
633 if (irqstatus & IRQ0STATUS_RSZ_DONE_IRQ)
634 omap3isp_resizer_isr(&isp->isp_res);
635
636 if (irqstatus & IRQ0STATUS_H3A_AWB_DONE_IRQ)
637 omap3isp_stat_isr(&isp->isp_aewb);
638
639 if (irqstatus & IRQ0STATUS_H3A_AF_DONE_IRQ)
640 omap3isp_stat_isr(&isp->isp_af);
641
642 if (irqstatus & IRQ0STATUS_HIST_DONE_IRQ)
643 omap3isp_stat_isr(&isp->isp_hist);
644
645 omap3isp_flush(isp);
646
647#if defined(DEBUG) && defined(ISP_ISR_DEBUG)
648 isp_isr_dbg(isp, irqstatus);
649#endif
650
651 return IRQ_HANDLED;
652}
653
68429f50
LP		 654static const struct media_device_ops isp_media_ops = {
655 .link_notify = v4l2_pipeline_link_notify,
656};
657
448de7e7
SA		 658/* -----------------------------------------------------------------------------
659 * Pipeline stream management
660 */
661
662/*
663 * isp_pipeline_enable - Enable streaming on a pipeline
664 * @pipe: ISP pipeline
665 * @mode: Stream mode (single shot or continuous)
666 *
667 * Walk the entities chain starting at the pipeline output video node and start
668 * all modules in the chain in the given mode.
669 *
25985edc 670 * Return 0 if successful, or the return value of the failed video::s_stream
448de7e7
SA		 671 * operation otherwise.
672 */
673static int isp_pipeline_enable(struct isp_pipeline *pipe,
674 enum isp_pipeline_stream_state mode)
675{
676 struct isp_device *isp = pipe->output->isp;
677 struct media_entity *entity;
678 struct media_pad *pad;
679 struct v4l2_subdev *subdev;
680 unsigned long flags;
c62e2a19 681 int ret;
448de7e7 682
112eee0c
LP		 683 /* Refuse to start streaming if an entity included in the pipeline has
684 * crashed. This check must be performed before the loop below to avoid
685 * starting entities if the pipeline won't start anyway (those entities
686 * would then likely fail to stop, making the problem worse).
1567bb7d 687 */
17d3d405 688 if (media_entity_enum_intersects(&pipe->ent_enum, &isp->crashed))
1567bb7d
LP		 689 return -EIO;
690
448de7e7
SA		 691 spin_lock_irqsave(&pipe->lock, flags);
692 pipe->state &= ~(ISP_PIPELINE_IDLE_INPUT | ISP_PIPELINE_IDLE_OUTPUT);
693 spin_unlock_irqrestore(&pipe->lock, flags);
694
695 pipe->do_propagation = false;
696
697 entity = &pipe->output->video.entity;
698 while (1) {
699 pad = &entity->pads[0];
700 if (!(pad->flags & MEDIA_PAD_FL_SINK))
701 break;
702
1bddf1b3 703 pad = media_entity_remote_pad(pad);
3efdf62c 704 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
448de7e7
SA		 705 break;
706
707 entity = pad->entity;
708 subdev = media_entity_to_v4l2_subdev(entity);
709
710 ret = v4l2_subdev_call(subdev, video, s_stream, mode);
711 if (ret < 0 && ret != -ENOIOCTLCMD)
c62e2a19 712 return ret;
448de7e7
SA		 713
714 if (subdev == &isp->isp_ccdc.subdev) {
715 v4l2_subdev_call(&isp->isp_aewb.subdev, video,
716 s_stream, mode);
717 v4l2_subdev_call(&isp->isp_af.subdev, video,
718 s_stream, mode);
719 v4l2_subdev_call(&isp->isp_hist.subdev, video,
720 s_stream, mode);
721 pipe->do_propagation = true;
722 }
723 }
724
c62e2a19 725 return 0;
448de7e7
SA		 726}
727
728static int isp_pipeline_wait_resizer(struct isp_device *isp)
729{
730 return omap3isp_resizer_busy(&isp->isp_res);
731}
732
733static int isp_pipeline_wait_preview(struct isp_device *isp)
734{
735 return omap3isp_preview_busy(&isp->isp_prev);
736}
737
738static int isp_pipeline_wait_ccdc(struct isp_device *isp)
739{
740 return omap3isp_stat_busy(&isp->isp_af)
741 || omap3isp_stat_busy(&isp->isp_aewb)
742 || omap3isp_stat_busy(&isp->isp_hist)
743 || omap3isp_ccdc_busy(&isp->isp_ccdc);
744}
745
746#define ISP_STOP_TIMEOUT msecs_to_jiffies(1000)
747
748static int isp_pipeline_wait(struct isp_device *isp,
749 int(*busy)(struct isp_device *isp))
750{
751 unsigned long timeout = jiffies + ISP_STOP_TIMEOUT;
752
753 while (!time_after(jiffies, timeout)) {
754 if (!busy(isp))
755 return 0;
756 }
757
758 return 1;
759}
760
761/*
762 * isp_pipeline_disable - Disable streaming on a pipeline
763 * @pipe: ISP pipeline
764 *
765 * Walk the entities chain starting at the pipeline output video node and stop
766 * all modules in the chain. Wait synchronously for the modules to be stopped if
767 * necessary.
768 *
769 * Return 0 if all modules have been properly stopped, or -ETIMEDOUT if a module
770 * can't be stopped (in which case a software reset of the ISP is probably
771 * necessary).
772 */
773static int isp_pipeline_disable(struct isp_pipeline *pipe)
774{
775 struct isp_device *isp = pipe->output->isp;
776 struct media_entity *entity;
777 struct media_pad *pad;
778 struct v4l2_subdev *subdev;
779 int failure = 0;
780 int ret;
781
782 /*
783 * We need to stop all the modules after CCDC first or they'll
784 * never stop since they may not get a full frame from CCDC.
785 */
786 entity = &pipe->output->video.entity;
787 while (1) {
788 pad = &entity->pads[0];
789 if (!(pad->flags & MEDIA_PAD_FL_SINK))
790 break;
791
1bddf1b3 792 pad = media_entity_remote_pad(pad);
3efdf62c 793 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
448de7e7
SA		 794 break;
795
796 entity = pad->entity;
797 subdev = media_entity_to_v4l2_subdev(entity);
798
799 if (subdev == &isp->isp_ccdc.subdev) {
800 v4l2_subdev_call(&isp->isp_aewb.subdev,
801 video, s_stream, 0);
802 v4l2_subdev_call(&isp->isp_af.subdev,
803 video, s_stream, 0);
804 v4l2_subdev_call(&isp->isp_hist.subdev,
805 video, s_stream, 0);
806 }
807
eb228e89 808 ret = v4l2_subdev_call(subdev, video, s_stream, 0);
448de7e7
SA		 809
810 if (subdev == &isp->isp_res.subdev)
eb228e89 811 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_resizer);
448de7e7 812 else if (subdev == &isp->isp_prev.subdev)
eb228e89 813 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_preview);
448de7e7 814 else if (subdev == &isp->isp_ccdc.subdev)
eb228e89 815 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_ccdc);
448de7e7 816
112eee0c
LP		 817 /* Handle stop failures. An entity that fails to stop can
818 * usually just be restarted. Flag the stop failure nonetheless
819 * to trigger an ISP reset the next time the device is released,
820 * just in case.
821 *
822 * The preview engine is a special case. A failure to stop can
823 * mean a hardware crash. When that happens the preview engine
824 * won't respond to read/write operations on the L4 bus anymore,
825 * resulting in a bus fault and a kernel oops next time it gets
826 * accessed. Mark it as crashed to prevent pipelines including
827 * it from being started.
828 */
448de7e7
SA		 829 if (ret) {
830 dev_info(isp->dev, "Unable to stop %s\n", subdev->name);
112eee0c 831 isp->stop_failure = true;
17d3d405
SA		 832 if (subdev == &isp->isp_prev.subdev)
833 media_entity_enum_set(&isp->crashed,
834 &subdev->entity);
448de7e7
SA		 835 failure = -ETIMEDOUT;
836 }
837 }
838
839 return failure;
840}
841
842/*
843 * omap3isp_pipeline_set_stream - Enable/disable streaming on a pipeline
844 * @pipe: ISP pipeline
845 * @state: Stream state (stopped, single shot or continuous)
846 *
847 * Set the pipeline to the given stream state. Pipelines can be started in
848 * single-shot or continuous mode.
849 *
25985edc 850 * Return 0 if successful, or the return value of the failed video::s_stream
994d5375
LP		 851 * operation otherwise. The pipeline state is not updated when the operation
852 * fails, except when stopping the pipeline.
448de7e7
SA		 853 */
854int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
855 enum isp_pipeline_stream_state state)
856{
857 int ret;
858
859 if (state == ISP_PIPELINE_STREAM_STOPPED)
860 ret = isp_pipeline_disable(pipe);
861 else
862 ret = isp_pipeline_enable(pipe, state);
994d5375
LP		 863
864 if (ret == 0 || state == ISP_PIPELINE_STREAM_STOPPED)
865 pipe->stream_state = state;
448de7e7
SA		 866
867 return ret;
868}
869
661112cb
LP		 870/*
871 * omap3isp_pipeline_cancel_stream - Cancel stream on a pipeline
872 * @pipe: ISP pipeline
873 *
874 * Cancelling a stream mark all buffers on all video nodes in the pipeline as
875 * erroneous and makes sure no new buffer can be queued. This function is called
876 * when a fatal error that prevents any further operation on the pipeline
877 * occurs.
878 */
879void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe)
880{
881 if (pipe->input)
882 omap3isp_video_cancel_stream(pipe->input);
883 if (pipe->output)
884 omap3isp_video_cancel_stream(pipe->output);
885}
886
448de7e7
SA		 887/*
888 * isp_pipeline_resume - Resume streaming on a pipeline
889 * @pipe: ISP pipeline
890 *
891 * Resume video output and input and re-enable pipeline.
892 */
893static void isp_pipeline_resume(struct isp_pipeline *pipe)
894{
895 int singleshot = pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT;
896
897 omap3isp_video_resume(pipe->output, !singleshot);
898 if (singleshot)
899 omap3isp_video_resume(pipe->input, 0);
900 isp_pipeline_enable(pipe, pipe->stream_state);
901}
902
903/*
904 * isp_pipeline_suspend - Suspend streaming on a pipeline
905 * @pipe: ISP pipeline
906 *
907 * Suspend pipeline.
908 */
909static void isp_pipeline_suspend(struct isp_pipeline *pipe)
910{
911 isp_pipeline_disable(pipe);
912}
913
914/*
915 * isp_pipeline_is_last - Verify if entity has an enabled link to the output
4a3fad70 916 * video node
448de7e7
SA		 917 * @me: ISP module's media entity
918 *
919 * Returns 1 if the entity has an enabled link to the output video node or 0
920 * otherwise. It's true only while pipeline can have no more than one output
921 * node.
922 */
923static int isp_pipeline_is_last(struct media_entity *me)
924{
925 struct isp_pipeline *pipe;
926 struct media_pad *pad;
927
928 if (!me->pipe)
929 return 0;
930 pipe = to_isp_pipeline(me);
931 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED)
932 return 0;
1bddf1b3 933 pad = media_entity_remote_pad(&pipe->output->pad);
448de7e7
SA		 934 return pad->entity == me;
935}
936
937/*
938 * isp_suspend_module_pipeline - Suspend pipeline to which belongs the module
939 * @me: ISP module's media entity
940 *
941 * Suspend the whole pipeline if module's entity has an enabled link to the
942 * output video node. It works only while pipeline can have no more than one
943 * output node.
944 */
945static void isp_suspend_module_pipeline(struct media_entity *me)
946{
947 if (isp_pipeline_is_last(me))
948 isp_pipeline_suspend(to_isp_pipeline(me));
949}
950
951/*
952 * isp_resume_module_pipeline - Resume pipeline to which belongs the module
953 * @me: ISP module's media entity
954 *
955 * Resume the whole pipeline if module's entity has an enabled link to the
956 * output video node. It works only while pipeline can have no more than one
957 * output node.
958 */
959static void isp_resume_module_pipeline(struct media_entity *me)
960{
961 if (isp_pipeline_is_last(me))
962 isp_pipeline_resume(to_isp_pipeline(me));
963}
964
965/*
966 * isp_suspend_modules - Suspend ISP submodules.
967 * @isp: OMAP3 ISP device
968 *
969 * Returns 0 if suspend left in idle state all the submodules properly,
970 * or returns 1 if a general Reset is required to suspend the submodules.
971 */
972static int isp_suspend_modules(struct isp_device *isp)
973{
974 unsigned long timeout;
975
976 omap3isp_stat_suspend(&isp->isp_aewb);
977 omap3isp_stat_suspend(&isp->isp_af);
978 omap3isp_stat_suspend(&isp->isp_hist);
979 isp_suspend_module_pipeline(&isp->isp_res.subdev.entity);
980 isp_suspend_module_pipeline(&isp->isp_prev.subdev.entity);
981 isp_suspend_module_pipeline(&isp->isp_ccdc.subdev.entity);
982 isp_suspend_module_pipeline(&isp->isp_csi2a.subdev.entity);
983 isp_suspend_module_pipeline(&isp->isp_ccp2.subdev.entity);
984
985 timeout = jiffies + ISP_STOP_TIMEOUT;
986 while (omap3isp_stat_busy(&isp->isp_af)
987 || omap3isp_stat_busy(&isp->isp_aewb)
988 || omap3isp_stat_busy(&isp->isp_hist)
989 || omap3isp_preview_busy(&isp->isp_prev)
990 || omap3isp_resizer_busy(&isp->isp_res)
991 || omap3isp_ccdc_busy(&isp->isp_ccdc)) {
992 if (time_after(jiffies, timeout)) {
993 dev_info(isp->dev, "can't stop modules.\n");
994 return 1;
995 }
996 msleep(1);
997 }
998
999 return 0;
1000}
1001
1002/*
1003 * isp_resume_modules - Resume ISP submodules.
1004 * @isp: OMAP3 ISP device
1005 */
1006static void isp_resume_modules(struct isp_device *isp)
1007{
1008 omap3isp_stat_resume(&isp->isp_aewb);
1009 omap3isp_stat_resume(&isp->isp_af);
1010 omap3isp_stat_resume(&isp->isp_hist);
1011 isp_resume_module_pipeline(&isp->isp_res.subdev.entity);
1012 isp_resume_module_pipeline(&isp->isp_prev.subdev.entity);
1013 isp_resume_module_pipeline(&isp->isp_ccdc.subdev.entity);
1014 isp_resume_module_pipeline(&isp->isp_csi2a.subdev.entity);
1015 isp_resume_module_pipeline(&isp->isp_ccp2.subdev.entity);
1016}
1017
1018/*
1019 * isp_reset - Reset ISP with a timeout wait for idle.
1020 * @isp: OMAP3 ISP device
1021 */
1022static int isp_reset(struct isp_device *isp)
1023{
1024 unsigned long timeout = 0;
1025
1026 isp_reg_writel(isp,
1027 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG)
1028 | ISP_SYSCONFIG_SOFTRESET,
1029 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
1030 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN,
1031 ISP_SYSSTATUS) & 0x1)) {
1032 if (timeout++ > 10000) {
1033 dev_alert(isp->dev, "cannot reset ISP\n");
1034 return -ETIMEDOUT;
1035 }
1036 udelay(1);
1037 }
1038
112eee0c 1039 isp->stop_failure = false;
17d3d405 1040 media_entity_enum_zero(&isp->crashed);
448de7e7
SA		 1041 return 0;
1042}
1043
1044/*
1045 * isp_save_context - Saves the values of the ISP module registers.
1046 * @isp: OMAP3 ISP device
1047 * @reg_list: Structure containing pairs of register address and value to
1048 * modify on OMAP.
1049 */
1050static void
1051isp_save_context(struct isp_device *isp, struct isp_reg *reg_list)
1052{
1053 struct isp_reg *next = reg_list;
1054
1055 for (; next->reg != ISP_TOK_TERM; next++)
1056 next->val = isp_reg_readl(isp, next->mmio_range, next->reg);
1057}
1058
1059/*
1060 * isp_restore_context - Restores the values of the ISP module registers.
1061 * @isp: OMAP3 ISP device
1062 * @reg_list: Structure containing pairs of register address and value to
1063 * modify on OMAP.
1064 */
1065static void
1066isp_restore_context(struct isp_device *isp, struct isp_reg *reg_list)
1067{
1068 struct isp_reg *next = reg_list;
1069
1070 for (; next->reg != ISP_TOK_TERM; next++)
1071 isp_reg_writel(isp, next->val, next->mmio_range, next->reg);
1072}
1073
1074/*
1075 * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1076 * @isp: OMAP3 ISP device
1077 *
1078 * Routine for saving the context of each module in the ISP.
1079 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1080 */
1081static void isp_save_ctx(struct isp_device *isp)
1082{
1083 isp_save_context(isp, isp_reg_list);
fabdbca8 1084 omap_iommu_save_ctx(isp->dev);
448de7e7
SA		 1085}
1086
1087/*
1088 * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1089 * @isp: OMAP3 ISP device
1090 *
1091 * Routine for restoring the context of each module in the ISP.
1092 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1093 */
1094static void isp_restore_ctx(struct isp_device *isp)
1095{
1096 isp_restore_context(isp, isp_reg_list);
fabdbca8 1097 omap_iommu_restore_ctx(isp->dev);
448de7e7
SA		 1098 omap3isp_ccdc_restore_context(isp);
1099 omap3isp_preview_restore_context(isp);
1100}
1101
1102/* -----------------------------------------------------------------------------
1103 * SBL resources management
1104 */
1105#define OMAP3_ISP_SBL_READ (OMAP3_ISP_SBL_CSI1_READ | \
1106 OMAP3_ISP_SBL_CCDC_LSC_READ | \
1107 OMAP3_ISP_SBL_PREVIEW_READ | \
1108 OMAP3_ISP_SBL_RESIZER_READ)
1109#define OMAP3_ISP_SBL_WRITE (OMAP3_ISP_SBL_CSI1_WRITE | \
1110 OMAP3_ISP_SBL_CSI2A_WRITE | \
1111 OMAP3_ISP_SBL_CSI2C_WRITE | \
1112 OMAP3_ISP_SBL_CCDC_WRITE | \
1113 OMAP3_ISP_SBL_PREVIEW_WRITE)
1114
1115void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res)
1116{
1117 u32 sbl = 0;
1118
1119 isp->sbl_resources |= res;
1120
1121 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ)
1122 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1123
1124 if (isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ)
1125 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1126
1127 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE)
1128 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1129
1130 if (isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE)
1131 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1132
1133 if (isp->sbl_resources & OMAP3_ISP_SBL_WRITE)
1134 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1135
1136 if (isp->sbl_resources & OMAP3_ISP_SBL_READ)
1137 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1138
1139 isp_reg_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1140}
1141
1142void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res)
1143{
1144 u32 sbl = 0;
1145
1146 isp->sbl_resources &= ~res;
1147
1148 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ))
1149 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1150
1151 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ))
1152 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1153
1154 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE))
1155 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1156
1157 if (!(isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE))
1158 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1159
1160 if (!(isp->sbl_resources & OMAP3_ISP_SBL_WRITE))
1161 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1162
1163 if (!(isp->sbl_resources & OMAP3_ISP_SBL_READ))
1164 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1165
1166 isp_reg_clr(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1167}
1168
1169/*
1170 * isp_module_sync_idle - Helper to sync module with its idle state
1171 * @me: ISP submodule's media entity
1172 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1173 * @stopping: flag which tells module wants to stop
1174 *
1175 * This function checks if ISP submodule needs to wait for next interrupt. If
1176 * yes, makes the caller to sleep while waiting for such event.
1177 */
1178int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
1179 atomic_t *stopping)
1180{
1181 struct isp_pipeline *pipe = to_isp_pipeline(me);
1182
1183 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED ||
1184 (pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1185 !isp_pipeline_ready(pipe)))
1186 return 0;
1187
1188 /*
1189 * atomic_set() doesn't include memory barrier on ARM platform for SMP
1190 * scenario. We'll call it here to avoid race conditions.
1191 */
1192 atomic_set(stopping, 1);
1193 smp_mb();
1194
1195 /*
1196 * If module is the last one, it's writing to memory. In this case,
1197 * it's necessary to check if the module is already paused due to
1198 * DMA queue underrun or if it has to wait for next interrupt to be
1199 * idle.
1200 * If it isn't the last one, the function won't sleep but *stopping
1201 * will still be set to warn next submodule caller's interrupt the
1202 * module wants to be idle.
1203 */
1204 if (isp_pipeline_is_last(me)) {
1205 struct isp_video *video = pipe->output;
1206 unsigned long flags;
e8feb876 1207 spin_lock_irqsave(&video->irqlock, flags);
448de7e7 1208 if (video->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
e8feb876 1209 spin_unlock_irqrestore(&video->irqlock, flags);
448de7e7
SA		 1210 atomic_set(stopping, 0);
1211 smp_mb();
1212 return 0;
1213 }
e8feb876 1214 spin_unlock_irqrestore(&video->irqlock, flags);
448de7e7
SA		 1215 if (!wait_event_timeout(*wait, !atomic_read(stopping),
1216 msecs_to_jiffies(1000))) {
1217 atomic_set(stopping, 0);
1218 smp_mb();
1219 return -ETIMEDOUT;
1220 }
1221 }
1222
1223 return 0;
1224}
1225
1226/*
1e9c4d49 1227 * omap3isp_module_sync_is_stopping - Helper to verify if module was stopping
448de7e7
SA		 1228 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1229 * @stopping: flag which tells module wants to stop
1230 *
1231 * This function checks if ISP submodule was stopping. In case of yes, it
1232 * notices the caller by setting stopping to 0 and waking up the wait queue.
1233 * Returns 1 if it was stopping or 0 otherwise.
1234 */
1235int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
1236 atomic_t *stopping)
1237{
1238 if (atomic_cmpxchg(stopping, 1, 0)) {
1239 wake_up(wait);
1240 return 1;
1241 }
1242
1243 return 0;
1244}
1245
1246/* --------------------------------------------------------------------------
1247 * Clock management
1248 */
1249
1250#define ISPCTRL_CLKS_MASK (ISPCTRL_H3A_CLK_EN | \
1251 ISPCTRL_HIST_CLK_EN | \
1252 ISPCTRL_RSZ_CLK_EN | \
1253 (ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN) | \
1254 (ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN))
1255
1256static void __isp_subclk_update(struct isp_device *isp)
1257{
1258 u32 clk = 0;
1259
be9a1b98
LP		 1260 /* AEWB and AF share the same clock. */
1261 if (isp->subclk_resources &
1262 (OMAP3_ISP_SUBCLK_AEWB | OMAP3_ISP_SUBCLK_AF))
448de7e7
SA		 1263 clk |= ISPCTRL_H3A_CLK_EN;
1264
1265 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_HIST)
1266 clk |= ISPCTRL_HIST_CLK_EN;
1267
1268 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_RESIZER)
1269 clk |= ISPCTRL_RSZ_CLK_EN;
1270
1271 /* NOTE: For CCDC & Preview submodules, we need to affect internal
25985edc 1272 * RAM as well.
448de7e7
SA		 1273 */
1274 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_CCDC)
1275 clk |= ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN;
1276
1277 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_PREVIEW)
1278 clk |= ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN;
1279
1280 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
1281 ISPCTRL_CLKS_MASK, clk);
1282}
1283
1284void omap3isp_subclk_enable(struct isp_device *isp,
1285 enum isp_subclk_resource res)
1286{
1287 isp->subclk_resources |= res;
1288
1289 __isp_subclk_update(isp);
1290}
1291
1292void omap3isp_subclk_disable(struct isp_device *isp,
1293 enum isp_subclk_resource res)
1294{
1295 isp->subclk_resources &= ~res;
1296
1297 __isp_subclk_update(isp);
1298}
1299
1300/*
1301 * isp_enable_clocks - Enable ISP clocks
1302 * @isp: OMAP3 ISP device
1303 *
b057c3c3
LP		 1304 * Return 0 if successful, or clk_prepare_enable return value if any of them
1305 * fails.
448de7e7
SA		 1306 */
1307static int isp_enable_clocks(struct isp_device *isp)
1308{
1309 int r;
1310 unsigned long rate;
448de7e7 1311
b057c3c3 1312 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]);
448de7e7 1313 if (r) {
b057c3c3 1314 dev_err(isp->dev, "failed to enable cam_ick clock\n");
448de7e7
SA		 1315 goto out_clk_enable_ick;
1316 }
6d1aa02f 1317 r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ);
448de7e7 1318 if (r) {
6d1aa02f 1319 dev_err(isp->dev, "clk_set_rate for cam_mclk failed\n");
448de7e7
SA		 1320 goto out_clk_enable_mclk;
1321 }
b057c3c3 1322 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
448de7e7 1323 if (r) {
b057c3c3 1324 dev_err(isp->dev, "failed to enable cam_mclk clock\n");
448de7e7
SA		 1325 goto out_clk_enable_mclk;
1326 }
1327 rate = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
1328 if (rate != CM_CAM_MCLK_HZ)
1329 dev_warn(isp->dev, "unexpected cam_mclk rate:\n"
1330 " expected : %d\n"
1331 " actual : %ld\n", CM_CAM_MCLK_HZ, rate);
b057c3c3 1332 r = clk_prepare_enable(isp->clock[ISP_CLK_CSI2_FCK]);
448de7e7 1333 if (r) {
b057c3c3 1334 dev_err(isp->dev, "failed to enable csi2_fck clock\n");
448de7e7
SA		 1335 goto out_clk_enable_csi2_fclk;
1336 }
1337 return 0;
1338
1339out_clk_enable_csi2_fclk:
b057c3c3 1340 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
448de7e7 1341out_clk_enable_mclk:
b057c3c3 1342 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
448de7e7
SA		 1343out_clk_enable_ick:
1344 return r;
1345}
1346
1347/*
1348 * isp_disable_clocks - Disable ISP clocks
1349 * @isp: OMAP3 ISP device
1350 */
1351static void isp_disable_clocks(struct isp_device *isp)
1352{
b057c3c3
LP		 1353 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
1354 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
1355 clk_disable_unprepare(isp->clock[ISP_CLK_CSI2_FCK]);
448de7e7
SA		 1356}
1357
1358static const char *isp_clocks[] = {
1359 "cam_ick",
1360 "cam_mclk",
448de7e7
SA		 1361 "csi2_96m_fck",
1362 "l3_ick",
1363};
1364
448de7e7
SA		 1365static int isp_get_clocks(struct isp_device *isp)
1366{
1367 struct clk *clk;
1368 unsigned int i;
1369
1370 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
cf2b4cf6 1371 clk = devm_clk_get(isp->dev, isp_clocks[i]);
448de7e7
SA		 1372 if (IS_ERR(clk)) {
1373 dev_err(isp->dev, "clk_get %s failed\n", isp_clocks[i]);
448de7e7
SA		 1374 return PTR_ERR(clk);
1375 }
1376
1377 isp->clock[i] = clk;
1378 }
1379
1380 return 0;
1381}
1382
1383/*
1384 * omap3isp_get - Acquire the ISP resource.
1385 *
1386 * Initializes the clocks for the first acquire.
1387 *
1388 * Increment the reference count on the ISP. If the first reference is taken,
1389 * enable clocks and power-up all submodules.
1390 *
25985edc 1391 * Return a pointer to the ISP device structure, or NULL if an error occurred.
448de7e7 1392 */
96d62ae2 1393static struct isp_device *__omap3isp_get(struct isp_device *isp, bool irq)
448de7e7
SA		 1394{
1395 struct isp_device *__isp = isp;
1396
1397 if (isp == NULL)
1398 return NULL;
1399
1400 mutex_lock(&isp->isp_mutex);
1401 if (isp->ref_count > 0)
1402 goto out;
1403
1404 if (isp_enable_clocks(isp) < 0) {
1405 __isp = NULL;
1406 goto out;
1407 }
1408
1409 /* We don't want to restore context before saving it! */
1410 if (isp->has_context)
1411 isp_restore_ctx(isp);
448de7e7 1412
96d62ae2
LP		 1413 if (irq)
1414 isp_enable_interrupts(isp);
448de7e7
SA		 1415
1416out:
1417 if (__isp != NULL)
1418 isp->ref_count++;
1419 mutex_unlock(&isp->isp_mutex);
1420
1421 return __isp;
1422}
1423
96d62ae2
LP		 1424struct isp_device *omap3isp_get(struct isp_device *isp)
1425{
1426 return __omap3isp_get(isp, true);
1427}
1428
448de7e7
SA		 1429/*
1430 * omap3isp_put - Release the ISP
1431 *
1432 * Decrement the reference count on the ISP. If the last reference is released,
1433 * power-down all submodules, disable clocks and free temporary buffers.
1434 */
2a0a5472 1435static void __omap3isp_put(struct isp_device *isp, bool save_ctx)
448de7e7
SA		 1436{
1437 if (isp == NULL)
1438 return;
1439
1440 mutex_lock(&isp->isp_mutex);
1441 BUG_ON(isp->ref_count == 0);
1442 if (--isp->ref_count == 0) {
1443 isp_disable_interrupts(isp);
2a0a5472 1444 if (save_ctx) {
a32f2f90 1445 isp_save_ctx(isp);
96d62ae2
LP		 1446 isp->has_context = 1;
1447 }
1567bb7d
LP		 1448 /* Reset the ISP if an entity has failed to stop. This is the
1449 * only way to recover from such conditions.
1450 */
17d3d405
SA		 1451 if (!media_entity_enum_empty(&isp->crashed) ||
1452 isp->stop_failure)
994d5375 1453 isp_reset(isp);
448de7e7
SA		 1454 isp_disable_clocks(isp);
1455 }
1456 mutex_unlock(&isp->isp_mutex);
1457}
1458
2a0a5472
LP		 1459void omap3isp_put(struct isp_device *isp)
1460{
1461 __omap3isp_put(isp, true);
1462}
1463
448de7e7
SA		 1464/* --------------------------------------------------------------------------
1465 * Platform device driver
1466 */
1467
1468/*
1469 * omap3isp_print_status - Prints the values of the ISP Control Module registers
1470 * @isp: OMAP3 ISP device
1471 */
1472#define ISP_PRINT_REGISTER(isp, name)\
1473 dev_dbg(isp->dev, "###ISP " #name "=0x%08x\n", \
1474 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_##name))
1475#define SBL_PRINT_REGISTER(isp, name)\
1476 dev_dbg(isp->dev, "###SBL " #name "=0x%08x\n", \
1477 isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_##name))
1478
1479void omap3isp_print_status(struct isp_device *isp)
1480{
1481 dev_dbg(isp->dev, "-------------ISP Register dump--------------\n");
1482
1483 ISP_PRINT_REGISTER(isp, SYSCONFIG);
1484 ISP_PRINT_REGISTER(isp, SYSSTATUS);
1485 ISP_PRINT_REGISTER(isp, IRQ0ENABLE);
1486 ISP_PRINT_REGISTER(isp, IRQ0STATUS);
1487 ISP_PRINT_REGISTER(isp, TCTRL_GRESET_LENGTH);
1488 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_REPLAY);
1489 ISP_PRINT_REGISTER(isp, CTRL);
1490 ISP_PRINT_REGISTER(isp, TCTRL_CTRL);
1491 ISP_PRINT_REGISTER(isp, TCTRL_FRAME);
1492 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_DELAY);
1493 ISP_PRINT_REGISTER(isp, TCTRL_STRB_DELAY);
1494 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_DELAY);
1495 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_LENGTH);
1496 ISP_PRINT_REGISTER(isp, TCTRL_STRB_LENGTH);
1497 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_LENGTH);
1498
1499 SBL_PRINT_REGISTER(isp, PCR);
1500 SBL_PRINT_REGISTER(isp, SDR_REQ_EXP);
1501
1502 dev_dbg(isp->dev, "--------------------------------------------\n");
1503}
1504
1505#ifdef CONFIG_PM
1506
1507/*
1508 * Power management support.
1509 *
1510 * As the ISP can't properly handle an input video stream interruption on a non
1511 * frame boundary, the ISP pipelines need to be stopped before sensors get
1512 * suspended. However, as suspending the sensors can require a running clock,
1513 * which can be provided by the ISP, the ISP can't be completely suspended
1514 * before the sensor.
1515 *
1516 * To solve this problem power management support is split into prepare/complete
1517 * and suspend/resume operations. The pipelines are stopped in prepare() and the
1518 * ISP clocks get disabled in suspend(). Similarly, the clocks are reenabled in
1519 * resume(), and the the pipelines are restarted in complete().
1520 *
39c1cb2b 1521 * TODO: PM dependencies between the ISP and sensors are not modelled explicitly
448de7e7
SA		 1522 * yet.
1523 */
1524static int isp_pm_prepare(struct device *dev)
1525{
1526 struct isp_device *isp = dev_get_drvdata(dev);
1527 int reset;
1528
1529 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1530
1531 if (isp->ref_count == 0)
1532 return 0;
1533
1534 reset = isp_suspend_modules(isp);
1535 isp_disable_interrupts(isp);
1536 isp_save_ctx(isp);
1537 if (reset)
1538 isp_reset(isp);
1539
1540 return 0;
1541}
1542
1543static int isp_pm_suspend(struct device *dev)
1544{
1545 struct isp_device *isp = dev_get_drvdata(dev);
1546
1547 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1548
1549 if (isp->ref_count)
1550 isp_disable_clocks(isp);
1551
1552 return 0;
1553}
1554
1555static int isp_pm_resume(struct device *dev)
1556{
1557 struct isp_device *isp = dev_get_drvdata(dev);
1558
1559 if (isp->ref_count == 0)
1560 return 0;
1561
1562 return isp_enable_clocks(isp);
1563}
1564
1565static void isp_pm_complete(struct device *dev)
1566{
1567 struct isp_device *isp = dev_get_drvdata(dev);
1568
1569 if (isp->ref_count == 0)
1570 return;
1571
1572 isp_restore_ctx(isp);
1573 isp_enable_interrupts(isp);
1574 isp_resume_modules(isp);
1575}
1576
1577#else
1578
1579#define isp_pm_prepare NULL
1580#define isp_pm_suspend NULL
1581#define isp_pm_resume NULL
1582#define isp_pm_complete NULL
1583
1584#endif /* CONFIG_PM */
1585
1586static void isp_unregister_entities(struct isp_device *isp)
1587{
1588 omap3isp_csi2_unregister_entities(&isp->isp_csi2a);
1589 omap3isp_ccp2_unregister_entities(&isp->isp_ccp2);
1590 omap3isp_ccdc_unregister_entities(&isp->isp_ccdc);
1591 omap3isp_preview_unregister_entities(&isp->isp_prev);
1592 omap3isp_resizer_unregister_entities(&isp->isp_res);
1593 omap3isp_stat_unregister_entities(&isp->isp_aewb);
1594 omap3isp_stat_unregister_entities(&isp->isp_af);
1595 omap3isp_stat_unregister_entities(&isp->isp_hist);
1596
1597 v4l2_device_unregister(&isp->v4l2_dev);
1598 media_device_unregister(&isp->media_dev);
9832e155 1599 media_device_cleanup(&isp->media_dev);
448de7e7
SA		 1600}
1601
703e6f62
SA		 1602static int isp_link_entity(
1603 struct isp_device *isp, struct media_entity *entity,
1604 enum isp_interface_type interface)
1605{
1606 struct media_entity *input;
1607 unsigned int flags;
1608 unsigned int pad;
1609 unsigned int i;
1610
1611 /* Connect the sensor to the correct interface module.
1612 * Parallel sensors are connected directly to the CCDC, while
1613 * serial sensors are connected to the CSI2a, CCP2b or CSI2c
1614 * receiver through CSIPHY1 or CSIPHY2.
1615 */
1616 switch (interface) {
1617 case ISP_INTERFACE_PARALLEL:
1618 input = &isp->isp_ccdc.subdev.entity;
1619 pad = CCDC_PAD_SINK;
1620 flags = 0;
1621 break;
1622
1623 case ISP_INTERFACE_CSI2A_PHY2:
1624 input = &isp->isp_csi2a.subdev.entity;
1625 pad = CSI2_PAD_SINK;
1626 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
1627 break;
1628
1629 case ISP_INTERFACE_CCP2B_PHY1:
1630 case ISP_INTERFACE_CCP2B_PHY2:
1631 input = &isp->isp_ccp2.subdev.entity;
1632 pad = CCP2_PAD_SINK;
1633 flags = 0;
1634 break;
1635
1636 case ISP_INTERFACE_CSI2C_PHY1:
1637 input = &isp->isp_csi2c.subdev.entity;
1638 pad = CSI2_PAD_SINK;
1639 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
1640 break;
1641
1642 default:
1643 dev_err(isp->dev, "%s: invalid interface type %u\n", __func__,
1644 interface);
1645 return -EINVAL;
1646 }
1647
1648 /*
1649 * Not all interfaces are available on all revisions of the
1650 * ISP. The sub-devices of those interfaces aren't initialised
1651 * in such a case. Check this by ensuring the num_pads is
1652 * non-zero.
1653 */
1654 if (!input->num_pads) {
1655 dev_err(isp->dev, "%s: invalid input %u\n", entity->name,
1656 interface);
1657 return -EINVAL;
1658 }
1659
1660 for (i = 0; i < entity->num_pads; i++) {
1661 if (entity->pads[i].flags & MEDIA_PAD_FL_SOURCE)
1662 break;
1663 }
1664 if (i == entity->num_pads) {
bce9e317
SA		 1665 dev_err(isp->dev, "%s: no source pad in external entity %s\n",
1666 __func__, entity->name);
703e6f62
SA		 1667 return -EINVAL;
1668 }
1669
8df00a15 1670 return media_create_pad_link(entity, i, input, pad, flags);
703e6f62
SA		 1671}
1672
448de7e7
SA		 1673static int isp_register_entities(struct isp_device *isp)
1674{
448de7e7
SA		 1675 int ret;
1676
1677 isp->media_dev.dev = isp->dev;
1678 strlcpy(isp->media_dev.model, "TI OMAP3 ISP",
1679 sizeof(isp->media_dev.model));
083eb078 1680 isp->media_dev.hw_revision = isp->revision;
68429f50 1681 isp->media_dev.ops = &isp_media_ops;
9832e155 1682 media_device_init(&isp->media_dev);
448de7e7
SA		 1683
1684 isp->v4l2_dev.mdev = &isp->media_dev;
1685 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
1686 if (ret < 0) {
4feca39b 1687 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
448de7e7
SA		 1688 __func__, ret);
1689 goto done;
1690 }
1691
1692 /* Register internal entities */
1693 ret = omap3isp_ccp2_register_entities(&isp->isp_ccp2, &isp->v4l2_dev);
1694 if (ret < 0)
1695 goto done;
1696
1697 ret = omap3isp_csi2_register_entities(&isp->isp_csi2a, &isp->v4l2_dev);
1698 if (ret < 0)
1699 goto done;
1700
1701 ret = omap3isp_ccdc_register_entities(&isp->isp_ccdc, &isp->v4l2_dev);
1702 if (ret < 0)
1703 goto done;
1704
1705 ret = omap3isp_preview_register_entities(&isp->isp_prev,
1706 &isp->v4l2_dev);
1707 if (ret < 0)
1708 goto done;
1709
1710 ret = omap3isp_resizer_register_entities(&isp->isp_res, &isp->v4l2_dev);
1711 if (ret < 0)
1712 goto done;
1713
1714 ret = omap3isp_stat_register_entities(&isp->isp_aewb, &isp->v4l2_dev);
1715 if (ret < 0)
1716 goto done;
1717
1718 ret = omap3isp_stat_register_entities(&isp->isp_af, &isp->v4l2_dev);
1719 if (ret < 0)
1720 goto done;
1721
1722 ret = omap3isp_stat_register_entities(&isp->isp_hist, &isp->v4l2_dev);
1723 if (ret < 0)
1724 goto done;
1725
448de7e7 1726done:
5d479386 1727 if (ret < 0)
448de7e7
SA		 1728 isp_unregister_entities(isp);
1729
1730 return ret;
1731}
1732
f2f6da0d 1733/*
b285d5af 1734 * isp_create_links() - Create links for internal and external ISP entities
f2f6da0d 1735 * @isp : Pointer to ISP device
b285d5af
JMC		 1736 *
1737 * This function creates all links between ISP internal and external entities.
1738 *
1739 * Return: A negative error code on failure or zero on success. Possible error
1740 * codes are those returned by media_create_pad_link().
f2f6da0d 1741 */
b285d5af 1742static int isp_create_links(struct isp_device *isp)
f2f6da0d
JMC		 1743{
1744 int ret;
1745
b5f6df06
JMC		 1746 /* Create links between entities and video nodes. */
1747 ret = media_create_pad_link(
1748 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1749 &isp->isp_csi2a.video_out.video.entity, 0, 0);
1750 if (ret < 0)
f2f6da0d 1751 return ret;
f2f6da0d 1752
b5f6df06
JMC		 1753 ret = media_create_pad_link(
1754 &isp->isp_ccp2.video_in.video.entity, 0,
1755 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SINK, 0);
1756 if (ret < 0)
f2f6da0d 1757 return ret;
f2f6da0d 1758
b5f6df06
JMC		 1759 ret = media_create_pad_link(
1760 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1761 &isp->isp_ccdc.video_out.video.entity, 0, 0);
1762 if (ret < 0)
f2f6da0d 1763 return ret;
f2f6da0d 1764
b5f6df06
JMC		 1765 ret = media_create_pad_link(
1766 &isp->isp_prev.video_in.video.entity, 0,
1767 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1768 if (ret < 0)
f2f6da0d 1769 return ret;
f2f6da0d 1770
b5f6df06
JMC		 1771 ret = media_create_pad_link(
1772 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1773 &isp->isp_prev.video_out.video.entity, 0, 0);
1774 if (ret < 0)
1775 return ret;
1776
1777 ret = media_create_pad_link(
1778 &isp->isp_res.video_in.video.entity, 0,
1779 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1780 if (ret < 0)
1781 return ret;
1782
1783 ret = media_create_pad_link(
1784 &isp->isp_res.subdev.entity, RESZ_PAD_SOURCE,
1785 &isp->isp_res.video_out.video.entity, 0, 0);
1786
1787 if (ret < 0)
f2f6da0d 1788 return ret;
f2f6da0d 1789
b5f6df06 1790 /* Create links between entities. */
f2f6da0d
JMC		 1791 ret = media_create_pad_link(
1792 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1793 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1794 if (ret < 0)
1795 return ret;
1796
1797 ret = media_create_pad_link(
1798 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SOURCE,
1799 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1800 if (ret < 0)
1801 return ret;
1802
1803 ret = media_create_pad_link(
1804 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1805 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1806 if (ret < 0)
1807 return ret;
1808
1809 ret = media_create_pad_link(
1810 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1811 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1812 if (ret < 0)
1813 return ret;
1814
1815 ret = media_create_pad_link(
1816 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1817 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1818 if (ret < 0)
1819 return ret;
1820
1821 ret = media_create_pad_link(
1822 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1823 &isp->isp_aewb.subdev.entity, 0,
1824 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1825 if (ret < 0)
1826 return ret;
1827
1828 ret = media_create_pad_link(
1829 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1830 &isp->isp_af.subdev.entity, 0,
1831 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1832 if (ret < 0)
1833 return ret;
1834
1835 ret = media_create_pad_link(
1836 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1837 &isp->isp_hist.subdev.entity, 0,
1838 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1839 if (ret < 0)
1840 return ret;
1841
1842 return 0;
1843}
1844
448de7e7
SA		 1845static void isp_cleanup_modules(struct isp_device *isp)
1846{
1847 omap3isp_h3a_aewb_cleanup(isp);
1848 omap3isp_h3a_af_cleanup(isp);
1849 omap3isp_hist_cleanup(isp);
1850 omap3isp_resizer_cleanup(isp);
1851 omap3isp_preview_cleanup(isp);
1852 omap3isp_ccdc_cleanup(isp);
1853 omap3isp_ccp2_cleanup(isp);
1854 omap3isp_csi2_cleanup(isp);
838a6c56 1855 omap3isp_csiphy_cleanup(isp);
448de7e7
SA		 1856}
1857
1858static int isp_initialize_modules(struct isp_device *isp)
1859{
1860 int ret;
1861
1862 ret = omap3isp_csiphy_init(isp);
1863 if (ret < 0) {
1864 dev_err(isp->dev, "CSI PHY initialization failed\n");
838a6c56 1865 return ret;
448de7e7
SA		 1866 }
1867
1868 ret = omap3isp_csi2_init(isp);
1869 if (ret < 0) {
1870 dev_err(isp->dev, "CSI2 initialization failed\n");
1871 goto error_csi2;
1872 }
1873
1874 ret = omap3isp_ccp2_init(isp);
1875 if (ret < 0) {
a4573084
PM		 1876 if (ret != -EPROBE_DEFER)
1877 dev_err(isp->dev, "CCP2 initialization failed\n");
448de7e7
SA		 1878 goto error_ccp2;
1879 }
1880
1881 ret = omap3isp_ccdc_init(isp);
1882 if (ret < 0) {
1883 dev_err(isp->dev, "CCDC initialization failed\n");
1884 goto error_ccdc;
1885 }
1886
1887 ret = omap3isp_preview_init(isp);
1888 if (ret < 0) {
1889 dev_err(isp->dev, "Preview initialization failed\n");
1890 goto error_preview;
1891 }
1892
1893 ret = omap3isp_resizer_init(isp);
1894 if (ret < 0) {
1895 dev_err(isp->dev, "Resizer initialization failed\n");
1896 goto error_resizer;
1897 }
1898
1899 ret = omap3isp_hist_init(isp);
1900 if (ret < 0) {
1901 dev_err(isp->dev, "Histogram initialization failed\n");
1902 goto error_hist;
1903 }
1904
1905 ret = omap3isp_h3a_aewb_init(isp);
1906 if (ret < 0) {
1907 dev_err(isp->dev, "H3A AEWB initialization failed\n");
1908 goto error_h3a_aewb;
1909 }
1910
1911 ret = omap3isp_h3a_af_init(isp);
1912 if (ret < 0) {
1913 dev_err(isp->dev, "H3A AF initialization failed\n");
1914 goto error_h3a_af;
1915 }
1916
448de7e7
SA		 1917 return 0;
1918
448de7e7
SA		 1919error_h3a_af:
1920 omap3isp_h3a_aewb_cleanup(isp);
1921error_h3a_aewb:
1922 omap3isp_hist_cleanup(isp);
1923error_hist:
1924 omap3isp_resizer_cleanup(isp);
1925error_resizer:
1926 omap3isp_preview_cleanup(isp);
1927error_preview:
1928 omap3isp_ccdc_cleanup(isp);
1929error_ccdc:
1930 omap3isp_ccp2_cleanup(isp);
1931error_ccp2:
1932 omap3isp_csi2_cleanup(isp);
1933error_csi2:
838a6c56
SA		 1934 omap3isp_csiphy_cleanup(isp);
1935
448de7e7
SA		 1936 return ret;
1937}
1938
2a0a5472
LP		 1939static void isp_detach_iommu(struct isp_device *isp)
1940{
1941 arm_iommu_release_mapping(isp->mapping);
1942 isp->mapping = NULL;
2a0a5472
LP		 1943}
1944
1945static int isp_attach_iommu(struct isp_device *isp)
1946{
1947 struct dma_iommu_mapping *mapping;
2a0a5472
LP		 1948 int ret;
1949
2a0a5472
LP		 1950 /*
1951 * Create the ARM mapping, used by the ARM DMA mapping core to allocate
1952 * VAs. This will allocate a corresponding IOMMU domain.
1953 */
1954 mapping = arm_iommu_create_mapping(&platform_bus_type, SZ_1G, SZ_2G);
1955 if (IS_ERR(mapping)) {
1956 dev_err(isp->dev, "failed to create ARM IOMMU mapping\n");
1957 ret = PTR_ERR(mapping);
1958 goto error;
1959 }
1960
1961 isp->mapping = mapping;
1962
1963 /* Attach the ARM VA mapping to the device. */
1964 ret = arm_iommu_attach_device(isp->dev, mapping);
1965 if (ret < 0) {
1966 dev_err(isp->dev, "failed to attach device to VA mapping\n");
1967 goto error;
1968 }
1969
1970 return 0;
1971
1972error:
1973 isp_detach_iommu(isp);
1974 return ret;
1975}
1976
448de7e7
SA		 1977/*
1978 * isp_remove - Remove ISP platform device
1979 * @pdev: Pointer to ISP platform device
1980 *
1981 * Always returns 0.
1982 */
4c62e976 1983static int isp_remove(struct platform_device *pdev)
448de7e7
SA		 1984{
1985 struct isp_device *isp = platform_get_drvdata(pdev);
448de7e7 1986
da7f3843 1987 v4l2_async_notifier_unregister(&isp->notifier);
448de7e7
SA		 1988 isp_unregister_entities(isp);
1989 isp_cleanup_modules(isp);
9b28ee3c 1990 isp_xclk_cleanup(isp);
448de7e7 1991
96d62ae2 1992 __omap3isp_get(isp, false);
2a0a5472
LP		 1993 isp_detach_iommu(isp);
1994 __omap3isp_put(isp, false);
448de7e7 1995
17d3d405 1996 media_entity_enum_cleanup(&isp->crashed);
df497566 1997 v4l2_async_notifier_cleanup(&isp->notifier);
17d3d405 1998
448de7e7
SA		 1999 return 0;
2000}
2001
da7f3843
SA		 2002enum isp_of_phy {
2003 ISP_OF_PHY_PARALLEL = 0,
2004 ISP_OF_PHY_CSIPHY1,
2005 ISP_OF_PHY_CSIPHY2,
2006};
2007
df497566
SA		 2008static int isp_fwnode_parse(struct device *dev,
2009 struct v4l2_fwnode_endpoint *vep,
2010 struct v4l2_async_subdev *asd)
da7f3843 2011{
df497566
SA		 2012 struct isp_async_subdev *isd =
2013 container_of(asd, struct isp_async_subdev, asd);
da7f3843 2014 struct isp_bus_cfg *buscfg = &isd->bus;
9211434b 2015 bool csi1 = false;
df497566 2016 unsigned int i;
da7f3843 2017
68d9c47b 2018 dev_dbg(dev, "parsing endpoint %pOF, interface %u\n",
df497566 2019 to_of_node(vep->base.local_fwnode), vep->base.port);
da7f3843 2020
df497566 2021 switch (vep->base.port) {
da7f3843
SA		 2022 case ISP_OF_PHY_PARALLEL:
2023 buscfg->interface = ISP_INTERFACE_PARALLEL;
2024 buscfg->bus.parallel.data_lane_shift =
df497566 2025 vep->bus.parallel.data_shift;
da7f3843 2026 buscfg->bus.parallel.clk_pol =
df497566 2027 !!(vep->bus.parallel.flags
da7f3843
SA		 2028 & V4L2_MBUS_PCLK_SAMPLE_FALLING);
2029 buscfg->bus.parallel.hs_pol =
df497566 2030 !!(vep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW);
da7f3843 2031 buscfg->bus.parallel.vs_pol =
df497566 2032 !!(vep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW);
da7f3843 2033 buscfg->bus.parallel.fld_pol =
df497566 2034 !!(vep->bus.parallel.flags & V4L2_MBUS_FIELD_EVEN_LOW);
da7f3843 2035 buscfg->bus.parallel.data_pol =
df497566
SA		 2036 !!(vep->bus.parallel.flags & V4L2_MBUS_DATA_ACTIVE_LOW);
2037 buscfg->bus.parallel.bt656 = vep->bus_type == V4L2_MBUS_BT656;
da7f3843
SA		 2038 break;
2039
2040 case ISP_OF_PHY_CSIPHY1:
2041 case ISP_OF_PHY_CSIPHY2:
df497566 2042 switch (vep->bus_type) {
9211434b
PM		 2043 case V4L2_MBUS_CCP2:
2044 case V4L2_MBUS_CSI1:
2045 dev_dbg(dev, "CSI-1/CCP-2 configuration\n");
2046 csi1 = true;
2047 break;
2048 case V4L2_MBUS_CSI2:
2049 dev_dbg(dev, "CSI-2 configuration\n");
2050 csi1 = false;
2051 break;
2052 default:
2053 dev_err(dev, "unsupported bus type %u\n",
df497566 2054 vep->bus_type);
9211434b
PM		 2055 return -EINVAL;
2056 }
2057
df497566 2058 switch (vep->base.port) {
da7f3843 2059 case ISP_OF_PHY_CSIPHY1:
9211434b
PM		 2060 if (csi1)
2061 buscfg->interface = ISP_INTERFACE_CCP2B_PHY1;
2062 else
2063 buscfg->interface = ISP_INTERFACE_CSI2C_PHY1;
da7f3843
SA		 2064 break;
2065 case ISP_OF_PHY_CSIPHY2:
9211434b
PM		 2066 if (csi1)
2067 buscfg->interface = ISP_INTERFACE_CCP2B_PHY2;
2068 else
2069 buscfg->interface = ISP_INTERFACE_CSI2A_PHY2;
da7f3843
SA		 2070 break;
2071 }
9211434b
PM		 2072 if (csi1) {
2073 buscfg->bus.ccp2.lanecfg.clk.pos =
df497566 2074 vep->bus.mipi_csi1.clock_lane;
9211434b 2075 buscfg->bus.ccp2.lanecfg.clk.pol =
df497566 2076 vep->bus.mipi_csi1.lane_polarity[0];
9211434b
PM		 2077 dev_dbg(dev, "clock lane polarity %u, pos %u\n",
2078 buscfg->bus.ccp2.lanecfg.clk.pol,
2079 buscfg->bus.ccp2.lanecfg.clk.pos);
2080
2081 buscfg->bus.ccp2.lanecfg.data[0].pos =
df497566 2082 vep->bus.mipi_csi1.data_lane;
9211434b 2083 buscfg->bus.ccp2.lanecfg.data[0].pol =
df497566 2084 vep->bus.mipi_csi1.lane_polarity[1];
9211434b 2085
5160fb4b 2086 dev_dbg(dev, "data lane polarity %u, pos %u\n",
9211434b
PM		 2087 buscfg->bus.ccp2.lanecfg.data[0].pol,
2088 buscfg->bus.ccp2.lanecfg.data[0].pos);
2089
2090 buscfg->bus.ccp2.strobe_clk_pol =
df497566
SA		 2091 vep->bus.mipi_csi1.clock_inv;
2092 buscfg->bus.ccp2.phy_layer = vep->bus.mipi_csi1.strobe;
9211434b 2093 buscfg->bus.ccp2.ccp2_mode =
df497566 2094 vep->bus_type == V4L2_MBUS_CCP2;
9211434b
PM		 2095 buscfg->bus.ccp2.vp_clk_pol = 1;
2096
2097 buscfg->bus.ccp2.crc = 1;
2098 } else {
2099 buscfg->bus.csi2.lanecfg.clk.pos =
df497566 2100 vep->bus.mipi_csi2.clock_lane;
9211434b 2101 buscfg->bus.csi2.lanecfg.clk.pol =
df497566 2102 vep->bus.mipi_csi2.lane_polarities[0];
9211434b
PM		 2103 dev_dbg(dev, "clock lane polarity %u, pos %u\n",
2104 buscfg->bus.csi2.lanecfg.clk.pol,
2105 buscfg->bus.csi2.lanecfg.clk.pos);
2106
2107 buscfg->bus.csi2.num_data_lanes =
df497566 2108 vep->bus.mipi_csi2.num_data_lanes;
9211434b
PM		 2109
2110 for (i = 0; i < buscfg->bus.csi2.num_data_lanes; i++) {
2111 buscfg->bus.csi2.lanecfg.data[i].pos =
df497566 2112 vep->bus.mipi_csi2.data_lanes[i];
9211434b 2113 buscfg->bus.csi2.lanecfg.data[i].pol =
df497566 2114 vep->bus.mipi_csi2.lane_polarities[i + 1];
9211434b
PM		 2115 dev_dbg(dev,
2116 "data lane %u polarity %u, pos %u\n", i,
2117 buscfg->bus.csi2.lanecfg.data[i].pol,
2118 buscfg->bus.csi2.lanecfg.data[i].pos);
2119 }
2120 /*
2121 * FIXME: now we assume the CRC is always there.
2122 * Implement a way to obtain this information from the
2123 * sensor. Frame descriptors, perhaps?
2124 */
2125 buscfg->bus.csi2.crc = 1;
da7f3843 2126 }
da7f3843
SA		 2127 break;
2128
2129 default:
68d9c47b 2130 dev_warn(dev, "%pOF: invalid interface %u\n",
df497566 2131 to_of_node(vep->base.local_fwnode), vep->base.port);
831f3494 2132 return -EINVAL;
da7f3843
SA		 2133 }
2134
2135 return 0;
2136}
2137
da7f3843
SA		 2138static int isp_subdev_notifier_complete(struct v4l2_async_notifier *async)
2139{
2140 struct isp_device *isp = container_of(async, struct isp_device,
2141 notifier);
68a57fa9
JMC		 2142 struct v4l2_device *v4l2_dev = &isp->v4l2_dev;
2143 struct v4l2_subdev *sd;
68a57fa9
JMC		 2144 int ret;
2145
17d3d405
SA		 2146 ret = media_entity_enum_init(&isp->crashed, &isp->media_dev);
2147 if (ret)
2148 return ret;
2149
68a57fa9 2150 list_for_each_entry(sd, &v4l2_dev->subdevs, list) {
eae4cf8f 2151 if (sd->notifier != &isp->notifier)
02b1ce92
SA		 2152 continue;
2153
2154 ret = isp_link_entity(isp, &sd->entity,
2155 v4l2_subdev_to_bus_cfg(sd)->interface);
2156 if (ret < 0)
2157 return ret;
68a57fa9 2158 }
da7f3843 2159
9832e155
JMC		 2160 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
2161 if (ret < 0)
2162 return ret;
2163
2164 return media_device_register(&isp->media_dev);
da7f3843
SA		 2165}
2166
b6ee3f0d
LP		 2167static const struct v4l2_async_notifier_operations isp_subdev_notifier_ops = {
2168 .complete = isp_subdev_notifier_complete,
2169};
2170
448de7e7
SA		 2171/*
2172 * isp_probe - Probe ISP platform device
2173 * @pdev: Pointer to ISP platform device
2174 *
2175 * Returns 0 if successful,
2176 * -ENOMEM if no memory available,
2177 * -ENODEV if no platform device resources found
2178 * or no space for remapping registers,
2179 * -EINVAL if couldn't install ISR,
2180 * or clk_get return error value.
2181 */
4c62e976 2182static int isp_probe(struct platform_device *pdev)
448de7e7 2183{
448de7e7 2184 struct isp_device *isp;
8644cdf9 2185 struct resource *mem;
448de7e7
SA		 2186 int ret;
2187 int i, m;
2188
cf2b4cf6 2189 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
448de7e7
SA		 2190 if (!isp) {
2191 dev_err(&pdev->dev, "could not allocate memory\n");
2192 return -ENOMEM;
2193 }
2194
859969b3
SA		 2195 ret = fwnode_property_read_u32(of_fwnode_handle(pdev->dev.of_node),
2196 "ti,phy-type", &isp->phy_type);
78c66fbc
LP		 2197 if (ret)
2198 return ret;
da7f3843 2199
78c66fbc
LP		 2200 isp->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2201 "syscon");
2202 if (IS_ERR(isp->syscon))
2203 return PTR_ERR(isp->syscon);
da7f3843 2204
859969b3
SA		 2205 ret = of_property_read_u32_index(pdev->dev.of_node,
2206 "syscon", 1, &isp->syscon_offset);
78c66fbc
LP		 2207 if (ret)
2208 return ret;
da7f3843 2209
448de7e7 2210 isp->autoidle = autoidle;
448de7e7
SA		 2211
2212 mutex_init(&isp->isp_mutex);
2213 spin_lock_init(&isp->stat_lock);
2214
df497566
SA		 2215 ret = v4l2_async_notifier_parse_fwnode_endpoints(
2216 &pdev->dev, &isp->notifier, sizeof(struct isp_async_subdev),
2217 isp_fwnode_parse);
2218 if (ret < 0)
2219 goto error;
2220
448de7e7 2221 isp->dev = &pdev->dev;
448de7e7
SA		 2222 isp->ref_count = 0;
2223
224ddca0
RK		 2224 ret = dma_coerce_mask_and_coherent(isp->dev, DMA_BIT_MASK(32));
2225 if (ret)
697cca21 2226 goto error;
448de7e7
SA		 2227
2228 platform_set_drvdata(pdev, isp);
2229
2230 /* Regulators */
3494bb05
SA		 2231 isp->isp_csiphy1.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy1");
2232 isp->isp_csiphy2.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy2");
448de7e7 2233
d8658bca
LP		 2234 /* Clocks
2235 *
2236 * The ISP clock tree is revision-dependent. We thus need to enable ICLK
2237 * manually to read the revision before calling __omap3isp_get().
8644cdf9
SA		 2238 *
2239 * Start by mapping the ISP MMIO area, which is in two pieces.
2240 * The ISP IOMMU is in between. Map both now, and fill in the
2241 * ISP revision specific portions a little later in the
2242 * function.
d8658bca 2243 */
8644cdf9
SA		 2244 for (i = 0; i < 2; i++) {
2245 unsigned int map_idx = i ? OMAP3_ISP_IOMEM_CSI2A_REGS1 : 0;
2246
2247 mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
2248 isp->mmio_base[map_idx] =
2249 devm_ioremap_resource(isp->dev, mem);
2250 if (IS_ERR(isp->mmio_base[map_idx]))
2251 return PTR_ERR(isp->mmio_base[map_idx]);
2252 }
448de7e7
SA		 2253
2254 ret = isp_get_clocks(isp);
2255 if (ret < 0)
2256 goto error;
2257
d8658bca
LP		 2258 ret = clk_enable(isp->clock[ISP_CLK_CAM_ICK]);
2259 if (ret < 0)
2260 goto error;
2261
2262 isp->revision = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
2263 dev_info(isp->dev, "Revision %d.%d found\n",
2264 (isp->revision & 0xf0) >> 4, isp->revision & 0x0f);
2265
2266 clk_disable(isp->clock[ISP_CLK_CAM_ICK]);
2267
0bd0dbee
PST		 2268 if (__omap3isp_get(isp, false) == NULL) {
2269 ret = -ENODEV;
448de7e7 2270 goto error;
0bd0dbee 2271 }
448de7e7
SA		 2272
2273 ret = isp_reset(isp);
2274 if (ret < 0)
2275 goto error_isp;
2276
9b28ee3c
LP		 2277 ret = isp_xclk_init(isp);
2278 if (ret < 0)
2279 goto error_isp;
2280
448de7e7 2281 /* Memory resources */
448de7e7
SA		 2282 for (m = 0; m < ARRAY_SIZE(isp_res_maps); m++)
2283 if (isp->revision == isp_res_maps[m].isp_rev)
2284 break;
2285
2286 if (m == ARRAY_SIZE(isp_res_maps)) {
2287 dev_err(isp->dev, "No resource map found for ISP rev %d.%d\n",
2288 (isp->revision & 0xf0) >> 4, isp->revision & 0xf);
2289 ret = -ENODEV;
2290 goto error_isp;
2291 }
2292
8644cdf9
SA		 2293 for (i = 1; i < OMAP3_ISP_IOMEM_CSI2A_REGS1; i++)
2294 isp->mmio_base[i] =
2295 isp->mmio_base[0] + isp_res_maps[m].offset[i];
2296
2297 for (i = OMAP3_ISP_IOMEM_CSIPHY2; i < OMAP3_ISP_IOMEM_LAST; i++)
2298 isp->mmio_base[i] =
2299 isp->mmio_base[OMAP3_ISP_IOMEM_CSI2A_REGS1]
2300 + isp_res_maps[m].offset[i];
2301
2302 isp->mmio_hist_base_phys =
2303 mem->start + isp_res_maps[m].offset[OMAP3_ISP_IOMEM_HIST];
448de7e7 2304
2a0a5472
LP		 2305 /* IOMMU */
2306 ret = isp_attach_iommu(isp);
2307 if (ret < 0) {
2308 dev_err(&pdev->dev, "unable to attach to IOMMU\n");
f626b52d
OBC		 2309 goto error_isp;
2310 }
2311
448de7e7 2312 /* Interrupt */
514580f9
AH		 2313 ret = platform_get_irq(pdev, 0);
2314 if (ret <= 0) {
448de7e7
SA		 2315 dev_err(isp->dev, "No IRQ resource\n");
2316 ret = -ENODEV;
2a0a5472 2317 goto error_iommu;
448de7e7 2318 }
514580f9 2319 isp->irq_num = ret;
448de7e7 2320
cf2b4cf6
LP		 2321 if (devm_request_irq(isp->dev, isp->irq_num, isp_isr, IRQF_SHARED,
2322 "OMAP3 ISP", isp)) {
448de7e7
SA		 2323 dev_err(isp->dev, "Unable to request IRQ\n");
2324 ret = -EINVAL;
2a0a5472 2325 goto error_iommu;
448de7e7
SA		 2326 }
2327
2328 /* Entities */
2329 ret = isp_initialize_modules(isp);
2330 if (ret < 0)
2a0a5472 2331 goto error_iommu;
448de7e7
SA		 2332
2333 ret = isp_register_entities(isp);
2334 if (ret < 0)
2335 goto error_modules;
2336
b285d5af 2337 ret = isp_create_links(isp);
f2f6da0d
JMC		 2338 if (ret < 0)
2339 goto error_register_entities;
2340
b6ee3f0d 2341 isp->notifier.ops = &isp_subdev_notifier_ops;
5d479386 2342
78c66fbc
LP		 2343 ret = v4l2_async_notifier_register(&isp->v4l2_dev, &isp->notifier);
2344 if (ret)
2345 goto error_register_entities;
5d479386 2346
96d62ae2 2347 isp_core_init(isp, 1);
448de7e7
SA		 2348 omap3isp_put(isp);
2349
2350 return 0;
2351
5d479386
SA		 2352error_register_entities:
2353 isp_unregister_entities(isp);
448de7e7
SA		 2354error_modules:
2355 isp_cleanup_modules(isp);
2a0a5472
LP		 2356error_iommu:
2357 isp_detach_iommu(isp);
448de7e7 2358error_isp:
9b28ee3c 2359 isp_xclk_cleanup(isp);
2a0a5472 2360 __omap3isp_put(isp, false);
448de7e7 2361error:
df497566 2362 v4l2_async_notifier_cleanup(&isp->notifier);
ed33ac8e 2363 mutex_destroy(&isp->isp_mutex);
448de7e7
SA		 2364
2365 return ret;
2366}
2367
2368static const struct dev_pm_ops omap3isp_pm_ops = {
2369 .prepare = isp_pm_prepare,
2370 .suspend = isp_pm_suspend,
2371 .resume = isp_pm_resume,
2372 .complete = isp_pm_complete,
2373};
2374
2375static struct platform_device_id omap3isp_id_table[] = {
2376 { "omap3isp", 0 },
2377 { },
2378};
2379MODULE_DEVICE_TABLE(platform, omap3isp_id_table);
2380
da7f3843
SA		 2381static const struct of_device_id omap3isp_of_table[] = {
2382 { .compatible = "ti,omap3-isp" },
2383 { },
2384};
8163ec29 2385MODULE_DEVICE_TABLE(of, omap3isp_of_table);
da7f3843 2386
448de7e7
SA		 2387static struct platform_driver omap3isp_driver = {
2388 .probe = isp_probe,
4c62e976 2389 .remove = isp_remove,
448de7e7
SA		 2390 .id_table = omap3isp_id_table,
2391 .driver = {
448de7e7
SA		 2392 .name = "omap3isp",
2393 .pm = &omap3isp_pm_ops,
da7f3843 2394 .of_match_table = omap3isp_of_table,
448de7e7
SA		 2395 },
2396};
2397
1d6629b1 2398module_platform_driver(omap3isp_driver);
448de7e7
SA		 2399
2400MODULE_AUTHOR("Nokia Corporation");
2401MODULE_DESCRIPTION("TI OMAP3 ISP driver");
2402MODULE_LICENSE("GPL");
64dc3c1a 2403MODULE_VERSION(ISP_VIDEO_DRIVER_VERSION);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git