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[thirdparty/kernel/stable.git] / drivers / media / platform / omap3isp / isp.c
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d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
448de7e7
SA		 2/*
3 * isp.c
4 *
5 * TI OMAP3 ISP - Core
6 *
7 * Copyright (C) 2006-2010 Nokia Corporation
8 * Copyright (C) 2007-2009 Texas Instruments, Inc.
9 *
10 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 * Sakari Ailus <sakari.ailus@iki.fi>
12 *
13 * Contributors:
14 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
15 * Sakari Ailus <sakari.ailus@iki.fi>
16 * David Cohen <dacohen@gmail.com>
17 * Stanimir Varbanov <svarbanov@mm-sol.com>
18 * Vimarsh Zutshi <vimarsh.zutshi@gmail.com>
19 * Tuukka Toivonen <tuukkat76@gmail.com>
20 * Sergio Aguirre <saaguirre@ti.com>
21 * Antti Koskipaa <akoskipa@gmail.com>
22 * Ivan T. Ivanov <iivanov@mm-sol.com>
23 * RaniSuneela <r-m@ti.com>
24 * Atanas Filipov <afilipov@mm-sol.com>
25 * Gjorgji Rosikopulos <grosikopulos@mm-sol.com>
26 * Hiroshi DOYU <hiroshi.doyu@nokia.com>
27 * Nayden Kanchev <nkanchev@mm-sol.com>
28 * Phil Carmody <ext-phil.2.carmody@nokia.com>
29 * Artem Bityutskiy <artem.bityutskiy@nokia.com>
30 * Dominic Curran <dcurran@ti.com>
31 * Ilkka Myllyperkio <ilkka.myllyperkio@sofica.fi>
32 * Pallavi Kulkarni <p-kulkarni@ti.com>
33 * Vaibhav Hiremath <hvaibhav@ti.com>
34 * Mohit Jalori <mjalori@ti.com>
35 * Sameer Venkatraman <sameerv@ti.com>
36 * Senthilvadivu Guruswamy <svadivu@ti.com>
37 * Thara Gopinath <thara@ti.com>
38 * Toni Leinonen <toni.leinonen@nokia.com>
39 * Troy Laramy <t-laramy@ti.com>
448de7e7
SA		 40 */
41
42#include <asm/cacheflush.h>
43
44#include <linux/clk.h>
9b28ee3c 45#include <linux/clkdev.h>
448de7e7
SA		 46#include <linux/delay.h>
47#include <linux/device.h>
48#include <linux/dma-mapping.h>
49#include <linux/i2c.h>
50#include <linux/interrupt.h>
503596a1 51#include <linux/mfd/syscon.h>
448de7e7 52#include <linux/module.h>
c8d35c84 53#include <linux/omap-iommu.h>
448de7e7 54#include <linux/platform_device.h>
859969b3 55#include <linux/property.h>
448de7e7
SA		 56#include <linux/regulator/consumer.h>
57#include <linux/slab.h>
58#include <linux/sched.h>
59#include <linux/vmalloc.h>
60
24313113 61#ifdef CONFIG_ARM_DMA_USE_IOMMU
2a0a5472 62#include <asm/dma-iommu.h>
24313113 63#endif
2a0a5472 64
448de7e7 65#include <media/v4l2-common.h>
859969b3 66#include <media/v4l2-fwnode.h>
448de7e7 67#include <media/v4l2-device.h>
506a47eb 68#include <media/v4l2-mc.h>
448de7e7
SA		 69
70#include "isp.h"
71#include "ispreg.h"
72#include "ispccdc.h"
73#include "isppreview.h"
74#include "ispresizer.h"
75#include "ispcsi2.h"
76#include "ispccp2.h"
77#include "isph3a.h"
78#include "isphist.h"
79
80static unsigned int autoidle;
81module_param(autoidle, int, 0444);
82MODULE_PARM_DESC(autoidle, "Enable OMAP3ISP AUTOIDLE support");
83
84static void isp_save_ctx(struct isp_device *isp);
85
86static void isp_restore_ctx(struct isp_device *isp);
87
88static const struct isp_res_mapping isp_res_maps[] = {
89 {
90 .isp_rev = ISP_REVISION_2_0,
8644cdf9
SA		 91 .offset = {
92 /* first MMIO area */
93 0x0000, /* base, len 0x0070 */
94 0x0400, /* ccp2, len 0x01f0 */
95 0x0600, /* ccdc, len 0x00a8 */
96 0x0a00, /* hist, len 0x0048 */
97 0x0c00, /* h3a, len 0x0060 */
98 0x0e00, /* preview, len 0x00a0 */
99 0x1000, /* resizer, len 0x00ac */
100 0x1200, /* sbl, len 0x00fc */
101 /* second MMIO area */
102 0x0000, /* csi2a, len 0x0170 */
103 0x0170, /* csiphy2, len 0x000c */
104 },
503596a1 105 .phy_type = ISP_PHY_TYPE_3430,
448de7e7
SA		 106 },
107 {
108 .isp_rev = ISP_REVISION_15_0,
8644cdf9
SA		 109 .offset = {
110 /* first MMIO area */
111 0x0000, /* base, len 0x0070 */
112 0x0400, /* ccp2, len 0x01f0 */
113 0x0600, /* ccdc, len 0x00a8 */
114 0x0a00, /* hist, len 0x0048 */
115 0x0c00, /* h3a, len 0x0060 */
116 0x0e00, /* preview, len 0x00a0 */
117 0x1000, /* resizer, len 0x00ac */
118 0x1200, /* sbl, len 0x00fc */
119 /* second MMIO area */
120 0x0000, /* csi2a, len 0x0170 (1st area) */
121 0x0170, /* csiphy2, len 0x000c */
122 0x01c0, /* csi2a, len 0x0040 (2nd area) */
123 0x0400, /* csi2c, len 0x0170 (1st area) */
124 0x0570, /* csiphy1, len 0x000c */
125 0x05c0, /* csi2c, len 0x0040 (2nd area) */
126 },
503596a1 127 .phy_type = ISP_PHY_TYPE_3630,
448de7e7
SA		 128 },
129};
130
131/* Structure for saving/restoring ISP module registers */
132static struct isp_reg isp_reg_list[] = {
133 {OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0},
134 {OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0},
135 {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0},
136 {0, ISP_TOK_TERM, 0}
137};
138
139/*
140 * omap3isp_flush - Post pending L3 bus writes by doing a register readback
141 * @isp: OMAP3 ISP device
142 *
143 * In order to force posting of pending writes, we need to write and
144 * readback the same register, in this case the revision register.
145 *
146 * See this link for reference:
147 * http://www.mail-archive.com/linux-omap@vger.kernel.org/msg08149.html
148 */
149void omap3isp_flush(struct isp_device *isp)
150{
151 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
152 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
153}
154
9b28ee3c
LP		 155/* -----------------------------------------------------------------------------
156 * XCLK
157 */
158
159#define to_isp_xclk(_hw) container_of(_hw, struct isp_xclk, hw)
160
161static void isp_xclk_update(struct isp_xclk *xclk, u32 divider)
162{
163 switch (xclk->id) {
164 case ISP_XCLK_A:
165 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
166 ISPTCTRL_CTRL_DIVA_MASK,
167 divider << ISPTCTRL_CTRL_DIVA_SHIFT);
168 break;
169 case ISP_XCLK_B:
170 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
171 ISPTCTRL_CTRL_DIVB_MASK,
172 divider << ISPTCTRL_CTRL_DIVB_SHIFT);
173 break;
174 }
175}
176
177static int isp_xclk_prepare(struct clk_hw *hw)
178{
179 struct isp_xclk *xclk = to_isp_xclk(hw);
180
181 omap3isp_get(xclk->isp);
182
183 return 0;
184}
185
186static void isp_xclk_unprepare(struct clk_hw *hw)
187{
188 struct isp_xclk *xclk = to_isp_xclk(hw);
189
190 omap3isp_put(xclk->isp);
191}
192
193static int isp_xclk_enable(struct clk_hw *hw)
194{
195 struct isp_xclk *xclk = to_isp_xclk(hw);
196 unsigned long flags;
197
198 spin_lock_irqsave(&xclk->lock, flags);
199 isp_xclk_update(xclk, xclk->divider);
200 xclk->enabled = true;
201 spin_unlock_irqrestore(&xclk->lock, flags);
202
203 return 0;
204}
205
206static void isp_xclk_disable(struct clk_hw *hw)
207{
208 struct isp_xclk *xclk = to_isp_xclk(hw);
209 unsigned long flags;
210
211 spin_lock_irqsave(&xclk->lock, flags);
212 isp_xclk_update(xclk, 0);
213 xclk->enabled = false;
214 spin_unlock_irqrestore(&xclk->lock, flags);
215}
216
217static unsigned long isp_xclk_recalc_rate(struct clk_hw *hw,
218 unsigned long parent_rate)
219{
220 struct isp_xclk *xclk = to_isp_xclk(hw);
221
222 return parent_rate / xclk->divider;
223}
224
225static u32 isp_xclk_calc_divider(unsigned long *rate, unsigned long parent_rate)
226{
227 u32 divider;
228
229 if (*rate >= parent_rate) {
230 *rate = parent_rate;
231 return ISPTCTRL_CTRL_DIV_BYPASS;
232 }
233
aadec012
LP		 234 if (*rate == 0)
235 *rate = 1;
236
9b28ee3c
LP		 237 divider = DIV_ROUND_CLOSEST(parent_rate, *rate);
238 if (divider >= ISPTCTRL_CTRL_DIV_BYPASS)
239 divider = ISPTCTRL_CTRL_DIV_BYPASS - 1;
240
241 *rate = parent_rate / divider;
242 return divider;
243}
244
245static long isp_xclk_round_rate(struct clk_hw *hw, unsigned long rate,
246 unsigned long *parent_rate)
247{
248 isp_xclk_calc_divider(&rate, *parent_rate);
249 return rate;
250}
251
252static int isp_xclk_set_rate(struct clk_hw *hw, unsigned long rate,
253 unsigned long parent_rate)
254{
255 struct isp_xclk *xclk = to_isp_xclk(hw);
256 unsigned long flags;
257 u32 divider;
258
259 divider = isp_xclk_calc_divider(&rate, parent_rate);
260
261 spin_lock_irqsave(&xclk->lock, flags);
262
263 xclk->divider = divider;
264 if (xclk->enabled)
265 isp_xclk_update(xclk, divider);
266
267 spin_unlock_irqrestore(&xclk->lock, flags);
268
269 dev_dbg(xclk->isp->dev, "%s: cam_xclk%c set to %lu Hz (div %u)\n",
270 __func__, xclk->id == ISP_XCLK_A ? 'a' : 'b', rate, divider);
271 return 0;
272}
273
274static const struct clk_ops isp_xclk_ops = {
275 .prepare = isp_xclk_prepare,
276 .unprepare = isp_xclk_unprepare,
277 .enable = isp_xclk_enable,
278 .disable = isp_xclk_disable,
279 .recalc_rate = isp_xclk_recalc_rate,
280 .round_rate = isp_xclk_round_rate,
281 .set_rate = isp_xclk_set_rate,
282};
283
284static const char *isp_xclk_parent_name = "cam_mclk";
285
64904b57
LP		 286static struct clk *isp_xclk_src_get(struct of_phandle_args *clkspec, void *data)
287{
288 unsigned int idx = clkspec->args[0];
289 struct isp_device *isp = data;
290
291 if (idx >= ARRAY_SIZE(isp->xclks))
292 return ERR_PTR(-ENOENT);
293
294 return isp->xclks[idx].clk;
295}
296
9b28ee3c
LP		 297static int isp_xclk_init(struct isp_device *isp)
298{
64904b57 299 struct device_node *np = isp->dev->of_node;
6c33d826 300 struct clk_init_data init = {};
9b28ee3c
LP		 301 unsigned int i;
302
f8e2ff26
SN		 303 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i)
304 isp->xclks[i].clk = ERR_PTR(-EINVAL);
305
9b28ee3c
LP		 306 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
307 struct isp_xclk *xclk = &isp->xclks[i];
9b28ee3c
LP		 308
309 xclk->isp = isp;
310 xclk->id = i == 0 ? ISP_XCLK_A : ISP_XCLK_B;
311 xclk->divider = 1;
312 spin_lock_init(&xclk->lock);
313
314 init.name = i == 0 ? "cam_xclka" : "cam_xclkb";
315 init.ops = &isp_xclk_ops;
316 init.parent_names = &isp_xclk_parent_name;
317 init.num_parents = 1;
318
319 xclk->hw.init = &init;
f8e2ff26
SN		 320 /*
321 * The first argument is NULL in order to avoid circular
322 * reference, as this driver takes reference on the
323 * sensor subdevice modules and the sensors would take
324 * reference on this module through clk_get().
325 */
326 xclk->clk = clk_register(NULL, &xclk->hw);
327 if (IS_ERR(xclk->clk))
328 return PTR_ERR(xclk->clk);
9b28ee3c
LP		 329 }
330
64904b57
LP		 331 if (np)
332 of_clk_add_provider(np, isp_xclk_src_get, isp);
333
9b28ee3c
LP		 334 return 0;
335}
336
337static void isp_xclk_cleanup(struct isp_device *isp)
338{
64904b57 339 struct device_node *np = isp->dev->of_node;
9b28ee3c
LP		 340 unsigned int i;
341
64904b57
LP		 342 if (np)
343 of_clk_del_provider(np);
344
9b28ee3c
LP		 345 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
346 struct isp_xclk *xclk = &isp->xclks[i];
347
f8e2ff26
SN		 348 if (!IS_ERR(xclk->clk))
349 clk_unregister(xclk->clk);
9b28ee3c
LP		 350 }
351}
352
353/* -----------------------------------------------------------------------------
354 * Interrupts
355 */
356
448de7e7
SA		 357/*
358 * isp_enable_interrupts - Enable ISP interrupts.
359 * @isp: OMAP3 ISP device
360 */
361static void isp_enable_interrupts(struct isp_device *isp)
362{
363 static const u32 irq = IRQ0ENABLE_CSIA_IRQ
364 | IRQ0ENABLE_CSIB_IRQ
365 | IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ
366 | IRQ0ENABLE_CCDC_LSC_DONE_IRQ
367 | IRQ0ENABLE_CCDC_VD0_IRQ
368 | IRQ0ENABLE_CCDC_VD1_IRQ
369 | IRQ0ENABLE_HS_VS_IRQ
370 | IRQ0ENABLE_HIST_DONE_IRQ
371 | IRQ0ENABLE_H3A_AWB_DONE_IRQ
372 | IRQ0ENABLE_H3A_AF_DONE_IRQ
373 | IRQ0ENABLE_PRV_DONE_IRQ
374 | IRQ0ENABLE_RSZ_DONE_IRQ;
375
376 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
377 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
378}
379
380/*
381 * isp_disable_interrupts - Disable ISP interrupts.
382 * @isp: OMAP3 ISP device
383 */
384static void isp_disable_interrupts(struct isp_device *isp)
385{
386 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
387}
388
448de7e7 389/*
96d62ae2 390 * isp_core_init - ISP core settings
448de7e7
SA		 391 * @isp: OMAP3 ISP device
392 * @idle: Consider idle state.
393 *
25aeb418 394 * Set the power settings for the ISP and SBL bus and configure the HS/VS
96d62ae2
LP		 395 * interrupt source.
396 *
397 * We need to configure the HS/VS interrupt source before interrupts get
398 * enabled, as the sensor might be free-running and the ISP default setting
399 * (HS edge) would put an unnecessary burden on the CPU.
448de7e7 400 */
96d62ae2 401static void isp_core_init(struct isp_device *isp, int idle)
448de7e7
SA		 402{
403 isp_reg_writel(isp,
404 ((idle ? ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY :
405 ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY) <<
406 ISP_SYSCONFIG_MIDLEMODE_SHIFT) |
407 ((isp->revision == ISP_REVISION_15_0) ?
408 ISP_SYSCONFIG_AUTOIDLE : 0),
409 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
410
96d62ae2
LP		 411 isp_reg_writel(isp,
412 (isp->autoidle ? ISPCTRL_SBL_AUTOIDLE : 0) |
413 ISPCTRL_SYNC_DETECT_VSRISE,
414 OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
448de7e7
SA		 415}
416
417/*
418 * Configure the bridge and lane shifter. Valid inputs are
419 *
420 * CCDC_INPUT_PARALLEL: Parallel interface
421 * CCDC_INPUT_CSI2A: CSI2a receiver
422 * CCDC_INPUT_CCP2B: CCP2b receiver
423 * CCDC_INPUT_CSI2C: CSI2c receiver
424 *
425 * The bridge and lane shifter are configured according to the selected input
426 * and the ISP platform data.
427 */
428void omap3isp_configure_bridge(struct isp_device *isp,
429 enum ccdc_input_entity input,
68908747 430 const struct isp_parallel_cfg *parcfg,
c51364ca 431 unsigned int shift, unsigned int bridge)
448de7e7
SA		 432{
433 u32 ispctrl_val;
434
435 ispctrl_val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
436 ispctrl_val &= ~ISPCTRL_SHIFT_MASK;
437 ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
438 ispctrl_val &= ~ISPCTRL_PAR_SER_CLK_SEL_MASK;
439 ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_MASK;
c51364ca 440 ispctrl_val |= bridge;
448de7e7
SA		 441
442 switch (input) {
443 case CCDC_INPUT_PARALLEL:
444 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
68908747 445 ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
74d1e7c0 446 shift += parcfg->data_lane_shift;
448de7e7
SA		 447 break;
448
449 case CCDC_INPUT_CSI2A:
450 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA;
451 break;
452
453 case CCDC_INPUT_CCP2B:
454 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB;
455 break;
456
457 case CCDC_INPUT_CSI2C:
458 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIC;
459 break;
460
461 default:
462 return;
463 }
464
c09af044
MJ		 465 ispctrl_val |= ((shift/2) << ISPCTRL_SHIFT_SHIFT) & ISPCTRL_SHIFT_MASK;
466
448de7e7
SA		 467 isp_reg_writel(isp, ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
468}
469
448de7e7
SA		 470void omap3isp_hist_dma_done(struct isp_device *isp)
471{
472 if (omap3isp_ccdc_busy(&isp->isp_ccdc) ||
473 omap3isp_stat_pcr_busy(&isp->isp_hist)) {
474 /* Histogram cannot be enabled in this frame anymore */
475 atomic_set(&isp->isp_hist.buf_err, 1);
d26da990
MCC		 476 dev_dbg(isp->dev,
477 "hist: Out of synchronization with CCDC. Ignoring next buffer.\n");
448de7e7
SA		 478 }
479}
480
481static inline void isp_isr_dbg(struct isp_device *isp, u32 irqstatus)
482{
483 static const char *name[] = {
484 "CSIA_IRQ",
485 "res1",
486 "res2",
487 "CSIB_LCM_IRQ",
488 "CSIB_IRQ",
489 "res5",
490 "res6",
491 "res7",
492 "CCDC_VD0_IRQ",
493 "CCDC_VD1_IRQ",
494 "CCDC_VD2_IRQ",
495 "CCDC_ERR_IRQ",
496 "H3A_AF_DONE_IRQ",
497 "H3A_AWB_DONE_IRQ",
498 "res14",
499 "res15",
500 "HIST_DONE_IRQ",
501 "CCDC_LSC_DONE",
502 "CCDC_LSC_PREFETCH_COMPLETED",
503 "CCDC_LSC_PREFETCH_ERROR",
504 "PRV_DONE_IRQ",
505 "CBUFF_IRQ",
506 "res22",
507 "res23",
508 "RSZ_DONE_IRQ",
509 "OVF_IRQ",
510 "res26",
511 "res27",
512 "MMU_ERR_IRQ",
513 "OCP_ERR_IRQ",
514 "SEC_ERR_IRQ",
515 "HS_VS_IRQ",
516 };
517 int i;
518
6c20c635 519 dev_dbg(isp->dev, "ISP IRQ: ");
448de7e7
SA		 520
521 for (i = 0; i < ARRAY_SIZE(name); i++) {
522 if ((1 << i) & irqstatus)
523 printk(KERN_CONT "%s ", name[i]);
524 }
525 printk(KERN_CONT "\n");
526}
527
528static void isp_isr_sbl(struct isp_device *isp)
529{
530 struct device *dev = isp->dev;
875e2e3e 531 struct isp_pipeline *pipe;
448de7e7
SA		 532 u32 sbl_pcr;
533
534 /*
535 * Handle shared buffer logic overflows for video buffers.
536 * ISPSBL_PCR_CCDCPRV_2_RSZ_OVF can be safely ignored.
537 */
538 sbl_pcr = isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
539 isp_reg_writel(isp, sbl_pcr, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
540 sbl_pcr &= ~ISPSBL_PCR_CCDCPRV_2_RSZ_OVF;
541
542 if (sbl_pcr)
543 dev_dbg(dev, "SBL overflow (PCR = 0x%08x)\n", sbl_pcr);
544
875e2e3e
LP		 545 if (sbl_pcr & ISPSBL_PCR_CSIB_WBL_OVF) {
546 pipe = to_isp_pipeline(&isp->isp_ccp2.subdev.entity);
547 if (pipe != NULL)
548 pipe->error = true;
549 }
550
551 if (sbl_pcr & ISPSBL_PCR_CSIA_WBL_OVF) {
552 pipe = to_isp_pipeline(&isp->isp_csi2a.subdev.entity);
553 if (pipe != NULL)
554 pipe->error = true;
555 }
556
557 if (sbl_pcr & ISPSBL_PCR_CCDC_WBL_OVF) {
558 pipe = to_isp_pipeline(&isp->isp_ccdc.subdev.entity);
559 if (pipe != NULL)
560 pipe->error = true;
448de7e7
SA		 561 }
562
563 if (sbl_pcr & ISPSBL_PCR_PRV_WBL_OVF) {
875e2e3e
LP		 564 pipe = to_isp_pipeline(&isp->isp_prev.subdev.entity);
565 if (pipe != NULL)
566 pipe->error = true;
448de7e7
SA		 567 }
568
569 if (sbl_pcr & (ISPSBL_PCR_RSZ1_WBL_OVF
570 | ISPSBL_PCR_RSZ2_WBL_OVF
571 | ISPSBL_PCR_RSZ3_WBL_OVF
875e2e3e
LP		 572 | ISPSBL_PCR_RSZ4_WBL_OVF)) {
573 pipe = to_isp_pipeline(&isp->isp_res.subdev.entity);
574 if (pipe != NULL)
575 pipe->error = true;
576 }
448de7e7
SA		 577
578 if (sbl_pcr & ISPSBL_PCR_H3A_AF_WBL_OVF)
579 omap3isp_stat_sbl_overflow(&isp->isp_af);
580
581 if (sbl_pcr & ISPSBL_PCR_H3A_AEAWB_WBL_OVF)
582 omap3isp_stat_sbl_overflow(&isp->isp_aewb);
583}
584
585/*
586 * isp_isr - Interrupt Service Routine for Camera ISP module.
587 * @irq: Not used currently.
588 * @_isp: Pointer to the OMAP3 ISP device
589 *
590 * Handles the corresponding callback if plugged in.
448de7e7
SA		 591 */
592static irqreturn_t isp_isr(int irq, void *_isp)
593{
594 static const u32 ccdc_events = IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ |
595 IRQ0STATUS_CCDC_LSC_DONE_IRQ |
596 IRQ0STATUS_CCDC_VD0_IRQ |
597 IRQ0STATUS_CCDC_VD1_IRQ |
598 IRQ0STATUS_HS_VS_IRQ;
599 struct isp_device *isp = _isp;
600 u32 irqstatus;
448de7e7
SA		 601
602 irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
603 isp_reg_writel(isp, irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
604
605 isp_isr_sbl(isp);
606
875e2e3e
LP		 607 if (irqstatus & IRQ0STATUS_CSIA_IRQ)
608 omap3isp_csi2_isr(&isp->isp_csi2a);
448de7e7 609
875e2e3e
LP		 610 if (irqstatus & IRQ0STATUS_CSIB_IRQ)
611 omap3isp_ccp2_isr(&isp->isp_ccp2);
448de7e7
SA		 612
613 if (irqstatus & IRQ0STATUS_CCDC_VD0_IRQ) {
614 if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW)
615 omap3isp_preview_isr_frame_sync(&isp->isp_prev);
616 if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER)
617 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
618 omap3isp_stat_isr_frame_sync(&isp->isp_aewb);
619 omap3isp_stat_isr_frame_sync(&isp->isp_af);
620 omap3isp_stat_isr_frame_sync(&isp->isp_hist);
621 }
622
623 if (irqstatus & ccdc_events)
624 omap3isp_ccdc_isr(&isp->isp_ccdc, irqstatus & ccdc_events);
625
626 if (irqstatus & IRQ0STATUS_PRV_DONE_IRQ) {
627 if (isp->isp_prev.output & PREVIEW_OUTPUT_RESIZER)
628 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
629 omap3isp_preview_isr(&isp->isp_prev);
630 }
631
632 if (irqstatus & IRQ0STATUS_RSZ_DONE_IRQ)
633 omap3isp_resizer_isr(&isp->isp_res);
634
635 if (irqstatus & IRQ0STATUS_H3A_AWB_DONE_IRQ)
636 omap3isp_stat_isr(&isp->isp_aewb);
637
638 if (irqstatus & IRQ0STATUS_H3A_AF_DONE_IRQ)
639 omap3isp_stat_isr(&isp->isp_af);
640
641 if (irqstatus & IRQ0STATUS_HIST_DONE_IRQ)
642 omap3isp_stat_isr(&isp->isp_hist);
643
644 omap3isp_flush(isp);
645
646#if defined(DEBUG) && defined(ISP_ISR_DEBUG)
647 isp_isr_dbg(isp, irqstatus);
648#endif
649
650 return IRQ_HANDLED;
651}
652
68429f50
LP		 653static const struct media_device_ops isp_media_ops = {
654 .link_notify = v4l2_pipeline_link_notify,
655};
656
448de7e7
SA		 657/* -----------------------------------------------------------------------------
658 * Pipeline stream management
659 */
660
661/*
662 * isp_pipeline_enable - Enable streaming on a pipeline
663 * @pipe: ISP pipeline
664 * @mode: Stream mode (single shot or continuous)
665 *
666 * Walk the entities chain starting at the pipeline output video node and start
667 * all modules in the chain in the given mode.
668 *
25985edc 669 * Return 0 if successful, or the return value of the failed video::s_stream
448de7e7
SA		 670 * operation otherwise.
671 */
672static int isp_pipeline_enable(struct isp_pipeline *pipe,
673 enum isp_pipeline_stream_state mode)
674{
675 struct isp_device *isp = pipe->output->isp;
676 struct media_entity *entity;
677 struct media_pad *pad;
678 struct v4l2_subdev *subdev;
679 unsigned long flags;
c62e2a19 680 int ret;
448de7e7 681
112eee0c
LP		 682 /* Refuse to start streaming if an entity included in the pipeline has
683 * crashed. This check must be performed before the loop below to avoid
684 * starting entities if the pipeline won't start anyway (those entities
685 * would then likely fail to stop, making the problem worse).
1567bb7d 686 */
17d3d405 687 if (media_entity_enum_intersects(&pipe->ent_enum, &isp->crashed))
1567bb7d
LP		 688 return -EIO;
689
448de7e7
SA		 690 spin_lock_irqsave(&pipe->lock, flags);
691 pipe->state &= ~(ISP_PIPELINE_IDLE_INPUT | ISP_PIPELINE_IDLE_OUTPUT);
692 spin_unlock_irqrestore(&pipe->lock, flags);
693
694 pipe->do_propagation = false;
695
696 entity = &pipe->output->video.entity;
697 while (1) {
698 pad = &entity->pads[0];
699 if (!(pad->flags & MEDIA_PAD_FL_SINK))
700 break;
701
1bddf1b3 702 pad = media_entity_remote_pad(pad);
3efdf62c 703 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
448de7e7
SA		 704 break;
705
706 entity = pad->entity;
707 subdev = media_entity_to_v4l2_subdev(entity);
708
709 ret = v4l2_subdev_call(subdev, video, s_stream, mode);
710 if (ret < 0 && ret != -ENOIOCTLCMD)
c62e2a19 711 return ret;
448de7e7
SA		 712
713 if (subdev == &isp->isp_ccdc.subdev) {
714 v4l2_subdev_call(&isp->isp_aewb.subdev, video,
715 s_stream, mode);
716 v4l2_subdev_call(&isp->isp_af.subdev, video,
717 s_stream, mode);
718 v4l2_subdev_call(&isp->isp_hist.subdev, video,
719 s_stream, mode);
720 pipe->do_propagation = true;
721 }
722 }
723
c62e2a19 724 return 0;
448de7e7
SA		 725}
726
727static int isp_pipeline_wait_resizer(struct isp_device *isp)
728{
729 return omap3isp_resizer_busy(&isp->isp_res);
730}
731
732static int isp_pipeline_wait_preview(struct isp_device *isp)
733{
734 return omap3isp_preview_busy(&isp->isp_prev);
735}
736
737static int isp_pipeline_wait_ccdc(struct isp_device *isp)
738{
739 return omap3isp_stat_busy(&isp->isp_af)
740 || omap3isp_stat_busy(&isp->isp_aewb)
741 || omap3isp_stat_busy(&isp->isp_hist)
742 || omap3isp_ccdc_busy(&isp->isp_ccdc);
743}
744
745#define ISP_STOP_TIMEOUT msecs_to_jiffies(1000)
746
747static int isp_pipeline_wait(struct isp_device *isp,
748 int(*busy)(struct isp_device *isp))
749{
750 unsigned long timeout = jiffies + ISP_STOP_TIMEOUT;
751
752 while (!time_after(jiffies, timeout)) {
753 if (!busy(isp))
754 return 0;
755 }
756
757 return 1;
758}
759
760/*
761 * isp_pipeline_disable - Disable streaming on a pipeline
762 * @pipe: ISP pipeline
763 *
764 * Walk the entities chain starting at the pipeline output video node and stop
765 * all modules in the chain. Wait synchronously for the modules to be stopped if
766 * necessary.
767 *
768 * Return 0 if all modules have been properly stopped, or -ETIMEDOUT if a module
769 * can't be stopped (in which case a software reset of the ISP is probably
770 * necessary).
771 */
772static int isp_pipeline_disable(struct isp_pipeline *pipe)
773{
774 struct isp_device *isp = pipe->output->isp;
775 struct media_entity *entity;
776 struct media_pad *pad;
777 struct v4l2_subdev *subdev;
778 int failure = 0;
779 int ret;
780
781 /*
782 * We need to stop all the modules after CCDC first or they'll
783 * never stop since they may not get a full frame from CCDC.
784 */
785 entity = &pipe->output->video.entity;
786 while (1) {
787 pad = &entity->pads[0];
788 if (!(pad->flags & MEDIA_PAD_FL_SINK))
789 break;
790
1bddf1b3 791 pad = media_entity_remote_pad(pad);
3efdf62c 792 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
448de7e7
SA		 793 break;
794
795 entity = pad->entity;
796 subdev = media_entity_to_v4l2_subdev(entity);
797
798 if (subdev == &isp->isp_ccdc.subdev) {
799 v4l2_subdev_call(&isp->isp_aewb.subdev,
800 video, s_stream, 0);
801 v4l2_subdev_call(&isp->isp_af.subdev,
802 video, s_stream, 0);
803 v4l2_subdev_call(&isp->isp_hist.subdev,
804 video, s_stream, 0);
805 }
806
eb228e89 807 ret = v4l2_subdev_call(subdev, video, s_stream, 0);
448de7e7
SA		 808
809 if (subdev == &isp->isp_res.subdev)
eb228e89 810 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_resizer);
448de7e7 811 else if (subdev == &isp->isp_prev.subdev)
eb228e89 812 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_preview);
448de7e7 813 else if (subdev == &isp->isp_ccdc.subdev)
eb228e89 814 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_ccdc);
448de7e7 815
112eee0c
LP		 816 /* Handle stop failures. An entity that fails to stop can
817 * usually just be restarted. Flag the stop failure nonetheless
818 * to trigger an ISP reset the next time the device is released,
819 * just in case.
820 *
821 * The preview engine is a special case. A failure to stop can
822 * mean a hardware crash. When that happens the preview engine
823 * won't respond to read/write operations on the L4 bus anymore,
824 * resulting in a bus fault and a kernel oops next time it gets
825 * accessed. Mark it as crashed to prevent pipelines including
826 * it from being started.
827 */
448de7e7
SA		 828 if (ret) {
829 dev_info(isp->dev, "Unable to stop %s\n", subdev->name);
112eee0c 830 isp->stop_failure = true;
17d3d405
SA		 831 if (subdev == &isp->isp_prev.subdev)
832 media_entity_enum_set(&isp->crashed,
833 &subdev->entity);
448de7e7
SA		 834 failure = -ETIMEDOUT;
835 }
836 }
837
838 return failure;
839}
840
841/*
842 * omap3isp_pipeline_set_stream - Enable/disable streaming on a pipeline
843 * @pipe: ISP pipeline
844 * @state: Stream state (stopped, single shot or continuous)
845 *
846 * Set the pipeline to the given stream state. Pipelines can be started in
847 * single-shot or continuous mode.
848 *
25985edc 849 * Return 0 if successful, or the return value of the failed video::s_stream
994d5375
LP		 850 * operation otherwise. The pipeline state is not updated when the operation
851 * fails, except when stopping the pipeline.
448de7e7
SA		 852 */
853int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
854 enum isp_pipeline_stream_state state)
855{
856 int ret;
857
858 if (state == ISP_PIPELINE_STREAM_STOPPED)
859 ret = isp_pipeline_disable(pipe);
860 else
861 ret = isp_pipeline_enable(pipe, state);
994d5375
LP		 862
863 if (ret == 0 || state == ISP_PIPELINE_STREAM_STOPPED)
864 pipe->stream_state = state;
448de7e7
SA		 865
866 return ret;
867}
868
661112cb
LP		 869/*
870 * omap3isp_pipeline_cancel_stream - Cancel stream on a pipeline
871 * @pipe: ISP pipeline
872 *
873 * Cancelling a stream mark all buffers on all video nodes in the pipeline as
874 * erroneous and makes sure no new buffer can be queued. This function is called
875 * when a fatal error that prevents any further operation on the pipeline
876 * occurs.
877 */
878void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe)
879{
880 if (pipe->input)
881 omap3isp_video_cancel_stream(pipe->input);
882 if (pipe->output)
883 omap3isp_video_cancel_stream(pipe->output);
884}
885
448de7e7
SA		 886/*
887 * isp_pipeline_resume - Resume streaming on a pipeline
888 * @pipe: ISP pipeline
889 *
890 * Resume video output and input and re-enable pipeline.
891 */
892static void isp_pipeline_resume(struct isp_pipeline *pipe)
893{
894 int singleshot = pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT;
895
896 omap3isp_video_resume(pipe->output, !singleshot);
897 if (singleshot)
898 omap3isp_video_resume(pipe->input, 0);
899 isp_pipeline_enable(pipe, pipe->stream_state);
900}
901
902/*
903 * isp_pipeline_suspend - Suspend streaming on a pipeline
904 * @pipe: ISP pipeline
905 *
906 * Suspend pipeline.
907 */
908static void isp_pipeline_suspend(struct isp_pipeline *pipe)
909{
910 isp_pipeline_disable(pipe);
911}
912
913/*
914 * isp_pipeline_is_last - Verify if entity has an enabled link to the output
4a3fad70 915 * video node
448de7e7
SA		 916 * @me: ISP module's media entity
917 *
918 * Returns 1 if the entity has an enabled link to the output video node or 0
919 * otherwise. It's true only while pipeline can have no more than one output
920 * node.
921 */
922static int isp_pipeline_is_last(struct media_entity *me)
923{
924 struct isp_pipeline *pipe;
925 struct media_pad *pad;
926
927 if (!me->pipe)
928 return 0;
929 pipe = to_isp_pipeline(me);
930 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED)
931 return 0;
1bddf1b3 932 pad = media_entity_remote_pad(&pipe->output->pad);
448de7e7
SA		 933 return pad->entity == me;
934}
935
936/*
937 * isp_suspend_module_pipeline - Suspend pipeline to which belongs the module
938 * @me: ISP module's media entity
939 *
940 * Suspend the whole pipeline if module's entity has an enabled link to the
941 * output video node. It works only while pipeline can have no more than one
942 * output node.
943 */
944static void isp_suspend_module_pipeline(struct media_entity *me)
945{
946 if (isp_pipeline_is_last(me))
947 isp_pipeline_suspend(to_isp_pipeline(me));
948}
949
950/*
951 * isp_resume_module_pipeline - Resume pipeline to which belongs the module
952 * @me: ISP module's media entity
953 *
954 * Resume the whole pipeline if module's entity has an enabled link to the
955 * output video node. It works only while pipeline can have no more than one
956 * output node.
957 */
958static void isp_resume_module_pipeline(struct media_entity *me)
959{
960 if (isp_pipeline_is_last(me))
961 isp_pipeline_resume(to_isp_pipeline(me));
962}
963
964/*
965 * isp_suspend_modules - Suspend ISP submodules.
966 * @isp: OMAP3 ISP device
967 *
968 * Returns 0 if suspend left in idle state all the submodules properly,
969 * or returns 1 if a general Reset is required to suspend the submodules.
970 */
6f3de838 971static int __maybe_unused isp_suspend_modules(struct isp_device *isp)
448de7e7
SA		 972{
973 unsigned long timeout;
974
975 omap3isp_stat_suspend(&isp->isp_aewb);
976 omap3isp_stat_suspend(&isp->isp_af);
977 omap3isp_stat_suspend(&isp->isp_hist);
978 isp_suspend_module_pipeline(&isp->isp_res.subdev.entity);
979 isp_suspend_module_pipeline(&isp->isp_prev.subdev.entity);
980 isp_suspend_module_pipeline(&isp->isp_ccdc.subdev.entity);
981 isp_suspend_module_pipeline(&isp->isp_csi2a.subdev.entity);
982 isp_suspend_module_pipeline(&isp->isp_ccp2.subdev.entity);
983
984 timeout = jiffies + ISP_STOP_TIMEOUT;
985 while (omap3isp_stat_busy(&isp->isp_af)
986 || omap3isp_stat_busy(&isp->isp_aewb)
987 || omap3isp_stat_busy(&isp->isp_hist)
988 || omap3isp_preview_busy(&isp->isp_prev)
989 || omap3isp_resizer_busy(&isp->isp_res)
990 || omap3isp_ccdc_busy(&isp->isp_ccdc)) {
991 if (time_after(jiffies, timeout)) {
992 dev_info(isp->dev, "can't stop modules.\n");
993 return 1;
994 }
995 msleep(1);
996 }
997
998 return 0;
999}
1000
1001/*
1002 * isp_resume_modules - Resume ISP submodules.
1003 * @isp: OMAP3 ISP device
1004 */
6f3de838 1005static void __maybe_unused isp_resume_modules(struct isp_device *isp)
448de7e7
SA		 1006{
1007 omap3isp_stat_resume(&isp->isp_aewb);
1008 omap3isp_stat_resume(&isp->isp_af);
1009 omap3isp_stat_resume(&isp->isp_hist);
1010 isp_resume_module_pipeline(&isp->isp_res.subdev.entity);
1011 isp_resume_module_pipeline(&isp->isp_prev.subdev.entity);
1012 isp_resume_module_pipeline(&isp->isp_ccdc.subdev.entity);
1013 isp_resume_module_pipeline(&isp->isp_csi2a.subdev.entity);
1014 isp_resume_module_pipeline(&isp->isp_ccp2.subdev.entity);
1015}
1016
1017/*
1018 * isp_reset - Reset ISP with a timeout wait for idle.
1019 * @isp: OMAP3 ISP device
1020 */
1021static int isp_reset(struct isp_device *isp)
1022{
1023 unsigned long timeout = 0;
1024
1025 isp_reg_writel(isp,
1026 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG)
1027 | ISP_SYSCONFIG_SOFTRESET,
1028 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
1029 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN,
1030 ISP_SYSSTATUS) & 0x1)) {
1031 if (timeout++ > 10000) {
1032 dev_alert(isp->dev, "cannot reset ISP\n");
1033 return -ETIMEDOUT;
1034 }
1035 udelay(1);
1036 }
1037
112eee0c 1038 isp->stop_failure = false;
17d3d405 1039 media_entity_enum_zero(&isp->crashed);
448de7e7
SA		 1040 return 0;
1041}
1042
1043/*
1044 * isp_save_context - Saves the values of the ISP module registers.
1045 * @isp: OMAP3 ISP device
1046 * @reg_list: Structure containing pairs of register address and value to
1047 * modify on OMAP.
1048 */
1049static void
1050isp_save_context(struct isp_device *isp, struct isp_reg *reg_list)
1051{
1052 struct isp_reg *next = reg_list;
1053
1054 for (; next->reg != ISP_TOK_TERM; next++)
1055 next->val = isp_reg_readl(isp, next->mmio_range, next->reg);
1056}
1057
1058/*
1059 * isp_restore_context - Restores the values of the ISP module registers.
1060 * @isp: OMAP3 ISP device
1061 * @reg_list: Structure containing pairs of register address and value to
1062 * modify on OMAP.
1063 */
1064static void
1065isp_restore_context(struct isp_device *isp, struct isp_reg *reg_list)
1066{
1067 struct isp_reg *next = reg_list;
1068
1069 for (; next->reg != ISP_TOK_TERM; next++)
1070 isp_reg_writel(isp, next->val, next->mmio_range, next->reg);
1071}
1072
1073/*
1074 * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1075 * @isp: OMAP3 ISP device
1076 *
1077 * Routine for saving the context of each module in the ISP.
1078 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1079 */
1080static void isp_save_ctx(struct isp_device *isp)
1081{
1082 isp_save_context(isp, isp_reg_list);
fabdbca8 1083 omap_iommu_save_ctx(isp->dev);
448de7e7
SA		 1084}
1085
1086/*
1087 * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1088 * @isp: OMAP3 ISP device
1089 *
1090 * Routine for restoring the context of each module in the ISP.
1091 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1092 */
1093static void isp_restore_ctx(struct isp_device *isp)
1094{
1095 isp_restore_context(isp, isp_reg_list);
fabdbca8 1096 omap_iommu_restore_ctx(isp->dev);
448de7e7
SA		 1097 omap3isp_ccdc_restore_context(isp);
1098 omap3isp_preview_restore_context(isp);
1099}
1100
1101/* -----------------------------------------------------------------------------
1102 * SBL resources management
1103 */
1104#define OMAP3_ISP_SBL_READ (OMAP3_ISP_SBL_CSI1_READ | \
1105 OMAP3_ISP_SBL_CCDC_LSC_READ | \
1106 OMAP3_ISP_SBL_PREVIEW_READ | \
1107 OMAP3_ISP_SBL_RESIZER_READ)
1108#define OMAP3_ISP_SBL_WRITE (OMAP3_ISP_SBL_CSI1_WRITE | \
1109 OMAP3_ISP_SBL_CSI2A_WRITE | \
1110 OMAP3_ISP_SBL_CSI2C_WRITE | \
1111 OMAP3_ISP_SBL_CCDC_WRITE | \
1112 OMAP3_ISP_SBL_PREVIEW_WRITE)
1113
1114void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res)
1115{
1116 u32 sbl = 0;
1117
1118 isp->sbl_resources |= res;
1119
1120 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ)
1121 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1122
1123 if (isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ)
1124 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1125
1126 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE)
1127 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1128
1129 if (isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE)
1130 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1131
1132 if (isp->sbl_resources & OMAP3_ISP_SBL_WRITE)
1133 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1134
1135 if (isp->sbl_resources & OMAP3_ISP_SBL_READ)
1136 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1137
1138 isp_reg_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1139}
1140
1141void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res)
1142{
1143 u32 sbl = 0;
1144
1145 isp->sbl_resources &= ~res;
1146
1147 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ))
1148 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1149
1150 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ))
1151 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1152
1153 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE))
1154 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1155
1156 if (!(isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE))
1157 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1158
1159 if (!(isp->sbl_resources & OMAP3_ISP_SBL_WRITE))
1160 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1161
1162 if (!(isp->sbl_resources & OMAP3_ISP_SBL_READ))
1163 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1164
1165 isp_reg_clr(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1166}
1167
1168/*
1169 * isp_module_sync_idle - Helper to sync module with its idle state
1170 * @me: ISP submodule's media entity
1171 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1172 * @stopping: flag which tells module wants to stop
1173 *
1174 * This function checks if ISP submodule needs to wait for next interrupt. If
1175 * yes, makes the caller to sleep while waiting for such event.
1176 */
1177int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
1178 atomic_t *stopping)
1179{
1180 struct isp_pipeline *pipe = to_isp_pipeline(me);
1181
1182 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED ||
1183 (pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1184 !isp_pipeline_ready(pipe)))
1185 return 0;
1186
1187 /*
1188 * atomic_set() doesn't include memory barrier on ARM platform for SMP
1189 * scenario. We'll call it here to avoid race conditions.
1190 */
1191 atomic_set(stopping, 1);
1192 smp_mb();
1193
1194 /*
1195 * If module is the last one, it's writing to memory. In this case,
1196 * it's necessary to check if the module is already paused due to
1197 * DMA queue underrun or if it has to wait for next interrupt to be
1198 * idle.
1199 * If it isn't the last one, the function won't sleep but *stopping
1200 * will still be set to warn next submodule caller's interrupt the
1201 * module wants to be idle.
1202 */
1203 if (isp_pipeline_is_last(me)) {
1204 struct isp_video *video = pipe->output;
1205 unsigned long flags;
e8feb876 1206 spin_lock_irqsave(&video->irqlock, flags);
448de7e7 1207 if (video->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
e8feb876 1208 spin_unlock_irqrestore(&video->irqlock, flags);
448de7e7
SA		 1209 atomic_set(stopping, 0);
1210 smp_mb();
1211 return 0;
1212 }
e8feb876 1213 spin_unlock_irqrestore(&video->irqlock, flags);
448de7e7
SA		 1214 if (!wait_event_timeout(*wait, !atomic_read(stopping),
1215 msecs_to_jiffies(1000))) {
1216 atomic_set(stopping, 0);
1217 smp_mb();
1218 return -ETIMEDOUT;
1219 }
1220 }
1221
1222 return 0;
1223}
1224
1225/*
1e9c4d49 1226 * omap3isp_module_sync_is_stopping - Helper to verify if module was stopping
448de7e7
SA		 1227 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1228 * @stopping: flag which tells module wants to stop
1229 *
1230 * This function checks if ISP submodule was stopping. In case of yes, it
1231 * notices the caller by setting stopping to 0 and waking up the wait queue.
1232 * Returns 1 if it was stopping or 0 otherwise.
1233 */
1234int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
1235 atomic_t *stopping)
1236{
1237 if (atomic_cmpxchg(stopping, 1, 0)) {
1238 wake_up(wait);
1239 return 1;
1240 }
1241
1242 return 0;
1243}
1244
1245/* --------------------------------------------------------------------------
1246 * Clock management
1247 */
1248
1249#define ISPCTRL_CLKS_MASK (ISPCTRL_H3A_CLK_EN | \
1250 ISPCTRL_HIST_CLK_EN | \
1251 ISPCTRL_RSZ_CLK_EN | \
1252 (ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN) | \
1253 (ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN))
1254
1255static void __isp_subclk_update(struct isp_device *isp)
1256{
1257 u32 clk = 0;
1258
be9a1b98
LP		 1259 /* AEWB and AF share the same clock. */
1260 if (isp->subclk_resources &
1261 (OMAP3_ISP_SUBCLK_AEWB | OMAP3_ISP_SUBCLK_AF))
448de7e7
SA		 1262 clk |= ISPCTRL_H3A_CLK_EN;
1263
1264 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_HIST)
1265 clk |= ISPCTRL_HIST_CLK_EN;
1266
1267 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_RESIZER)
1268 clk |= ISPCTRL_RSZ_CLK_EN;
1269
1270 /* NOTE: For CCDC & Preview submodules, we need to affect internal
25985edc 1271 * RAM as well.
448de7e7
SA		 1272 */
1273 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_CCDC)
1274 clk |= ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN;
1275
1276 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_PREVIEW)
1277 clk |= ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN;
1278
1279 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
1280 ISPCTRL_CLKS_MASK, clk);
1281}
1282
1283void omap3isp_subclk_enable(struct isp_device *isp,
1284 enum isp_subclk_resource res)
1285{
1286 isp->subclk_resources |= res;
1287
1288 __isp_subclk_update(isp);
1289}
1290
1291void omap3isp_subclk_disable(struct isp_device *isp,
1292 enum isp_subclk_resource res)
1293{
1294 isp->subclk_resources &= ~res;
1295
1296 __isp_subclk_update(isp);
1297}
1298
1299/*
1300 * isp_enable_clocks - Enable ISP clocks
1301 * @isp: OMAP3 ISP device
1302 *
b057c3c3
LP		 1303 * Return 0 if successful, or clk_prepare_enable return value if any of them
1304 * fails.
448de7e7
SA		 1305 */
1306static int isp_enable_clocks(struct isp_device *isp)
1307{
1308 int r;
1309 unsigned long rate;
448de7e7 1310
b057c3c3 1311 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]);
448de7e7 1312 if (r) {
b057c3c3 1313 dev_err(isp->dev, "failed to enable cam_ick clock\n");
448de7e7
SA		 1314 goto out_clk_enable_ick;
1315 }
6d1aa02f 1316 r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ);
448de7e7 1317 if (r) {
6d1aa02f 1318 dev_err(isp->dev, "clk_set_rate for cam_mclk failed\n");
448de7e7
SA		 1319 goto out_clk_enable_mclk;
1320 }
b057c3c3 1321 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
448de7e7 1322 if (r) {
b057c3c3 1323 dev_err(isp->dev, "failed to enable cam_mclk clock\n");
448de7e7
SA		 1324 goto out_clk_enable_mclk;
1325 }
1326 rate = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
1327 if (rate != CM_CAM_MCLK_HZ)
1328 dev_warn(isp->dev, "unexpected cam_mclk rate:\n"
1329 " expected : %d\n"
1330 " actual : %ld\n", CM_CAM_MCLK_HZ, rate);
b057c3c3 1331 r = clk_prepare_enable(isp->clock[ISP_CLK_CSI2_FCK]);
448de7e7 1332 if (r) {
b057c3c3 1333 dev_err(isp->dev, "failed to enable csi2_fck clock\n");
448de7e7
SA		 1334 goto out_clk_enable_csi2_fclk;
1335 }
1336 return 0;
1337
1338out_clk_enable_csi2_fclk:
b057c3c3 1339 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
448de7e7 1340out_clk_enable_mclk:
b057c3c3 1341 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
448de7e7
SA		 1342out_clk_enable_ick:
1343 return r;
1344}
1345
1346/*
1347 * isp_disable_clocks - Disable ISP clocks
1348 * @isp: OMAP3 ISP device
1349 */
1350static void isp_disable_clocks(struct isp_device *isp)
1351{
b057c3c3
LP		 1352 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
1353 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
1354 clk_disable_unprepare(isp->clock[ISP_CLK_CSI2_FCK]);
448de7e7
SA		 1355}
1356
1357static const char *isp_clocks[] = {
1358 "cam_ick",
1359 "cam_mclk",
448de7e7
SA		 1360 "csi2_96m_fck",
1361 "l3_ick",
1362};
1363
448de7e7
SA		 1364static int isp_get_clocks(struct isp_device *isp)
1365{
1366 struct clk *clk;
1367 unsigned int i;
1368
1369 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
cf2b4cf6 1370 clk = devm_clk_get(isp->dev, isp_clocks[i]);
448de7e7
SA		 1371 if (IS_ERR(clk)) {
1372 dev_err(isp->dev, "clk_get %s failed\n", isp_clocks[i]);
448de7e7
SA		 1373 return PTR_ERR(clk);
1374 }
1375
1376 isp->clock[i] = clk;
1377 }
1378
1379 return 0;
1380}
1381
1382/*
1383 * omap3isp_get - Acquire the ISP resource.
1384 *
1385 * Initializes the clocks for the first acquire.
1386 *
1387 * Increment the reference count on the ISP. If the first reference is taken,
1388 * enable clocks and power-up all submodules.
1389 *
25985edc 1390 * Return a pointer to the ISP device structure, or NULL if an error occurred.
448de7e7 1391 */
96d62ae2 1392static struct isp_device *__omap3isp_get(struct isp_device *isp, bool irq)
448de7e7
SA		 1393{
1394 struct isp_device *__isp = isp;
1395
1396 if (isp == NULL)
1397 return NULL;
1398
1399 mutex_lock(&isp->isp_mutex);
1400 if (isp->ref_count > 0)
1401 goto out;
1402
1403 if (isp_enable_clocks(isp) < 0) {
1404 __isp = NULL;
1405 goto out;
1406 }
1407
1408 /* We don't want to restore context before saving it! */
1409 if (isp->has_context)
1410 isp_restore_ctx(isp);
448de7e7 1411
96d62ae2
LP		 1412 if (irq)
1413 isp_enable_interrupts(isp);
448de7e7
SA		 1414
1415out:
1416 if (__isp != NULL)
1417 isp->ref_count++;
1418 mutex_unlock(&isp->isp_mutex);
1419
1420 return __isp;
1421}
1422
96d62ae2
LP		 1423struct isp_device *omap3isp_get(struct isp_device *isp)
1424{
1425 return __omap3isp_get(isp, true);
1426}
1427
448de7e7
SA		 1428/*
1429 * omap3isp_put - Release the ISP
1430 *
1431 * Decrement the reference count on the ISP. If the last reference is released,
1432 * power-down all submodules, disable clocks and free temporary buffers.
1433 */
2a0a5472 1434static void __omap3isp_put(struct isp_device *isp, bool save_ctx)
448de7e7
SA		 1435{
1436 if (isp == NULL)
1437 return;
1438
1439 mutex_lock(&isp->isp_mutex);
1440 BUG_ON(isp->ref_count == 0);
1441 if (--isp->ref_count == 0) {
1442 isp_disable_interrupts(isp);
2a0a5472 1443 if (save_ctx) {
a32f2f90 1444 isp_save_ctx(isp);
96d62ae2
LP		 1445 isp->has_context = 1;
1446 }
1567bb7d
LP		 1447 /* Reset the ISP if an entity has failed to stop. This is the
1448 * only way to recover from such conditions.
1449 */
17d3d405
SA		 1450 if (!media_entity_enum_empty(&isp->crashed) ||
1451 isp->stop_failure)
994d5375 1452 isp_reset(isp);
448de7e7
SA		 1453 isp_disable_clocks(isp);
1454 }
1455 mutex_unlock(&isp->isp_mutex);
1456}
1457
2a0a5472
LP		 1458void omap3isp_put(struct isp_device *isp)
1459{
1460 __omap3isp_put(isp, true);
1461}
1462
448de7e7
SA		 1463/* --------------------------------------------------------------------------
1464 * Platform device driver
1465 */
1466
1467/*
1468 * omap3isp_print_status - Prints the values of the ISP Control Module registers
1469 * @isp: OMAP3 ISP device
1470 */
1471#define ISP_PRINT_REGISTER(isp, name)\
1472 dev_dbg(isp->dev, "###ISP " #name "=0x%08x\n", \
1473 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_##name))
1474#define SBL_PRINT_REGISTER(isp, name)\
1475 dev_dbg(isp->dev, "###SBL " #name "=0x%08x\n", \
1476 isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_##name))
1477
1478void omap3isp_print_status(struct isp_device *isp)
1479{
1480 dev_dbg(isp->dev, "-------------ISP Register dump--------------\n");
1481
1482 ISP_PRINT_REGISTER(isp, SYSCONFIG);
1483 ISP_PRINT_REGISTER(isp, SYSSTATUS);
1484 ISP_PRINT_REGISTER(isp, IRQ0ENABLE);
1485 ISP_PRINT_REGISTER(isp, IRQ0STATUS);
1486 ISP_PRINT_REGISTER(isp, TCTRL_GRESET_LENGTH);
1487 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_REPLAY);
1488 ISP_PRINT_REGISTER(isp, CTRL);
1489 ISP_PRINT_REGISTER(isp, TCTRL_CTRL);
1490 ISP_PRINT_REGISTER(isp, TCTRL_FRAME);
1491 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_DELAY);
1492 ISP_PRINT_REGISTER(isp, TCTRL_STRB_DELAY);
1493 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_DELAY);
1494 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_LENGTH);
1495 ISP_PRINT_REGISTER(isp, TCTRL_STRB_LENGTH);
1496 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_LENGTH);
1497
1498 SBL_PRINT_REGISTER(isp, PCR);
1499 SBL_PRINT_REGISTER(isp, SDR_REQ_EXP);
1500
1501 dev_dbg(isp->dev, "--------------------------------------------\n");
1502}
1503
1504#ifdef CONFIG_PM
1505
1506/*
1507 * Power management support.
1508 *
1509 * As the ISP can't properly handle an input video stream interruption on a non
1510 * frame boundary, the ISP pipelines need to be stopped before sensors get
1511 * suspended. However, as suspending the sensors can require a running clock,
1512 * which can be provided by the ISP, the ISP can't be completely suspended
1513 * before the sensor.
1514 *
1515 * To solve this problem power management support is split into prepare/complete
1516 * and suspend/resume operations. The pipelines are stopped in prepare() and the
8b72c18d 1517 * ISP clocks get disabled in suspend(). Similarly, the clocks are re-enabled in
448de7e7
SA		 1518 * resume(), and the the pipelines are restarted in complete().
1519 *
39c1cb2b 1520 * TODO: PM dependencies between the ISP and sensors are not modelled explicitly
448de7e7
SA		 1521 * yet.
1522 */
1523static int isp_pm_prepare(struct device *dev)
1524{
1525 struct isp_device *isp = dev_get_drvdata(dev);
1526 int reset;
1527
1528 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1529
1530 if (isp->ref_count == 0)
1531 return 0;
1532
1533 reset = isp_suspend_modules(isp);
1534 isp_disable_interrupts(isp);
1535 isp_save_ctx(isp);
1536 if (reset)
1537 isp_reset(isp);
1538
1539 return 0;
1540}
1541
1542static int isp_pm_suspend(struct device *dev)
1543{
1544 struct isp_device *isp = dev_get_drvdata(dev);
1545
1546 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1547
1548 if (isp->ref_count)
1549 isp_disable_clocks(isp);
1550
1551 return 0;
1552}
1553
1554static int isp_pm_resume(struct device *dev)
1555{
1556 struct isp_device *isp = dev_get_drvdata(dev);
1557
1558 if (isp->ref_count == 0)
1559 return 0;
1560
1561 return isp_enable_clocks(isp);
1562}
1563
1564static void isp_pm_complete(struct device *dev)
1565{
1566 struct isp_device *isp = dev_get_drvdata(dev);
1567
1568 if (isp->ref_count == 0)
1569 return;
1570
1571 isp_restore_ctx(isp);
1572 isp_enable_interrupts(isp);
1573 isp_resume_modules(isp);
1574}
1575
1576#else
1577
1578#define isp_pm_prepare NULL
1579#define isp_pm_suspend NULL
1580#define isp_pm_resume NULL
1581#define isp_pm_complete NULL
1582
1583#endif /* CONFIG_PM */
1584
1585static void isp_unregister_entities(struct isp_device *isp)
1586{
30efae3d
SA		 1587 media_device_unregister(&isp->media_dev);
1588
448de7e7
SA		 1589 omap3isp_csi2_unregister_entities(&isp->isp_csi2a);
1590 omap3isp_ccp2_unregister_entities(&isp->isp_ccp2);
1591 omap3isp_ccdc_unregister_entities(&isp->isp_ccdc);
1592 omap3isp_preview_unregister_entities(&isp->isp_prev);
1593 omap3isp_resizer_unregister_entities(&isp->isp_res);
1594 omap3isp_stat_unregister_entities(&isp->isp_aewb);
1595 omap3isp_stat_unregister_entities(&isp->isp_af);
1596 omap3isp_stat_unregister_entities(&isp->isp_hist);
1597
1598 v4l2_device_unregister(&isp->v4l2_dev);
9832e155 1599 media_device_cleanup(&isp->media_dev);
448de7e7
SA		 1600}
1601
703e6f62
SA		 1602static int isp_link_entity(
1603 struct isp_device *isp, struct media_entity *entity,
1604 enum isp_interface_type interface)
1605{
1606 struct media_entity *input;
1607 unsigned int flags;
1608 unsigned int pad;
1609 unsigned int i;
1610
1611 /* Connect the sensor to the correct interface module.
1612 * Parallel sensors are connected directly to the CCDC, while
1613 * serial sensors are connected to the CSI2a, CCP2b or CSI2c
1614 * receiver through CSIPHY1 or CSIPHY2.
1615 */
1616 switch (interface) {
1617 case ISP_INTERFACE_PARALLEL:
1618 input = &isp->isp_ccdc.subdev.entity;
1619 pad = CCDC_PAD_SINK;
1620 flags = 0;
1621 break;
1622
1623 case ISP_INTERFACE_CSI2A_PHY2:
1624 input = &isp->isp_csi2a.subdev.entity;
1625 pad = CSI2_PAD_SINK;
1626 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
1627 break;
1628
1629 case ISP_INTERFACE_CCP2B_PHY1:
1630 case ISP_INTERFACE_CCP2B_PHY2:
1631 input = &isp->isp_ccp2.subdev.entity;
1632 pad = CCP2_PAD_SINK;
1633 flags = 0;
1634 break;
1635
1636 case ISP_INTERFACE_CSI2C_PHY1:
1637 input = &isp->isp_csi2c.subdev.entity;
1638 pad = CSI2_PAD_SINK;
1639 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
1640 break;
1641
1642 default:
1643 dev_err(isp->dev, "%s: invalid interface type %u\n", __func__,
1644 interface);
1645 return -EINVAL;
1646 }
1647
1648 /*
1649 * Not all interfaces are available on all revisions of the
1650 * ISP. The sub-devices of those interfaces aren't initialised
1651 * in such a case. Check this by ensuring the num_pads is
1652 * non-zero.
1653 */
1654 if (!input->num_pads) {
1655 dev_err(isp->dev, "%s: invalid input %u\n", entity->name,
1656 interface);
1657 return -EINVAL;
1658 }
1659
1660 for (i = 0; i < entity->num_pads; i++) {
1661 if (entity->pads[i].flags & MEDIA_PAD_FL_SOURCE)
1662 break;
1663 }
1664 if (i == entity->num_pads) {
bce9e317
SA		 1665 dev_err(isp->dev, "%s: no source pad in external entity %s\n",
1666 __func__, entity->name);
703e6f62
SA		 1667 return -EINVAL;
1668 }
1669
8df00a15 1670 return media_create_pad_link(entity, i, input, pad, flags);
703e6f62
SA		 1671}
1672
448de7e7
SA		 1673static int isp_register_entities(struct isp_device *isp)
1674{
448de7e7
SA		 1675 int ret;
1676
1677 isp->media_dev.dev = isp->dev;
c0decac1 1678 strscpy(isp->media_dev.model, "TI OMAP3 ISP",
448de7e7 1679 sizeof(isp->media_dev.model));
083eb078 1680 isp->media_dev.hw_revision = isp->revision;
68429f50 1681 isp->media_dev.ops = &isp_media_ops;
9832e155 1682 media_device_init(&isp->media_dev);
448de7e7
SA		 1683
1684 isp->v4l2_dev.mdev = &isp->media_dev;
1685 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
1686 if (ret < 0) {
4feca39b 1687 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
448de7e7
SA		 1688 __func__, ret);
1689 goto done;
1690 }
1691
1692 /* Register internal entities */
1693 ret = omap3isp_ccp2_register_entities(&isp->isp_ccp2, &isp->v4l2_dev);
1694 if (ret < 0)
1695 goto done;
1696
1697 ret = omap3isp_csi2_register_entities(&isp->isp_csi2a, &isp->v4l2_dev);
1698 if (ret < 0)
1699 goto done;
1700
1701 ret = omap3isp_ccdc_register_entities(&isp->isp_ccdc, &isp->v4l2_dev);
1702 if (ret < 0)
1703 goto done;
1704
1705 ret = omap3isp_preview_register_entities(&isp->isp_prev,
1706 &isp->v4l2_dev);
1707 if (ret < 0)
1708 goto done;
1709
1710 ret = omap3isp_resizer_register_entities(&isp->isp_res, &isp->v4l2_dev);
1711 if (ret < 0)
1712 goto done;
1713
1714 ret = omap3isp_stat_register_entities(&isp->isp_aewb, &isp->v4l2_dev);
1715 if (ret < 0)
1716 goto done;
1717
1718 ret = omap3isp_stat_register_entities(&isp->isp_af, &isp->v4l2_dev);
1719 if (ret < 0)
1720 goto done;
1721
1722 ret = omap3isp_stat_register_entities(&isp->isp_hist, &isp->v4l2_dev);
1723 if (ret < 0)
1724 goto done;
1725
448de7e7 1726done:
5d479386 1727 if (ret < 0)
448de7e7
SA		 1728 isp_unregister_entities(isp);
1729
1730 return ret;
1731}
1732
f2f6da0d 1733/*
b285d5af 1734 * isp_create_links() - Create links for internal and external ISP entities
f2f6da0d 1735 * @isp : Pointer to ISP device
b285d5af
JMC		 1736 *
1737 * This function creates all links between ISP internal and external entities.
1738 *
1739 * Return: A negative error code on failure or zero on success. Possible error
1740 * codes are those returned by media_create_pad_link().
f2f6da0d 1741 */
b285d5af 1742static int isp_create_links(struct isp_device *isp)
f2f6da0d
JMC		 1743{
1744 int ret;
1745
b5f6df06
JMC		 1746 /* Create links between entities and video nodes. */
1747 ret = media_create_pad_link(
1748 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1749 &isp->isp_csi2a.video_out.video.entity, 0, 0);
1750 if (ret < 0)
f2f6da0d 1751 return ret;
f2f6da0d 1752
b5f6df06
JMC		 1753 ret = media_create_pad_link(
1754 &isp->isp_ccp2.video_in.video.entity, 0,
1755 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SINK, 0);
1756 if (ret < 0)
f2f6da0d 1757 return ret;
f2f6da0d 1758
b5f6df06
JMC		 1759 ret = media_create_pad_link(
1760 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1761 &isp->isp_ccdc.video_out.video.entity, 0, 0);
1762 if (ret < 0)
f2f6da0d 1763 return ret;
f2f6da0d 1764
b5f6df06
JMC		 1765 ret = media_create_pad_link(
1766 &isp->isp_prev.video_in.video.entity, 0,
1767 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1768 if (ret < 0)
f2f6da0d 1769 return ret;
f2f6da0d 1770
b5f6df06
JMC		 1771 ret = media_create_pad_link(
1772 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1773 &isp->isp_prev.video_out.video.entity, 0, 0);
1774 if (ret < 0)
1775 return ret;
1776
1777 ret = media_create_pad_link(
1778 &isp->isp_res.video_in.video.entity, 0,
1779 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1780 if (ret < 0)
1781 return ret;
1782
1783 ret = media_create_pad_link(
1784 &isp->isp_res.subdev.entity, RESZ_PAD_SOURCE,
1785 &isp->isp_res.video_out.video.entity, 0, 0);
1786
1787 if (ret < 0)
f2f6da0d 1788 return ret;
f2f6da0d 1789
b5f6df06 1790 /* Create links between entities. */
f2f6da0d
JMC		 1791 ret = media_create_pad_link(
1792 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1793 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1794 if (ret < 0)
1795 return ret;
1796
1797 ret = media_create_pad_link(
1798 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SOURCE,
1799 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1800 if (ret < 0)
1801 return ret;
1802
1803 ret = media_create_pad_link(
1804 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1805 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1806 if (ret < 0)
1807 return ret;
1808
1809 ret = media_create_pad_link(
1810 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1811 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1812 if (ret < 0)
1813 return ret;
1814
1815 ret = media_create_pad_link(
1816 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1817 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1818 if (ret < 0)
1819 return ret;
1820
1821 ret = media_create_pad_link(
1822 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1823 &isp->isp_aewb.subdev.entity, 0,
1824 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1825 if (ret < 0)
1826 return ret;
1827
1828 ret = media_create_pad_link(
1829 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1830 &isp->isp_af.subdev.entity, 0,
1831 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1832 if (ret < 0)
1833 return ret;
1834
1835 ret = media_create_pad_link(
1836 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1837 &isp->isp_hist.subdev.entity, 0,
1838 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1839 if (ret < 0)
1840 return ret;
1841
1842 return 0;
1843}
1844
448de7e7
SA		 1845static void isp_cleanup_modules(struct isp_device *isp)
1846{
1847 omap3isp_h3a_aewb_cleanup(isp);
1848 omap3isp_h3a_af_cleanup(isp);
1849 omap3isp_hist_cleanup(isp);
1850 omap3isp_resizer_cleanup(isp);
1851 omap3isp_preview_cleanup(isp);
1852 omap3isp_ccdc_cleanup(isp);
1853 omap3isp_ccp2_cleanup(isp);
1854 omap3isp_csi2_cleanup(isp);
838a6c56 1855 omap3isp_csiphy_cleanup(isp);
448de7e7
SA		 1856}
1857
1858static int isp_initialize_modules(struct isp_device *isp)
1859{
1860 int ret;
1861
1862 ret = omap3isp_csiphy_init(isp);
1863 if (ret < 0) {
1864 dev_err(isp->dev, "CSI PHY initialization failed\n");
838a6c56 1865 return ret;
448de7e7
SA		 1866 }
1867
1868 ret = omap3isp_csi2_init(isp);
1869 if (ret < 0) {
1870 dev_err(isp->dev, "CSI2 initialization failed\n");
1871 goto error_csi2;
1872 }
1873
1874 ret = omap3isp_ccp2_init(isp);
1875 if (ret < 0) {
a4573084
PM		 1876 if (ret != -EPROBE_DEFER)
1877 dev_err(isp->dev, "CCP2 initialization failed\n");
448de7e7
SA		 1878 goto error_ccp2;
1879 }
1880
1881 ret = omap3isp_ccdc_init(isp);
1882 if (ret < 0) {
1883 dev_err(isp->dev, "CCDC initialization failed\n");
1884 goto error_ccdc;
1885 }
1886
1887 ret = omap3isp_preview_init(isp);
1888 if (ret < 0) {
1889 dev_err(isp->dev, "Preview initialization failed\n");
1890 goto error_preview;
1891 }
1892
1893 ret = omap3isp_resizer_init(isp);
1894 if (ret < 0) {
1895 dev_err(isp->dev, "Resizer initialization failed\n");
1896 goto error_resizer;
1897 }
1898
1899 ret = omap3isp_hist_init(isp);
1900 if (ret < 0) {
1901 dev_err(isp->dev, "Histogram initialization failed\n");
1902 goto error_hist;
1903 }
1904
1905 ret = omap3isp_h3a_aewb_init(isp);
1906 if (ret < 0) {
1907 dev_err(isp->dev, "H3A AEWB initialization failed\n");
1908 goto error_h3a_aewb;
1909 }
1910
1911 ret = omap3isp_h3a_af_init(isp);
1912 if (ret < 0) {
1913 dev_err(isp->dev, "H3A AF initialization failed\n");
1914 goto error_h3a_af;
1915 }
1916
448de7e7
SA		 1917 return 0;
1918
448de7e7
SA		 1919error_h3a_af:
1920 omap3isp_h3a_aewb_cleanup(isp);
1921error_h3a_aewb:
1922 omap3isp_hist_cleanup(isp);
1923error_hist:
1924 omap3isp_resizer_cleanup(isp);
1925error_resizer:
1926 omap3isp_preview_cleanup(isp);
1927error_preview:
1928 omap3isp_ccdc_cleanup(isp);
1929error_ccdc:
1930 omap3isp_ccp2_cleanup(isp);
1931error_ccp2:
1932 omap3isp_csi2_cleanup(isp);
1933error_csi2:
838a6c56
SA		 1934 omap3isp_csiphy_cleanup(isp);
1935
448de7e7
SA		 1936 return ret;
1937}
1938
2a0a5472
LP		 1939static void isp_detach_iommu(struct isp_device *isp)
1940{
24313113 1941#ifdef CONFIG_ARM_DMA_USE_IOMMU
b7e1e685 1942 arm_iommu_detach_device(isp->dev);
2a0a5472
LP		 1943 arm_iommu_release_mapping(isp->mapping);
1944 isp->mapping = NULL;
24313113 1945#endif
2a0a5472
LP		 1946}
1947
1948static int isp_attach_iommu(struct isp_device *isp)
1949{
24313113 1950#ifdef CONFIG_ARM_DMA_USE_IOMMU
2a0a5472 1951 struct dma_iommu_mapping *mapping;
2a0a5472
LP		 1952 int ret;
1953
2a0a5472
LP		 1954 /*
1955 * Create the ARM mapping, used by the ARM DMA mapping core to allocate
1956 * VAs. This will allocate a corresponding IOMMU domain.
1957 */
1958 mapping = arm_iommu_create_mapping(&platform_bus_type, SZ_1G, SZ_2G);
1959 if (IS_ERR(mapping)) {
1960 dev_err(isp->dev, "failed to create ARM IOMMU mapping\n");
b7e1e685 1961 return PTR_ERR(mapping);
2a0a5472
LP		 1962 }
1963
1964 isp->mapping = mapping;
1965
1966 /* Attach the ARM VA mapping to the device. */
1967 ret = arm_iommu_attach_device(isp->dev, mapping);
1968 if (ret < 0) {
1969 dev_err(isp->dev, "failed to attach device to VA mapping\n");
1970 goto error;
1971 }
1972
1973 return 0;
1974
1975error:
b7e1e685
SA		 1976 arm_iommu_release_mapping(isp->mapping);
1977 isp->mapping = NULL;
2a0a5472 1978 return ret;
24313113
AB		 1979#else
1980 return -ENODEV;
1981#endif
2a0a5472
LP		 1982}
1983
448de7e7
SA		 1984/*
1985 * isp_remove - Remove ISP platform device
1986 * @pdev: Pointer to ISP platform device
1987 *
1988 * Always returns 0.
1989 */
4c62e976 1990static int isp_remove(struct platform_device *pdev)
448de7e7
SA		 1991{
1992 struct isp_device *isp = platform_get_drvdata(pdev);
448de7e7 1993
da7f3843 1994 v4l2_async_notifier_unregister(&isp->notifier);
448de7e7
SA		 1995 isp_unregister_entities(isp);
1996 isp_cleanup_modules(isp);
9b28ee3c 1997 isp_xclk_cleanup(isp);
448de7e7 1998
96d62ae2 1999 __omap3isp_get(isp, false);
2a0a5472
LP		 2000 isp_detach_iommu(isp);
2001 __omap3isp_put(isp, false);
448de7e7 2002
17d3d405 2003 media_entity_enum_cleanup(&isp->crashed);
df497566 2004 v4l2_async_notifier_cleanup(&isp->notifier);
17d3d405 2005
448de7e7
SA		 2006 return 0;
2007}
2008
da7f3843
SA		 2009enum isp_of_phy {
2010 ISP_OF_PHY_PARALLEL = 0,
2011 ISP_OF_PHY_CSIPHY1,
2012 ISP_OF_PHY_CSIPHY2,
2013};
2014
df497566
SA		 2015static int isp_fwnode_parse(struct device *dev,
2016 struct v4l2_fwnode_endpoint *vep,
2017 struct v4l2_async_subdev *asd)
da7f3843 2018{
df497566
SA		 2019 struct isp_async_subdev *isd =
2020 container_of(asd, struct isp_async_subdev, asd);
da7f3843 2021 struct isp_bus_cfg *buscfg = &isd->bus;
9211434b 2022 bool csi1 = false;
df497566 2023 unsigned int i;
da7f3843 2024
68d9c47b 2025 dev_dbg(dev, "parsing endpoint %pOF, interface %u\n",
df497566 2026 to_of_node(vep->base.local_fwnode), vep->base.port);
da7f3843 2027
df497566 2028 switch (vep->base.port) {
da7f3843
SA		 2029 case ISP_OF_PHY_PARALLEL:
2030 buscfg->interface = ISP_INTERFACE_PARALLEL;
2031 buscfg->bus.parallel.data_lane_shift =
df497566 2032 vep->bus.parallel.data_shift;
da7f3843 2033 buscfg->bus.parallel.clk_pol =
df497566 2034 !!(vep->bus.parallel.flags
da7f3843
SA		 2035 & V4L2_MBUS_PCLK_SAMPLE_FALLING);
2036 buscfg->bus.parallel.hs_pol =
df497566 2037 !!(vep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW);
da7f3843 2038 buscfg->bus.parallel.vs_pol =
df497566 2039 !!(vep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW);
da7f3843 2040 buscfg->bus.parallel.fld_pol =
df497566 2041 !!(vep->bus.parallel.flags & V4L2_MBUS_FIELD_EVEN_LOW);
da7f3843 2042 buscfg->bus.parallel.data_pol =
df497566
SA		 2043 !!(vep->bus.parallel.flags & V4L2_MBUS_DATA_ACTIVE_LOW);
2044 buscfg->bus.parallel.bt656 = vep->bus_type == V4L2_MBUS_BT656;
da7f3843
SA		 2045 break;
2046
2047 case ISP_OF_PHY_CSIPHY1:
2048 case ISP_OF_PHY_CSIPHY2:
df497566 2049 switch (vep->bus_type) {
9211434b
PM		 2050 case V4L2_MBUS_CCP2:
2051 case V4L2_MBUS_CSI1:
2052 dev_dbg(dev, "CSI-1/CCP-2 configuration\n");
2053 csi1 = true;
2054 break;
2d95e7ed 2055 case V4L2_MBUS_CSI2_DPHY:
9211434b
PM		 2056 dev_dbg(dev, "CSI-2 configuration\n");
2057 csi1 = false;
2058 break;
2059 default:
2060 dev_err(dev, "unsupported bus type %u\n",
df497566 2061 vep->bus_type);
9211434b
PM		 2062 return -EINVAL;
2063 }
2064
df497566 2065 switch (vep->base.port) {
da7f3843 2066 case ISP_OF_PHY_CSIPHY1:
9211434b
PM		 2067 if (csi1)
2068 buscfg->interface = ISP_INTERFACE_CCP2B_PHY1;
2069 else
2070 buscfg->interface = ISP_INTERFACE_CSI2C_PHY1;
da7f3843
SA		 2071 break;
2072 case ISP_OF_PHY_CSIPHY2:
9211434b
PM		 2073 if (csi1)
2074 buscfg->interface = ISP_INTERFACE_CCP2B_PHY2;
2075 else
2076 buscfg->interface = ISP_INTERFACE_CSI2A_PHY2;
da7f3843
SA		 2077 break;
2078 }
9211434b
PM		 2079 if (csi1) {
2080 buscfg->bus.ccp2.lanecfg.clk.pos =
df497566 2081 vep->bus.mipi_csi1.clock_lane;
9211434b 2082 buscfg->bus.ccp2.lanecfg.clk.pol =
df497566 2083 vep->bus.mipi_csi1.lane_polarity[0];
9211434b
PM		 2084 dev_dbg(dev, "clock lane polarity %u, pos %u\n",
2085 buscfg->bus.ccp2.lanecfg.clk.pol,
2086 buscfg->bus.ccp2.lanecfg.clk.pos);
2087
2088 buscfg->bus.ccp2.lanecfg.data[0].pos =
df497566 2089 vep->bus.mipi_csi1.data_lane;
9211434b 2090 buscfg->bus.ccp2.lanecfg.data[0].pol =
df497566 2091 vep->bus.mipi_csi1.lane_polarity[1];
9211434b 2092
5160fb4b 2093 dev_dbg(dev, "data lane polarity %u, pos %u\n",
9211434b
PM		 2094 buscfg->bus.ccp2.lanecfg.data[0].pol,
2095 buscfg->bus.ccp2.lanecfg.data[0].pos);
2096
2097 buscfg->bus.ccp2.strobe_clk_pol =
df497566
SA		 2098 vep->bus.mipi_csi1.clock_inv;
2099 buscfg->bus.ccp2.phy_layer = vep->bus.mipi_csi1.strobe;
9211434b 2100 buscfg->bus.ccp2.ccp2_mode =
df497566 2101 vep->bus_type == V4L2_MBUS_CCP2;
9211434b
PM		 2102 buscfg->bus.ccp2.vp_clk_pol = 1;
2103
2104 buscfg->bus.ccp2.crc = 1;
2105 } else {
2106 buscfg->bus.csi2.lanecfg.clk.pos =
df497566 2107 vep->bus.mipi_csi2.clock_lane;
9211434b 2108 buscfg->bus.csi2.lanecfg.clk.pol =
df497566 2109 vep->bus.mipi_csi2.lane_polarities[0];
9211434b
PM		 2110 dev_dbg(dev, "clock lane polarity %u, pos %u\n",
2111 buscfg->bus.csi2.lanecfg.clk.pol,
2112 buscfg->bus.csi2.lanecfg.clk.pos);
2113
2114 buscfg->bus.csi2.num_data_lanes =
df497566 2115 vep->bus.mipi_csi2.num_data_lanes;
9211434b
PM		 2116
2117 for (i = 0; i < buscfg->bus.csi2.num_data_lanes; i++) {
2118 buscfg->bus.csi2.lanecfg.data[i].pos =
df497566 2119 vep->bus.mipi_csi2.data_lanes[i];
9211434b 2120 buscfg->bus.csi2.lanecfg.data[i].pol =
df497566 2121 vep->bus.mipi_csi2.lane_polarities[i + 1];
9211434b
PM		 2122 dev_dbg(dev,
2123 "data lane %u polarity %u, pos %u\n", i,
2124 buscfg->bus.csi2.lanecfg.data[i].pol,
2125 buscfg->bus.csi2.lanecfg.data[i].pos);
2126 }
2127 /*
2128 * FIXME: now we assume the CRC is always there.
2129 * Implement a way to obtain this information from the
2130 * sensor. Frame descriptors, perhaps?
2131 */
2132 buscfg->bus.csi2.crc = 1;
da7f3843 2133 }
da7f3843
SA		 2134 break;
2135
2136 default:
68d9c47b 2137 dev_warn(dev, "%pOF: invalid interface %u\n",
df497566 2138 to_of_node(vep->base.local_fwnode), vep->base.port);
831f3494 2139 return -EINVAL;
da7f3843
SA		 2140 }
2141
2142 return 0;
2143}
2144
da7f3843
SA		 2145static int isp_subdev_notifier_complete(struct v4l2_async_notifier *async)
2146{
2147 struct isp_device *isp = container_of(async, struct isp_device,
2148 notifier);
68a57fa9
JMC		 2149 struct v4l2_device *v4l2_dev = &isp->v4l2_dev;
2150 struct v4l2_subdev *sd;
68a57fa9
JMC		 2151 int ret;
2152
17d3d405
SA		 2153 ret = media_entity_enum_init(&isp->crashed, &isp->media_dev);
2154 if (ret)
2155 return ret;
2156
68a57fa9 2157 list_for_each_entry(sd, &v4l2_dev->subdevs, list) {
eae4cf8f 2158 if (sd->notifier != &isp->notifier)
02b1ce92
SA		 2159 continue;
2160
2161 ret = isp_link_entity(isp, &sd->entity,
2162 v4l2_subdev_to_bus_cfg(sd)->interface);
2163 if (ret < 0)
2164 return ret;
68a57fa9 2165 }
da7f3843 2166
9832e155
JMC		 2167 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
2168 if (ret < 0)
2169 return ret;
2170
2171 return media_device_register(&isp->media_dev);
da7f3843
SA		 2172}
2173
b6ee3f0d
LP		 2174static const struct v4l2_async_notifier_operations isp_subdev_notifier_ops = {
2175 .complete = isp_subdev_notifier_complete,
2176};
2177
448de7e7
SA		 2178/*
2179 * isp_probe - Probe ISP platform device
2180 * @pdev: Pointer to ISP platform device
2181 *
2182 * Returns 0 if successful,
2183 * -ENOMEM if no memory available,
2184 * -ENODEV if no platform device resources found
2185 * or no space for remapping registers,
2186 * -EINVAL if couldn't install ISR,
2187 * or clk_get return error value.
2188 */
4c62e976 2189static int isp_probe(struct platform_device *pdev)
448de7e7 2190{
448de7e7 2191 struct isp_device *isp;
8644cdf9 2192 struct resource *mem;
448de7e7
SA		 2193 int ret;
2194 int i, m;
2195
cf2b4cf6 2196 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
448de7e7
SA		 2197 if (!isp) {
2198 dev_err(&pdev->dev, "could not allocate memory\n");
2199 return -ENOMEM;
2200 }
2201
859969b3
SA		 2202 ret = fwnode_property_read_u32(of_fwnode_handle(pdev->dev.of_node),
2203 "ti,phy-type", &isp->phy_type);
78c66fbc
LP		 2204 if (ret)
2205 return ret;
da7f3843 2206
78c66fbc
LP		 2207 isp->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2208 "syscon");
2209 if (IS_ERR(isp->syscon))
2210 return PTR_ERR(isp->syscon);
da7f3843 2211
859969b3
SA		 2212 ret = of_property_read_u32_index(pdev->dev.of_node,
2213 "syscon", 1, &isp->syscon_offset);
78c66fbc
LP		 2214 if (ret)
2215 return ret;
da7f3843 2216
448de7e7 2217 isp->autoidle = autoidle;
448de7e7
SA		 2218
2219 mutex_init(&isp->isp_mutex);
2220 spin_lock_init(&isp->stat_lock);
eae2aed1 2221 v4l2_async_notifier_init(&isp->notifier);
448de7e7 2222
df497566
SA		 2223 ret = v4l2_async_notifier_parse_fwnode_endpoints(
2224 &pdev->dev, &isp->notifier, sizeof(struct isp_async_subdev),
2225 isp_fwnode_parse);
2226 if (ret < 0)
2227 goto error;
2228
448de7e7 2229 isp->dev = &pdev->dev;
448de7e7
SA		 2230 isp->ref_count = 0;
2231
224ddca0
RK		 2232 ret = dma_coerce_mask_and_coherent(isp->dev, DMA_BIT_MASK(32));
2233 if (ret)
697cca21 2234 goto error;
448de7e7
SA		 2235
2236 platform_set_drvdata(pdev, isp);
2237
2238 /* Regulators */
3494bb05
SA		 2239 isp->isp_csiphy1.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy1");
2240 isp->isp_csiphy2.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy2");
448de7e7 2241
d8658bca
LP		 2242 /* Clocks
2243 *
2244 * The ISP clock tree is revision-dependent. We thus need to enable ICLK
2245 * manually to read the revision before calling __omap3isp_get().
8644cdf9
SA		 2246 *
2247 * Start by mapping the ISP MMIO area, which is in two pieces.
2248 * The ISP IOMMU is in between. Map both now, and fill in the
2249 * ISP revision specific portions a little later in the
2250 * function.
d8658bca 2251 */
8644cdf9
SA		 2252 for (i = 0; i < 2; i++) {
2253 unsigned int map_idx = i ? OMAP3_ISP_IOMEM_CSI2A_REGS1 : 0;
2254
2255 mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
2256 isp->mmio_base[map_idx] =
2257 devm_ioremap_resource(isp->dev, mem);
2258 if (IS_ERR(isp->mmio_base[map_idx]))
2259 return PTR_ERR(isp->mmio_base[map_idx]);
2260 }
448de7e7
SA		 2261
2262 ret = isp_get_clocks(isp);
2263 if (ret < 0)
2264 goto error;
2265
d8658bca
LP		 2266 ret = clk_enable(isp->clock[ISP_CLK_CAM_ICK]);
2267 if (ret < 0)
2268 goto error;
2269
2270 isp->revision = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
2271 dev_info(isp->dev, "Revision %d.%d found\n",
2272 (isp->revision & 0xf0) >> 4, isp->revision & 0x0f);
2273
2274 clk_disable(isp->clock[ISP_CLK_CAM_ICK]);
2275
0bd0dbee
PST		 2276 if (__omap3isp_get(isp, false) == NULL) {
2277 ret = -ENODEV;
448de7e7 2278 goto error;
0bd0dbee 2279 }
448de7e7
SA		 2280
2281 ret = isp_reset(isp);
2282 if (ret < 0)
2283 goto error_isp;
2284
9b28ee3c
LP		 2285 ret = isp_xclk_init(isp);
2286 if (ret < 0)
2287 goto error_isp;
2288
448de7e7 2289 /* Memory resources */
448de7e7
SA		 2290 for (m = 0; m < ARRAY_SIZE(isp_res_maps); m++)
2291 if (isp->revision == isp_res_maps[m].isp_rev)
2292 break;
2293
2294 if (m == ARRAY_SIZE(isp_res_maps)) {
2295 dev_err(isp->dev, "No resource map found for ISP rev %d.%d\n",
2296 (isp->revision & 0xf0) >> 4, isp->revision & 0xf);
2297 ret = -ENODEV;
2298 goto error_isp;
2299 }
2300
8644cdf9
SA		 2301 for (i = 1; i < OMAP3_ISP_IOMEM_CSI2A_REGS1; i++)
2302 isp->mmio_base[i] =
2303 isp->mmio_base[0] + isp_res_maps[m].offset[i];
2304
2305 for (i = OMAP3_ISP_IOMEM_CSIPHY2; i < OMAP3_ISP_IOMEM_LAST; i++)
2306 isp->mmio_base[i] =
2307 isp->mmio_base[OMAP3_ISP_IOMEM_CSI2A_REGS1]
2308 + isp_res_maps[m].offset[i];
2309
2310 isp->mmio_hist_base_phys =
2311 mem->start + isp_res_maps[m].offset[OMAP3_ISP_IOMEM_HIST];
448de7e7 2312
2a0a5472
LP		 2313 /* IOMMU */
2314 ret = isp_attach_iommu(isp);
2315 if (ret < 0) {
2316 dev_err(&pdev->dev, "unable to attach to IOMMU\n");
f626b52d
OBC		 2317 goto error_isp;
2318 }
2319
448de7e7 2320 /* Interrupt */
514580f9
AH		 2321 ret = platform_get_irq(pdev, 0);
2322 if (ret <= 0) {
448de7e7
SA		 2323 dev_err(isp->dev, "No IRQ resource\n");
2324 ret = -ENODEV;
2a0a5472 2325 goto error_iommu;
448de7e7 2326 }
514580f9 2327 isp->irq_num = ret;
448de7e7 2328
cf2b4cf6
LP		 2329 if (devm_request_irq(isp->dev, isp->irq_num, isp_isr, IRQF_SHARED,
2330 "OMAP3 ISP", isp)) {
448de7e7
SA		 2331 dev_err(isp->dev, "Unable to request IRQ\n");
2332 ret = -EINVAL;
2a0a5472 2333 goto error_iommu;
448de7e7
SA		 2334 }
2335
2336 /* Entities */
2337 ret = isp_initialize_modules(isp);
2338 if (ret < 0)
2a0a5472 2339 goto error_iommu;
448de7e7
SA		 2340
2341 ret = isp_register_entities(isp);
2342 if (ret < 0)
2343 goto error_modules;
2344
b285d5af 2345 ret = isp_create_links(isp);
f2f6da0d
JMC		 2346 if (ret < 0)
2347 goto error_register_entities;
2348
b6ee3f0d 2349 isp->notifier.ops = &isp_subdev_notifier_ops;
5d479386 2350
78c66fbc
LP		 2351 ret = v4l2_async_notifier_register(&isp->v4l2_dev, &isp->notifier);
2352 if (ret)
2353 goto error_register_entities;
5d479386 2354
96d62ae2 2355 isp_core_init(isp, 1);
448de7e7
SA		 2356 omap3isp_put(isp);
2357
2358 return 0;
2359
5d479386
SA		 2360error_register_entities:
2361 isp_unregister_entities(isp);
448de7e7
SA		 2362error_modules:
2363 isp_cleanup_modules(isp);
2a0a5472
LP		 2364error_iommu:
2365 isp_detach_iommu(isp);
448de7e7 2366error_isp:
9b28ee3c 2367 isp_xclk_cleanup(isp);
2a0a5472 2368 __omap3isp_put(isp, false);
448de7e7 2369error:
df497566 2370 v4l2_async_notifier_cleanup(&isp->notifier);
ed33ac8e 2371 mutex_destroy(&isp->isp_mutex);
448de7e7
SA		 2372
2373 return ret;
2374}
2375
2376static const struct dev_pm_ops omap3isp_pm_ops = {
2377 .prepare = isp_pm_prepare,
2378 .suspend = isp_pm_suspend,
2379 .resume = isp_pm_resume,
2380 .complete = isp_pm_complete,
2381};
2382
2383static struct platform_device_id omap3isp_id_table[] = {
2384 { "omap3isp", 0 },
2385 { },
2386};
2387MODULE_DEVICE_TABLE(platform, omap3isp_id_table);
2388
da7f3843
SA		 2389static const struct of_device_id omap3isp_of_table[] = {
2390 { .compatible = "ti,omap3-isp" },
2391 { },
2392};
8163ec29 2393MODULE_DEVICE_TABLE(of, omap3isp_of_table);
da7f3843 2394
448de7e7
SA		 2395static struct platform_driver omap3isp_driver = {
2396 .probe = isp_probe,
4c62e976 2397 .remove = isp_remove,
448de7e7
SA		 2398 .id_table = omap3isp_id_table,
2399 .driver = {
448de7e7
SA		 2400 .name = "omap3isp",
2401 .pm = &omap3isp_pm_ops,
da7f3843 2402 .of_match_table = omap3isp_of_table,
448de7e7
SA		 2403 },
2404};
2405
1d6629b1 2406module_platform_driver(omap3isp_driver);
448de7e7
SA		 2407
2408MODULE_AUTHOR("Nokia Corporation");
2409MODULE_DESCRIPTION("TI OMAP3 ISP driver");
2410MODULE_LICENSE("GPL");
64dc3c1a 2411MODULE_VERSION(ISP_VIDEO_DRIVER_VERSION);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git