projects / thirdparty / kernel / stable.git / blame
| Commit | Line | Data |
|---|---|---|
| c942fddf | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 265a6510 ST |
2 | /* |
| 3 | * Driver for the Auvitek USB bridge | |
| 4 | * | |
| 6d897616 | 5 | * Copyright (c) 2008 Steven Toth <stoth@linuxtv.org> |
| 265a6510 ST |
6 | */ |
| 7 | ||
| a9c36aad ST |
8 | /* We'll start to rename these registers once we have a better |
| 9 | * understanding of their meaning. | |
| 10 | */ | |
| 265a6510 ST |
11 | #define REG_000 0x000 |
| 12 | #define REG_001 0x001 | |
| 13 | #define REG_002 0x002 | |
| 14 | #define REG_003 0x003 | |
| 15 | ||
| 8b2f0795 DH |
16 | #define AU0828_SENSORCTRL_100 0x100 |
| 17 | #define AU0828_SENSORCTRL_VBI_103 0x103 | |
| 18 | ||
| 9beb0de9 DH |
19 | /* I2C registers */ |
| 20 | #define AU0828_I2C_TRIGGER_200 0x200 | |
| 21 | #define AU0828_I2C_STATUS_201 0x201 | |
| 22 | #define AU0828_I2C_CLK_DIVIDER_202 0x202 | |
| 23 | #define AU0828_I2C_DEST_ADDR_203 0x203 | |
| 24 | #define AU0828_I2C_WRITE_FIFO_205 0x205 | |
| 25 | #define AU0828_I2C_READ_FIFO_209 0x209 | |
| 26 | #define AU0828_I2C_MULTIBYTE_MODE_2FF 0x2ff | |
| 265a6510 | 27 | |
| 8b2f0795 DH |
28 | /* Audio registers */ |
| 29 | #define AU0828_AUDIOCTRL_50C 0x50C | |
| 30 | ||
| 265a6510 | 31 | #define REG_600 0x600 |
| 9beb0de9 DH |
32 | |
| 33 | /*********************************************************************/ | |
| 34 | /* Here are constants for values associated with the above registers */ | |
| 35 | ||
| 36 | /* I2C Trigger (Reg 0x200) */ | |
| 37 | #define AU0828_I2C_TRIGGER_WRITE 0x01 | |
| 38 | #define AU0828_I2C_TRIGGER_READ 0x20 | |
| 39 | #define AU0828_I2C_TRIGGER_HOLD 0x40 | |
| 40 | ||
| 41 | /* I2C Status (Reg 0x201) */ | |
| 42 | #define AU0828_I2C_STATUS_READ_DONE 0x01 | |
| 43 | #define AU0828_I2C_STATUS_NO_READ_ACK 0x02 | |
| 44 | #define AU0828_I2C_STATUS_WRITE_DONE 0x04 | |
| 45 | #define AU0828_I2C_STATUS_NO_WRITE_ACK 0x08 | |
| 46 | #define AU0828_I2C_STATUS_BUSY 0x10 | |
| 47 | ||
| 48 | /* I2C Clock Divider (Reg 0x202) */ | |
| 49 | #define AU0828_I2C_CLK_250KHZ 0x07 | |
| 50 | #define AU0828_I2C_CLK_100KHZ 0x14 | |
| 51 | #define AU0828_I2C_CLK_30KHZ 0x40 | |
| 21dc61d3 | 52 | #define AU0828_I2C_CLK_20KHZ 0x60 |