]> git.ipfire.org Git - thirdparty/kernel/stable.git/blame - drivers/memory/omap-gpmc.c
projects / thirdparty / kernel / stable.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'net-hns-bugfixes-for-HNS-Driver'
[thirdparty/kernel/stable.git] / drivers / memory / omap-gpmc.c
CommitLineData
4bbbc1ad
JY		 1/*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
44169075
SS		 8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
4bbbc1ad
JY		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
db97eb7d 15#include <linux/irq.h>
4bbbc1ad
JY		 16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/err.h>
19#include <linux/clk.h>
f37e4580
ID		 20#include <linux/ioport.h>
21#include <linux/spinlock.h>
fced80c7 22#include <linux/io.h>
d2d00862 23#include <linux/gpio/driver.h>
a0752e9c 24#include <linux/gpio/consumer.h> /* GPIO descriptor enum */
db97eb7d 25#include <linux/interrupt.h>
384258f2 26#include <linux/irqdomain.h>
da496873 27#include <linux/platform_device.h>
bc6b1e7b 28#include <linux/of.h>
cdd6928c 29#include <linux/of_address.h>
bc6b1e7b 30#include <linux/of_device.h>
b1dc1ca9 31#include <linux/of_platform.h>
e639cd5b 32#include <linux/omap-gpmc.h>
b3f5525c 33#include <linux/pm_runtime.h>
4bbbc1ad 34
bc3668ea 35#include <linux/platform_data/mtd-nand-omap2.h>
4bbbc1ad 36
7f245162 37#include <asm/mach-types.h>
72d0f1c3 38
4be48fd5
AM		 39#define DEVICE_NAME "omap-gpmc"
40
fd1dc87d 41/* GPMC register offsets */
4bbbc1ad
JY		 42#define GPMC_REVISION 0x00
43#define GPMC_SYSCONFIG 0x10
44#define GPMC_SYSSTATUS 0x14
45#define GPMC_IRQSTATUS 0x18
46#define GPMC_IRQENABLE 0x1c
47#define GPMC_TIMEOUT_CONTROL 0x40
48#define GPMC_ERR_ADDRESS 0x44
49#define GPMC_ERR_TYPE 0x48
50#define GPMC_CONFIG 0x50
51#define GPMC_STATUS 0x54
52#define GPMC_PREFETCH_CONFIG1 0x1e0
53#define GPMC_PREFETCH_CONFIG2 0x1e4
15e02a3b 54#define GPMC_PREFETCH_CONTROL 0x1ec
4bbbc1ad
JY		 55#define GPMC_PREFETCH_STATUS 0x1f0
56#define GPMC_ECC_CONFIG 0x1f4
57#define GPMC_ECC_CONTROL 0x1f8
58#define GPMC_ECC_SIZE_CONFIG 0x1fc
948d38e7 59#define GPMC_ECC1_RESULT 0x200
8d602cf5 60#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
2fdf0c98
AM		 61#define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
62#define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
63#define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
27c9fd60 64#define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
65#define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
66#define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
4bbbc1ad 67
2c65e744
YY		 68/* GPMC ECC control settings */
69#define GPMC_ECC_CTRL_ECCCLEAR 0x100
70#define GPMC_ECC_CTRL_ECCDISABLE 0x000
71#define GPMC_ECC_CTRL_ECCREG1 0x001
72#define GPMC_ECC_CTRL_ECCREG2 0x002
73#define GPMC_ECC_CTRL_ECCREG3 0x003
74#define GPMC_ECC_CTRL_ECCREG4 0x004
75#define GPMC_ECC_CTRL_ECCREG5 0x005
76#define GPMC_ECC_CTRL_ECCREG6 0x006
77#define GPMC_ECC_CTRL_ECCREG7 0x007
78#define GPMC_ECC_CTRL_ECCREG8 0x008
79#define GPMC_ECC_CTRL_ECCREG9 0x009
80
e378d22b
RQ		 81#define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
82
512d73d1
RQ		 83#define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
84
559d94b0
AM		 85#define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
86#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
87#define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
88#define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
89#define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
90#define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
91
948d38e7 92#define GPMC_CS0_OFFSET 0x60
4bbbc1ad 93#define GPMC_CS_SIZE 0x30
2fdf0c98 94#define GPMC_BCH_SIZE 0x10
4bbbc1ad 95
bdd7e033
RQ		 96/*
97 * The first 1MB of GPMC address space is typically mapped to
98 * the internal ROM. Never allocate the first page, to
99 * facilitate bug detection; even if we didn't boot from ROM.
100 * As GPMC minimum partition size is 16MB we can only start from
101 * there.
102 */
103#define GPMC_MEM_START 0x1000000
f37e4580 104#define GPMC_MEM_END 0x3FFFFFFF
f37e4580
ID		 105
106#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
107#define GPMC_SECTION_SHIFT 28 /* 128 MB */
108
59e9c5ae 109#define CS_NUM_SHIFT 24
110#define ENABLE_PREFETCH (0x1 << 7)
111#define DMA_MPU_MODE 2
112
da496873
AM		 113#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
114#define GPMC_REVISION_MINOR(l) (l & 0xf)
115
116#define GPMC_HAS_WR_ACCESS 0x1
117#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
aa8d4767 118#define GPMC_HAS_MUX_AAD 0x4
da496873 119
9f833156
JH		 120#define GPMC_NR_WAITPINS 4
121
e639cd5b
TL		 122#define GPMC_CS_CONFIG1 0x00
123#define GPMC_CS_CONFIG2 0x04
124#define GPMC_CS_CONFIG3 0x08
125#define GPMC_CS_CONFIG4 0x0c
126#define GPMC_CS_CONFIG5 0x10
127#define GPMC_CS_CONFIG6 0x14
128#define GPMC_CS_CONFIG7 0x18
129#define GPMC_CS_NAND_COMMAND 0x1c
130#define GPMC_CS_NAND_ADDRESS 0x20
131#define GPMC_CS_NAND_DATA 0x24
132
133/* Control Commands */
134#define GPMC_CONFIG_RDY_BSY 0x00000001
135#define GPMC_CONFIG_DEV_SIZE 0x00000002
136#define GPMC_CONFIG_DEV_TYPE 0x00000003
e639cd5b
TL		 137
138#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
139#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
140#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
141#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
142#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
143#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
144#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
145#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
4b613e9b
RA		 146/** CLKACTIVATIONTIME Max Ticks */
147#define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
e639cd5b 148#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
4b613e9b
RA		 149/** ATTACHEDDEVICEPAGELENGTH Max Value */
150#define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
e639cd5b
TL		 151#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
152#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
2e676901
RA		 153#define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
154/** WAITMONITORINGTIME Max Ticks */
155#define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
e639cd5b
TL		 156#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
157#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
158#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
4b613e9b
RA		 159/** DEVICESIZE Max Value */
160#define GPMC_CONFIG1_DEVICESIZE_MAX 1
e639cd5b
TL		 161#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
162#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
163#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
164#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
165#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
166#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
167#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
168#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
169#define GPMC_CONFIG7_CSVALID (1 << 6)
170
9c4f757e
SP		 171#define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
172#define GPMC_CONFIG7_CSVALID_MASK BIT(6)
173#define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
174#define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
175/* All CONFIG7 bits except reserved bits */
176#define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
177 GPMC_CONFIG7_CSVALID_MASK | \
178 GPMC_CONFIG7_MASKADDRESS_MASK)
179
e639cd5b
TL		 180#define GPMC_DEVICETYPE_NOR 0
181#define GPMC_DEVICETYPE_NAND 2
182#define GPMC_CONFIG_WRITEPROTECT 0x00000010
183#define WR_RD_PIN_MONITORING 0x00600000
184
e639cd5b
TL		 185/* ECC commands */
186#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
187#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
188#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
189
b2bac25a 190#define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
6b6c32fc 191
7f2e8c58
RA		 192enum gpmc_clk_domain {
193 GPMC_CD_FCLK,
194 GPMC_CD_CLK
195};
196
9ed7a776
TL		 197struct gpmc_cs_data {
198 const char *name;
199
200#define GPMC_CS_RESERVED (1 << 0)
201 u32 flags;
202
203 struct resource mem;
204};
205
a2d3e7ba
RN		 206/* Structure to save gpmc cs context */
207struct gpmc_cs_config {
208 u32 config1;
209 u32 config2;
210 u32 config3;
211 u32 config4;
212 u32 config5;
213 u32 config6;
214 u32 config7;
215 int is_valid;
216};
217
218/*
219 * Structure to save/restore gpmc context
220 * to support core off on OMAP3
221 */
222struct omap3_gpmc_regs {
223 u32 sysconfig;
224 u32 irqenable;
225 u32 timeout_ctrl;
226 u32 config;
227 u32 prefetch_config1;
228 u32 prefetch_config2;
229 u32 prefetch_control;
230 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
231};
232
384258f2
RQ		 233struct gpmc_device {
234 struct device *dev;
235 int irq;
236 struct irq_chip irq_chip;
d2d00862 237 struct gpio_chip gpio_chip;
b2bac25a 238 int nirqs;
384258f2
RQ		 239};
240
241static struct irq_domain *gpmc_irq_domain;
6b6c32fc 242
f37e4580 243static struct resource gpmc_mem_root;
9ed7a776 244static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
87b247c4 245static DEFINE_SPINLOCK(gpmc_mem_lock);
6797b4fe 246/* Define chip-selects as reserved by default until probe completes */
f34f3716 247static unsigned int gpmc_cs_num = GPMC_CS_NUM;
9f833156 248static unsigned int gpmc_nr_waitpins;
da496873
AM		 249static resource_size_t phys_base, mem_size;
250static unsigned gpmc_capability;
fd1dc87d 251static void __iomem *gpmc_base;
4bbbc1ad 252
fd1dc87d 253static struct clk *gpmc_l3_clk;
4bbbc1ad 254
db97eb7d
SG		 255static irqreturn_t gpmc_handle_irq(int irq, void *dev);
256
4bbbc1ad
JY		 257static void gpmc_write_reg(int idx, u32 val)
258{
edfaf05c 259 writel_relaxed(val, gpmc_base + idx);
4bbbc1ad
JY		 260}
261
262static u32 gpmc_read_reg(int idx)
263{
edfaf05c 264 return readl_relaxed(gpmc_base + idx);
4bbbc1ad
JY		 265}
266
267void gpmc_cs_write_reg(int cs, int idx, u32 val)
268{
269 void __iomem *reg_addr;
270
948d38e7 271 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
edfaf05c 272 writel_relaxed(val, reg_addr);
4bbbc1ad
JY		 273}
274
3fc089e7 275static u32 gpmc_cs_read_reg(int cs, int idx)
4bbbc1ad 276{
fd1dc87d
PW		 277 void __iomem *reg_addr;
278
948d38e7 279 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
edfaf05c 280 return readl_relaxed(reg_addr);
4bbbc1ad
JY		 281}
282
fd1dc87d 283/* TODO: Add support for gpmc_fck to clock framework and use it */
3fc089e7 284static unsigned long gpmc_get_fclk_period(void)
4bbbc1ad 285{
fd1dc87d
PW		 286 unsigned long rate = clk_get_rate(gpmc_l3_clk);
287
fd1dc87d
PW		 288 rate /= 1000;
289 rate = 1000000000 / rate; /* In picoseconds */
290
291 return rate;
4bbbc1ad
JY		 292}
293
7f2e8c58
RA		 294/**
295 * gpmc_get_clk_period - get period of selected clock domain in ps
296 * @cs Chip Select Region.
297 * @cd Clock Domain.
298 *
299 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
300 * prior to calling this function with GPMC_CD_CLK.
301 */
302static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
303{
304
305 unsigned long tick_ps = gpmc_get_fclk_period();
306 u32 l;
307 int div;
308
309 switch (cd) {
310 case GPMC_CD_CLK:
311 /* get current clk divider */
312 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
313 div = (l & 0x03) + 1;
314 /* get GPMC_CLK period */
315 tick_ps *= div;
316 break;
317 case GPMC_CD_FCLK:
318 /* FALL-THROUGH */
319 default:
320 break;
321 }
322
323 return tick_ps;
324
325}
326
327static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
328 enum gpmc_clk_domain cd)
4bbbc1ad
JY		 329{
330 unsigned long tick_ps;
331
332 /* Calculate in picosecs to yield more exact results */
7f2e8c58 333 tick_ps = gpmc_get_clk_period(cs, cd);
4bbbc1ad
JY		 334
335 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
336}
337
7f2e8c58
RA		 338static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
339{
340 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
341}
342
3fc089e7 343static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
a3551f5b
AH		 344{
345 unsigned long tick_ps;
346
347 /* Calculate in picosecs to yield more exact results */
348 tick_ps = gpmc_get_fclk_period();
349
350 return (time_ps + tick_ps - 1) / tick_ps;
351}
352
3950fffd
BX		 353static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
354 enum gpmc_clk_domain cd)
7f2e8c58
RA		 355{
356 return ticks * gpmc_get_clk_period(cs, cd) / 1000;
357}
358
fd1dc87d
PW		 359unsigned int gpmc_ticks_to_ns(unsigned int ticks)
360{
7f2e8c58 361 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
fd1dc87d
PW		 362}
363
246da26d
AM		 364static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
365{
366 return ticks * gpmc_get_fclk_period();
367}
368
369static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
370{
371 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
372
373 return ticks * gpmc_get_fclk_period();
374}
375
559d94b0
AM		 376static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
377{
378 u32 l;
379
380 l = gpmc_cs_read_reg(cs, reg);
381 if (value)
382 l |= mask;
383 else
384 l &= ~mask;
385 gpmc_cs_write_reg(cs, reg, l);
386}
387
388static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
389{
390 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
391 GPMC_CONFIG1_TIME_PARA_GRAN,
392 p->time_para_granularity);
393 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
394 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
395 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
396 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
397 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
398 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
399 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
8f50b8e5 400 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
559d94b0
AM		 401 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
402 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
403 p->cycle2cyclesamecsen);
404 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
405 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
406 p->cycle2cyclediffcsen);
407}
408
63aa945b 409#ifdef CONFIG_OMAP_GPMC_DEBUG
563dbb26
RA		 410/**
411 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
412 * @cs: Chip Select Region
413 * @reg: GPMC_CS_CONFIGn register offset.
414 * @st_bit: Start Bit
415 * @end_bit: End Bit. Must be >= @st_bit.
4b613e9b
RA		 416 * @ma:x Maximum parameter value (before optional @shift).
417 * If 0, maximum is as high as @st_bit and @end_bit allow.
563dbb26 418 * @name: DTS node name, w/o "gpmc,"
7f2e8c58
RA		 419 * @cd: Clock Domain of timing parameter.
420 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
563dbb26
RA		 421 * @raw: Raw Format Option.
422 * raw format: gpmc,name = <value>
423 * tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
424 * Where x ns -- y ns result in the same tick value.
4b613e9b 425 * When @max is exceeded, "invalid" is printed inside comment.
563dbb26 426 * @noval: Parameter values equal to 0 are not printed.
563dbb26
RA		 427 * @return: Specified timing parameter (after optional @shift).
428 *
429 */
7f2e8c58
RA		 430static int get_gpmc_timing_reg(
431 /* timing specifiers */
4b613e9b 432 int cs, int reg, int st_bit, int end_bit, int max,
7f2e8c58
RA		 433 const char *name, const enum gpmc_clk_domain cd,
434 /* value transform */
435 int shift,
436 /* format specifiers */
437 bool raw, bool noval)
35ac051e
TL		 438{
439 u32 l;
563dbb26
RA		 440 int nr_bits;
441 int mask;
4b613e9b 442 bool invalid;
35ac051e
TL		 443
444 l = gpmc_cs_read_reg(cs, reg);
445 nr_bits = end_bit - st_bit + 1;
563dbb26
RA		 446 mask = (1 << nr_bits) - 1;
447 l = (l >> st_bit) & mask;
4b613e9b
RA		 448 if (!max)
449 max = mask;
450 invalid = l > max;
35ac051e
TL		 451 if (shift)
452 l = (shift << l);
453 if (noval && (l == 0))
454 return 0;
455 if (!raw) {
563dbb26
RA		 456 /* DTS tick format for timings in ns */
457 unsigned int time_ns;
458 unsigned int time_ns_min = 0;
35ac051e 459
563dbb26 460 if (l)
7f2e8c58
RA		 461 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
462 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
95c278b2 463 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
4b613e9b
RA		 464 name, time_ns, time_ns_min, time_ns, l,
465 invalid ? "; invalid " : " ");
35ac051e 466 } else {
563dbb26 467 /* raw format */
95c278b2 468 pr_info("gpmc,%s = <%u>;%s\n", name, l,
4b613e9b 469 invalid ? " /* invalid */" : "");
35ac051e
TL		 470 }
471
472 return l;
473}
474
475#define GPMC_PRINT_CONFIG(cs, config) \
476 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
477 gpmc_cs_read_reg(cs, config))
478#define GPMC_GET_RAW(reg, st, end, field) \
4b613e9b
RA		 479 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
480#define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
481 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
35ac051e 482#define GPMC_GET_RAW_BOOL(reg, st, end, field) \
4b613e9b
RA		 483 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
484#define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
485 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
35ac051e 486#define GPMC_GET_TICKS(reg, st, end, field) \
4b613e9b 487 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
7f2e8c58 488#define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
4b613e9b
RA		 489 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
490#define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
491 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
35ac051e
TL		 492
493static void gpmc_show_regs(int cs, const char *desc)
494{
495 pr_info("gpmc cs%i %s:\n", cs, desc);
496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
499 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
500 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
501 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
502}
503
504/*
505 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
506 * see commit c9fb809.
507 */
508static void gpmc_cs_show_timings(int cs, const char *desc)
509{
510 gpmc_show_regs(cs, desc);
511
512 pr_info("gpmc cs%i access configuration:\n", cs);
513 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
514 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
aff523fb 515 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
4b613e9b 516 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
35ac051e
TL		 517 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
518 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
519 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
4b613e9b
RA		 520 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
521 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
522 "burst-length");
35ac051e
TL		 523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
525 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
527 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
528
529 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
530
531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
532
533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
534 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
535
536 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
537 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
538
539 pr_info("gpmc cs%i timings configuration:\n", cs);
540 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
541 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
542 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
543
544 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
545 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
546 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
2c92c04b
NA		 547 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
548 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
549 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
550 "adv-aad-mux-rd-off-ns");
551 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
552 "adv-aad-mux-wr-off-ns");
553 }
35ac051e
TL		 554
555 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
556 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
2c92c04b
NA		 557 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
558 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
560 }
35ac051e
TL		 561 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
562 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
563
564 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
565 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
566 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
567
568 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
569
570 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
571 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
572
4b613e9b
RA		 573 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
574 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
575 "wait-monitoring-ns", GPMC_CD_CLK);
576 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
577 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
578 "clk-activation-ns", GPMC_CD_FCLK);
35ac051e
TL		 579
580 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
581 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
582}
4bbbc1ad 583#else
35ac051e
TL		 584static inline void gpmc_cs_show_timings(int cs, const char *desc)
585{
586}
4bbbc1ad 587#endif
35ac051e 588
7f2e8c58
RA		 589/**
590 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
591 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
592 * prior to calling this function with @cd equal to GPMC_CD_CLK.
593 *
594 * @cs: Chip Select Region.
595 * @reg: GPMC_CS_CONFIGn register offset.
596 * @st_bit: Start Bit
597 * @end_bit: End Bit. Must be >= @st_bit.
4b613e9b
RA		 598 * @max: Maximum parameter value.
599 * If 0, maximum is as high as @st_bit and @end_bit allow.
7f2e8c58
RA		 600 * @time: Timing parameter in ns.
601 * @cd: Timing parameter clock domain.
602 * @name: Timing parameter name.
603 * @return: 0 on success, -1 on error.
604 */
4b613e9b 605static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
7f2e8c58 606 int time, enum gpmc_clk_domain cd, const char *name)
4bbbc1ad
JY		 607{
608 u32 l;
609 int ticks, mask, nr_bits;
610
611 if (time == 0)
612 ticks = 0;
613 else
7f2e8c58 614 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
4bbbc1ad 615 nr_bits = end_bit - st_bit + 1;
80323742
RQ		 616 mask = (1 << nr_bits) - 1;
617
4b613e9b
RA		 618 if (!max)
619 max = mask;
620
621 if (ticks > max) {
7f2e8c58 622 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
4b613e9b 623 __func__, cs, name, time, ticks, max);
80323742 624
4bbbc1ad 625 return -1;
1c22cc13 626 }
4bbbc1ad 627
4bbbc1ad 628 l = gpmc_cs_read_reg(cs, reg);
63aa945b 629#ifdef CONFIG_OMAP_GPMC_DEBUG
f585070b 630 pr_info(
2affc816 631 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
7f2e8c58 632 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
1c22cc13 633 (l >> st_bit) & mask, time);
4bbbc1ad
JY		 634#endif
635 l &= ~(mask << st_bit);
636 l |= ticks << st_bit;
637 gpmc_cs_write_reg(cs, reg, l);
638
639 return 0;
640}
641
4b613e9b
RA		 642#define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \
643 if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
644 t->field, (cd), #field) < 0) \
4bbbc1ad 645 return -1
4bbbc1ad 646
7f2e8c58 647#define GPMC_SET_ONE(reg, st, end, field) \
4b613e9b 648 GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
7f2e8c58 649
2e676901
RA		 650/**
651 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
652 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
653 * read --> don't sample bus too early
654 * write --> data is longer on bus
655 *
656 * Formula:
657 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
658 * / waitmonitoring_ticks)
659 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
660 * div <= 0 check.
661 *
662 * @wait_monitoring: WAITMONITORINGTIME in ns.
663 * @return: -1 on failure to scale, else proper divider > 0.
664 */
665static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
666{
667
668 int div = gpmc_ns_to_ticks(wait_monitoring);
669
670 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
671 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
672
673 if (div > 4)
674 return -1;
675 if (div <= 0)
676 div = 1;
677
678 return div;
679
680}
681
682/**
683 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
684 * @sync_clk: GPMC_CLK period in ps.
685 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
686 * Else, returns -1.
687 */
1b47ca1a 688int gpmc_calc_divider(unsigned int sync_clk)
4bbbc1ad 689{
2e676901 690 int div = gpmc_ps_to_ticks(sync_clk);
4bbbc1ad 691
4bbbc1ad
JY		 692 if (div > 4)
693 return -1;
1c22cc13 694 if (div <= 0)
4bbbc1ad
JY		 695 div = 1;
696
697 return div;
698}
699
2e676901
RA		 700/**
701 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
702 * @cs: Chip Select Region.
703 * @t: GPMC timing parameters.
704 * @s: GPMC timing settings.
705 * @return: 0 on success, -1 on error.
706 */
707int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
708 const struct gpmc_settings *s)
4bbbc1ad
JY		 709{
710 int div;
711 u32 l;
712
1b47ca1a 713 div = gpmc_calc_divider(t->sync_clk);
4bbbc1ad 714 if (div < 0)
a032d33b 715 return div;
4bbbc1ad 716
2e676901
RA		 717 /*
718 * See if we need to change the divider for waitmonitoringtime.
719 *
720 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
721 * pure asynchronous accesses, i.e. both read and write asynchronous.
722 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
723 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
724 *
725 * This statement must not change div to scale async WAITMONITORINGTIME
726 * to protect mixed synchronous and asynchronous accesses.
727 *
728 * We raise an error later if WAITMONITORINGTIME does not fit.
729 */
730 if (!s->sync_read && !s->sync_write &&
731 (s->wait_on_read || s->wait_on_write)
732 ) {
733
734 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
735 if (div < 0) {
736 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
737 __func__,
738 t->wait_monitoring
739 );
740 return -1;
741 }
742 }
743
4bbbc1ad
JY		 744 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
745 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
746 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
747
748 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
749 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
750 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
2c92c04b
NA		 751 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
752 GPMC_SET_ONE(GPMC_CS_CONFIG3, 4, 6, adv_aad_mux_on);
753 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
754 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
755 }
4bbbc1ad
JY		 756
757 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
758 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
2c92c04b
NA		 759 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
760 GPMC_SET_ONE(GPMC_CS_CONFIG4, 4, 6, oe_aad_mux_on);
761 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
762 }
4bbbc1ad
JY		 763 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
764 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
765
766 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
767 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
768 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
769
770 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
771
559d94b0
AM		 772 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
773 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
774
da496873 775 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
cc26b3b0 776 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
da496873 777 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
cc26b3b0 778 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
cc26b3b0 779
1c22cc13 780 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
7f2e8c58
RA		 781 l &= ~0x03;
782 l |= (div - 1);
783 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
784
4b613e9b
RA		 785 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
786 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
787 wait_monitoring, GPMC_CD_CLK);
788 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
789 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
790 clk_activation, GPMC_CD_FCLK);
7f2e8c58 791
63aa945b 792#ifdef CONFIG_OMAP_GPMC_DEBUG
f585070b
RA		 793 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
794 cs, (div * gpmc_get_fclk_period()) / 1000, div);
4bbbc1ad 795#endif
4bbbc1ad 796
559d94b0 797 gpmc_cs_bool_timings(cs, &t->bool_timings);
35ac051e 798 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
559d94b0 799
4bbbc1ad
JY		 800 return 0;
801}
802
4cf27d2e 803static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
f37e4580
ID		 804{
805 u32 l;
806 u32 mask;
807
c71f8e9b
JH		 808 /*
809 * Ensure that base address is aligned on a
810 * boundary equal to or greater than size.
811 */
812 if (base & (size - 1))
813 return -EINVAL;
814
9c4f757e 815 base >>= GPMC_CHUNK_SHIFT;
f37e4580 816 mask = (1 << GPMC_SECTION_SHIFT) - size;
9c4f757e
SP		 817 mask >>= GPMC_CHUNK_SHIFT;
818 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
819
f37e4580 820 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
9c4f757e
SP		 821 l &= ~GPMC_CONFIG7_MASK;
822 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
823 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
a2d3e7ba 824 l |= GPMC_CONFIG7_CSVALID;
f37e4580 825 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
c71f8e9b
JH		 826
827 return 0;
f37e4580
ID		 828}
829
4cf27d2e
RQ		 830static void gpmc_cs_enable_mem(int cs)
831{
832 u32 l;
833
834 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
835 l |= GPMC_CONFIG7_CSVALID;
836 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
837}
838
f37e4580
ID		 839static void gpmc_cs_disable_mem(int cs)
840{
841 u32 l;
842
843 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
a2d3e7ba 844 l &= ~GPMC_CONFIG7_CSVALID;
f37e4580
ID		 845 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
846}
847
848static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
849{
850 u32 l;
851 u32 mask;
852
853 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
854 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
855 mask = (l >> 8) & 0x0f;
856 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
857}
858
859static int gpmc_cs_mem_enabled(int cs)
860{
861 u32 l;
862
863 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
a2d3e7ba 864 return l & GPMC_CONFIG7_CSVALID;
f37e4580
ID		 865}
866
f5d8edaf 867static void gpmc_cs_set_reserved(int cs, int reserved)
4bbbc1ad 868{
9ed7a776
TL		 869 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
870
871 gpmc->flags |= GPMC_CS_RESERVED;
f37e4580
ID		 872}
873
ae9d908a 874static bool gpmc_cs_reserved(int cs)
f37e4580 875{
9ed7a776
TL		 876 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
877
878 return gpmc->flags & GPMC_CS_RESERVED;
879}
880
881static void gpmc_cs_set_name(int cs, const char *name)
882{
883 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
884
885 gpmc->name = name;
886}
887
2e25b0ec 888static const char *gpmc_cs_get_name(int cs)
9ed7a776
TL		 889{
890 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
891
892 return gpmc->name;
f37e4580
ID		 893}
894
895static unsigned long gpmc_mem_align(unsigned long size)
896{
897 int order;
898
899 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
900 order = GPMC_CHUNK_SHIFT - 1;
901 do {
902 size >>= 1;
903 order++;
904 } while (size);
905 size = 1 << order;
906 return size;
907}
908
909static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
910{
9ed7a776
TL		 911 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
912 struct resource *res = &gpmc->mem;
f37e4580
ID		 913 int r;
914
915 size = gpmc_mem_align(size);
916 spin_lock(&gpmc_mem_lock);
917 res->start = base;
918 res->end = base + size - 1;
919 r = request_resource(&gpmc_mem_root, res);
920 spin_unlock(&gpmc_mem_lock);
921
922 return r;
923}
924
da496873
AM		 925static int gpmc_cs_delete_mem(int cs)
926{
9ed7a776
TL		 927 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
928 struct resource *res = &gpmc->mem;
da496873
AM		 929 int r;
930
931 spin_lock(&gpmc_mem_lock);
efe80723 932 r = release_resource(res);
da496873
AM		 933 res->start = 0;
934 res->end = 0;
935 spin_unlock(&gpmc_mem_lock);
936
937 return r;
938}
939
cdd6928c
JH		 940/**
941 * gpmc_cs_remap - remaps a chip-select physical base address
942 * @cs: chip-select to remap
943 * @base: physical base address to re-map chip-select to
944 *
945 * Re-maps a chip-select to a new physical base address specified by
946 * "base". Returns 0 on success and appropriate negative error code
947 * on failure.
948 */
949static int gpmc_cs_remap(int cs, u32 base)
950{
951 int ret;
952 u32 old_base, size;
953
f34f3716
GP		 954 if (cs > gpmc_cs_num) {
955 pr_err("%s: requested chip-select is disabled\n", __func__);
cdd6928c 956 return -ENODEV;
f34f3716 957 }
fb677ef7
TL		 958
959 /*
960 * Make sure we ignore any device offsets from the GPMC partition
961 * allocated for the chip select and that the new base confirms
962 * to the GPMC 16MB minimum granularity.
963 */
964 base &= ~(SZ_16M - 1);
965
cdd6928c
JH		 966 gpmc_cs_get_memconf(cs, &old_base, &size);
967 if (base == old_base)
968 return 0;
4cf27d2e 969
cdd6928c
JH		 970 ret = gpmc_cs_delete_mem(cs);
971 if (ret < 0)
972 return ret;
4cf27d2e 973
cdd6928c 974 ret = gpmc_cs_insert_mem(cs, base, size);
c71f8e9b
JH		 975 if (ret < 0)
976 return ret;
cdd6928c 977
4cf27d2e
RQ		 978 ret = gpmc_cs_set_memconf(cs, base, size);
979
980 return ret;
cdd6928c
JH		 981}
982
f37e4580
ID		 983int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
984{
9ed7a776
TL		 985 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
986 struct resource *res = &gpmc->mem;
f37e4580
ID		 987 int r = -1;
988
f34f3716
GP		 989 if (cs > gpmc_cs_num) {
990 pr_err("%s: requested chip-select is disabled\n", __func__);
f37e4580 991 return -ENODEV;
f34f3716 992 }
f37e4580
ID		 993 size = gpmc_mem_align(size);
994 if (size > (1 << GPMC_SECTION_SHIFT))
995 return -ENOMEM;
996
997 spin_lock(&gpmc_mem_lock);
998 if (gpmc_cs_reserved(cs)) {
999 r = -EBUSY;
1000 goto out;
1001 }
1002 if (gpmc_cs_mem_enabled(cs))
1003 r = adjust_resource(res, res->start & ~(size - 1), size);
1004 if (r < 0)
1005 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1006 size, NULL, NULL);
1007 if (r < 0)
1008 goto out;
1009
4cf27d2e
RQ		 1010 /* Disable CS while changing base address and size mask */
1011 gpmc_cs_disable_mem(cs);
1012
1013 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
c71f8e9b
JH		 1014 if (r < 0) {
1015 release_resource(res);
1016 goto out;
1017 }
1018
4cf27d2e
RQ		 1019 /* Enable CS */
1020 gpmc_cs_enable_mem(cs);
f37e4580
ID		 1021 *base = res->start;
1022 gpmc_cs_set_reserved(cs, 1);
1023out:
1024 spin_unlock(&gpmc_mem_lock);
1025 return r;
1026}
fd1dc87d 1027EXPORT_SYMBOL(gpmc_cs_request);
f37e4580
ID		 1028
1029void gpmc_cs_free(int cs)
1030{
9ed7a776
TL		 1031 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1032 struct resource *res = &gpmc->mem;
efe80723 1033
f37e4580 1034 spin_lock(&gpmc_mem_lock);
f34f3716 1035 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
f37e4580
ID		 1036 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1037 BUG();
1038 spin_unlock(&gpmc_mem_lock);
1039 return;
1040 }
1041 gpmc_cs_disable_mem(cs);
efe80723
TL		 1042 if (res->flags)
1043 release_resource(res);
f37e4580
ID		 1044 gpmc_cs_set_reserved(cs, 0);
1045 spin_unlock(&gpmc_mem_lock);
1046}
fd1dc87d 1047EXPORT_SYMBOL(gpmc_cs_free);
f37e4580 1048
948d38e7 1049/**
3a544354 1050 * gpmc_configure - write request to configure gpmc
948d38e7
SG		 1051 * @cmd: command type
1052 * @wval: value to write
1053 * @return status of the operation
1054 */
3a544354 1055int gpmc_configure(int cmd, int wval)
948d38e7 1056{
3a544354 1057 u32 regval;
948d38e7
SG		 1058
1059 switch (cmd) {
948d38e7
SG		 1060 case GPMC_CONFIG_WP:
1061 regval = gpmc_read_reg(GPMC_CONFIG);
1062 if (wval)
1063 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1064 else
1065 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
1066 gpmc_write_reg(GPMC_CONFIG, regval);
1067 break;
1068
948d38e7 1069 default:
3a544354
JH		 1070 pr_err("%s: command not supported\n", __func__);
1071 return -EINVAL;
948d38e7
SG		 1072 }
1073
3a544354 1074 return 0;
948d38e7 1075}
3a544354 1076EXPORT_SYMBOL(gpmc_configure);
948d38e7 1077
a622c641
LM		 1078static bool gpmc_nand_writebuffer_empty(void)
1079{
1080 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1081 return true;
1082
1083 return false;
1084}
1085
1086static struct gpmc_nand_ops nand_ops = {
1087 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1088};
1089
1090/**
1091 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1092 * @regs: the GPMC NAND register map exclusive for NAND use.
1093 * @cs: GPMC chip select number on which the NAND sits. The
1094 * register map returned will be specific to this chip select.
1095 *
1096 * Returns NULL on error e.g. invalid cs.
1097 */
1098struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
52bd138d 1099{
2fdf0c98
AM		 1100 int i;
1101
a622c641
LM		 1102 if (cs >= gpmc_cs_num)
1103 return NULL;
1104
52bd138d
AM		 1105 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1106 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1107 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1108 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1109 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1110 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1111 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1112 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1113 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1114 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1115 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1116 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1117 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1118 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
2fdf0c98
AM		 1119
1120 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1121 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1122 GPMC_BCH_SIZE * i;
1123 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1124 GPMC_BCH_SIZE * i;
1125 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1126 GPMC_BCH_SIZE * i;
1127 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1128 GPMC_BCH_SIZE * i;
27c9fd60 1129 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1130 i * GPMC_BCH_SIZE;
1131 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1132 i * GPMC_BCH_SIZE;
1133 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1134 i * GPMC_BCH_SIZE;
2fdf0c98 1135 }
f47fcad6
RQ		 1136
1137 return &nand_ops;
1138}
1139EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1140
a758f50f
LM		 1141static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1142 struct gpmc_settings *s,
1143 int freq, int latency)
1144{
1145 struct gpmc_device_timings dev_t;
1146 const int t_cer = 15;
1147 const int t_avdp = 12;
1148 const int t_cez = 20; /* max of t_cez, t_oez */
1149 const int t_wpl = 40;
1150 const int t_wph = 30;
1151 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1152
1153 switch (freq) {
1154 case 104:
1155 min_gpmc_clk_period = 9600; /* 104 MHz */
1156 t_ces = 3;
1157 t_avds = 4;
1158 t_avdh = 2;
1159 t_ach = 3;
1160 t_aavdh = 6;
1161 t_rdyo = 6;
1162 break;
1163 case 83:
1164 min_gpmc_clk_period = 12000; /* 83 MHz */
1165 t_ces = 5;
1166 t_avds = 4;
1167 t_avdh = 2;
1168 t_ach = 6;
1169 t_aavdh = 6;
1170 t_rdyo = 9;
1171 break;
1172 case 66:
1173 min_gpmc_clk_period = 15000; /* 66 MHz */
1174 t_ces = 6;
1175 t_avds = 5;
1176 t_avdh = 2;
1177 t_ach = 6;
1178 t_aavdh = 6;
1179 t_rdyo = 11;
1180 break;
1181 default:
1182 min_gpmc_clk_period = 18500; /* 54 MHz */
1183 t_ces = 7;
1184 t_avds = 7;
1185 t_avdh = 7;
1186 t_ach = 9;
1187 t_aavdh = 7;
1188 t_rdyo = 15;
1189 break;
1190 }
1191
1192 /* Set synchronous read timings */
1193 memset(&dev_t, 0, sizeof(dev_t));
1194
1195 if (!s->sync_write) {
1196 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1197 dev_t.t_wpl = t_wpl * 1000;
1198 dev_t.t_wph = t_wph * 1000;
1199 dev_t.t_aavdh = t_aavdh * 1000;
1200 }
1201 dev_t.ce_xdelay = true;
1202 dev_t.avd_xdelay = true;
1203 dev_t.oe_xdelay = true;
1204 dev_t.we_xdelay = true;
1205 dev_t.clk = min_gpmc_clk_period;
1206 dev_t.t_bacc = dev_t.clk;
1207 dev_t.t_ces = t_ces * 1000;
1208 dev_t.t_avds = t_avds * 1000;
1209 dev_t.t_avdh = t_avdh * 1000;
1210 dev_t.t_ach = t_ach * 1000;
1211 dev_t.cyc_iaa = (latency + 1);
1212 dev_t.t_cez_r = t_cez * 1000;
1213 dev_t.t_cez_w = dev_t.t_cez_r;
1214 dev_t.cyc_aavdh_oe = 1;
1215 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1216
1217 gpmc_calc_timings(t, s, &dev_t);
1218}
1219
1220int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1221 int latency,
1222 struct gpmc_onenand_info *info)
1223{
1224 int ret;
1225 struct gpmc_timings gpmc_t;
1226 struct gpmc_settings gpmc_s;
1227
1228 gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1229
1230 info->sync_read = gpmc_s.sync_read;
1231 info->sync_write = gpmc_s.sync_write;
1232 info->burst_len = gpmc_s.burst_len;
1233
1234 if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1235 return 0;
1236
1237 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1238
1239 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1240 if (ret < 0)
1241 return ret;
1242
1243 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1244}
1245EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1246
6b6c32fc
AM		 1247int gpmc_get_client_irq(unsigned irq_config)
1248{
384258f2
RQ		 1249 if (!gpmc_irq_domain) {
1250 pr_warn("%s called before GPMC IRQ domain available\n",
1251 __func__);
6b6c32fc 1252 return 0;
384258f2 1253 }
6b6c32fc 1254
b2bac25a
RQ		 1255 /* we restrict this to NAND IRQs only */
1256 if (irq_config >= GPMC_NR_NAND_IRQS)
384258f2 1257 return 0;
6b6c32fc 1258
384258f2 1259 return irq_create_mapping(gpmc_irq_domain, irq_config);
6b6c32fc
AM		 1260}
1261
384258f2 1262static int gpmc_irq_endis(unsigned long hwirq, bool endis)
6b6c32fc 1263{
6b6c32fc
AM		 1264 u32 regval;
1265
b2bac25a
RQ		 1266 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1267 if (hwirq >= GPMC_NR_NAND_IRQS)
1268 hwirq += 8 - GPMC_NR_NAND_IRQS;
1269
384258f2
RQ		 1270 regval = gpmc_read_reg(GPMC_IRQENABLE);
1271 if (endis)
1272 regval |= BIT(hwirq);
1273 else
1274 regval &= ~BIT(hwirq);
1275 gpmc_write_reg(GPMC_IRQENABLE, regval);
6b6c32fc
AM		 1276
1277 return 0;
1278}
1279
1280static void gpmc_irq_disable(struct irq_data *p)
1281{
384258f2 1282 gpmc_irq_endis(p->hwirq, false);
6b6c32fc
AM		 1283}
1284
1285static void gpmc_irq_enable(struct irq_data *p)
1286{
384258f2 1287 gpmc_irq_endis(p->hwirq, true);
6b6c32fc
AM		 1288}
1289
b2bac25a
RQ		 1290static void gpmc_irq_mask(struct irq_data *d)
1291{
1292 gpmc_irq_endis(d->hwirq, false);
1293}
1294
1295static void gpmc_irq_unmask(struct irq_data *d)
1296{
1297 gpmc_irq_endis(d->hwirq, true);
1298}
1299
1300static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1301{
1302 u32 regval;
1303
1304 /* NAND IRQs polarity is not configurable */
1305 if (hwirq < GPMC_NR_NAND_IRQS)
1306 return;
1307
1308 /* WAITPIN starts at BIT 8 */
1309 hwirq += 8 - GPMC_NR_NAND_IRQS;
1310
1311 regval = gpmc_read_reg(GPMC_CONFIG);
1312 if (rising_edge)
1313 regval &= ~BIT(hwirq);
1314 else
1315 regval |= BIT(hwirq);
1316
1317 gpmc_write_reg(GPMC_CONFIG, regval);
1318}
1319
1320static void gpmc_irq_ack(struct irq_data *d)
1321{
1322 unsigned int hwirq = d->hwirq;
1323
1324 /* skip reserved bits */
1325 if (hwirq >= GPMC_NR_NAND_IRQS)
1326 hwirq += 8 - GPMC_NR_NAND_IRQS;
1327
1328 /* Setting bit to 1 clears (or Acks) the interrupt */
1329 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1330}
1331
1332static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1333{
1334 /* can't set type for NAND IRQs */
1335 if (d->hwirq < GPMC_NR_NAND_IRQS)
1336 return -EINVAL;
1337
1338 /* We can support either rising or falling edge at a time */
1339 if (trigger == IRQ_TYPE_EDGE_FALLING)
1340 gpmc_irq_edge_config(d->hwirq, false);
1341 else if (trigger == IRQ_TYPE_EDGE_RISING)
1342 gpmc_irq_edge_config(d->hwirq, true);
1343 else
1344 return -EINVAL;
6b6c32fc 1345
b2bac25a
RQ		 1346 return 0;
1347}
6b6c32fc 1348
384258f2
RQ		 1349static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1350 irq_hw_number_t hw)
6b6c32fc 1351{
384258f2
RQ		 1352 struct gpmc_device *gpmc = d->host_data;
1353
1354 irq_set_chip_data(virq, gpmc);
b2bac25a
RQ		 1355 if (hw < GPMC_NR_NAND_IRQS) {
1356 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1357 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1358 handle_simple_irq);
1359 } else {
1360 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1361 handle_edge_irq);
1362 }
384258f2
RQ		 1363
1364 return 0;
1365}
1366
1367static const struct irq_domain_ops gpmc_irq_domain_ops = {
1368 .map = gpmc_irq_map,
1369 .xlate = irq_domain_xlate_twocell,
1370};
1371
1372static irqreturn_t gpmc_handle_irq(int irq, void *data)
1373{
1374 int hwirq, virq;
b2bac25a 1375 u32 regval, regvalx;
384258f2 1376 struct gpmc_device *gpmc = data;
6b6c32fc 1377
384258f2 1378 regval = gpmc_read_reg(GPMC_IRQSTATUS);
b2bac25a 1379 regvalx = regval;
6b6c32fc 1380
384258f2
RQ		 1381 if (!regval)
1382 return IRQ_NONE;
6b6c32fc 1383
b2bac25a
RQ		 1384 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1385 /* skip reserved status bits */
1386 if (hwirq == GPMC_NR_NAND_IRQS)
1387 regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1388
1389 if (regvalx & BIT(hwirq)) {
384258f2
RQ		 1390 virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1391 if (!virq) {
1392 dev_warn(gpmc->dev,
1393 "spurious irq detected hwirq %d, virq %d\n",
1394 hwirq, virq);
1395 }
1396
1397 generic_handle_irq(virq);
1398 }
6b6c32fc
AM		 1399 }
1400
384258f2
RQ		 1401 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1402
1403 return IRQ_HANDLED;
1404}
1405
1406static int gpmc_setup_irq(struct gpmc_device *gpmc)
1407{
1408 u32 regval;
1409 int rc;
1410
6b6c32fc
AM		 1411 /* Disable interrupts */
1412 gpmc_write_reg(GPMC_IRQENABLE, 0);
1413
1414 /* clear interrupts */
1415 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1416 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1417
384258f2 1418 gpmc->irq_chip.name = "gpmc";
384258f2
RQ		 1419 gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1420 gpmc->irq_chip.irq_disable = gpmc_irq_disable;
b2bac25a
RQ		 1421 gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1422 gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1423 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1424 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
384258f2
RQ		 1425
1426 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
b2bac25a 1427 gpmc->nirqs,
384258f2
RQ		 1428 &gpmc_irq_domain_ops,
1429 gpmc);
1430 if (!gpmc_irq_domain) {
1431 dev_err(gpmc->dev, "IRQ domain add failed\n");
1432 return -ENODEV;
1433 }
1434
1435 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1436 if (rc) {
1437 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1438 gpmc->irq, rc);
1439 irq_domain_remove(gpmc_irq_domain);
1440 gpmc_irq_domain = NULL;
1441 }
1442
1443 return rc;
6b6c32fc
AM		 1444}
1445
384258f2 1446static int gpmc_free_irq(struct gpmc_device *gpmc)
da496873 1447{
384258f2 1448 int hwirq;
da496873 1449
384258f2 1450 free_irq(gpmc->irq, gpmc);
da496873 1451
b2bac25a 1452 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
384258f2 1453 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
da496873 1454
384258f2
RQ		 1455 irq_domain_remove(gpmc_irq_domain);
1456 gpmc_irq_domain = NULL;
da496873
AM		 1457
1458 return 0;
1459}
1460
351a102d 1461static void gpmc_mem_exit(void)
da496873
AM		 1462{
1463 int cs;
1464
f34f3716 1465 for (cs = 0; cs < gpmc_cs_num; cs++) {
da496873
AM		 1466 if (!gpmc_cs_mem_enabled(cs))
1467 continue;
1468 gpmc_cs_delete_mem(cs);
1469 }
1470
1471}
1472
84b00f0e 1473static void gpmc_mem_init(void)
f37e4580 1474{
84b00f0e 1475 int cs;
f37e4580 1476
bdd7e033 1477 gpmc_mem_root.start = GPMC_MEM_START;
f37e4580
ID		 1478 gpmc_mem_root.end = GPMC_MEM_END;
1479
1480 /* Reserve all regions that has been set up by bootloader */
f34f3716 1481 for (cs = 0; cs < gpmc_cs_num; cs++) {
f37e4580
ID		 1482 u32 base, size;
1483
1484 if (!gpmc_cs_mem_enabled(cs))
1485 continue;
1486 gpmc_cs_get_memconf(cs, &base, &size);
84b00f0e
JH		 1487 if (gpmc_cs_insert_mem(cs, base, size)) {
1488 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1489 __func__, cs, base, base + size);
1490 gpmc_cs_disable_mem(cs);
8119024e 1491 }
f37e4580 1492 }
4bbbc1ad
JY		 1493}
1494
246da26d
AM		 1495static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1496{
1497 u32 temp;
1498 int div;
1499
1500 div = gpmc_calc_divider(sync_clk);
1501 temp = gpmc_ps_to_ticks(time_ps);
1502 temp = (temp + div - 1) / div;
1503 return gpmc_ticks_to_ps(temp * div);
1504}
1505
1506/* XXX: can the cycles be avoided ? */
1507static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1508 struct gpmc_device_timings *dev_t,
1509 bool mux)
246da26d 1510{
246da26d
AM		 1511 u32 temp;
1512
1513 /* adv_rd_off */
1514 temp = dev_t->t_avdp_r;
1515 /* XXX: mux check required ? */
1516 if (mux) {
1517 /* XXX: t_avdp not to be required for sync, only added for tusb
1518 * this indirectly necessitates requirement of t_avdp_r and
1519 * t_avdp_w instead of having a single t_avdp
1520 */
1521 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1522 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1523 }
1524 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1525
1526 /* oe_on */
1527 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1528 if (mux) {
1529 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1530 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1531 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1532 }
1533 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1534
1535 /* access */
1536 /* XXX: any scope for improvement ?, by combining oe_on
1537 * and clk_activation, need to check whether
1538 * access = clk_activation + round to sync clk ?
1539 */
1540 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1541 temp += gpmc_t->clk_activation;
1542 if (dev_t->cyc_oe)
1543 temp = max_t(u32, temp, gpmc_t->oe_on +
1544 gpmc_ticks_to_ps(dev_t->cyc_oe));
1545 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1546
1547 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1548 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1549
1550 /* rd_cycle */
1551 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1552 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1553 gpmc_t->access;
1554 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1555 if (dev_t->t_ce_rdyz)
1556 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1557 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1558
1559 return 0;
1560}
1561
1562static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1563 struct gpmc_device_timings *dev_t,
1564 bool mux)
246da26d 1565{
246da26d
AM		 1566 u32 temp;
1567
1568 /* adv_wr_off */
1569 temp = dev_t->t_avdp_w;
1570 if (mux) {
1571 temp = max_t(u32, temp,
1572 gpmc_t->clk_activation + dev_t->t_avdh);
1573 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1574 }
1575 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1576
1577 /* wr_data_mux_bus */
1578 temp = max_t(u32, dev_t->t_weasu,
1579 gpmc_t->clk_activation + dev_t->t_rdyo);
1580 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1581 * and in that case remember to handle we_on properly
1582 */
1583 if (mux) {
1584 temp = max_t(u32, temp,
1585 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1586 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1587 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1588 }
1589 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1590
1591 /* we_on */
1592 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1593 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1594 else
1595 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1596
1597 /* wr_access */
1598 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1599 gpmc_t->wr_access = gpmc_t->access;
1600
1601 /* we_off */
1602 temp = gpmc_t->we_on + dev_t->t_wpl;
1603 temp = max_t(u32, temp,
1604 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1605 temp = max_t(u32, temp,
1606 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1607 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1608
1609 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1610 dev_t->t_wph);
1611
1612 /* wr_cycle */
1613 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1614 temp += gpmc_t->wr_access;
1615 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1616 if (dev_t->t_ce_rdyz)
1617 temp = max_t(u32, temp,
1618 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1619 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1620
1621 return 0;
1622}
1623
1624static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1625 struct gpmc_device_timings *dev_t,
1626 bool mux)
246da26d 1627{
246da26d
AM		 1628 u32 temp;
1629
1630 /* adv_rd_off */
1631 temp = dev_t->t_avdp_r;
1632 if (mux)
1633 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1634 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1635
1636 /* oe_on */
1637 temp = dev_t->t_oeasu;
1638 if (mux)
1639 temp = max_t(u32, temp,
1640 gpmc_t->adv_rd_off + dev_t->t_aavdh);
1641 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1642
1643 /* access */
1644 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1645 gpmc_t->oe_on + dev_t->t_oe);
1646 temp = max_t(u32, temp,
1647 gpmc_t->cs_on + dev_t->t_ce);
1648 temp = max_t(u32, temp,
1649 gpmc_t->adv_on + dev_t->t_aa);
1650 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1651
1652 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1653 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1654
1655 /* rd_cycle */
1656 temp = max_t(u32, dev_t->t_rd_cycle,
1657 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1658 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1659 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1660
1661 return 0;
1662}
1663
1664static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1665 struct gpmc_device_timings *dev_t,
1666 bool mux)
246da26d 1667{
246da26d
AM		 1668 u32 temp;
1669
1670 /* adv_wr_off */
1671 temp = dev_t->t_avdp_w;
1672 if (mux)
1673 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1674 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1675
1676 /* wr_data_mux_bus */
1677 temp = dev_t->t_weasu;
1678 if (mux) {
1679 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1680 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1681 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1682 }
1683 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1684
1685 /* we_on */
1686 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1687 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1688 else
1689 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1690
1691 /* we_off */
1692 temp = gpmc_t->we_on + dev_t->t_wpl;
1693 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1694
1695 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1696 dev_t->t_wph);
1697
1698 /* wr_cycle */
1699 temp = max_t(u32, dev_t->t_wr_cycle,
1700 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1701 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1702
1703 return 0;
1704}
1705
1706static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1707 struct gpmc_device_timings *dev_t)
1708{
1709 u32 temp;
1710
1711 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1712 gpmc_get_fclk_period();
1713
1714 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1715 dev_t->t_bacc,
1716 gpmc_t->sync_clk);
1717
1718 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1719 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1720
1721 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1722 return 0;
1723
1724 if (dev_t->ce_xdelay)
1725 gpmc_t->bool_timings.cs_extra_delay = true;
1726 if (dev_t->avd_xdelay)
1727 gpmc_t->bool_timings.adv_extra_delay = true;
1728 if (dev_t->oe_xdelay)
1729 gpmc_t->bool_timings.oe_extra_delay = true;
1730 if (dev_t->we_xdelay)
1731 gpmc_t->bool_timings.we_extra_delay = true;
1732
1733 return 0;
1734}
1735
1736static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1737 struct gpmc_device_timings *dev_t,
1738 bool sync)
246da26d
AM		 1739{
1740 u32 temp;
1741
1742 /* cs_on */
1743 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1744
1745 /* adv_on */
1746 temp = dev_t->t_avdasu;
1747 if (dev_t->t_ce_avd)
1748 temp = max_t(u32, temp,
1749 gpmc_t->cs_on + dev_t->t_ce_avd);
1750 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1751
c3be5b45 1752 if (sync)
246da26d
AM		 1753 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1754
1755 return 0;
1756}
1757
1758/* TODO: remove this function once all peripherals are confirmed to
1759 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1760 * has to be modified to handle timings in ps instead of ns
1761*/
1762static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1763{
1764 t->cs_on /= 1000;
1765 t->cs_rd_off /= 1000;
1766 t->cs_wr_off /= 1000;
1767 t->adv_on /= 1000;
1768 t->adv_rd_off /= 1000;
1769 t->adv_wr_off /= 1000;
1770 t->we_on /= 1000;
1771 t->we_off /= 1000;
1772 t->oe_on /= 1000;
1773 t->oe_off /= 1000;
1774 t->page_burst_access /= 1000;
1775 t->access /= 1000;
1776 t->rd_cycle /= 1000;
1777 t->wr_cycle /= 1000;
1778 t->bus_turnaround /= 1000;
1779 t->cycle2cycle_delay /= 1000;
1780 t->wait_monitoring /= 1000;
1781 t->clk_activation /= 1000;
1782 t->wr_access /= 1000;
1783 t->wr_data_mux_bus /= 1000;
1784}
1785
1786int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
c3be5b45
JH		 1787 struct gpmc_settings *gpmc_s,
1788 struct gpmc_device_timings *dev_t)
246da26d 1789{
c3be5b45
JH		 1790 bool mux = false, sync = false;
1791
1792 if (gpmc_s) {
1793 mux = gpmc_s->mux_add_data ? true : false;
1794 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1795 }
1796
246da26d
AM		 1797 memset(gpmc_t, 0, sizeof(*gpmc_t));
1798
c3be5b45 1799 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
246da26d 1800
c3be5b45
JH		 1801 if (gpmc_s && gpmc_s->sync_read)
1802 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
246da26d 1803 else
c3be5b45 1804 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
246da26d 1805
c3be5b45
JH		 1806 if (gpmc_s && gpmc_s->sync_write)
1807 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
246da26d 1808 else
c3be5b45 1809 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
246da26d
AM		 1810
1811 /* TODO: remove, see function definition */
1812 gpmc_convert_ps_to_ns(gpmc_t);
1813
1814 return 0;
1815}
1816
aa8d4767
JH		 1817/**
1818 * gpmc_cs_program_settings - programs non-timing related settings
1819 * @cs: GPMC chip-select to program
1820 * @p: pointer to GPMC settings structure
1821 *
1822 * Programs non-timing related settings for a GPMC chip-select, such as
1823 * bus-width, burst configuration, etc. Function should be called once
1824 * for each chip-select that is being used and must be called before
1825 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1826 * register will be initialised to zero by this function. Returns 0 on
1827 * success and appropriate negative error code on failure.
1828 */
1829int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1830{
1831 u32 config1;
1832
1833 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1834 pr_err("%s: invalid width %d!", __func__, p->device_width);
1835 return -EINVAL;
1836 }
1837
1838 /* Address-data multiplexing not supported for NAND devices */
1839 if (p->device_nand && p->mux_add_data) {
1840 pr_err("%s: invalid configuration!\n", __func__);
1841 return -EINVAL;
1842 }
1843
1844 if ((p->mux_add_data > GPMC_MUX_AD) ||
1845 ((p->mux_add_data == GPMC_MUX_AAD) &&
1846 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1847 pr_err("%s: invalid multiplex configuration!\n", __func__);
1848 return -EINVAL;
1849 }
1850
1851 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1852 if (p->burst_read || p->burst_write) {
1853 switch (p->burst_len) {
1854 case GPMC_BURST_4:
1855 case GPMC_BURST_8:
1856 case GPMC_BURST_16:
1857 break;
1858 default:
1859 pr_err("%s: invalid page/burst-length (%d)\n",
1860 __func__, p->burst_len);
1861 return -EINVAL;
1862 }
1863 }
1864
2b54057c 1865 if (p->wait_pin > gpmc_nr_waitpins) {
aa8d4767
JH		 1866 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1867 return -EINVAL;
1868 }
1869
1870 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1871
1872 if (p->sync_read)
1873 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1874 if (p->sync_write)
1875 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1876 if (p->wait_on_read)
1877 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1878 if (p->wait_on_write)
1879 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1880 if (p->wait_on_read || p->wait_on_write)
1881 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1882 if (p->device_nand)
1883 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1884 if (p->mux_add_data)
1885 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1886 if (p->burst_read)
1887 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1888 if (p->burst_write)
1889 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1890 if (p->burst_read || p->burst_write) {
1891 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1892 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1893 }
1894
1895 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1896
1897 return 0;
1898}
1899
bc6b1e7b 1900#ifdef CONFIG_OF
31957609 1901static const struct of_device_id gpmc_dt_ids[] = {
bc6b1e7b
DM		 1902 { .compatible = "ti,omap2420-gpmc" },
1903 { .compatible = "ti,omap2430-gpmc" },
1904 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1905 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1906 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1907 { }
1908};
bc6b1e7b 1909
8c8a7771
JH		 1910/**
1911 * gpmc_read_settings_dt - read gpmc settings from device-tree
1912 * @np: pointer to device-tree node for a gpmc child device
1913 * @p: pointer to gpmc settings structure
1914 *
1915 * Reads the GPMC settings for a GPMC child device from device-tree and
1916 * stores them in the GPMC settings structure passed. The GPMC settings
1917 * structure is initialised to zero by this function and so any
1918 * previously stored settings will be cleared.
1919 */
1920void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1921{
1922 memset(p, 0, sizeof(struct gpmc_settings));
1923
1924 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1925 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
8c8a7771
JH		 1926 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1927 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1928
1929 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1930 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1931 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1932 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1933 if (!p->burst_read && !p->burst_write)
1934 pr_warn("%s: page/burst-length set but not used!\n",
1935 __func__);
1936 }
1937
1938 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1939 p->wait_on_read = of_property_read_bool(np,
1940 "gpmc,wait-on-read");
1941 p->wait_on_write = of_property_read_bool(np,
1942 "gpmc,wait-on-write");
1943 if (!p->wait_on_read && !p->wait_on_write)
2b54057c
RQ		 1944 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1945 __func__);
8c8a7771
JH		 1946 }
1947}
1948
bc6b1e7b
DM		 1949static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1950 struct gpmc_timings *gpmc_t)
1951{
d36b4cd4
JH		 1952 struct gpmc_bool_timings *p;
1953
1954 if (!np || !gpmc_t)
1955 return;
bc6b1e7b
DM		 1956
1957 memset(gpmc_t, 0, sizeof(*gpmc_t));
1958
1959 /* minimum clock period for syncronous mode */
d36b4cd4 1960 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
bc6b1e7b
DM		 1961
1962 /* chip select timtings */
d36b4cd4
JH		 1963 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1964 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1965 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
bc6b1e7b
DM		 1966
1967 /* ADV signal timings */
d36b4cd4
JH		 1968 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1969 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1970 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
2c92c04b
NA		 1971 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1972 &gpmc_t->adv_aad_mux_on);
1973 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1974 &gpmc_t->adv_aad_mux_rd_off);
1975 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1976 &gpmc_t->adv_aad_mux_wr_off);
bc6b1e7b
DM		 1977
1978 /* WE signal timings */
d36b4cd4
JH		 1979 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1980 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
bc6b1e7b
DM		 1981
1982 /* OE signal timings */
d36b4cd4
JH		 1983 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1984 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
2c92c04b
NA		 1985 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1986 &gpmc_t->oe_aad_mux_on);
1987 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1988 &gpmc_t->oe_aad_mux_off);
bc6b1e7b
DM		 1989
1990 /* access and cycle timings */
d36b4cd4
JH		 1991 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1992 &gpmc_t->page_burst_access);
1993 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1994 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1995 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1996 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1997 &gpmc_t->bus_turnaround);
1998 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1999 &gpmc_t->cycle2cycle_delay);
2000 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2001 &gpmc_t->wait_monitoring);
2002 of_property_read_u32(np, "gpmc,clk-activation-ns",
2003 &gpmc_t->clk_activation);
2004
2005 /* only applicable to OMAP3+ */
2006 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2007 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2008 &gpmc_t->wr_data_mux_bus);
2009
2010 /* bool timing parameters */
2011 p = &gpmc_t->bool_timings;
2012
2013 p->cycle2cyclediffcsen =
2014 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2015 p->cycle2cyclesamecsen =
2016 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2017 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2018 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2019 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2020 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2021 p->time_para_granularity =
2022 of_property_read_bool(np, "gpmc,time-para-granularity");
bc6b1e7b
DM		 2023}
2024
cdd6928c 2025/**
3af91cf7 2026 * gpmc_probe_generic_child - configures the gpmc for a child device
cdd6928c 2027 * @pdev: pointer to gpmc platform device
3af91cf7 2028 * @child: pointer to device-tree node for child device
cdd6928c 2029 *
3af91cf7 2030 * Allocates and configures a GPMC chip-select for a child device.
cdd6928c
JH		 2031 * Returns 0 on success and appropriate negative error code on failure.
2032 */
3af91cf7 2033static int gpmc_probe_generic_child(struct platform_device *pdev,
cdd6928c
JH		 2034 struct device_node *child)
2035{
2036 struct gpmc_settings gpmc_s;
2037 struct gpmc_timings gpmc_t;
2038 struct resource res;
2039 unsigned long base;
9ed7a776 2040 const char *name;
cdd6928c 2041 int ret, cs;
e378d22b 2042 u32 val;
210325f0
RQ		 2043 struct gpio_desc *waitpin_desc = NULL;
2044 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
cdd6928c
JH		 2045
2046 if (of_property_read_u32(child, "reg", &cs) < 0) {
db749d17
RH		 2047 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2048 child);
cdd6928c
JH		 2049 return -ENODEV;
2050 }
2051
2052 if (of_address_to_resource(child, 0, &res) < 0) {
db749d17
RH		 2053 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2054 child);
cdd6928c
JH		 2055 return -ENODEV;
2056 }
2057
9ed7a776
TL		 2058 /*
2059 * Check if we have multiple instances of the same device
2060 * on a single chip select. If so, use the already initialized
2061 * timings.
2062 */
2063 name = gpmc_cs_get_name(cs);
c2ade654 2064 if (name && of_node_name_eq(child, name))
d507178f 2065 goto no_timings;
9ed7a776 2066
cdd6928c
JH		 2067 ret = gpmc_cs_request(cs, resource_size(&res), &base);
2068 if (ret < 0) {
2069 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2070 return ret;
2071 }
c2ade654 2072 gpmc_cs_set_name(cs, child->full_name);
cdd6928c 2073
35ac051e
TL		 2074 gpmc_read_settings_dt(child, &gpmc_s);
2075 gpmc_read_timings_dt(child, &gpmc_t);
cdd6928c 2076
fd4446f2
TL		 2077 /*
2078 * For some GPMC devices we still need to rely on the bootloader
35ac051e
TL		 2079 * timings because the devices can be connected via FPGA.
2080 * REVISIT: Add timing support from slls644g.pdf.
fd4446f2 2081 */
35ac051e
TL		 2082 if (!gpmc_t.cs_rd_off) {
2083 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2084 cs);
2085 gpmc_cs_show_timings(cs,
2086 "please add GPMC bootloader timings to .dts");
fd4446f2
TL		 2087 goto no_timings;
2088 }
2089
4cf27d2e
RQ		 2090 /* CS must be disabled while making changes to gpmc configuration */
2091 gpmc_cs_disable_mem(cs);
2092
cdd6928c
JH		 2093 /*
2094 * FIXME: gpmc_cs_request() will map the CS to an arbitary
2095 * location in the gpmc address space. When booting with
2096 * device-tree we want the NOR flash to be mapped to the
2097 * location specified in the device-tree blob. So remap the
2098 * CS to this location. Once DT migration is complete should
2099 * just make gpmc_cs_request() map a specific address.
2100 */
2101 ret = gpmc_cs_remap(cs, res.start);
2102 if (ret < 0) {
f70bf2a3
FE		 2103 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2104 cs, &res.start);
bdd7e033
RQ		 2105 if (res.start < GPMC_MEM_START) {
2106 dev_info(&pdev->dev,
2107 "GPMC CS %d start cannot be lesser than 0x%x\n",
2108 cs, GPMC_MEM_START);
2109 } else if (res.end > GPMC_MEM_END) {
2110 dev_info(&pdev->dev,
2111 "GPMC CS %d end cannot be greater than 0x%x\n",
2112 cs, GPMC_MEM_END);
2113 }
cdd6928c
JH		 2114 goto err;
2115 }
2116
c2ade654 2117 if (of_node_name_eq(child, "nand")) {
c9711ec5
RQ		 2118 /* Warn about older DT blobs with no compatible property */
2119 if (!of_property_read_bool(child, "compatible")) {
2120 dev_warn(&pdev->dev,
2121 "Incompatible NAND node: missing compatible");
2122 ret = -EINVAL;
2123 goto err;
2124 }
2125 }
2126
c2ade654 2127 if (of_node_name_eq(child, "onenand")) {
a758f50f
LM		 2128 /* Warn about older DT blobs with no compatible property */
2129 if (!of_property_read_bool(child, "compatible")) {
2130 dev_warn(&pdev->dev,
2131 "Incompatible OneNAND node: missing compatible");
2132 ret = -EINVAL;
2133 goto err;
2134 }
2135 }
2136
c9711ec5
RQ		 2137 if (of_device_is_compatible(child, "ti,omap2-nand")) {
2138 /* NAND specific setup */
f679888f
BB		 2139 val = 8;
2140 of_property_read_u32(child, "nand-bus-width", &val);
c9711ec5
RQ		 2141 switch (val) {
2142 case 8:
2143 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2144 break;
2145 case 16:
2146 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2147 break;
2148 default:
c86f9854
RH		 2149 dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2150 child);
c9711ec5
RQ		 2151 ret = -EINVAL;
2152 goto err;
2153 }
2154
2155 /* disable write protect */
2156 gpmc_configure(GPMC_CONFIG_WP, 0);
2157 gpmc_s.device_nand = true;
2158 } else {
2159 ret = of_property_read_u32(child, "bank-width",
2160 &gpmc_s.device_width);
c18a7ac3
LM		 2161 if (ret < 0 && !gpmc_s.device_width) {
2162 dev_err(&pdev->dev,
2163 "%pOF has no 'gpmc,device-width' property\n",
db749d17 2164 child);
c9711ec5 2165 goto err;
c9eabf40 2166 }
c9711ec5 2167 }
cdd6928c 2168
210325f0
RQ		 2169 /* Reserve wait pin if it is required and valid */
2170 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2171 unsigned int wait_pin = gpmc_s.wait_pin;
2172
2173 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
21abf103
LW		 2174 wait_pin, "WAITPIN",
2175 0);
210325f0
RQ		 2176 if (IS_ERR(waitpin_desc)) {
2177 dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2178 ret = PTR_ERR(waitpin_desc);
2179 goto err;
2180 }
2181 }
2182
fd820a1e 2183 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
210325f0 2184
cdd6928c
JH		 2185 ret = gpmc_cs_program_settings(cs, &gpmc_s);
2186 if (ret < 0)
210325f0 2187 goto err_cs;
cdd6928c 2188
2e676901 2189 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
7604baf3 2190 if (ret) {
c86f9854
RH		 2191 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2192 child);
210325f0 2193 goto err_cs;
7604baf3 2194 }
cdd6928c 2195
e378d22b
RQ		 2196 /* Clear limited address i.e. enable A26-A11 */
2197 val = gpmc_read_reg(GPMC_CONFIG);
2198 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2199 gpmc_write_reg(GPMC_CONFIG, val);
2200
4cf27d2e
RQ		 2201 /* Enable CS region */
2202 gpmc_cs_enable_mem(cs);
cdd6928c 2203
fd4446f2 2204no_timings:
b1dc1ca9
RA		 2205
2206 /* create platform device, NULL on error or when disabled */
2207 if (!of_platform_device_create(child, NULL, &pdev->dev))
2208 goto err_child_fail;
2209
2210 /* is child a common bus? */
2211 if (of_match_node(of_default_bus_match_table, child))
2212 /* create children and other common bus children */
9f2c519c 2213 if (of_platform_default_populate(child, NULL, &pdev->dev))
b1dc1ca9
RA		 2214 goto err_child_fail;
2215
2216 return 0;
2217
2218err_child_fail:
cdd6928c 2219
c86f9854 2220 dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
e8ffd6fd 2221 ret = -ENODEV;
cdd6928c 2222
210325f0 2223err_cs:
3f41a3c4 2224 gpiochip_free_own_desc(waitpin_desc);
cdd6928c
JH		 2225err:
2226 gpmc_cs_free(cs);
2227
2228 return ret;
2229}
2230
bc6b1e7b
DM		 2231static int gpmc_probe_dt(struct platform_device *pdev)
2232{
2233 int ret;
bc6b1e7b
DM		 2234 const struct of_device_id *of_id =
2235 of_match_device(gpmc_dt_ids, &pdev->dev);
2236
2237 if (!of_id)
2238 return 0;
2239
f34f3716
GP		 2240 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2241 &gpmc_cs_num);
2242 if (ret < 0) {
2243 pr_err("%s: number of chip-selects not defined\n", __func__);
2244 return ret;
2245 } else if (gpmc_cs_num < 1) {
2246 pr_err("%s: all chip-selects are disabled\n", __func__);
2247 return -EINVAL;
2248 } else if (gpmc_cs_num > GPMC_CS_NUM) {
2249 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2250 __func__, GPMC_CS_NUM);
2251 return -EINVAL;
2252 }
2253
9f833156
JH		 2254 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2255 &gpmc_nr_waitpins);
2256 if (ret < 0) {
2257 pr_err("%s: number of wait pins not found!\n", __func__);
2258 return ret;
2259 }
2260
d2d00862
RQ		 2261 return 0;
2262}
2263
23540d6e 2264static void gpmc_probe_dt_children(struct platform_device *pdev)
d2d00862
RQ		 2265{
2266 int ret;
2267 struct device_node *child;
2268
68e2eb53 2269 for_each_available_child_of_node(pdev->dev.of_node, child) {
a758f50f 2270 ret = gpmc_probe_generic_child(pdev, child);
23540d6e 2271 if (ret) {
c86f9854
RH		 2272 dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2273 child, ret);
23540d6e 2274 }
5330dc16 2275 }
bc6b1e7b
DM		 2276}
2277#else
2278static int gpmc_probe_dt(struct platform_device *pdev)
2279{
2280 return 0;
2281}
d2d00862 2282
23540d6e 2283static void gpmc_probe_dt_children(struct platform_device *pdev)
d2d00862 2284{
d2d00862 2285}
32dd625a
RQ		 2286#endif /* CONFIG_OF */
2287
2288static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2289{
2290 return 1; /* we're input only */
2291}
2292
2293static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2294 unsigned int offset)
2295{
2296 return 0; /* we're input only */
2297}
2298
2299static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2300 unsigned int offset, int value)
2301{
2302 return -EINVAL; /* we're input only */
2303}
2304
2305static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2306 int value)
2307{
2308}
2309
2310static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2311{
2312 u32 reg;
2313
2314 offset += 8;
2315
2316 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2317
2318 return !!reg;
2319}
2320
2321static int gpmc_gpio_init(struct gpmc_device *gpmc)
2322{
2323 int ret;
2324
2325 gpmc->gpio_chip.parent = gpmc->dev;
2326 gpmc->gpio_chip.owner = THIS_MODULE;
2327 gpmc->gpio_chip.label = DEVICE_NAME;
2328 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2329 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2330 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2331 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2332 gpmc->gpio_chip.set = gpmc_gpio_set;
2333 gpmc->gpio_chip.get = gpmc_gpio_get;
2334 gpmc->gpio_chip.base = -1;
2335
525fe43f 2336 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
32dd625a
RQ		 2337 if (ret < 0) {
2338 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2339 return ret;
2340 }
2341
2342 return 0;
2343}
2344
351a102d 2345static int gpmc_probe(struct platform_device *pdev)
4bbbc1ad 2346{
8119024e 2347 int rc;
6b6c32fc 2348 u32 l;
da496873 2349 struct resource *res;
384258f2
RQ		 2350 struct gpmc_device *gpmc;
2351
2352 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2353 if (!gpmc)
2354 return -ENOMEM;
2355
2356 gpmc->dev = &pdev->dev;
2357 platform_set_drvdata(pdev, gpmc);
4bbbc1ad 2358
da496873
AM		 2359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2360 if (res == NULL)
2361 return -ENOENT;
8d08436d 2362
da496873
AM		 2363 phys_base = res->start;
2364 mem_size = resource_size(res);
fd1dc87d 2365
5857bd98
TR		 2366 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2367 if (IS_ERR(gpmc_base))
2368 return PTR_ERR(gpmc_base);
da496873
AM		 2369
2370 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
384258f2
RQ		 2371 if (!res) {
2372 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2373 return -ENOENT;
2374 }
2375
2376 gpmc->irq = res->start;
da496873 2377
8bf9be56 2378 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
da496873 2379 if (IS_ERR(gpmc_l3_clk)) {
8bf9be56 2380 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
da496873 2381 return PTR_ERR(gpmc_l3_clk);
fd1dc87d
PW		 2382 }
2383
8bf9be56
RQ		 2384 if (!clk_get_rate(gpmc_l3_clk)) {
2385 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2386 return -EINVAL;
2387 }
2388
d2d00862
RQ		 2389 if (pdev->dev.of_node) {
2390 rc = gpmc_probe_dt(pdev);
2391 if (rc)
2392 return rc;
2393 } else {
2394 gpmc_cs_num = GPMC_CS_NUM;
2395 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2396 }
2397
b3f5525c 2398 pm_runtime_enable(&pdev->dev);
2399 pm_runtime_get_sync(&pdev->dev);
1daa8c1d 2400
4bbbc1ad 2401 l = gpmc_read_reg(GPMC_REVISION);
aa8d4767
JH		 2402
2403 /*
2404 * FIXME: Once device-tree migration is complete the below flags
2405 * should be populated based upon the device-tree compatible
2406 * string. For now just use the IP revision. OMAP3+ devices have
2407 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2408 * devices support the addr-addr-data multiplex protocol.
2409 *
2410 * GPMC IP revisions:
2411 * - OMAP24xx = 2.0
2412 * - OMAP3xxx = 5.0
2413 * - OMAP44xx/54xx/AM335x = 6.0
2414 */
da496873
AM		 2415 if (GPMC_REVISION_MAJOR(l) > 0x4)
2416 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
aa8d4767
JH		 2417 if (GPMC_REVISION_MAJOR(l) > 0x5)
2418 gpmc_capability |= GPMC_HAS_MUX_AAD;
384258f2 2419 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
da496873
AM		 2420 GPMC_REVISION_MINOR(l));
2421
84b00f0e 2422 gpmc_mem_init();
d2d00862
RQ		 2423 rc = gpmc_gpio_init(gpmc);
2424 if (rc)
2425 goto gpio_init_failed;
db97eb7d 2426
b2bac25a 2427 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
384258f2
RQ		 2428 rc = gpmc_setup_irq(gpmc);
2429 if (rc) {
2430 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
525fe43f 2431 goto gpio_init_failed;
384258f2 2432 }
da496873 2433
23540d6e 2434 gpmc_probe_dt_children(pdev);
bc6b1e7b 2435
da496873 2436 return 0;
384258f2 2437
d2d00862
RQ		 2438gpio_init_failed:
2439 gpmc_mem_exit();
384258f2 2440 pm_runtime_put_sync(&pdev->dev);
d2d00862
RQ		 2441 pm_runtime_disable(&pdev->dev);
2442
384258f2 2443 return rc;
da496873
AM		 2444}
2445
351a102d 2446static int gpmc_remove(struct platform_device *pdev)
da496873 2447{
384258f2
RQ		 2448 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2449
2450 gpmc_free_irq(gpmc);
da496873 2451 gpmc_mem_exit();
b3f5525c 2452 pm_runtime_put_sync(&pdev->dev);
2453 pm_runtime_disable(&pdev->dev);
384258f2 2454
da496873
AM		 2455 return 0;
2456}
2457
b536dd41 2458#ifdef CONFIG_PM_SLEEP
2459static int gpmc_suspend(struct device *dev)
2460{
2461 omap3_gpmc_save_context();
2462 pm_runtime_put_sync(dev);
2463 return 0;
2464}
2465
2466static int gpmc_resume(struct device *dev)
2467{
2468 pm_runtime_get_sync(dev);
2469 omap3_gpmc_restore_context();
2470 return 0;
2471}
2472#endif
2473
2474static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2475
da496873
AM		 2476static struct platform_driver gpmc_driver = {
2477 .probe = gpmc_probe,
351a102d 2478 .remove = gpmc_remove,
da496873
AM		 2479 .driver = {
2480 .name = DEVICE_NAME,
bc6b1e7b 2481 .of_match_table = of_match_ptr(gpmc_dt_ids),
b536dd41 2482 .pm = &gpmc_pm_ops,
da496873
AM		 2483 },
2484};
2485
2486static __init int gpmc_init(void)
2487{
2488 return platform_driver_register(&gpmc_driver);
2489}
a8612809 2490postcore_initcall(gpmc_init);
db97eb7d 2491
a2d3e7ba
RN		 2492static struct omap3_gpmc_regs gpmc_context;
2493
b2fa3b7c 2494void omap3_gpmc_save_context(void)
a2d3e7ba
RN		 2495{
2496 int i;
b2fa3b7c 2497
e984a179
TV		 2498 if (!gpmc_base)
2499 return;
2500
a2d3e7ba
RN		 2501 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2502 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2503 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2504 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2505 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2506 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2507 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
f34f3716 2508 for (i = 0; i < gpmc_cs_num; i++) {
a2d3e7ba
RN		 2509 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2510 if (gpmc_context.cs_context[i].is_valid) {
2511 gpmc_context.cs_context[i].config1 =
2512 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2513 gpmc_context.cs_context[i].config2 =
2514 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2515 gpmc_context.cs_context[i].config3 =
2516 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2517 gpmc_context.cs_context[i].config4 =
2518 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2519 gpmc_context.cs_context[i].config5 =
2520 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2521 gpmc_context.cs_context[i].config6 =
2522 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2523 gpmc_context.cs_context[i].config7 =
2524 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2525 }
2526 }
2527}
2528
b2fa3b7c 2529void omap3_gpmc_restore_context(void)
a2d3e7ba
RN		 2530{
2531 int i;
b2fa3b7c 2532
e984a179
TV		 2533 if (!gpmc_base)
2534 return;
2535
a2d3e7ba
RN		 2536 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2537 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2538 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2539 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2540 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2541 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2542 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
f34f3716 2543 for (i = 0; i < gpmc_cs_num; i++) {
a2d3e7ba
RN		 2544 if (gpmc_context.cs_context[i].is_valid) {
2545 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2546 gpmc_context.cs_context[i].config1);
2547 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2548 gpmc_context.cs_context[i].config2);
2549 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2550 gpmc_context.cs_context[i].config3);
2551 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2552 gpmc_context.cs_context[i].config4);
2553 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2554 gpmc_context.cs_context[i].config5);
2555 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2556 gpmc_context.cs_context[i].config6);
2557 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2558 gpmc_context.cs_context[i].config7);
2559 }
2560 }
2561}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git