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17cdd29d KM |
1 | /** |
2 | * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI | |
3 | * | |
03a8f438 | 4 | * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com |
17cdd29d | 5 | * Author: Keshava Munegowda <keshava_mgowda@ti.com> |
03a8f438 | 6 | * Author: Roger Quadros <rogerq@ti.com> |
17cdd29d KM |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 of | |
10 | * the License as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | #include <linux/kernel.h> | |
417e206b | 21 | #include <linux/module.h> |
17cdd29d KM |
22 | #include <linux/types.h> |
23 | #include <linux/slab.h> | |
24 | #include <linux/delay.h> | |
17cdd29d KM |
25 | #include <linux/clk.h> |
26 | #include <linux/dma-mapping.h> | |
c05995c3 | 27 | #include <linux/gpio.h> |
e8c4a7ac FB |
28 | #include <linux/platform_device.h> |
29 | #include <linux/platform_data/usb-omap.h> | |
1e7fe1a9 | 30 | #include <linux/pm_runtime.h> |
03a8f438 RQ |
31 | #include <linux/of.h> |
32 | #include <linux/of_platform.h> | |
d011c450 | 33 | #include <linux/err.h> |
17cdd29d | 34 | |
e8c4a7ac FB |
35 | #include "omap-usb.h" |
36 | ||
a6d3a662 | 37 | #define USBHS_DRIVER_NAME "usbhs_omap" |
17cdd29d KM |
38 | #define OMAP_EHCI_DEVICE "ehci-omap" |
39 | #define OMAP_OHCI_DEVICE "ohci-omap3" | |
40 | ||
41 | /* OMAP USBHOST Register addresses */ | |
42 | ||
17cdd29d KM |
43 | /* UHH Register Set */ |
44 | #define OMAP_UHH_REVISION (0x00) | |
45 | #define OMAP_UHH_SYSCONFIG (0x10) | |
46 | #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) | |
47 | #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) | |
48 | #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) | |
49 | #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) | |
50 | #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) | |
51 | #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0) | |
52 | ||
53 | #define OMAP_UHH_SYSSTATUS (0x14) | |
54 | #define OMAP_UHH_HOSTCONFIG (0x40) | |
55 | #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0) | |
56 | #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0) | |
57 | #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) | |
58 | #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) | |
59 | #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) | |
60 | #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) | |
61 | #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) | |
62 | #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) | |
63 | #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8) | |
64 | #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9) | |
65 | #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10) | |
66 | #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31) | |
67 | ||
68 | /* OMAP4-specific defines */ | |
69 | #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2) | |
70 | #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2) | |
71 | #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4) | |
72 | #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4) | |
73 | #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0) | |
74 | ||
75 | #define OMAP4_P1_MODE_CLEAR (3 << 16) | |
76 | #define OMAP4_P1_MODE_TLL (1 << 16) | |
77 | #define OMAP4_P1_MODE_HSIC (3 << 16) | |
78 | #define OMAP4_P2_MODE_CLEAR (3 << 18) | |
79 | #define OMAP4_P2_MODE_TLL (1 << 18) | |
80 | #define OMAP4_P2_MODE_HSIC (3 << 18) | |
81 | ||
17cdd29d KM |
82 | #define OMAP_UHH_DEBUG_CSR (0x44) |
83 | ||
84 | /* Values of UHH_REVISION - Note: these are not given in the TRM */ | |
85 | #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */ | |
86 | #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */ | |
87 | ||
88 | #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1) | |
89 | #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2) | |
90 | ||
91 | #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY) | |
92 | #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL) | |
93 | #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC) | |
94 | ||
95 | ||
96 | struct usbhs_hcd_omap { | |
d7eaf866 | 97 | int nports; |
06ba7dc7 | 98 | struct clk **utmi_clk; |
340c64ea RQ |
99 | struct clk **hsic60m_clk; |
100 | struct clk **hsic480m_clk; | |
d7eaf866 | 101 | |
17cdd29d KM |
102 | struct clk *xclk60mhsp1_ck; |
103 | struct clk *xclk60mhsp2_ck; | |
06ba7dc7 RQ |
104 | struct clk *utmi_p1_gfclk; |
105 | struct clk *utmi_p2_gfclk; | |
17cdd29d | 106 | struct clk *init_60m_fclk; |
1e7fe1a9 | 107 | struct clk *ehci_logic_fck; |
17cdd29d KM |
108 | |
109 | void __iomem *uhh_base; | |
17cdd29d | 110 | |
9d9c6ae7 | 111 | struct usbhs_omap_platform_data *pdata; |
17cdd29d KM |
112 | |
113 | u32 usbhs_rev; | |
17cdd29d KM |
114 | }; |
115 | /*-------------------------------------------------------------------------*/ | |
116 | ||
7844b989 | 117 | static const char usbhs_driver_name[] = USBHS_DRIVER_NAME; |
cbb8c220 | 118 | static u64 usbhs_dmamask = DMA_BIT_MASK(32); |
17cdd29d KM |
119 | |
120 | /*-------------------------------------------------------------------------*/ | |
121 | ||
122 | static inline void usbhs_write(void __iomem *base, u32 reg, u32 val) | |
123 | { | |
9981a314 | 124 | writel_relaxed(val, base + reg); |
17cdd29d KM |
125 | } |
126 | ||
127 | static inline u32 usbhs_read(void __iomem *base, u32 reg) | |
128 | { | |
9981a314 | 129 | return readl_relaxed(base + reg); |
17cdd29d KM |
130 | } |
131 | ||
17cdd29d KM |
132 | /*-------------------------------------------------------------------------*/ |
133 | ||
03a8f438 RQ |
134 | /** |
135 | * Map 'enum usbhs_omap_port_mode' found in <linux/platform_data/usb-omap.h> | |
136 | * to the device tree binding portN-mode found in | |
137 | * 'Documentation/devicetree/bindings/mfd/omap-usb-host.txt' | |
138 | */ | |
139 | static const char * const port_modes[] = { | |
140 | [OMAP_USBHS_PORT_MODE_UNUSED] = "", | |
141 | [OMAP_EHCI_PORT_MODE_PHY] = "ehci-phy", | |
142 | [OMAP_EHCI_PORT_MODE_TLL] = "ehci-tll", | |
143 | [OMAP_EHCI_PORT_MODE_HSIC] = "ehci-hsic", | |
144 | [OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0] = "ohci-phy-6pin-datse0", | |
145 | [OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM] = "ohci-phy-6pin-dpdm", | |
146 | [OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0] = "ohci-phy-3pin-datse0", | |
147 | [OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM] = "ohci-phy-4pin-dpdm", | |
148 | [OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0] = "ohci-tll-6pin-datse0", | |
149 | [OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM] = "ohci-tll-6pin-dpdm", | |
150 | [OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0] = "ohci-tll-3pin-datse0", | |
151 | [OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM] = "ohci-tll-4pin-dpdm", | |
152 | [OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0] = "ohci-tll-2pin-datse0", | |
153 | [OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM] = "ohci-tll-2pin-dpdm", | |
154 | }; | |
155 | ||
17cdd29d KM |
156 | static struct platform_device *omap_usbhs_alloc_child(const char *name, |
157 | struct resource *res, int num_resources, void *pdata, | |
158 | size_t pdata_size, struct device *dev) | |
159 | { | |
160 | struct platform_device *child; | |
161 | int ret; | |
162 | ||
163 | child = platform_device_alloc(name, 0); | |
164 | ||
165 | if (!child) { | |
166 | dev_err(dev, "platform_device_alloc %s failed\n", name); | |
167 | goto err_end; | |
168 | } | |
169 | ||
170 | ret = platform_device_add_resources(child, res, num_resources); | |
171 | if (ret) { | |
172 | dev_err(dev, "platform_device_add_resources failed\n"); | |
173 | goto err_alloc; | |
174 | } | |
175 | ||
176 | ret = platform_device_add_data(child, pdata, pdata_size); | |
177 | if (ret) { | |
178 | dev_err(dev, "platform_device_add_data failed\n"); | |
179 | goto err_alloc; | |
180 | } | |
181 | ||
182 | child->dev.dma_mask = &usbhs_dmamask; | |
cbb8c220 | 183 | dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32)); |
17cdd29d KM |
184 | child->dev.parent = dev; |
185 | ||
186 | ret = platform_device_add(child); | |
187 | if (ret) { | |
188 | dev_err(dev, "platform_device_add failed\n"); | |
189 | goto err_alloc; | |
190 | } | |
191 | ||
192 | return child; | |
193 | ||
194 | err_alloc: | |
195 | platform_device_put(child); | |
196 | ||
197 | err_end: | |
198 | return NULL; | |
199 | } | |
200 | ||
201 | static int omap_usbhs_alloc_children(struct platform_device *pdev) | |
202 | { | |
203 | struct device *dev = &pdev->dev; | |
334a41ce | 204 | struct usbhs_omap_platform_data *pdata = dev_get_platdata(dev); |
17cdd29d KM |
205 | struct platform_device *ehci; |
206 | struct platform_device *ohci; | |
207 | struct resource *res; | |
208 | struct resource resources[2]; | |
209 | int ret; | |
210 | ||
17cdd29d KM |
211 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci"); |
212 | if (!res) { | |
213 | dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n"); | |
214 | ret = -ENODEV; | |
215 | goto err_end; | |
216 | } | |
217 | resources[0] = *res; | |
218 | ||
219 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq"); | |
220 | if (!res) { | |
221 | dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n"); | |
222 | ret = -ENODEV; | |
223 | goto err_end; | |
224 | } | |
225 | resources[1] = *res; | |
226 | ||
9d9c6ae7 RQ |
227 | ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata, |
228 | sizeof(*pdata), dev); | |
17cdd29d KM |
229 | |
230 | if (!ehci) { | |
231 | dev_err(dev, "omap_usbhs_alloc_child failed\n"); | |
d910774f | 232 | ret = -ENOMEM; |
17cdd29d KM |
233 | goto err_end; |
234 | } | |
235 | ||
236 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci"); | |
237 | if (!res) { | |
238 | dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n"); | |
239 | ret = -ENODEV; | |
240 | goto err_ehci; | |
241 | } | |
242 | resources[0] = *res; | |
243 | ||
244 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq"); | |
245 | if (!res) { | |
246 | dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n"); | |
247 | ret = -ENODEV; | |
248 | goto err_ehci; | |
249 | } | |
250 | resources[1] = *res; | |
251 | ||
9d9c6ae7 RQ |
252 | ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata, |
253 | sizeof(*pdata), dev); | |
17cdd29d KM |
254 | if (!ohci) { |
255 | dev_err(dev, "omap_usbhs_alloc_child failed\n"); | |
d910774f | 256 | ret = -ENOMEM; |
17cdd29d KM |
257 | goto err_ehci; |
258 | } | |
259 | ||
260 | return 0; | |
261 | ||
262 | err_ehci: | |
d910774f | 263 | platform_device_unregister(ehci); |
17cdd29d KM |
264 | |
265 | err_end: | |
266 | return ret; | |
267 | } | |
268 | ||
17cdd29d KM |
269 | static bool is_ohci_port(enum usbhs_omap_port_mode pmode) |
270 | { | |
271 | switch (pmode) { | |
272 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: | |
273 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: | |
274 | case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: | |
275 | case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: | |
276 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: | |
277 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: | |
278 | case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: | |
279 | case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: | |
280 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: | |
281 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: | |
282 | return true; | |
283 | ||
284 | default: | |
285 | return false; | |
286 | } | |
287 | } | |
288 | ||
1e7fe1a9 | 289 | static int usbhs_runtime_resume(struct device *dev) |
17cdd29d KM |
290 | { |
291 | struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); | |
9d9c6ae7 | 292 | struct usbhs_omap_platform_data *pdata = omap->pdata; |
06ba7dc7 | 293 | int i, r; |
1e7fe1a9 KM |
294 | |
295 | dev_dbg(dev, "usbhs_runtime_resume\n"); | |
17cdd29d | 296 | |
9f4a3ece | 297 | omap_tll_enable(pdata); |
17cdd29d | 298 | |
06ba7dc7 | 299 | if (!IS_ERR(omap->ehci_logic_fck)) |
b0e59926 | 300 | clk_prepare_enable(omap->ehci_logic_fck); |
1e7fe1a9 | 301 | |
06ba7dc7 | 302 | for (i = 0; i < omap->nports; i++) { |
340c64ea RQ |
303 | switch (pdata->port_mode[i]) { |
304 | case OMAP_EHCI_PORT_MODE_HSIC: | |
305 | if (!IS_ERR(omap->hsic60m_clk[i])) { | |
b0e59926 | 306 | r = clk_prepare_enable(omap->hsic60m_clk[i]); |
340c64ea RQ |
307 | if (r) { |
308 | dev_err(dev, | |
309 | "Can't enable port %d hsic60m clk:%d\n", | |
310 | i, r); | |
311 | } | |
312 | } | |
313 | ||
314 | if (!IS_ERR(omap->hsic480m_clk[i])) { | |
b0e59926 | 315 | r = clk_prepare_enable(omap->hsic480m_clk[i]); |
340c64ea RQ |
316 | if (r) { |
317 | dev_err(dev, | |
318 | "Can't enable port %d hsic480m clk:%d\n", | |
319 | i, r); | |
320 | } | |
321 | } | |
322 | /* Fall through as HSIC mode needs utmi_clk */ | |
323 | ||
324 | case OMAP_EHCI_PORT_MODE_TLL: | |
325 | if (!IS_ERR(omap->utmi_clk[i])) { | |
b0e59926 | 326 | r = clk_prepare_enable(omap->utmi_clk[i]); |
340c64ea RQ |
327 | if (r) { |
328 | dev_err(dev, | |
329 | "Can't enable port %d clk : %d\n", | |
330 | i, r); | |
331 | } | |
332 | } | |
333 | break; | |
334 | default: | |
335 | break; | |
336 | } | |
06ba7dc7 | 337 | } |
1e7fe1a9 | 338 | |
1e7fe1a9 KM |
339 | return 0; |
340 | } | |
341 | ||
342 | static int usbhs_runtime_suspend(struct device *dev) | |
343 | { | |
344 | struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); | |
9d9c6ae7 | 345 | struct usbhs_omap_platform_data *pdata = omap->pdata; |
06ba7dc7 | 346 | int i; |
1e7fe1a9 KM |
347 | |
348 | dev_dbg(dev, "usbhs_runtime_suspend\n"); | |
349 | ||
06ba7dc7 | 350 | for (i = 0; i < omap->nports; i++) { |
340c64ea RQ |
351 | switch (pdata->port_mode[i]) { |
352 | case OMAP_EHCI_PORT_MODE_HSIC: | |
353 | if (!IS_ERR(omap->hsic60m_clk[i])) | |
b0e59926 | 354 | clk_disable_unprepare(omap->hsic60m_clk[i]); |
340c64ea RQ |
355 | |
356 | if (!IS_ERR(omap->hsic480m_clk[i])) | |
b0e59926 | 357 | clk_disable_unprepare(omap->hsic480m_clk[i]); |
340c64ea RQ |
358 | /* Fall through as utmi_clks were used in HSIC mode */ |
359 | ||
360 | case OMAP_EHCI_PORT_MODE_TLL: | |
361 | if (!IS_ERR(omap->utmi_clk[i])) | |
b0e59926 | 362 | clk_disable_unprepare(omap->utmi_clk[i]); |
340c64ea RQ |
363 | break; |
364 | default: | |
365 | break; | |
366 | } | |
06ba7dc7 | 367 | } |
1e7fe1a9 | 368 | |
06ba7dc7 | 369 | if (!IS_ERR(omap->ehci_logic_fck)) |
b0e59926 | 370 | clk_disable_unprepare(omap->ehci_logic_fck); |
1e7fe1a9 | 371 | |
9f4a3ece | 372 | omap_tll_disable(pdata); |
1e7fe1a9 KM |
373 | |
374 | return 0; | |
375 | } | |
376 | ||
c4df00ae RQ |
377 | static unsigned omap_usbhs_rev1_hostconfig(struct usbhs_hcd_omap *omap, |
378 | unsigned reg) | |
379 | { | |
380 | struct usbhs_omap_platform_data *pdata = omap->pdata; | |
381 | int i; | |
382 | ||
383 | for (i = 0; i < omap->nports; i++) { | |
384 | switch (pdata->port_mode[i]) { | |
385 | case OMAP_USBHS_PORT_MODE_UNUSED: | |
386 | reg &= ~(OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS << i); | |
387 | break; | |
388 | case OMAP_EHCI_PORT_MODE_PHY: | |
389 | if (pdata->single_ulpi_bypass) | |
390 | break; | |
391 | ||
392 | if (i == 0) | |
393 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; | |
394 | else | |
395 | reg &= ~(OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS | |
396 | << (i-1)); | |
397 | break; | |
398 | default: | |
399 | if (pdata->single_ulpi_bypass) | |
400 | break; | |
401 | ||
402 | if (i == 0) | |
403 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; | |
404 | else | |
405 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS | |
406 | << (i-1); | |
407 | break; | |
408 | } | |
409 | } | |
410 | ||
411 | if (pdata->single_ulpi_bypass) { | |
412 | /* bypass ULPI only if none of the ports use PHY mode */ | |
413 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; | |
414 | ||
415 | for (i = 0; i < omap->nports; i++) { | |
416 | if (is_ehci_phy_mode(pdata->port_mode[i])) { | |
46de8ff8 | 417 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; |
c4df00ae RQ |
418 | break; |
419 | } | |
420 | } | |
421 | } | |
422 | ||
423 | return reg; | |
424 | } | |
425 | ||
426 | static unsigned omap_usbhs_rev2_hostconfig(struct usbhs_hcd_omap *omap, | |
427 | unsigned reg) | |
428 | { | |
429 | struct usbhs_omap_platform_data *pdata = omap->pdata; | |
430 | int i; | |
431 | ||
432 | for (i = 0; i < omap->nports; i++) { | |
433 | /* Clear port mode fields for PHY mode */ | |
434 | reg &= ~(OMAP4_P1_MODE_CLEAR << 2 * i); | |
435 | ||
436 | if (is_ehci_tll_mode(pdata->port_mode[i]) || | |
437 | (is_ohci_port(pdata->port_mode[i]))) | |
438 | reg |= OMAP4_P1_MODE_TLL << 2 * i; | |
439 | else if (is_ehci_hsic_mode(pdata->port_mode[i])) | |
440 | reg |= OMAP4_P1_MODE_HSIC << 2 * i; | |
441 | } | |
442 | ||
443 | return reg; | |
444 | } | |
445 | ||
1e7fe1a9 KM |
446 | static void omap_usbhs_init(struct device *dev) |
447 | { | |
448 | struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); | |
1e7fe1a9 KM |
449 | unsigned reg; |
450 | ||
451 | dev_dbg(dev, "starting TI HSUSB Controller\n"); | |
452 | ||
760189b3 | 453 | pm_runtime_get_sync(dev); |
17cdd29d | 454 | |
17cdd29d KM |
455 | reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG); |
456 | /* setup ULPI bypass and burst configurations */ | |
457 | reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | |
458 | | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | |
459 | | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); | |
460 | reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK; | |
461 | reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; | |
462 | ||
c4df00ae RQ |
463 | switch (omap->usbhs_rev) { |
464 | case OMAP_USBHS_REV1: | |
26bacba1 | 465 | reg = omap_usbhs_rev1_hostconfig(omap, reg); |
c4df00ae RQ |
466 | break; |
467 | ||
468 | case OMAP_USBHS_REV2: | |
26bacba1 | 469 | reg = omap_usbhs_rev2_hostconfig(omap, reg); |
c4df00ae RQ |
470 | break; |
471 | ||
472 | default: /* newer revisions */ | |
26bacba1 | 473 | reg = omap_usbhs_rev2_hostconfig(omap, reg); |
c4df00ae | 474 | break; |
17cdd29d KM |
475 | } |
476 | ||
477 | usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); | |
478 | dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); | |
479 | ||
760189b3 | 480 | pm_runtime_put_sync(dev); |
1e7fe1a9 KM |
481 | } |
482 | ||
03a8f438 RQ |
483 | static int usbhs_omap_get_dt_pdata(struct device *dev, |
484 | struct usbhs_omap_platform_data *pdata) | |
485 | { | |
486 | int ret, i; | |
487 | struct device_node *node = dev->of_node; | |
488 | ||
489 | ret = of_property_read_u32(node, "num-ports", &pdata->nports); | |
490 | if (ret) | |
491 | pdata->nports = 0; | |
492 | ||
493 | if (pdata->nports > OMAP3_HS_USB_PORTS) { | |
494 | dev_warn(dev, "Too many num_ports <%d> in device tree. Max %d\n", | |
495 | pdata->nports, OMAP3_HS_USB_PORTS); | |
496 | return -ENODEV; | |
497 | } | |
498 | ||
499 | /* get port modes */ | |
500 | for (i = 0; i < OMAP3_HS_USB_PORTS; i++) { | |
501 | char prop[11]; | |
502 | const char *mode; | |
503 | ||
504 | pdata->port_mode[i] = OMAP_USBHS_PORT_MODE_UNUSED; | |
505 | ||
506 | snprintf(prop, sizeof(prop), "port%d-mode", i + 1); | |
507 | ret = of_property_read_string(node, prop, &mode); | |
508 | if (ret < 0) | |
509 | continue; | |
510 | ||
4c74a1fc YX |
511 | /* get 'enum usbhs_omap_port_mode' from port mode string */ |
512 | ret = match_string(port_modes, ARRAY_SIZE(port_modes), mode); | |
03a8f438 RQ |
513 | if (ret < 0) { |
514 | dev_warn(dev, "Invalid port%d-mode \"%s\" in device tree\n", | |
515 | i, mode); | |
516 | return -ENODEV; | |
517 | } | |
518 | ||
519 | dev_dbg(dev, "port%d-mode: %s -> %d\n", i, mode, ret); | |
520 | pdata->port_mode[i] = ret; | |
521 | } | |
522 | ||
523 | /* get flags */ | |
524 | pdata->single_ulpi_bypass = of_property_read_bool(node, | |
525 | "single-ulpi-bypass"); | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
a7cfee81 | 530 | static const struct of_device_id usbhs_child_match_table[] = { |
10492ee8 TL |
531 | { .compatible = "ti,ehci-omap", }, |
532 | { .compatible = "ti,ohci-omap3", }, | |
03a8f438 RQ |
533 | { } |
534 | }; | |
535 | ||
1e7fe1a9 KM |
536 | /** |
537 | * usbhs_omap_probe - initialize TI-based HCDs | |
538 | * | |
539 | * Allocates basic resources for this USB host controller. | |
540 | */ | |
f791be49 | 541 | static int usbhs_omap_probe(struct platform_device *pdev) |
17cdd29d | 542 | { |
1e7fe1a9 | 543 | struct device *dev = &pdev->dev; |
334a41ce | 544 | struct usbhs_omap_platform_data *pdata = dev_get_platdata(dev); |
1e7fe1a9 KM |
545 | struct usbhs_hcd_omap *omap; |
546 | struct resource *res; | |
547 | int ret = 0; | |
548 | int i; | |
06ba7dc7 | 549 | bool need_logic_fck; |
17cdd29d | 550 | |
03a8f438 RQ |
551 | if (dev->of_node) { |
552 | /* For DT boot we populate platform data from OF node */ | |
553 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
554 | if (!pdata) | |
555 | return -ENOMEM; | |
556 | ||
557 | ret = usbhs_omap_get_dt_pdata(dev, pdata); | |
558 | if (ret) | |
559 | return ret; | |
560 | ||
561 | dev->platform_data = pdata; | |
562 | } | |
563 | ||
1e7fe1a9 KM |
564 | if (!pdata) { |
565 | dev_err(dev, "Missing platform data\n"); | |
27d4f2c6 | 566 | return -ENODEV; |
1e7fe1a9 | 567 | } |
17cdd29d | 568 | |
03a8f438 RQ |
569 | if (pdata->nports > OMAP3_HS_USB_PORTS) { |
570 | dev_info(dev, "Too many num_ports <%d> in platform_data. Max %d\n", | |
571 | pdata->nports, OMAP3_HS_USB_PORTS); | |
572 | return -ENODEV; | |
573 | } | |
574 | ||
27d4f2c6 | 575 | omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); |
1e7fe1a9 KM |
576 | if (!omap) { |
577 | dev_err(dev, "Memory allocation failed\n"); | |
27d4f2c6 RQ |
578 | return -ENOMEM; |
579 | } | |
580 | ||
03a8f438 | 581 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
d011c450 SK |
582 | omap->uhh_base = devm_ioremap_resource(dev, res); |
583 | if (IS_ERR(omap->uhh_base)) | |
584 | return PTR_ERR(omap->uhh_base); | |
17cdd29d | 585 | |
9d9c6ae7 | 586 | omap->pdata = pdata; |
17cdd29d | 587 | |
9f4a3ece RQ |
588 | /* Initialize the TLL subsystem */ |
589 | omap_tll_init(pdata); | |
590 | ||
1e7fe1a9 | 591 | pm_runtime_enable(dev); |
17cdd29d | 592 | |
d7eaf866 RQ |
593 | platform_set_drvdata(pdev, omap); |
594 | pm_runtime_get_sync(dev); | |
595 | ||
596 | omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); | |
597 | ||
598 | /* we need to call runtime suspend before we update omap->nports | |
599 | * to prevent unbalanced clk_disable() | |
600 | */ | |
601 | pm_runtime_put_sync(dev); | |
602 | ||
ccac71a7 RQ |
603 | /* |
604 | * If platform data contains nports then use that | |
605 | * else make out number of ports from USBHS revision | |
606 | */ | |
607 | if (pdata->nports) { | |
608 | omap->nports = pdata->nports; | |
609 | } else { | |
610 | switch (omap->usbhs_rev) { | |
611 | case OMAP_USBHS_REV1: | |
612 | omap->nports = 3; | |
613 | break; | |
614 | case OMAP_USBHS_REV2: | |
615 | omap->nports = 2; | |
616 | break; | |
617 | default: | |
618 | omap->nports = OMAP3_HS_USB_PORTS; | |
619 | dev_dbg(dev, | |
ddde06b1 | 620 | "USB HOST Rev:0x%x not recognized, assuming %d ports\n", |
ccac71a7 RQ |
621 | omap->usbhs_rev, omap->nports); |
622 | break; | |
623 | } | |
662e469e | 624 | pdata->nports = omap->nports; |
d7eaf866 RQ |
625 | } |
626 | ||
06ba7dc7 RQ |
627 | i = sizeof(struct clk *) * omap->nports; |
628 | omap->utmi_clk = devm_kzalloc(dev, i, GFP_KERNEL); | |
340c64ea RQ |
629 | omap->hsic480m_clk = devm_kzalloc(dev, i, GFP_KERNEL); |
630 | omap->hsic60m_clk = devm_kzalloc(dev, i, GFP_KERNEL); | |
631 | ||
632 | if (!omap->utmi_clk || !omap->hsic480m_clk || !omap->hsic60m_clk) { | |
06ba7dc7 RQ |
633 | dev_err(dev, "Memory allocation failed\n"); |
634 | ret = -ENOMEM; | |
635 | goto err_mem; | |
636 | } | |
637 | ||
3aca446a RQ |
638 | /* Set all clocks as invalid to begin with */ |
639 | omap->ehci_logic_fck = ERR_PTR(-ENODEV); | |
640 | omap->init_60m_fclk = ERR_PTR(-ENODEV); | |
641 | omap->utmi_p1_gfclk = ERR_PTR(-ENODEV); | |
642 | omap->utmi_p2_gfclk = ERR_PTR(-ENODEV); | |
643 | omap->xclk60mhsp1_ck = ERR_PTR(-ENODEV); | |
644 | omap->xclk60mhsp2_ck = ERR_PTR(-ENODEV); | |
645 | ||
06ba7dc7 | 646 | for (i = 0; i < omap->nports; i++) { |
3aca446a RQ |
647 | omap->utmi_clk[i] = ERR_PTR(-ENODEV); |
648 | omap->hsic480m_clk[i] = ERR_PTR(-ENODEV); | |
649 | omap->hsic60m_clk[i] = ERR_PTR(-ENODEV); | |
06ba7dc7 RQ |
650 | } |
651 | ||
3aca446a RQ |
652 | /* for OMAP3 i.e. USBHS REV1 */ |
653 | if (omap->usbhs_rev == OMAP_USBHS_REV1) { | |
654 | need_logic_fck = false; | |
655 | for (i = 0; i < omap->nports; i++) { | |
656 | if (is_ehci_phy_mode(pdata->port_mode[i]) || | |
657 | is_ehci_tll_mode(pdata->port_mode[i]) || | |
658 | is_ehci_hsic_mode(pdata->port_mode[i])) | |
659 | ||
660 | need_logic_fck |= true; | |
661 | } | |
662 | ||
663 | if (need_logic_fck) { | |
664 | omap->ehci_logic_fck = devm_clk_get(dev, | |
775bb078 | 665 | "usbhost_120m_fck"); |
3aca446a RQ |
666 | if (IS_ERR(omap->ehci_logic_fck)) { |
667 | ret = PTR_ERR(omap->ehci_logic_fck); | |
775bb078 RQ |
668 | dev_err(dev, "usbhost_120m_fck failed:%d\n", |
669 | ret); | |
fedb2e7c | 670 | goto err_mem; |
3aca446a | 671 | } |
1e7fe1a9 | 672 | } |
3aca446a | 673 | goto initialize; |
06ba7dc7 | 674 | } |
17cdd29d | 675 | |
3aca446a | 676 | /* for OMAP4+ i.e. USBHS REV2+ */ |
61b7025f | 677 | omap->utmi_p1_gfclk = devm_clk_get(dev, "utmi_p1_gfclk"); |
06ba7dc7 RQ |
678 | if (IS_ERR(omap->utmi_p1_gfclk)) { |
679 | ret = PTR_ERR(omap->utmi_p1_gfclk); | |
680 | dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret); | |
61b7025f | 681 | goto err_mem; |
06ba7dc7 RQ |
682 | } |
683 | ||
61b7025f | 684 | omap->utmi_p2_gfclk = devm_clk_get(dev, "utmi_p2_gfclk"); |
06ba7dc7 RQ |
685 | if (IS_ERR(omap->utmi_p2_gfclk)) { |
686 | ret = PTR_ERR(omap->utmi_p2_gfclk); | |
687 | dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret); | |
61b7025f | 688 | goto err_mem; |
17cdd29d KM |
689 | } |
690 | ||
051fc06d | 691 | omap->xclk60mhsp1_ck = devm_clk_get(dev, "refclk_60m_ext_p1"); |
1e7fe1a9 KM |
692 | if (IS_ERR(omap->xclk60mhsp1_ck)) { |
693 | ret = PTR_ERR(omap->xclk60mhsp1_ck); | |
051fc06d | 694 | dev_err(dev, "refclk_60m_ext_p1 failed error:%d\n", ret); |
61b7025f | 695 | goto err_mem; |
17cdd29d KM |
696 | } |
697 | ||
051fc06d | 698 | omap->xclk60mhsp2_ck = devm_clk_get(dev, "refclk_60m_ext_p2"); |
1e7fe1a9 KM |
699 | if (IS_ERR(omap->xclk60mhsp2_ck)) { |
700 | ret = PTR_ERR(omap->xclk60mhsp2_ck); | |
051fc06d | 701 | dev_err(dev, "refclk_60m_ext_p2 failed error:%d\n", ret); |
61b7025f | 702 | goto err_mem; |
17cdd29d KM |
703 | } |
704 | ||
051fc06d | 705 | omap->init_60m_fclk = devm_clk_get(dev, "refclk_60m_int"); |
1e7fe1a9 KM |
706 | if (IS_ERR(omap->init_60m_fclk)) { |
707 | ret = PTR_ERR(omap->init_60m_fclk); | |
051fc06d | 708 | dev_err(dev, "refclk_60m_int failed error:%d\n", ret); |
61b7025f | 709 | goto err_mem; |
06ba7dc7 RQ |
710 | } |
711 | ||
712 | for (i = 0; i < omap->nports; i++) { | |
340c64ea | 713 | char clkname[30]; |
06ba7dc7 RQ |
714 | |
715 | /* clock names are indexed from 1*/ | |
716 | snprintf(clkname, sizeof(clkname), | |
717 | "usb_host_hs_utmi_p%d_clk", i + 1); | |
718 | ||
719 | /* If a clock is not found we won't bail out as not all | |
720 | * platforms have all clocks and we can function without | |
721 | * them | |
722 | */ | |
61b7025f | 723 | omap->utmi_clk[i] = devm_clk_get(dev, clkname); |
fedb2e7c RQ |
724 | if (IS_ERR(omap->utmi_clk[i])) { |
725 | ret = PTR_ERR(omap->utmi_clk[i]); | |
726 | dev_err(dev, "Failed to get clock : %s : %d\n", | |
727 | clkname, ret); | |
728 | goto err_mem; | |
729 | } | |
340c64ea RQ |
730 | |
731 | snprintf(clkname, sizeof(clkname), | |
732 | "usb_host_hs_hsic480m_p%d_clk", i + 1); | |
61b7025f | 733 | omap->hsic480m_clk[i] = devm_clk_get(dev, clkname); |
fedb2e7c RQ |
734 | if (IS_ERR(omap->hsic480m_clk[i])) { |
735 | ret = PTR_ERR(omap->hsic480m_clk[i]); | |
736 | dev_err(dev, "Failed to get clock : %s : %d\n", | |
737 | clkname, ret); | |
738 | goto err_mem; | |
739 | } | |
340c64ea RQ |
740 | |
741 | snprintf(clkname, sizeof(clkname), | |
742 | "usb_host_hs_hsic60m_p%d_clk", i + 1); | |
61b7025f | 743 | omap->hsic60m_clk[i] = devm_clk_get(dev, clkname); |
fedb2e7c RQ |
744 | if (IS_ERR(omap->hsic60m_clk[i])) { |
745 | ret = PTR_ERR(omap->hsic60m_clk[i]); | |
746 | dev_err(dev, "Failed to get clock : %s : %d\n", | |
747 | clkname, ret); | |
748 | goto err_mem; | |
749 | } | |
17cdd29d KM |
750 | } |
751 | ||
1e7fe1a9 | 752 | if (is_ehci_phy_mode(pdata->port_mode[0])) { |
06ba7dc7 | 753 | ret = clk_set_parent(omap->utmi_p1_gfclk, |
1e7fe1a9 | 754 | omap->xclk60mhsp1_ck); |
fedb2e7c RQ |
755 | if (ret != 0) { |
756 | dev_err(dev, "xclk60mhsp1_ck set parent failed: %d\n", | |
757 | ret); | |
758 | goto err_mem; | |
759 | } | |
1e7fe1a9 | 760 | } else if (is_ehci_tll_mode(pdata->port_mode[0])) { |
06ba7dc7 | 761 | ret = clk_set_parent(omap->utmi_p1_gfclk, |
1e7fe1a9 | 762 | omap->init_60m_fclk); |
fedb2e7c RQ |
763 | if (ret != 0) { |
764 | dev_err(dev, "P0 init_60m_fclk set parent failed: %d\n", | |
765 | ret); | |
766 | goto err_mem; | |
767 | } | |
1e7fe1a9 | 768 | } |
17cdd29d | 769 | |
1e7fe1a9 | 770 | if (is_ehci_phy_mode(pdata->port_mode[1])) { |
06ba7dc7 | 771 | ret = clk_set_parent(omap->utmi_p2_gfclk, |
1e7fe1a9 | 772 | omap->xclk60mhsp2_ck); |
fedb2e7c RQ |
773 | if (ret != 0) { |
774 | dev_err(dev, "xclk60mhsp2_ck set parent failed: %d\n", | |
775 | ret); | |
776 | goto err_mem; | |
777 | } | |
1e7fe1a9 | 778 | } else if (is_ehci_tll_mode(pdata->port_mode[1])) { |
06ba7dc7 | 779 | ret = clk_set_parent(omap->utmi_p2_gfclk, |
1e7fe1a9 | 780 | omap->init_60m_fclk); |
fedb2e7c RQ |
781 | if (ret != 0) { |
782 | dev_err(dev, "P1 init_60m_fclk set parent failed: %d\n", | |
783 | ret); | |
784 | goto err_mem; | |
785 | } | |
1e7fe1a9 | 786 | } |
6eb6fbbf | 787 | |
3aca446a | 788 | initialize: |
f0447a69 | 789 | omap_usbhs_init(dev); |
03a8f438 RQ |
790 | |
791 | if (dev->of_node) { | |
792 | ret = of_platform_populate(dev->of_node, | |
793 | usbhs_child_match_table, NULL, dev); | |
794 | ||
795 | if (ret) { | |
796 | dev_err(dev, "Failed to create DT children: %d\n", ret); | |
61b7025f | 797 | goto err_mem; |
03a8f438 RQ |
798 | } |
799 | ||
800 | } else { | |
801 | ret = omap_usbhs_alloc_children(pdev); | |
802 | if (ret) { | |
803 | dev_err(dev, "omap_usbhs_alloc_children failed: %d\n", | |
804 | ret); | |
61b7025f | 805 | goto err_mem; |
03a8f438 | 806 | } |
1e7fe1a9 KM |
807 | } |
808 | ||
27d4f2c6 | 809 | return 0; |
1e7fe1a9 | 810 | |
06ba7dc7 | 811 | err_mem: |
1e7fe1a9 | 812 | pm_runtime_disable(dev); |
1e7fe1a9 | 813 | |
1e7fe1a9 | 814 | return ret; |
17cdd29d | 815 | } |
17cdd29d | 816 | |
03a8f438 RQ |
817 | static int usbhs_omap_remove_child(struct device *dev, void *data) |
818 | { | |
819 | dev_info(dev, "unregistering\n"); | |
820 | platform_device_unregister(to_platform_device(dev)); | |
821 | return 0; | |
822 | } | |
823 | ||
1e7fe1a9 KM |
824 | /** |
825 | * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs | |
826 | * @pdev: USB Host Controller being removed | |
827 | * | |
828 | * Reverses the effect of usbhs_omap_probe(). | |
829 | */ | |
4740f73f | 830 | static int usbhs_omap_remove(struct platform_device *pdev) |
17cdd29d | 831 | { |
1e7fe1a9 | 832 | pm_runtime_disable(&pdev->dev); |
1e7fe1a9 | 833 | |
03a8f438 RQ |
834 | /* remove children */ |
835 | device_for_each_child(&pdev->dev, NULL, usbhs_omap_remove_child); | |
1e7fe1a9 | 836 | return 0; |
17cdd29d | 837 | } |
1e7fe1a9 KM |
838 | |
839 | static const struct dev_pm_ops usbhsomap_dev_pm_ops = { | |
840 | .runtime_suspend = usbhs_runtime_suspend, | |
841 | .runtime_resume = usbhs_runtime_resume, | |
842 | }; | |
17cdd29d | 843 | |
03a8f438 RQ |
844 | static const struct of_device_id usbhs_omap_dt_ids[] = { |
845 | { .compatible = "ti,usbhs-host" }, | |
846 | { } | |
847 | }; | |
848 | ||
849 | MODULE_DEVICE_TABLE(of, usbhs_omap_dt_ids); | |
850 | ||
851 | ||
17cdd29d KM |
852 | static struct platform_driver usbhs_omap_driver = { |
853 | .driver = { | |
854 | .name = (char *)usbhs_driver_name, | |
1e7fe1a9 | 855 | .pm = &usbhsomap_dev_pm_ops, |
0f54e1e1 | 856 | .of_match_table = usbhs_omap_dt_ids, |
17cdd29d | 857 | }, |
10492ee8 | 858 | .probe = usbhs_omap_probe, |
ab3f2a86 | 859 | .remove = usbhs_omap_remove, |
17cdd29d KM |
860 | }; |
861 | ||
862 | MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>"); | |
03a8f438 | 863 | MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>"); |
17cdd29d KM |
864 | MODULE_ALIAS("platform:" USBHS_DRIVER_NAME); |
865 | MODULE_LICENSE("GPL v2"); | |
866 | MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI"); | |
867 | ||
10492ee8 | 868 | static int omap_usbhs_drvinit(void) |
17cdd29d | 869 | { |
10492ee8 | 870 | return platform_driver_register(&usbhs_omap_driver); |
17cdd29d KM |
871 | } |
872 | ||
873 | /* | |
874 | * init before ehci and ohci drivers; | |
875 | * The usbhs core driver should be initialized much before | |
876 | * the omap ehci and ohci probe functions are called. | |
4dc2cceb KM |
877 | * This usbhs core driver should be initialized after |
878 | * usb tll driver | |
17cdd29d | 879 | */ |
4dc2cceb | 880 | fs_initcall_sync(omap_usbhs_drvinit); |
17cdd29d | 881 | |
10492ee8 | 882 | static void omap_usbhs_drvexit(void) |
17cdd29d KM |
883 | { |
884 | platform_driver_unregister(&usbhs_omap_driver); | |
885 | } | |
886 | module_exit(omap_usbhs_drvexit); |