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Commit | Line | Data |
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0b11dbf7 MY |
1 | # |
2 | # Multifunction miscellaneous devices | |
3 | # | |
4 | ||
5 | menu "Multifunction device drivers" | |
6 | ||
4395e06e TC |
7 | config MISC |
8 | bool "Enable Driver Model for Misc drivers" | |
9 | depends on DM | |
10 | help | |
11 | Enable driver model for miscellaneous devices. This class is | |
12 | used only for those do not fit other more general classes. A | |
13 | set of generic read, write and ioctl methods may be used to | |
14 | access the device. | |
15 | ||
aaba703f SG |
16 | config SPL_MISC |
17 | bool "Enable Driver Model for Misc drivers in SPL" | |
18 | depends on SPL_DM | |
19 | help | |
20 | Enable driver model for miscellaneous devices. This class is | |
21 | used only for those do not fit other more general classes. A | |
22 | set of generic read, write and ioctl methods may be used to | |
23 | access the device. | |
24 | ||
25 | config TPL_MISC | |
26 | bool "Enable Driver Model for Misc drivers in TPL" | |
27 | depends on TPL_DM | |
28 | help | |
29 | Enable driver model for miscellaneous devices. This class is | |
30 | used only for those do not fit other more general classes. A | |
31 | set of generic read, write and ioctl methods may be used to | |
32 | access the device. | |
33 | ||
ca844dd8 TC |
34 | config ALTERA_SYSID |
35 | bool "Altera Sysid support" | |
36 | depends on MISC | |
37 | help | |
38 | Select this to enable a sysid for Altera devices. Please find | |
39 | details on the "Embedded Peripherals IP User Guide" of Altera. | |
40 | ||
aa5eb9a3 MB |
41 | config ATSHA204A |
42 | bool "Support for Atmel ATSHA204A module" | |
467f0c4d | 43 | select BITREVERSE |
aa5eb9a3 MB |
44 | depends on MISC |
45 | help | |
46 | Enable support for I2C connected Atmel's ATSHA204A | |
47 | CryptoAuthentication module found for example on the Turris Omnia | |
48 | board. | |
49 | ||
8479b9e6 TH |
50 | config GATEWORKS_SC |
51 | bool "Gateworks System Controller Support" | |
52 | depends on MISC | |
53 | help | |
54 | Enable access for the Gateworks System Controller used on Gateworks | |
55 | boards to provide a boot watchdog, power control, temperature monitor, | |
56 | voltage ADCs, and EEPROM. | |
57 | ||
49cd8e85 PT |
58 | config ROCKCHIP_EFUSE |
59 | bool "Rockchip e-fuse support" | |
60 | depends on MISC | |
61 | help | |
62 | Enable (read-only) access for the e-fuse block found in Rockchip | |
63 | SoCs: accesses can either be made using byte addressing and a length | |
64 | or through child-nodes that are generated based on the e-fuse map | |
65 | retrieved from the DTS. | |
66 | ||
67 | This driver currently supports the RK3399 only, but can easily be | |
68 | extended (by porting the read function from the Linux kernel sources) | |
69 | to support other recent Rockchip devices. | |
70 | ||
a907dc3f FX |
71 | config ROCKCHIP_OTP |
72 | bool "Rockchip OTP Support" | |
73 | depends on MISC | |
74 | help | |
75 | Enable (read-only) access for the one-time-programmable memory block | |
76 | found in Rockchip SoCs: accesses can either be made using byte | |
77 | addressing and a length or through child-nodes that are generated | |
78 | based on the e-fuse map retrieved from the DTS. | |
79 | ||
05307213 PP |
80 | config SIFIVE_OTP |
81 | bool "SiFive eMemory OTP driver" | |
82 | depends on MISC | |
83 | help | |
84 | Enable support for reading and writing the eMemory OTP on the | |
85 | SiFive SoCs. | |
86 | ||
0fabfeb2 LD |
87 | config VEXPRESS_CONFIG |
88 | bool "Enable support for Arm Versatile Express config bus" | |
89 | depends on MISC | |
90 | help | |
91 | If you say Y here, you will get support for accessing the | |
92 | configuration bus on the Arm Versatile Express boards via | |
93 | a sysreg driver. | |
94 | ||
6fb9ac15 SG |
95 | config CMD_CROS_EC |
96 | bool "Enable crosec command" | |
97 | depends on CROS_EC | |
98 | help | |
99 | Enable command-line access to the Chrome OS EC (Embedded | |
100 | Controller). This provides the 'crosec' command which has | |
101 | a number of sub-commands for performing EC tasks such as | |
102 | updating its flash, accessing a small saved context area | |
103 | and talking to the I2C bus behind the EC (if there is one). | |
104 | ||
105 | config CROS_EC | |
106 | bool "Enable Chrome OS EC" | |
107 | help | |
108 | Enable access to the Chrome OS EC. This is a separate | |
109 | microcontroller typically available on a SPI bus on Chromebooks. It | |
110 | provides access to the keyboard, some internal storage and may | |
111 | control access to the battery and main PMIC depending on the | |
112 | device. You can use the 'crosec' command to access it. | |
113 | ||
aaba703f SG |
114 | config SPL_CROS_EC |
115 | bool "Enable Chrome OS EC in SPL" | |
a074667d | 116 | depends on SPL |
aaba703f SG |
117 | help |
118 | Enable access to the Chrome OS EC in SPL. This is a separate | |
119 | microcontroller typically available on a SPI bus on Chromebooks. It | |
120 | provides access to the keyboard, some internal storage and may | |
121 | control access to the battery and main PMIC depending on the | |
122 | device. You can use the 'crosec' command to access it. | |
123 | ||
124 | config TPL_CROS_EC | |
125 | bool "Enable Chrome OS EC in TPL" | |
a074667d | 126 | depends on TPL |
aaba703f SG |
127 | help |
128 | Enable access to the Chrome OS EC in TPL. This is a separate | |
129 | microcontroller typically available on a SPI bus on Chromebooks. It | |
130 | provides access to the keyboard, some internal storage and may | |
131 | control access to the battery and main PMIC depending on the | |
132 | device. You can use the 'crosec' command to access it. | |
133 | ||
747093dd SG |
134 | config VPL_CROS_EC |
135 | bool "Enable Chrome OS EC in VPL" | |
136 | depends on VPL | |
137 | help | |
138 | Enable access to the Chrome OS EC in VPL. This is a separate | |
139 | microcontroller typically available on a SPI bus on Chromebooks. It | |
140 | provides access to the keyboard, some internal storage and may | |
141 | control access to the battery and main PMIC depending on the | |
142 | device. You can use the 'crosec' command to access it. | |
143 | ||
6fb9ac15 SG |
144 | config CROS_EC_I2C |
145 | bool "Enable Chrome OS EC I2C driver" | |
146 | depends on CROS_EC | |
147 | help | |
148 | Enable I2C access to the Chrome OS EC. This is used on older | |
149 | ARM Chromebooks such as snow and spring before the standard bus | |
150 | changed to SPI. The EC will accept commands across the I2C using | |
151 | a special message protocol, and provide responses. | |
152 | ||
153 | config CROS_EC_LPC | |
154 | bool "Enable Chrome OS EC LPC driver" | |
155 | depends on CROS_EC | |
156 | help | |
157 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
158 | Chromebooks such as link and falco. The keyboard is provided | |
159 | through a legacy port interface, so on x86 machines the main | |
160 | function of the EC is power and thermal management. | |
161 | ||
aaba703f SG |
162 | config SPL_CROS_EC_LPC |
163 | bool "Enable Chrome OS EC LPC driver in SPL" | |
164 | depends on CROS_EC | |
165 | help | |
166 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
167 | Chromebooks such as link and falco. The keyboard is provided | |
168 | through a legacy port interface, so on x86 machines the main | |
169 | function of the EC is power and thermal management. | |
170 | ||
171 | config TPL_CROS_EC_LPC | |
172 | bool "Enable Chrome OS EC LPC driver in TPL" | |
173 | depends on CROS_EC | |
174 | help | |
175 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
176 | Chromebooks such as link and falco. The keyboard is provided | |
177 | through a legacy port interface, so on x86 machines the main | |
178 | function of the EC is power and thermal management. | |
179 | ||
747093dd SG |
180 | config VPL_CROS_EC_LPC |
181 | bool "Enable Chrome OS EC LPC driver in VPL" | |
182 | depends on CROS_EC | |
183 | help | |
184 | Enable I2C access to the Chrome OS EC. This is used on x86 | |
185 | Chromebooks such as link and falco. The keyboard is provided | |
186 | through a legacy port interface, so on x86 machines the main | |
187 | function of the EC is power and thermal management. | |
188 | ||
47cb8c65 SG |
189 | config CROS_EC_SANDBOX |
190 | bool "Enable Chrome OS EC sandbox driver" | |
191 | depends on CROS_EC && SANDBOX | |
192 | help | |
193 | Enable a sandbox emulation of the Chrome OS EC. This supports | |
194 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
195 | EC flash read/write/erase support and a few other things. It is | |
196 | enough to perform a Chrome OS verified boot on sandbox. | |
197 | ||
aaba703f SG |
198 | config SPL_CROS_EC_SANDBOX |
199 | bool "Enable Chrome OS EC sandbox driver in SPL" | |
200 | depends on SPL_CROS_EC && SANDBOX | |
201 | help | |
202 | Enable a sandbox emulation of the Chrome OS EC in SPL. This supports | |
203 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
204 | EC flash read/write/erase support and a few other things. It is | |
205 | enough to perform a Chrome OS verified boot on sandbox. | |
206 | ||
207 | config TPL_CROS_EC_SANDBOX | |
208 | bool "Enable Chrome OS EC sandbox driver in TPL" | |
209 | depends on TPL_CROS_EC && SANDBOX | |
210 | help | |
211 | Enable a sandbox emulation of the Chrome OS EC in TPL. This supports | |
212 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
213 | EC flash read/write/erase support and a few other things. It is | |
214 | enough to perform a Chrome OS verified boot on sandbox. | |
215 | ||
747093dd SG |
216 | config VPL_CROS_EC_SANDBOX |
217 | bool "Enable Chrome OS EC sandbox driver in VPL" | |
218 | depends on VPL_CROS_EC && SANDBOX | |
219 | help | |
220 | Enable a sandbox emulation of the Chrome OS EC in VPL. This supports | |
221 | keyboard (use the -l flag to enable the LCD), verified boot context, | |
222 | EC flash read/write/erase support and a few other things. It is | |
223 | enough to perform a Chrome OS verified boot on sandbox. | |
224 | ||
6fb9ac15 SG |
225 | config CROS_EC_SPI |
226 | bool "Enable Chrome OS EC SPI driver" | |
227 | depends on CROS_EC | |
228 | help | |
229 | Enable SPI access to the Chrome OS EC. This is used on newer | |
230 | ARM Chromebooks such as pit, pi and nyan-big. The SPI interface | |
231 | provides a faster and more robust interface than I2C but the bugs | |
232 | are less interesting. | |
233 | ||
879704d8 SG |
234 | config DS4510 |
235 | bool "Enable support for DS4510 CPU supervisor" | |
236 | help | |
237 | Enable support for the Maxim DS4510 CPU supervisor. It has an | |
238 | integrated 64-byte EEPROM, four programmable non-volatile I/O pins | |
239 | and a configurable timer for the supervisor function. The device is | |
240 | connected over I2C. | |
241 | ||
c12e0d93 | 242 | config FSL_SEC_MON |
fe78378d | 243 | bool "Enable FSL SEC_MON Driver" |
244 | help | |
245 | Freescale Security Monitor block is responsible for monitoring | |
246 | system states. | |
247 | Security Monitor can be transitioned on any security failures, | |
248 | like software violations or hardware security violations. | |
1cdd9412 | 249 | |
79d66a6a | 250 | config IRQ |
182c5f1e | 251 | bool "Interrupt controller" |
79d66a6a | 252 | help |
182c5f1e | 253 | This enables support for interrupt controllers, including ITSS. |
79d66a6a SG |
254 | Some devices have extra features, such as Apollo Lake. The |
255 | device has its own uclass since there are several operations | |
256 | involved. | |
257 | ||
b5392c50 PB |
258 | config JZ4780_EFUSE |
259 | bool "Ingenic JZ4780 eFUSE support" | |
260 | depends on ARCH_JZ47XX | |
261 | help | |
262 | This selects support for the eFUSE on Ingenic JZ4780 SoCs. | |
263 | ||
3e020f03 PF |
264 | config MXC_OCOTP |
265 | bool "Enable MXC OCOTP Driver" | |
994ab731 | 266 | depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 |
0a6f625d | 267 | default y |
3e020f03 PF |
268 | help |
269 | If you say Y here, you will get support for the One Time | |
270 | Programmable memory pages that are stored on the some | |
271 | Freescale i.MX processors. | |
272 | ||
33e9a695 MS |
273 | config SPL_MXC_OCOTP |
274 | bool "Enable MXC OCOTP driver in SPL" | |
275 | depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) | |
276 | default y | |
277 | help | |
278 | If you say Y here, you will get support for the One Time | |
279 | Programmable memory pages, that are stored on some | |
280 | Freescale i.MX processors, in SPL. | |
281 | ||
4cf9e464 SR |
282 | config NUVOTON_NCT6102D |
283 | bool "Enable Nuvoton NCT6102D Super I/O driver" | |
284 | help | |
285 | If you say Y here, you will get support for the Nuvoton | |
286 | NCT6102D Super I/O driver. This can be used to enable or | |
287 | disable the legacy UART, the watchdog or other devices | |
288 | in the Nuvoton Super IO chips on X86 platforms. | |
289 | ||
5bee27aa | 290 | config P2SB |
d872e7da | 291 | bool "Intel Primary to Sideband Bridge" |
5bee27aa SG |
292 | depends on X86 || SANDBOX |
293 | help | |
d872e7da | 294 | This enables support for the Intel Primary to Sideband Bridge, |
5bee27aa SG |
295 | abbreviated to P2SB. The P2SB is used to access various peripherals |
296 | such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI | |
297 | space. The space is segmented into different channels and peripherals | |
298 | are accessed by device-specific means within those channels. Devices | |
299 | should be added in the device tree as subnodes of the P2SB. A | |
300 | Peripheral Channel Register? (PCR) API is provided to access those | |
301 | devices - see pcr_readl(), etc. | |
302 | ||
303 | config SPL_P2SB | |
d872e7da | 304 | bool "Intel Primary to Sideband Bridge in SPL" |
5bee27aa SG |
305 | depends on SPL && (X86 || SANDBOX) |
306 | help | |
d872e7da | 307 | The Primary to Sideband Bridge is used to access various peripherals |
5bee27aa SG |
308 | through memory-mapped I/O in a large chunk of PCI space. The space is |
309 | segmented into different channels and peripherals are accessed by | |
310 | device-specific means within those channels. Devices should be added | |
311 | in the device tree as subnodes of the p2sb. | |
312 | ||
313 | config TPL_P2SB | |
d872e7da | 314 | bool "Intel Primary to Sideband Bridge in TPL" |
5bee27aa SG |
315 | depends on TPL && (X86 || SANDBOX) |
316 | help | |
d872e7da | 317 | The Primary to Sideband Bridge is used to access various peripherals |
5bee27aa SG |
318 | through memory-mapped I/O in a large chunk of PCI space. The space is |
319 | segmented into different channels and peripherals are accessed by | |
320 | device-specific means within those channels. Devices should be added | |
321 | in the device tree as subnodes of the p2sb. | |
322 | ||
5fd6badb SG |
323 | config PWRSEQ |
324 | bool "Enable power-sequencing drivers" | |
325 | depends on DM | |
326 | help | |
327 | Power-sequencing drivers provide support for controlling power for | |
328 | devices. They are typically referenced by a phandle from another | |
329 | device. When the device is started up, its power sequence can be | |
330 | initiated. | |
331 | ||
332 | config SPL_PWRSEQ | |
333 | bool "Enable power-sequencing drivers for SPL" | |
334 | depends on PWRSEQ | |
335 | help | |
336 | Power-sequencing drivers provide support for controlling power for | |
337 | devices. They are typically referenced by a phandle from another | |
338 | device. When the device is started up, its power sequence can be | |
339 | initiated. | |
340 | ||
1cdd9412 SR |
341 | config PCA9551_LED |
342 | bool "Enable PCA9551 LED driver" | |
343 | help | |
344 | Enable driver for PCA9551 LED controller. This controller | |
345 | is connected via I2C. So I2C needs to be enabled. | |
346 | ||
347 | config PCA9551_I2C_ADDR | |
348 | hex "I2C address of PCA9551 LED controller" | |
349 | depends on PCA9551_LED | |
350 | default 0x60 | |
351 | help | |
352 | The I2C address of the PCA9551 LED controller. | |
f9917454 | 353 | |
c3600e1f PD |
354 | config STM32MP_FUSE |
355 | bool "Enable STM32MP fuse wrapper providing the fuse API" | |
356 | depends on ARCH_STM32MP && MISC | |
357 | default y if CMD_FUSE | |
358 | help | |
359 | If you say Y here, you will get support for the fuse API (OTP) | |
360 | for STM32MP architecture. | |
361 | This API is needed for CMD_FUSE. | |
362 | ||
4e280b91 CK |
363 | config STM32_RCC |
364 | bool "Enable RCC driver for the STM32 SoC's family" | |
71f6354b | 365 | depends on (ARCH_STM32 || ARCH_STM32MP) && MISC |
4e280b91 CK |
366 | help |
367 | Enable the STM32 RCC driver. The RCC block (Reset and Clock Control | |
368 | block) is responsible of the management of the clock and reset | |
369 | generation. | |
370 | This driver is similar to an MFD driver in the Linux kernel. | |
371 | ||
bd3ee84a SW |
372 | config TEGRA_CAR |
373 | bool "Enable support for the Tegra CAR driver" | |
374 | depends on TEGRA_NO_BPMP | |
375 | help | |
376 | The Tegra CAR (Clock and Reset Controller) is a HW module that | |
377 | controls almost all clocks and resets in a Tegra SoC. | |
378 | ||
73dd5c4c SW |
379 | config TEGRA186_BPMP |
380 | bool "Enable support for the Tegra186 BPMP driver" | |
381 | depends on TEGRA186 | |
382 | help | |
383 | The Tegra BPMP (Boot and Power Management Processor) is a separate | |
384 | auxiliary CPU embedded into Tegra to perform power management work, | |
385 | and controls related features such as clocks, resets, power domains, | |
386 | PMIC I2C bus, etc. This driver provides the core low-level | |
387 | communication path by which feature-specific drivers (such as clock) | |
388 | can make requests to the BPMP. This driver is similar to an MFD | |
389 | driver in the Linux kernel. | |
390 | ||
079ac595 SG |
391 | config TEST_DRV |
392 | bool "Enable support for test drivers" | |
393 | default y if SANDBOX | |
394 | help | |
395 | This enables drivers and uclasses that provides a way of testing the | |
396 | operations of memory allocation and driver/uclass methods in driver | |
397 | model. This should only be enabled for testing as it is not useful for | |
398 | anything else. | |
399 | ||
cc3fedb2 AF |
400 | config TWL4030_LED |
401 | bool "Enable TWL4030 LED controller" | |
402 | help | |
403 | Enable this to add support for the TWL4030 LED controller. | |
404 | ||
85056932 SR |
405 | config WINBOND_W83627 |
406 | bool "Enable Winbond Super I/O driver" | |
407 | help | |
408 | If you say Y here, you will get support for the Winbond | |
409 | W83627 Super I/O driver. This can be used to enable the | |
410 | legacy UART or other devices in the Winbond Super IO chips | |
411 | on X86 platforms. | |
412 | ||
fcf5c041 MY |
413 | config QFW |
414 | bool | |
415 | help | |
5b0b43e0 AC |
416 | Hidden option to enable QEMU fw_cfg interface and uclass. This will |
417 | be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. | |
418 | ||
419 | config QFW_PIO | |
420 | bool | |
421 | depends on QFW | |
422 | help | |
423 | Hidden option to enable PIO QEMU fw_cfg interface. This will be | |
424 | selected by the appropriate QEMU board. | |
fcf5c041 | 425 | |
5830b57b AC |
426 | config QFW_MMIO |
427 | bool | |
428 | depends on QFW | |
429 | help | |
430 | Hidden option to enable MMIO QEMU fw_cfg interface. This will be | |
431 | selected by the appropriate QEMU board. | |
432 | ||
d7e28918 | 433 | config I2C_EEPROM |
434 | bool "Enable driver for generic I2C-attached EEPROMs" | |
435 | depends on MISC | |
436 | help | |
437 | Enable a generic driver for EEPROMs attached via I2C. | |
e3f24d4f | 438 | |
d81a1de9 WY |
439 | |
440 | config SPL_I2C_EEPROM | |
441 | bool "Enable driver for generic I2C-attached EEPROMs for SPL" | |
442 | depends on MISC && SPL && SPL_DM | |
443 | help | |
444 | This option is an SPL-variant of the I2C_EEPROM option. | |
445 | See the help of I2C_EEPROM for details. | |
446 | ||
e3f24d4f AF |
447 | config SYS_I2C_EEPROM_ADDR |
448 | hex "Chip address of the EEPROM device" | |
88cd7d0e | 449 | depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM |
e3f24d4f AF |
450 | default 0 |
451 | ||
88cd7d0e | 452 | if I2C_EEPROM |
e3f24d4f AF |
453 | |
454 | config SYS_I2C_EEPROM_ADDR_OVERFLOW | |
455 | hex "EEPROM Address Overflow" | |
5fd4a7ed | 456 | default 0x0 |
e3f24d4f AF |
457 | help |
458 | EEPROM chips that implement "address overflow" are ones | |
459 | like Catalyst 24WC04/08/16 which has 9/10/11 bits of | |
460 | address and the extra bits end up in the "chip address" bit | |
461 | slots. This makes a 24WC08 (1Kbyte) chip look like four 256 | |
462 | byte chips. | |
463 | ||
464 | endif | |
465 | ||
86da8c12 MS |
466 | config GDSYS_RXAUI_CTRL |
467 | bool "Enable gdsys RXAUI control driver" | |
468 | depends on MISC | |
469 | help | |
470 | Support gdsys FPGA's RXAUI control. | |
7e86242b MS |
471 | |
472 | config GDSYS_IOEP | |
473 | bool "Enable gdsys IOEP driver" | |
474 | depends on MISC | |
475 | help | |
476 | Support gdsys FPGA's IO endpoint driver. | |
d2166319 MS |
477 | |
478 | config MPC83XX_SERDES | |
479 | bool "Enable MPC83xx serdes driver" | |
480 | depends on MISC | |
481 | help | |
482 | Support for serdes found on MPC83xx SoCs. | |
483 | ||
62030004 TFC |
484 | config FS_LOADER |
485 | bool "Enable loader driver for file system" | |
486 | help | |
487 | This is file system generic loader which can be used to load | |
488 | the file image from the storage into target such as memory. | |
489 | ||
490 | The consumer driver would then use this loader to program whatever, | |
491 | ie. the FPGA device. | |
492 | ||
b071a077 K |
493 | config SPL_FS_LOADER |
494 | bool "Enable loader driver for file system" | |
495 | help | |
496 | This is file system generic loader which can be used to load | |
497 | the file image from the storage into target such as memory. | |
498 | ||
499 | The consumer driver would then use this loader to program whatever, | |
500 | ie. the FPGA device. | |
501 | ||
c0a2b086 MS |
502 | config GDSYS_SOC |
503 | bool "Enable gdsys SOC driver" | |
504 | depends on MISC | |
505 | help | |
506 | Support for gdsys IHS SOC, a simple bus associated with each gdsys | |
507 | IHS (Integrated Hardware Systems) FPGA, which holds all devices whose | |
508 | register maps are contained within the FPGA's register map. | |
509 | ||
ab88bd2b MS |
510 | config IHS_FPGA |
511 | bool "Enable IHS FPGA driver" | |
512 | depends on MISC | |
513 | help | |
514 | Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on | |
515 | gdsys devices, which supply the majority of the functionality offered | |
516 | by the devices. This driver supports both CON and CPU variants of the | |
517 | devices, depending on the device tree entry. | |
344eb6d5 TK |
518 | config ESM_K3 |
519 | bool "Enable K3 ESM driver" | |
520 | depends on ARCH_K3 | |
521 | help | |
522 | Support ESM (Error Signaling Module) on TI K3 SoCs. | |
ab88bd2b | 523 | |
f8164958 EH |
524 | config MICROCHIP_FLEXCOM |
525 | bool "Enable Microchip Flexcom driver" | |
526 | depends on MISC | |
527 | help | |
528 | The Atmel Flexcom is just a wrapper which embeds a SPI controller, | |
529 | an I2C controller and an USART. | |
530 | Only one function can be used at a time and is chosen at boot time | |
531 | according to the device tree. | |
532 | ||
9d233b4e TK |
533 | config K3_AVS0 |
534 | depends on ARCH_K3 && SPL_DM_REGULATOR | |
535 | bool "AVS class 0 support for K3 devices" | |
536 | help | |
537 | K3 devices have the optimized voltage values for the main voltage | |
538 | domains stored in efuse within the VTM IP. This driver reads the | |
539 | optimized voltage from the efuse, so that it can be programmed | |
540 | to the PMIC on board. | |
541 | ||
3b36b38f TK |
542 | config ESM_PMIC |
543 | bool "Enable PMIC ESM driver" | |
544 | depends on DM_PMIC | |
545 | help | |
546 | Support ESM (Error Signal Monitor) on PMIC devices. ESM is used | |
547 | typically to reboot the board in error condition. | |
548 | ||
98ab831d TR |
549 | config FSL_IFC |
550 | bool | |
551 | ||
42595eb7 MW |
552 | config SL28CPLD |
553 | bool "Enable Kontron sl28cpld multi-function driver" | |
554 | depends on DM_I2C | |
555 | help | |
556 | Support for the Kontron sl28cpld management controller. This is | |
557 | the base driver which provides common access methods for the | |
558 | sub-drivers. | |
559 | ||
0b11dbf7 | 560 | endmenu |