[people/ms/u-boot.git] / drivers / misc / ali512x.c

/*
 * (C) Copyright 2002
 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Based on sc520cdp.c from rolo 1.6:
 *----------------------------------------------------------------------
 * (C) Copyright 2000
 * Sysgo Real-Time Solutions GmbH
 * Klein-Winternheim, Germany
 *----------------------------------------------------------------------
 */

#include <config.h>

#include <common.h>
#include <asm/io.h>
#include <ali512x.h>


/* ALI M5123 Logical device numbers:
 * 0 FDC
 * 1 unused?
 * 2 unused?
 * 3 lpt
 * 4 UART1
 * 5 UART2
 * 6 RTC
 * 7 mouse/kbd
 * 8 CIO
 */

/*
 ************************************************************
 *  Some access primitives for the ALi chip:                *
 ************************************************************
 */

static void ali_write(u8 index, u8 value)
{
	/* write an arbirary register */
	outb(index, ALI_INDEX);
	outb(value, ALI_DATA);
}

#if 0
static int ali_read(u8 index)
{
	outb(index, ALI_INDEX);
	return inb(ALI_DATA);
}
#endif

#define ALI_OPEN() \
	outb(0x51, ALI_INDEX); \
	outb(0x23, ALI_INDEX)


#define ALI_CLOSE() \
	outb(0xbb, ALI_INDEX)

/* Select a logical device */
#define ALI_SELDEV(dev)	\
	ali_write(0x07, dev)


void ali512x_init(void)
{
	ALI_OPEN();

	ali_write(0x02, 0x01);	/* soft reset */
	ali_write(0x03, 0x03);	/* disable access to CIOs */
	ali_write(0x22, 0x00);	/* disable direct powerdown */
	ali_write(0x23, 0x00);	/* disable auto powerdown */
	ali_write(0x24, 0x00);	/* IR 8 is active hi, pin26 is PDIR */

	ALI_CLOSE();
}

void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel)
{
	ALI_OPEN();
	ALI_SELDEV(0);

	ali_write(0x30, enabled?1:0);
	if (enabled) {
		ali_write(0x60, io >> 8);
		ali_write(0x61, io & 0xff);
		ali_write(0x70, irq);
		ali_write(0x74, dma_channel);

		/* AT mode, no drive swap */
		ali_write(0xf0, 0x08);
		ali_write(0xf1, 0x00);
		ali_write(0xf2, 0xff);
		ali_write(0xf4, 0x00);
	}
	ALI_CLOSE();
}


void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel)
{
	ALI_OPEN();
	ALI_SELDEV(3);

	ali_write(0x30, enabled?1:0);
	if (enabled) {
		ali_write(0x60, io >> 8);
		ali_write(0x61, io & 0xff);
		ali_write(0x70, irq);
		ali_write(0x74, dma_channel);

		/* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */
		ali_write(0xf0, 0xbc);
		/* 12 MHz, Burst DMA in ECP */
		ali_write(0xf1, 0x05);
	}
	ALI_CLOSE();

}

void ali512x_set_uart(int enabled, int index, u16 io, u8 irq)
{
	ALI_OPEN();
	ALI_SELDEV(index?5:4);

	ali_write(0x30, enabled?1:0);
	if (enabled) {
		ali_write(0x60, io >> 8);
		ali_write(0x61, io & 0xff);
		ali_write(0x70, irq);

		ali_write(0xf0, 0x00);
		ali_write(0xf1, 0x00);

		/* huh? write 0xf2 twice - a typo in rolo
		 * or some secret ali errata? Who knows?
		 */
		if (index) {
			ali_write(0xf2, 0x00);
		}
		ali_write(0xf2, 0x0c);
	}
	ALI_CLOSE();

}

void ali512x_set_uart2_irda(int enabled)
{
	ALI_OPEN();
	ALI_SELDEV(5);

	ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */
	ALI_CLOSE();

}

void ali512x_set_rtc(int enabled, u16 io, u8 irq)
{
	ALI_OPEN();
	ALI_SELDEV(6);

	ali_write(0x30, enabled?1:0);
	if (enabled) {
		ali_write(0x60, io >> 8);
		ali_write(0x61, io & 0xff);
		ali_write(0x70, irq);

		ali_write(0xf0, 0x00);
	}
	ALI_CLOSE();
}

void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq)
{
	ALI_OPEN();
	ALI_SELDEV(7);

	ali_write(0x30, enabled?1:0);
	if (enabled) {
		ali_write(0x70, kbc_irq);
		ali_write(0x72, mouse_irq);

		ali_write(0xf0, 0x00);
	}
	ALI_CLOSE();
}


/* Common I/O
 *
 * (This descripotsion is base on several incompete sources
 *  since I have not been able to obtain any datasheet for the device
 *  there may be some mis-understandings burried in here.
 *  -- Daniel daniel@omicron.se)
 *
 * There are 22 CIO pins numbered
 * 10-17
 * 20-25
 * 30-37
 *
 * 20-24 are dedicated CIO pins, the other 17 are muliplexed with
 * other functions.
 *
 *           Secondary
 * CIO Pin   Function    Decription
 * =======================================================
 * CIO10     IRQIN1      Interrupt input 1?
 * CIO11     IRQIN2      Interrupt input 2?
 * CIO12     IRRX        IrDa Receive
 * CIO13     IRTX        IrDa Transmit
 * CIO14     P21         KBC P21 fucntion
 * CIO15     P20         KBC P21 fucntion
 * CIO16     I2C_CLK     I2C Clock
 * CIO17     I2C_DAT     I2C Data
 *
 * CIO20     -
 * CIO21     -
 * CIO22     -
 * CIO23     -
 * CIO24     -
 * CIO25     LOCK        Keylock
 *
 * CIO30     KBC_CLK     Keybaord Clock
 * CIO31     CS0J        General Chip Select decoder CS0J
 * CIO32     CS1J        General Chip Select decoder CS1J
 * CIO33     ALT_KCLK    Alternative Keyboard Clock
 * CIO34     ALT_KDAT    Alternative Keyboard Data
 * CIO35     ALT_MCLK    Alternative Mouse Clock
 * CIO36     ALT_MDAT    Alternative Mouse Data
 * CIO37     ALT_KBC     Alternative KBC select
 *
 * The CIO use an indirect address scheme.
 *
 * Reigster 3 in the SIO is used to select the index and data
 * port addresses where the CIO I/O registers show up.
 * The function selection registers are accessible under
 * function SIO 8.
 *
 * SIO reigster 3 (CIO Address Selection) bit definitions:
 * bit 7   CIO index and data registers enabled
 * bit 1-0 CIO indirect registers port address select
 *	 0  index = 0xE0 data = 0xE1
 *       1  index = 0xE2 data = 0xE3
 *       2  index = 0xE4 data = 0xE5
 *       3  index = 0xEA data = 0xEB
 *
 * There are three CIO I/O register accessed via CIO index port and CIO data port
 * 0x01     CIO 10-17 data
 * 0x02     CIO 20-25 data (bits 7-6 unused)
 * 0x03     CIO 30-37 data
 *
 *
 * The pin function is accessed through normal
 * SIO registers, each register have the same format:
 *
 * Bit   Function                     Value
 * 0     Input/output                 1=input
 * 1     Polarity of signal           1=inverted
 * 2     Unused                       ??
 * 3     Function (normal or special) 1=special
 * 7-4   Unused
 *
 * SIO REG
 * 0xe0     CIO 10 Config
 * 0xe1     CIO 11 Config
 * 0xe2     CIO 12 Config
 * 0xe3     CIO 13 Config
 * 0xe4     CIO 14 Config
 * 0xe5     CIO 15 Config
 * 0xe6     CIO 16 Config
 * 0xe7     CIO 16 Config
 *
 * 0xe8     CIO 20 Config
 * 0xe9     CIO 21 Config
 * 0xea     CIO 22 Config
 * 0xeb     CIO 23 Config
 * 0xec     CIO 24 Config
 * 0xed     CIO 25 Config
 *
 * 0xf5     CIO 30 Config
 * 0xf6     CIO 31 Config
 * 0xf7     CIO 32 Config
 * 0xf8     CIO 33 Config
 * 0xf9     CIO 34 Config
 * 0xfa     CIO 35 Config
 * 0xfb     CIO 36 Config
 * 0xfc     CIO 37 Config
 *
 */

#define ALI_CIO_PORT_SEL 0x83
#define ALI_CIO_INDEX    0xea
#define ALI_CIO_DATA     0xeb

void ali512x_set_cio(int enabled)
{
	int i;

	ALI_OPEN();

	if (enabled) {
		ali_write(0x3, ALI_CIO_PORT_SEL);    /* Enable CIO data register */
	} else {
		ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80);
	}

	ALI_SELDEV(8);

	ali_write(0x30, enabled?1:0);

	/* set all pins to input to start with */
	for (i=0xe0;i<0xee;i++) {
		ali_write(i, 1);
	}

	for (i=0xf5;i<0xfe;i++) {
		ali_write(i, 1);
	}

	ALI_CLOSE();
}


void ali512x_cio_function(int pin, int special, int inv, int input)
{
	u8 data;
	u8 addr;

	/* valid pins are 10-17, 20-25 and 30-37 */
	if (pin >= 10 && pin <= 17) {
		addr = 0xe0+(pin&7);
	} else if (pin >= 20 && pin <= 25) {
		addr = 0xe8+(pin&7);
	} else if (pin >= 30 && pin <= 37) {
		addr = 0xf5+(pin&7);
	} else {
		return;
	}

	ALI_OPEN();

	ALI_SELDEV(8);


	data=0xf4;
	if (special) {
		data |= 0x08;
	} else {
		if (inv) {
			data |= 0x02;
		}
		if (input) {
			data |= 0x01;
		}
	}

	ali_write(addr, data);

	ALI_CLOSE();
}

void ali512x_cio_out(int pin, int value)
{
	u8 reg;
	u8 data;
	u8 bit;

	reg = pin/10;
	bit = 1 << (pin%10);


	outb(reg, ALI_CIO_INDEX);     /* select I/O register */
	data = inb(ALI_CIO_DATA);
	if (value) {
		data |= bit;
	} else {
		data &= ~bit;
	}
	outb(data, ALI_CIO_DATA);
}

int ali512x_cio_in(int pin)
{
	u8 reg;
	u8 data;
	u8 bit;

	/* valid pins are 10-17, 20-25 and 30-37 */
	reg = pin/10;
	bit = 1 << (pin%10);


	outb(reg, ALI_CIO_INDEX);     /* select I/O register */
	data = inb(ALI_CIO_DATA);

	return data & bit;
}
Commit	Line	Data
2262cfee WD	1	/*
2262cfee WD	2	* (C) Copyright 2002
fa82f871	3	* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
2262cfee WD	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* Based on sc520cdp.c from rolo 1.6:
	26	*----------------------------------------------------------------------
	27	* (C) Copyright 2000
	28	* Sysgo Real-Time Solutions GmbH
	29	* Klein-Winternheim, Germany
	30	*----------------------------------------------------------------------
	31	*/
	32
7a8e9bed WD	33	#include <config.h>
7a8e9bed WD	34
2262cfee WD	35	#include <common.h>
2262cfee WD	36	#include <asm/io.h>
ece444b4	37	#include <ali512x.h>
2262cfee WD	38
	39
	40	/* ALI M5123 Logical device numbers:
	41	* 0 FDC
	42	* 1 unused?
	43	* 2 unused?
	44	* 3 lpt
	45	* 4 UART1
	46	* 5 UART2
	47	* 6 RTC
	48	* 7 mouse/kbd
	49	* 8 CIO
	50	*/
	51
	52	/*
	53	************************************************************
	54	* Some access primitives for the ALi chip: *
	55	************************************************************
	56	*/
	57
	58	static void ali_write(u8 index, u8 value)
8bde7f77	59	{
2262cfee WD	60	/* write an arbirary register */
	61	outb(index, ALI_INDEX);
	62	outb(value, ALI_DATA);
	63	}
	64
7a8e9bed	65	#if 0
2262cfee WD	66	static int ali_read(u8 index)
	67	{
	68	outb(index, ALI_INDEX);
	69	return inb(ALI_DATA);
	70	}
7a8e9bed	71	#endif
2262cfee WD	72
2262cfee WD	73	#define ALI_OPEN() \
7a8e9bed	74	outb(0x51, ALI_INDEX); \
8bde7f77	75	outb(0x23, ALI_INDEX)
2262cfee WD	76
	77
	78	#define ALI_CLOSE() \
7a8e9bed	79	outb(0xbb, ALI_INDEX)
2262cfee WD	80
	81	/* Select a logical device */
	82	#define ALI_SELDEV(dev) \
8bde7f77	83	ali_write(0x07, dev)
2262cfee WD	84
	85
	86	void ali512x_init(void)
	87	{
	88	ALI_OPEN();
	89
	90	ali_write(0x02, 0x01); /* soft reset */
	91	ali_write(0x03, 0x03); /* disable access to CIOs */
	92	ali_write(0x22, 0x00); /* disable direct powerdown */
	93	ali_write(0x23, 0x00); /* disable auto powerdown */
	94	ali_write(0x24, 0x00); /* IR 8 is active hi, pin26 is PDIR */
	95
	96	ALI_CLOSE();
	97	}
	98
	99	void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel)
	100	{
	101	ALI_OPEN();
	102	ALI_SELDEV(0);
8bde7f77	103
2262cfee WD	104	ali_write(0x30, enabled?1:0);
	105	if (enabled) {
	106	ali_write(0x60, io >> 8);
	107	ali_write(0x61, io & 0xff);
	108	ali_write(0x70, irq);
	109	ali_write(0x74, dma_channel);
8bde7f77	110
2262cfee WD	111	/* AT mode, no drive swap */
	112	ali_write(0xf0, 0x08);
	113	ali_write(0xf1, 0x00);
	114	ali_write(0xf2, 0xff);
	115	ali_write(0xf4, 0x00);
	116	}
	117	ALI_CLOSE();
	118	}
	119
	120
	121	void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel)
	122	{
	123	ALI_OPEN();
	124	ALI_SELDEV(3);
8bde7f77	125
2262cfee WD	126	ali_write(0x30, enabled?1:0);
	127	if (enabled) {
	128	ali_write(0x60, io >> 8);
	129	ali_write(0x61, io & 0xff);
	130	ali_write(0x70, irq);
	131	ali_write(0x74, dma_channel);
8bde7f77	132
2262cfee WD	133	/* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */
	134	ali_write(0xf0, 0xbc);
	135	/* 12 MHz, Burst DMA in ECP */
	136	ali_write(0xf1, 0x05);
	137	}
	138	ALI_CLOSE();
	139
	140	}
	141
	142	void ali512x_set_uart(int enabled, int index, u16 io, u8 irq)
	143	{
	144	ALI_OPEN();
	145	ALI_SELDEV(index?5:4);
8bde7f77	146
2262cfee WD	147	ali_write(0x30, enabled?1:0);
	148	if (enabled) {
	149	ali_write(0x60, io >> 8);
	150	ali_write(0x61, io & 0xff);
	151	ali_write(0x70, irq);
8bde7f77	152
2262cfee WD	153	ali_write(0xf0, 0x00);
2262cfee WD	154	ali_write(0xf1, 0x00);
8bde7f77	155
2262cfee	156	/* huh? write 0xf2 twice - a typo in rolo
8bde7f77	157	* or some secret ali errata? Who knows?
2262cfee WD	158	*/
	159	if (index) {
	160	ali_write(0xf2, 0x00);
	161	}
	162	ali_write(0xf2, 0x0c);
	163	}
	164	ALI_CLOSE();
	165
	166	}
	167
	168	void ali512x_set_uart2_irda(int enabled)
	169	{
	170	ALI_OPEN();
	171	ALI_SELDEV(5);
8bde7f77	172
2262cfee WD	173	ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */
	174	ALI_CLOSE();
	175
	176	}
	177
	178	void ali512x_set_rtc(int enabled, u16 io, u8 irq)
	179	{
	180	ALI_OPEN();
	181	ALI_SELDEV(6);
8bde7f77	182
2262cfee WD	183	ali_write(0x30, enabled?1:0);
	184	if (enabled) {
	185	ali_write(0x60, io >> 8);
	186	ali_write(0x61, io & 0xff);
	187	ali_write(0x70, irq);
	188
	189	ali_write(0xf0, 0x00);
	190	}
	191	ALI_CLOSE();
	192	}
	193
	194	void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq)
	195	{
	196	ALI_OPEN();
	197	ALI_SELDEV(7);
8bde7f77	198
2262cfee WD	199	ali_write(0x30, enabled?1:0);
	200	if (enabled) {
	201	ali_write(0x70, kbc_irq);
8bde7f77 WD	202	ali_write(0x72, mouse_irq);
8bde7f77 WD	203
2262cfee WD	204	ali_write(0xf0, 0x00);
	205	}
	206	ALI_CLOSE();
	207	}
	208
	209
	210	/* Common I/O
8bde7f77	211	*
2262cfee WD	212	* (This descripotsion is base on several incompete sources
2262cfee WD	213	* since I have not been able to obtain any datasheet for the device
8bde7f77	214	* there may be some mis-understandings burried in here.
2262cfee	215	* -- Daniel daniel@omicron.se)
8bde7f77	216	*
2262cfee WD	217	* There are 22 CIO pins numbered
	218	* 10-17
	219	* 20-25
	220	* 30-37
8bde7f77	221	*
2262cfee WD	222	* 20-24 are dedicated CIO pins, the other 17 are muliplexed with
2262cfee WD	223	* other functions.
8bde7f77 WD	224	*
8bde7f77 WD	225	* Secondary
2262cfee WD	226	* CIO Pin Function Decription
	227	* =======================================================
	228	* CIO10 IRQIN1 Interrupt input 1?
	229	* CIO11 IRQIN2 Interrupt input 2?
	230	* CIO12 IRRX IrDa Receive
	231	* CIO13 IRTX IrDa Transmit
	232	* CIO14 P21 KBC P21 fucntion
	233	* CIO15 P20 KBC P21 fucntion
	234	* CIO16 I2C_CLK I2C Clock
	235	* CIO17 I2C_DAT I2C Data
8bde7f77	236	*
2262cfee WD	237	* CIO20 -
	238	* CIO21 -
	239	* CIO22 -
	240	* CIO23 -
	241	* CIO24 -
	242	* CIO25 LOCK Keylock
8bde7f77	243	*
2262cfee WD	244	* CIO30 KBC_CLK Keybaord Clock
	245	* CIO31 CS0J General Chip Select decoder CS0J
	246	* CIO32 CS1J General Chip Select decoder CS1J
	247	* CIO33 ALT_KCLK Alternative Keyboard Clock
	248	* CIO34 ALT_KDAT Alternative Keyboard Data
	249	* CIO35 ALT_MCLK Alternative Mouse Clock
	250	* CIO36 ALT_MDAT Alternative Mouse Data
	251	* CIO37 ALT_KBC Alternative KBC select
	252	*
8bde7f77 WD	253	* The CIO use an indirect address scheme.
8bde7f77 WD	254	*
7a8e9bed WD	255	* Reigster 3 in the SIO is used to select the index and data
7a8e9bed WD	256	* port addresses where the CIO I/O registers show up.
8bde7f77 WD	257	* The function selection registers are accessible under
	258	* function SIO 8.
	259	*
2262cfee	260	* SIO reigster 3 (CIO Address Selection) bit definitions:
7a8e9bed WD	261	* bit 7 CIO index and data registers enabled
7a8e9bed WD	262	* bit 1-0 CIO indirect registers port address select
53677ef1	263	* 0 index = 0xE0 data = 0xE1
2262cfee WD	264	* 1 index = 0xE2 data = 0xE3
	265	* 2 index = 0xE4 data = 0xE5
	266	* 3 index = 0xEA data = 0xEB
8bde7f77	267	*
7a8e9bed	268	* There are three CIO I/O register accessed via CIO index port and CIO data port
2262cfee WD	269	* 0x01 CIO 10-17 data
	270	* 0x02 CIO 20-25 data (bits 7-6 unused)
	271	* 0x03 CIO 30-37 data
8bde7f77 WD	272	*
	273	*
	274	* The pin function is accessed through normal
2262cfee	275	* SIO registers, each register have the same format:
8bde7f77	276	*
2262cfee	277	* Bit Function Value
8bde7f77	278	* 0 Input/output 1=input
2262cfee WD	279	* 1 Polarity of signal 1=inverted
	280	* 2 Unused ??
	281	* 3 Function (normal or special) 1=special
	282	* 7-4 Unused
8bde7f77	283	*
2262cfee WD	284	* SIO REG
	285	* 0xe0 CIO 10 Config
	286	* 0xe1 CIO 11 Config
	287	* 0xe2 CIO 12 Config
	288	* 0xe3 CIO 13 Config
	289	* 0xe4 CIO 14 Config
	290	* 0xe5 CIO 15 Config
	291	* 0xe6 CIO 16 Config
	292	* 0xe7 CIO 16 Config
	293	*
	294	* 0xe8 CIO 20 Config
	295	* 0xe9 CIO 21 Config
	296	* 0xea CIO 22 Config
	297	* 0xeb CIO 23 Config
	298	* 0xec CIO 24 Config
	299	* 0xed CIO 25 Config
	300	*
	301	* 0xf5 CIO 30 Config
	302	* 0xf6 CIO 31 Config
	303	* 0xf7 CIO 32 Config
	304	* 0xf8 CIO 33 Config
	305	* 0xf9 CIO 34 Config
	306	* 0xfa CIO 35 Config
	307	* 0xfb CIO 36 Config
	308	* 0xfc CIO 37 Config
8bde7f77	309	*
2262cfee WD	310	*/
2262cfee WD	311
7a8e9bed WD	312	#define ALI_CIO_PORT_SEL 0x83
	313	#define ALI_CIO_INDEX 0xea
	314	#define ALI_CIO_DATA 0xeb
	315
2262cfee WD	316	void ali512x_set_cio(int enabled)
	317	{
	318	int i;
8bde7f77	319
2262cfee	320	ALI_OPEN();
8bde7f77	321
7a8e9bed WD	322	if (enabled) {
	323	ali_write(0x3, ALI_CIO_PORT_SEL); /* Enable CIO data register */
	324	} else {
	325	ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80);
	326	}
8bde7f77	327
2262cfee	328	ALI_SELDEV(8);
8bde7f77	329
2262cfee	330	ali_write(0x30, enabled?1:0);
8bde7f77	331
2262cfee WD	332	/* set all pins to input to start with */
	333	for (i=0xe0;i<0xee;i++) {
	334	ali_write(i, 1);
	335	}
8bde7f77	336
2262cfee WD	337	for (i=0xf5;i<0xfe;i++) {
	338	ali_write(i, 1);
	339	}
8bde7f77	340
2262cfee WD	341	ALI_CLOSE();
	342	}
	343
7a8e9bed	344
2262cfee WD	345	void ali512x_cio_function(int pin, int special, int inv, int input)
	346	{
	347	u8 data;
	348	u8 addr;
8bde7f77	349
2262cfee	350	/* valid pins are 10-17, 20-25 and 30-37 */
8bde7f77	351	if (pin >= 10 && pin <= 17) {
7a8e9bed	352	addr = 0xe0+(pin&7);
2262cfee	353	} else if (pin >= 20 && pin <= 25) {
7a8e9bed	354	addr = 0xe8+(pin&7);
8bde7f77	355	} else if (pin >= 30 && pin <= 37) {
7a8e9bed	356	addr = 0xf5+(pin&7);
2262cfee WD	357	} else {
	358	return;
	359	}
8bde7f77	360
2262cfee	361	ALI_OPEN();
7a8e9bed	362
2262cfee	363	ALI_SELDEV(8);
8bde7f77 WD	364
8bde7f77 WD	365
7a8e9bed	366	data=0xf4;
2262cfee WD	367	if (special) {
	368	data \|= 0x08;
	369	} else {
	370	if (inv) {
	371	data \|= 0x02;
	372	}
	373	if (input) {
	374	data \|= 0x01;
	375	}
	376	}
8bde7f77	377
2262cfee	378	ali_write(addr, data);
8bde7f77	379
2262cfee WD	380	ALI_CLOSE();
	381	}
	382
8bde7f77	383	void ali512x_cio_out(int pin, int value)
2262cfee WD	384	{
	385	u8 reg;
	386	u8 data;
	387	u8 bit;
8bde7f77	388
7a8e9bed WD	389	reg = pin/10;
7a8e9bed WD	390	bit = 1 << (pin%10);
8bde7f77 WD	391
8bde7f77 WD	392
7a8e9bed WD	393	outb(reg, ALI_CIO_INDEX); /* select I/O register */
7a8e9bed WD	394	data = inb(ALI_CIO_DATA);
2262cfee WD	395	if (value) {
	396	data \|= bit;
	397	} else {
	398	data &= ~bit;
	399	}
7a8e9bed	400	outb(data, ALI_CIO_DATA);
2262cfee WD	401	}
	402
	403	int ali512x_cio_in(int pin)
	404	{
	405	u8 reg;
	406	u8 data;
	407	u8 bit;
8bde7f77	408
2262cfee	409	/* valid pins are 10-17, 20-25 and 30-37 */
7a8e9bed WD	410	reg = pin/10;
7a8e9bed WD	411	bit = 1 << (pin%10);
8bde7f77 WD	412
8bde7f77 WD	413
7a8e9bed WD	414	outb(reg, ALI_CIO_INDEX); /* select I/O register */
7a8e9bed WD	415	data = inb(ALI_CIO_DATA);
8bde7f77 WD	416
8bde7f77 WD	417	return data & bit;
2262cfee	418	}