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Merge tag 'misc-habanalabs-fixes-2019-06-06' of git://people.freedesktop.org/~gabbayo...
[thirdparty/kernel/linux.git] / drivers / misc / habanalabs / goya / goya_coresight.c
CommitLineData
315bc055
OS		 1// SPDX-License-Identifier: GPL-2.0
2
3/*
4 * Copyright 2016-2019 HabanaLabs, Ltd.
5 * All Rights Reserved.
6 */
7
8#include "goyaP.h"
8ba2876d
OS		 9#include "include/goya/goya_coresight.h"
10#include "include/goya/asic_reg/goya_regs.h"
11
12#include <uapi/misc/habanalabs.h>
13
14#include <linux/coresight.h>
15
16#define GOYA_PLDM_CORESIGHT_TIMEOUT_USEC (CORESIGHT_TIMEOUT_USEC * 100)
17
18static u64 debug_stm_regs[GOYA_STM_LAST + 1] = {
19 [GOYA_STM_CPU] = mmCPU_STM_BASE,
20 [GOYA_STM_DMA_CH_0_CS] = mmDMA_CH_0_CS_STM_BASE,
21 [GOYA_STM_DMA_CH_1_CS] = mmDMA_CH_1_CS_STM_BASE,
22 [GOYA_STM_DMA_CH_2_CS] = mmDMA_CH_2_CS_STM_BASE,
23 [GOYA_STM_DMA_CH_3_CS] = mmDMA_CH_3_CS_STM_BASE,
24 [GOYA_STM_DMA_CH_4_CS] = mmDMA_CH_4_CS_STM_BASE,
25 [GOYA_STM_DMA_MACRO_CS] = mmDMA_MACRO_CS_STM_BASE,
26 [GOYA_STM_MME1_SBA] = mmMME1_SBA_STM_BASE,
27 [GOYA_STM_MME3_SBB] = mmMME3_SBB_STM_BASE,
28 [GOYA_STM_MME4_WACS2] = mmMME4_WACS2_STM_BASE,
29 [GOYA_STM_MME4_WACS] = mmMME4_WACS_STM_BASE,
30 [GOYA_STM_MMU_CS] = mmMMU_CS_STM_BASE,
31 [GOYA_STM_PCIE] = mmPCIE_STM_BASE,
32 [GOYA_STM_PSOC] = mmPSOC_STM_BASE,
33 [GOYA_STM_TPC0_EML] = mmTPC0_EML_STM_BASE,
34 [GOYA_STM_TPC1_EML] = mmTPC1_EML_STM_BASE,
35 [GOYA_STM_TPC2_EML] = mmTPC2_EML_STM_BASE,
36 [GOYA_STM_TPC3_EML] = mmTPC3_EML_STM_BASE,
37 [GOYA_STM_TPC4_EML] = mmTPC4_EML_STM_BASE,
38 [GOYA_STM_TPC5_EML] = mmTPC5_EML_STM_BASE,
39 [GOYA_STM_TPC6_EML] = mmTPC6_EML_STM_BASE,
40 [GOYA_STM_TPC7_EML] = mmTPC7_EML_STM_BASE
41};
42
43static u64 debug_etf_regs[GOYA_ETF_LAST + 1] = {
44 [GOYA_ETF_CPU_0] = mmCPU_ETF_0_BASE,
45 [GOYA_ETF_CPU_1] = mmCPU_ETF_1_BASE,
46 [GOYA_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE,
47 [GOYA_ETF_DMA_CH_0_CS] = mmDMA_CH_0_CS_ETF_BASE,
48 [GOYA_ETF_DMA_CH_1_CS] = mmDMA_CH_1_CS_ETF_BASE,
49 [GOYA_ETF_DMA_CH_2_CS] = mmDMA_CH_2_CS_ETF_BASE,
50 [GOYA_ETF_DMA_CH_3_CS] = mmDMA_CH_3_CS_ETF_BASE,
51 [GOYA_ETF_DMA_CH_4_CS] = mmDMA_CH_4_CS_ETF_BASE,
52 [GOYA_ETF_DMA_MACRO_CS] = mmDMA_MACRO_CS_ETF_BASE,
53 [GOYA_ETF_MME1_SBA] = mmMME1_SBA_ETF_BASE,
54 [GOYA_ETF_MME3_SBB] = mmMME3_SBB_ETF_BASE,
55 [GOYA_ETF_MME4_WACS2] = mmMME4_WACS2_ETF_BASE,
56 [GOYA_ETF_MME4_WACS] = mmMME4_WACS_ETF_BASE,
57 [GOYA_ETF_MMU_CS] = mmMMU_CS_ETF_BASE,
58 [GOYA_ETF_PCIE] = mmPCIE_ETF_BASE,
59 [GOYA_ETF_PSOC] = mmPSOC_ETF_BASE,
60 [GOYA_ETF_TPC0_EML] = mmTPC0_EML_ETF_BASE,
61 [GOYA_ETF_TPC1_EML] = mmTPC1_EML_ETF_BASE,
62 [GOYA_ETF_TPC2_EML] = mmTPC2_EML_ETF_BASE,
63 [GOYA_ETF_TPC3_EML] = mmTPC3_EML_ETF_BASE,
64 [GOYA_ETF_TPC4_EML] = mmTPC4_EML_ETF_BASE,
65 [GOYA_ETF_TPC5_EML] = mmTPC5_EML_ETF_BASE,
66 [GOYA_ETF_TPC6_EML] = mmTPC6_EML_ETF_BASE,
67 [GOYA_ETF_TPC7_EML] = mmTPC7_EML_ETF_BASE
68};
69
70static u64 debug_funnel_regs[GOYA_FUNNEL_LAST + 1] = {
71 [GOYA_FUNNEL_CPU] = mmCPU_FUNNEL_BASE,
72 [GOYA_FUNNEL_DMA_CH_6_1] = mmDMA_CH_FUNNEL_6_1_BASE,
73 [GOYA_FUNNEL_DMA_MACRO_3_1] = mmDMA_MACRO_FUNNEL_3_1_BASE,
74 [GOYA_FUNNEL_MME0_RTR] = mmMME0_RTR_FUNNEL_BASE,
75 [GOYA_FUNNEL_MME1_RTR] = mmMME1_RTR_FUNNEL_BASE,
76 [GOYA_FUNNEL_MME2_RTR] = mmMME2_RTR_FUNNEL_BASE,
77 [GOYA_FUNNEL_MME3_RTR] = mmMME3_RTR_FUNNEL_BASE,
78 [GOYA_FUNNEL_MME4_RTR] = mmMME4_RTR_FUNNEL_BASE,
79 [GOYA_FUNNEL_MME5_RTR] = mmMME5_RTR_FUNNEL_BASE,
80 [GOYA_FUNNEL_PCIE] = mmPCIE_FUNNEL_BASE,
81 [GOYA_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE,
82 [GOYA_FUNNEL_TPC0_EML] = mmTPC0_EML_FUNNEL_BASE,
83 [GOYA_FUNNEL_TPC1_EML] = mmTPC1_EML_FUNNEL_BASE,
84 [GOYA_FUNNEL_TPC1_RTR] = mmTPC1_RTR_FUNNEL_BASE,
85 [GOYA_FUNNEL_TPC2_EML] = mmTPC2_EML_FUNNEL_BASE,
86 [GOYA_FUNNEL_TPC2_RTR] = mmTPC2_RTR_FUNNEL_BASE,
87 [GOYA_FUNNEL_TPC3_EML] = mmTPC3_EML_FUNNEL_BASE,
88 [GOYA_FUNNEL_TPC3_RTR] = mmTPC3_RTR_FUNNEL_BASE,
89 [GOYA_FUNNEL_TPC4_EML] = mmTPC4_EML_FUNNEL_BASE,
90 [GOYA_FUNNEL_TPC4_RTR] = mmTPC4_RTR_FUNNEL_BASE,
91 [GOYA_FUNNEL_TPC5_EML] = mmTPC5_EML_FUNNEL_BASE,
92 [GOYA_FUNNEL_TPC5_RTR] = mmTPC5_RTR_FUNNEL_BASE,
93 [GOYA_FUNNEL_TPC6_EML] = mmTPC6_EML_FUNNEL_BASE,
94 [GOYA_FUNNEL_TPC6_RTR] = mmTPC6_RTR_FUNNEL_BASE,
95 [GOYA_FUNNEL_TPC7_EML] = mmTPC7_EML_FUNNEL_BASE
96};
97
98static u64 debug_bmon_regs[GOYA_BMON_LAST + 1] = {
99 [GOYA_BMON_CPU_RD] = mmCPU_RD_BMON_BASE,
100 [GOYA_BMON_CPU_WR] = mmCPU_WR_BMON_BASE,
101 [GOYA_BMON_DMA_CH_0_0] = mmDMA_CH_0_BMON_0_BASE,
102 [GOYA_BMON_DMA_CH_0_1] = mmDMA_CH_0_BMON_1_BASE,
103 [GOYA_BMON_DMA_CH_1_0] = mmDMA_CH_1_BMON_0_BASE,
104 [GOYA_BMON_DMA_CH_1_1] = mmDMA_CH_1_BMON_1_BASE,
105 [GOYA_BMON_DMA_CH_2_0] = mmDMA_CH_2_BMON_0_BASE,
106 [GOYA_BMON_DMA_CH_2_1] = mmDMA_CH_2_BMON_1_BASE,
107 [GOYA_BMON_DMA_CH_3_0] = mmDMA_CH_3_BMON_0_BASE,
108 [GOYA_BMON_DMA_CH_3_1] = mmDMA_CH_3_BMON_1_BASE,
109 [GOYA_BMON_DMA_CH_4_0] = mmDMA_CH_4_BMON_0_BASE,
110 [GOYA_BMON_DMA_CH_4_1] = mmDMA_CH_4_BMON_1_BASE,
111 [GOYA_BMON_DMA_MACRO_0] = mmDMA_MACRO_BMON_0_BASE,
112 [GOYA_BMON_DMA_MACRO_1] = mmDMA_MACRO_BMON_1_BASE,
113 [GOYA_BMON_DMA_MACRO_2] = mmDMA_MACRO_BMON_2_BASE,
114 [GOYA_BMON_DMA_MACRO_3] = mmDMA_MACRO_BMON_3_BASE,
115 [GOYA_BMON_DMA_MACRO_4] = mmDMA_MACRO_BMON_4_BASE,
116 [GOYA_BMON_DMA_MACRO_5] = mmDMA_MACRO_BMON_5_BASE,
117 [GOYA_BMON_DMA_MACRO_6] = mmDMA_MACRO_BMON_6_BASE,
118 [GOYA_BMON_DMA_MACRO_7] = mmDMA_MACRO_BMON_7_BASE,
119 [GOYA_BMON_MME1_SBA_0] = mmMME1_SBA_BMON0_BASE,
120 [GOYA_BMON_MME1_SBA_1] = mmMME1_SBA_BMON1_BASE,
121 [GOYA_BMON_MME3_SBB_0] = mmMME3_SBB_BMON0_BASE,
122 [GOYA_BMON_MME3_SBB_1] = mmMME3_SBB_BMON1_BASE,
123 [GOYA_BMON_MME4_WACS2_0] = mmMME4_WACS2_BMON0_BASE,
124 [GOYA_BMON_MME4_WACS2_1] = mmMME4_WACS2_BMON1_BASE,
125 [GOYA_BMON_MME4_WACS2_2] = mmMME4_WACS2_BMON2_BASE,
126 [GOYA_BMON_MME4_WACS_0] = mmMME4_WACS_BMON0_BASE,
127 [GOYA_BMON_MME4_WACS_1] = mmMME4_WACS_BMON1_BASE,
128 [GOYA_BMON_MME4_WACS_2] = mmMME4_WACS_BMON2_BASE,
129 [GOYA_BMON_MME4_WACS_3] = mmMME4_WACS_BMON3_BASE,
130 [GOYA_BMON_MME4_WACS_4] = mmMME4_WACS_BMON4_BASE,
131 [GOYA_BMON_MME4_WACS_5] = mmMME4_WACS_BMON5_BASE,
132 [GOYA_BMON_MME4_WACS_6] = mmMME4_WACS_BMON6_BASE,
133 [GOYA_BMON_MMU_0] = mmMMU_BMON_0_BASE,
134 [GOYA_BMON_MMU_1] = mmMMU_BMON_1_BASE,
135 [GOYA_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE,
136 [GOYA_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE,
137 [GOYA_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE,
138 [GOYA_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE,
139 [GOYA_BMON_TPC0_EML_0] = mmTPC0_EML_BUSMON_0_BASE,
140 [GOYA_BMON_TPC0_EML_1] = mmTPC0_EML_BUSMON_1_BASE,
141 [GOYA_BMON_TPC0_EML_2] = mmTPC0_EML_BUSMON_2_BASE,
142 [GOYA_BMON_TPC0_EML_3] = mmTPC0_EML_BUSMON_3_BASE,
143 [GOYA_BMON_TPC1_EML_0] = mmTPC1_EML_BUSMON_0_BASE,
144 [GOYA_BMON_TPC1_EML_1] = mmTPC1_EML_BUSMON_1_BASE,
145 [GOYA_BMON_TPC1_EML_2] = mmTPC1_EML_BUSMON_2_BASE,
146 [GOYA_BMON_TPC1_EML_3] = mmTPC1_EML_BUSMON_3_BASE,
147 [GOYA_BMON_TPC2_EML_0] = mmTPC2_EML_BUSMON_0_BASE,
148 [GOYA_BMON_TPC2_EML_1] = mmTPC2_EML_BUSMON_1_BASE,
149 [GOYA_BMON_TPC2_EML_2] = mmTPC2_EML_BUSMON_2_BASE,
150 [GOYA_BMON_TPC2_EML_3] = mmTPC2_EML_BUSMON_3_BASE,
151 [GOYA_BMON_TPC3_EML_0] = mmTPC3_EML_BUSMON_0_BASE,
152 [GOYA_BMON_TPC3_EML_1] = mmTPC3_EML_BUSMON_1_BASE,
153 [GOYA_BMON_TPC3_EML_2] = mmTPC3_EML_BUSMON_2_BASE,
154 [GOYA_BMON_TPC3_EML_3] = mmTPC3_EML_BUSMON_3_BASE,
155 [GOYA_BMON_TPC4_EML_0] = mmTPC4_EML_BUSMON_0_BASE,
156 [GOYA_BMON_TPC4_EML_1] = mmTPC4_EML_BUSMON_1_BASE,
157 [GOYA_BMON_TPC4_EML_2] = mmTPC4_EML_BUSMON_2_BASE,
158 [GOYA_BMON_TPC4_EML_3] = mmTPC4_EML_BUSMON_3_BASE,
159 [GOYA_BMON_TPC5_EML_0] = mmTPC5_EML_BUSMON_0_BASE,
160 [GOYA_BMON_TPC5_EML_1] = mmTPC5_EML_BUSMON_1_BASE,
161 [GOYA_BMON_TPC5_EML_2] = mmTPC5_EML_BUSMON_2_BASE,
162 [GOYA_BMON_TPC5_EML_3] = mmTPC5_EML_BUSMON_3_BASE,
163 [GOYA_BMON_TPC6_EML_0] = mmTPC6_EML_BUSMON_0_BASE,
164 [GOYA_BMON_TPC6_EML_1] = mmTPC6_EML_BUSMON_1_BASE,
165 [GOYA_BMON_TPC6_EML_2] = mmTPC6_EML_BUSMON_2_BASE,
166 [GOYA_BMON_TPC6_EML_3] = mmTPC6_EML_BUSMON_3_BASE,
167 [GOYA_BMON_TPC7_EML_0] = mmTPC7_EML_BUSMON_0_BASE,
168 [GOYA_BMON_TPC7_EML_1] = mmTPC7_EML_BUSMON_1_BASE,
169 [GOYA_BMON_TPC7_EML_2] = mmTPC7_EML_BUSMON_2_BASE,
170 [GOYA_BMON_TPC7_EML_3] = mmTPC7_EML_BUSMON_3_BASE
171};
172
173static u64 debug_spmu_regs[GOYA_SPMU_LAST + 1] = {
174 [GOYA_SPMU_DMA_CH_0_CS] = mmDMA_CH_0_CS_SPMU_BASE,
175 [GOYA_SPMU_DMA_CH_1_CS] = mmDMA_CH_1_CS_SPMU_BASE,
176 [GOYA_SPMU_DMA_CH_2_CS] = mmDMA_CH_2_CS_SPMU_BASE,
177 [GOYA_SPMU_DMA_CH_3_CS] = mmDMA_CH_3_CS_SPMU_BASE,
178 [GOYA_SPMU_DMA_CH_4_CS] = mmDMA_CH_4_CS_SPMU_BASE,
179 [GOYA_SPMU_DMA_MACRO_CS] = mmDMA_MACRO_CS_SPMU_BASE,
180 [GOYA_SPMU_MME1_SBA] = mmMME1_SBA_SPMU_BASE,
181 [GOYA_SPMU_MME3_SBB] = mmMME3_SBB_SPMU_BASE,
182 [GOYA_SPMU_MME4_WACS2] = mmMME4_WACS2_SPMU_BASE,
183 [GOYA_SPMU_MME4_WACS] = mmMME4_WACS_SPMU_BASE,
184 [GOYA_SPMU_MMU_CS] = mmMMU_CS_SPMU_BASE,
185 [GOYA_SPMU_PCIE] = mmPCIE_SPMU_BASE,
186 [GOYA_SPMU_TPC0_EML] = mmTPC0_EML_SPMU_BASE,
187 [GOYA_SPMU_TPC1_EML] = mmTPC1_EML_SPMU_BASE,
188 [GOYA_SPMU_TPC2_EML] = mmTPC2_EML_SPMU_BASE,
189 [GOYA_SPMU_TPC3_EML] = mmTPC3_EML_SPMU_BASE,
190 [GOYA_SPMU_TPC4_EML] = mmTPC4_EML_SPMU_BASE,
191 [GOYA_SPMU_TPC5_EML] = mmTPC5_EML_SPMU_BASE,
192 [GOYA_SPMU_TPC6_EML] = mmTPC6_EML_SPMU_BASE,
193 [GOYA_SPMU_TPC7_EML] = mmTPC7_EML_SPMU_BASE
194};
195
196static int goya_coresight_timeout(struct hl_device *hdev, u64 addr,
197 int position, bool up)
198{
199 int rc;
200 u32 val, timeout_usec;
201
202 if (hdev->pldm)
203 timeout_usec = GOYA_PLDM_CORESIGHT_TIMEOUT_USEC;
204 else
205 timeout_usec = CORESIGHT_TIMEOUT_USEC;
206
207 rc = hl_poll_timeout(
208 hdev,
209 addr,
210 val,
211 up ? val & BIT(position) : !(val & BIT(position)),
212 1000,
213 timeout_usec);
214
215 if (rc) {
216 dev_err(hdev->dev,
217 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n",
218 addr, position, up);
219 return -EFAULT;
220 }
221
222 return 0;
223}
224
225static int goya_config_stm(struct hl_device *hdev,
226 struct hl_debug_params *params)
227{
228 struct hl_debug_params_stm *input;
229 u64 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
230 int rc;
231
232 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
233
234 if (params->enable) {
235 input = params->input;
236
237 if (!input)
238 return -EINVAL;
239
240 WREG32(base_reg + 0xE80, 0x80004);
241 WREG32(base_reg + 0xD64, 7);
242 WREG32(base_reg + 0xD60, 0);
243 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
244 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask));
245 WREG32(base_reg + 0xD60, 1);
246 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
247 WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask));
248 WREG32(base_reg + 0xE70, 0x10);
249 WREG32(base_reg + 0xE60, 0);
250 WREG32(base_reg + 0xE64, 0x420000);
251 WREG32(base_reg + 0xE00, 0xFFFFFFFF);
252 WREG32(base_reg + 0xE20, 0xFFFFFFFF);
253 WREG32(base_reg + 0xEF4, input->id);
254 WREG32(base_reg + 0xDF4, 0x80);
255 WREG32(base_reg + 0xE8C, input->frequency);
256 WREG32(base_reg + 0xE90, 0x7FF);
257 WREG32(base_reg + 0xE80, 0x7 | (input->id << 16));
258 } else {
259 WREG32(base_reg + 0xE80, 4);
260 WREG32(base_reg + 0xD64, 0);
261 WREG32(base_reg + 0xD60, 1);
262 WREG32(base_reg + 0xD00, 0);
263 WREG32(base_reg + 0xD20, 0);
264 WREG32(base_reg + 0xD60, 0);
265 WREG32(base_reg + 0xE20, 0);
266 WREG32(base_reg + 0xE00, 0);
267 WREG32(base_reg + 0xDF4, 0x80);
268 WREG32(base_reg + 0xE70, 0);
269 WREG32(base_reg + 0xE60, 0);
270 WREG32(base_reg + 0xE64, 0);
271 WREG32(base_reg + 0xE8C, 0);
272
273 rc = goya_coresight_timeout(hdev, base_reg + 0xE80, 23, false);
274 if (rc) {
275 dev_err(hdev->dev,
276 "Failed to disable STM on timeout, error %d\n",
277 rc);
278 return rc;
279 }
280
281 WREG32(base_reg + 0xE80, 4);
282 }
283
284 return 0;
285}
286
287static int goya_config_etf(struct hl_device *hdev,
288 struct hl_debug_params *params)
289{
290 struct hl_debug_params_etf *input;
291 u64 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE;
292 u32 val;
293 int rc;
294
295 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
296
297 val = RREG32(base_reg + 0x304);
298 val |= 0x1000;
299 WREG32(base_reg + 0x304, val);
300 val |= 0x40;
301 WREG32(base_reg + 0x304, val);
302
303 rc = goya_coresight_timeout(hdev, base_reg + 0x304, 6, false);
304 if (rc) {
305 dev_err(hdev->dev,
306 "Failed to %s ETF on timeout, error %d\n",
307 params->enable ? "enable" : "disable", rc);
308 return rc;
309 }
310
311 rc = goya_coresight_timeout(hdev, base_reg + 0xC, 2, true);
312 if (rc) {
313 dev_err(hdev->dev,
314 "Failed to %s ETF on timeout, error %d\n",
315 params->enable ? "enable" : "disable", rc);
316 return rc;
317 }
318
319 WREG32(base_reg + 0x20, 0);
320
321 if (params->enable) {
322 input = params->input;
323
324 if (!input)
325 return -EINVAL;
326
327 WREG32(base_reg + 0x34, 0x3FFC);
328 WREG32(base_reg + 0x28, input->sink_mode);
329 WREG32(base_reg + 0x304, 0x4001);
330 WREG32(base_reg + 0x308, 0xA);
331 WREG32(base_reg + 0x20, 1);
332 } else {
333 WREG32(base_reg + 0x34, 0);
334 WREG32(base_reg + 0x28, 0);
335 WREG32(base_reg + 0x304, 0);
336 }
337
338 return 0;
339}
340
341static int goya_etr_validate_address(struct hl_device *hdev, u64 addr,
342 u32 size)
343{
344 struct asic_fixed_properties *prop = &hdev->asic_prop;
345 u64 range_start, range_end;
346
347 if (hdev->mmu_enable) {
348 range_start = prop->va_space_dram_start_address;
349 range_end = prop->va_space_dram_end_address;
350 } else {
351 range_start = prop->dram_user_base_address;
352 range_end = prop->dram_end_address;
353 }
354
355 return hl_mem_area_inside_range(addr, size, range_start, range_end);
356}
357
358static int goya_config_etr(struct hl_device *hdev,
359 struct hl_debug_params *params)
360{
361 struct hl_debug_params_etr *input;
362 u64 base_reg = mmPSOC_ETR_BASE - CFG_BASE;
363 u32 val;
364 int rc;
365
366 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
367
368 val = RREG32(base_reg + 0x304);
369 val |= 0x1000;
370 WREG32(base_reg + 0x304, val);
371 val |= 0x40;
372 WREG32(base_reg + 0x304, val);
373
374 rc = goya_coresight_timeout(hdev, base_reg + 0x304, 6, false);
375 if (rc) {
376 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
377 params->enable ? "enable" : "disable", rc);
378 return rc;
379 }
380
381 rc = goya_coresight_timeout(hdev, base_reg + 0xC, 2, true);
382 if (rc) {
383 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
384 params->enable ? "enable" : "disable", rc);
385 return rc;
386 }
387
388 WREG32(base_reg + 0x20, 0);
389
390 if (params->enable) {
391 input = params->input;
392
393 if (!input)
394 return -EINVAL;
395
396 if (input->buffer_size == 0) {
397 dev_err(hdev->dev,
398 "ETR buffer size should be bigger than 0\n");
399 return -EINVAL;
400 }
401
402 if (!goya_etr_validate_address(hdev,
403 input->buffer_address, input->buffer_size)) {
404 dev_err(hdev->dev, "buffer address is not valid\n");
405 return -EINVAL;
406 }
407
408 WREG32(base_reg + 0x34, 0x3FFC);
409 WREG32(base_reg + 0x4, input->buffer_size);
410 WREG32(base_reg + 0x28, input->sink_mode);
411 WREG32(base_reg + 0x110, 0x700);
412 WREG32(base_reg + 0x118,
413 lower_32_bits(input->buffer_address));
414 WREG32(base_reg + 0x11C,
415 upper_32_bits(input->buffer_address));
416 WREG32(base_reg + 0x304, 3);
417 WREG32(base_reg + 0x308, 0xA);
418 WREG32(base_reg + 0x20, 1);
419 } else {
420 WREG32(base_reg + 0x34, 0);
421 WREG32(base_reg + 0x4, 0x400);
422 WREG32(base_reg + 0x118, 0);
423 WREG32(base_reg + 0x11C, 0);
424 WREG32(base_reg + 0x308, 0);
425 WREG32(base_reg + 0x28, 0);
426 WREG32(base_reg + 0x304, 0);
427
1f65105f
TT		 428 if (params->output_size >= sizeof(u64)) {
429 u32 rwp, rwphi;
430
431 /*
432 * The trace buffer address is 40 bits wide. The end of
433 * the buffer is set in the RWP register (lower 32
434 * bits), and in the RWPHI register (upper 8 bits).
435 */
436 rwp = RREG32(base_reg + 0x18);
437 rwphi = RREG32(base_reg + 0x3c) & 0xff;
438 *(u64 *) params->output = ((u64) rwphi << 32) | rwp;
439 }
8ba2876d
OS		 440 }
441
442 return 0;
443}
444
445static int goya_config_funnel(struct hl_device *hdev,
446 struct hl_debug_params *params)
447{
448 WREG32(debug_funnel_regs[params->reg_idx] - CFG_BASE + 0xFB0,
449 CORESIGHT_UNLOCK);
450
451 WREG32(debug_funnel_regs[params->reg_idx] - CFG_BASE,
452 params->enable ? 0x33F : 0);
453
454 return 0;
455}
456
457static int goya_config_bmon(struct hl_device *hdev,
458 struct hl_debug_params *params)
459{
460 struct hl_debug_params_bmon *input;
461 u64 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE;
462 u32 pcie_base = 0;
463
464 WREG32(base_reg + 0x104, 1);
465
466 if (params->enable) {
467 input = params->input;
468
469 if (!input)
470 return -EINVAL;
471
d691171d
OG		 472 WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0));
473 WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0));
474 WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0));
475 WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0));
476 WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1));
477 WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1));
478 WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1));
479 WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1));
8ba2876d
OS		 480 WREG32(base_reg + 0x224, 0);
481 WREG32(base_reg + 0x234, 0);
482 WREG32(base_reg + 0x30C, input->bw_win);
483 WREG32(base_reg + 0x308, input->win_capture);
484
485 /* PCIE IF BMON bug WA */
486 if (params->reg_idx != GOYA_BMON_PCIE_MSTR_RD &&
487 params->reg_idx != GOYA_BMON_PCIE_MSTR_WR &&
488 params->reg_idx != GOYA_BMON_PCIE_SLV_RD &&
489 params->reg_idx != GOYA_BMON_PCIE_SLV_WR)
490 pcie_base = 0xA000000;
491
492 WREG32(base_reg + 0x700, pcie_base | 0xB00 | (input->id << 12));
493 WREG32(base_reg + 0x708, pcie_base | 0xA00 | (input->id << 12));
494 WREG32(base_reg + 0x70C, pcie_base | 0xC00 | (input->id << 12));
495
496 WREG32(base_reg + 0x100, 0x11);
497 WREG32(base_reg + 0x304, 0x1);
498 } else {
d691171d
OG		 499 WREG32(base_reg + 0x200, 0);
500 WREG32(base_reg + 0x204, 0);
8ba2876d
OS		 501 WREG32(base_reg + 0x208, 0xFFFFFFFF);
502 WREG32(base_reg + 0x20C, 0xFFFFFFFF);
d691171d
OG		 503 WREG32(base_reg + 0x240, 0);
504 WREG32(base_reg + 0x244, 0);
8ba2876d
OS		 505 WREG32(base_reg + 0x248, 0xFFFFFFFF);
506 WREG32(base_reg + 0x24C, 0xFFFFFFFF);
507 WREG32(base_reg + 0x224, 0xFFFFFFFF);
508 WREG32(base_reg + 0x234, 0x1070F);
509 WREG32(base_reg + 0x30C, 0);
510 WREG32(base_reg + 0x308, 0xFFFF);
511 WREG32(base_reg + 0x700, 0xA000B00);
512 WREG32(base_reg + 0x708, 0xA000A00);
513 WREG32(base_reg + 0x70C, 0xA000C00);
514 WREG32(base_reg + 0x100, 1);
515 WREG32(base_reg + 0x304, 0);
516 WREG32(base_reg + 0x104, 0);
517 }
518
519 return 0;
520}
521
522static int goya_config_spmu(struct hl_device *hdev,
523 struct hl_debug_params *params)
524{
525 u64 base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE;
526 struct hl_debug_params_spmu *input = params->input;
527 u64 *output;
528 u32 output_arr_len;
529 u32 events_num;
530 u32 overflow_idx;
531 u32 cycle_cnt_idx;
532 int i;
533
534 if (params->enable) {
535 input = params->input;
536
537 if (!input)
538 return -EINVAL;
539
540 if (input->event_types_num < 3) {
541 dev_err(hdev->dev,
542 "not enough values for SPMU enable\n");
543 return -EINVAL;
544 }
545
546 WREG32(base_reg + 0xE04, 0x41013046);
547 WREG32(base_reg + 0xE04, 0x41013040);
548
549 for (i = 0 ; i < input->event_types_num ; i++)
550 WREG32(base_reg + 0x400 + i * 4, input->event_types[i]);
551
552 WREG32(base_reg + 0xE04, 0x41013041);
553 WREG32(base_reg + 0xC00, 0x8000003F);
554 } else {
555 output = params->output;
556 output_arr_len = params->output_size / 8;
557 events_num = output_arr_len - 2;
558 overflow_idx = output_arr_len - 2;
559 cycle_cnt_idx = output_arr_len - 1;
560
561 if (!output)
562 return -EINVAL;
563
564 if (output_arr_len < 3) {
565 dev_err(hdev->dev,
566 "not enough values for SPMU disable\n");
567 return -EINVAL;
568 }
569
570 WREG32(base_reg + 0xE04, 0x41013040);
571
572 for (i = 0 ; i < events_num ; i++)
573 output[i] = RREG32(base_reg + i * 8);
574
575 output[overflow_idx] = RREG32(base_reg + 0xCC0);
576
577 output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);
578 output[cycle_cnt_idx] <<= 32;
579 output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);
580
581 WREG32(base_reg + 0xCC0, 0);
582 }
583
584 return 0;
585}
586
587static int goya_config_timestamp(struct hl_device *hdev,
588 struct hl_debug_params *params)
589{
590 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
591 if (params->enable) {
592 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
593 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
594 WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
595 }
596
597 return 0;
598}
315bc055
OS		 599
600int goya_debug_coresight(struct hl_device *hdev, void *data)
601{
8ba2876d
OS		 602 struct hl_debug_params *params = data;
603 u32 val;
604 int rc;
605
606 switch (params->op) {
607 case HL_DEBUG_OP_STM:
608 rc = goya_config_stm(hdev, params);
609 break;
610 case HL_DEBUG_OP_ETF:
611 rc = goya_config_etf(hdev, params);
612 break;
613 case HL_DEBUG_OP_ETR:
614 rc = goya_config_etr(hdev, params);
615 break;
616 case HL_DEBUG_OP_FUNNEL:
617 rc = goya_config_funnel(hdev, params);
618 break;
619 case HL_DEBUG_OP_BMON:
620 rc = goya_config_bmon(hdev, params);
621 break;
622 case HL_DEBUG_OP_SPMU:
623 rc = goya_config_spmu(hdev, params);
624 break;
625 case HL_DEBUG_OP_TIMESTAMP:
626 rc = goya_config_timestamp(hdev, params);
627 break;
628
629 default:
630 dev_err(hdev->dev, "Unknown coresight id %d\n", params->op);
631 return -EINVAL;
632 }
633
634 /* Perform read from the device to flush all configuration */
635 val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
636
637 return rc;
315bc055 638}
89225ce4
OS		 639
640void goya_halt_coresight(struct hl_device *hdev)
641{
642 struct hl_debug_params params = {};
643 int i, rc;
644
645 for (i = GOYA_ETF_FIRST ; i <= GOYA_ETF_LAST ; i++) {
646 params.reg_idx = i;
647 rc = goya_config_etf(hdev, &params);
648 if (rc)
649 dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i);
650 }
651
652 rc = goya_config_etr(hdev, &params);
653 if (rc)
654 dev_err(hdev->dev, "halt ETR failed, %d\n", rc);
655}
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