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9fff0425 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
9dc64d6a | 2 | /* |
907b471c | 3 | * Copyright (c) 2012-2019, Intel Corporation. All rights reserved. |
9dc64d6a | 4 | * Intel Management Engine Interface (Intel MEI) Linux driver |
66ef5ea9 | 5 | */ |
66ef5ea9 | 6 | |
9dc64d6a TW |
7 | #ifndef _MEI_INTERFACE_H_ |
8 | #define _MEI_INTERFACE_H_ | |
66ef5ea9 | 9 | |
81ec5502 | 10 | #include <linux/irqreturn.h> |
4ad96db6 TW |
11 | #include <linux/pci.h> |
12 | #include <linux/mei.h> | |
13 | ||
9dc64d6a | 14 | #include "mei_dev.h" |
52c34561 | 15 | #include "client.h" |
66ef5ea9 | 16 | |
4ad96db6 TW |
17 | /* |
18 | * mei_cfg - mei device configuration | |
19 | * | |
20 | * @fw_status: FW status | |
21 | * @quirk_probe: device exclusion quirk | |
7026a5fd | 22 | * @dma_size: device DMA buffers size |
f8204f0d | 23 | * @fw_ver_supported: is fw version retrievable from FW |
52f6efdf | 24 | * @hw_trc_supported: does the hw support trc register |
4ad96db6 TW |
25 | */ |
26 | struct mei_cfg { | |
27 | const struct mei_fw_status fw_status; | |
28 | bool (*quirk_probe)(struct pci_dev *pdev); | |
7026a5fd | 29 | size_t dma_size[DMA_DSCR_NUM]; |
f8204f0d | 30 | u32 fw_ver_supported:1; |
52f6efdf | 31 | u32 hw_trc_supported:1; |
4ad96db6 TW |
32 | }; |
33 | ||
34 | ||
35 | #define MEI_PCI_DEVICE(dev, cfg) \ | |
36 | .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \ | |
37 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ | |
f5ac3c49 | 38 | .driver_data = (kernel_ulong_t)(cfg), |
4ad96db6 | 39 | |
180ea05b TW |
40 | #define MEI_ME_RPM_TIMEOUT 500 /* ms */ |
41 | ||
4ad96db6 | 42 | /** |
ce23139c AU |
43 | * struct mei_me_hw - me hw specific data |
44 | * | |
4ad96db6 | 45 | * @cfg: per device generation config and ops |
bb9f4d26 | 46 | * @mem_addr: io memory address |
261b3e1f | 47 | * @irq: irq number |
bb9f4d26 AU |
48 | * @pg_state: power gating state |
49 | * @d0i3_supported: di03 support | |
8c8d964c | 50 | * @hbuf_depth: depth of hardware host/write buffer in slots |
261e071a | 51 | * @read_fws: read FW status register handler |
4ad96db6 | 52 | */ |
52c34561 | 53 | struct mei_me_hw { |
4ad96db6 | 54 | const struct mei_cfg *cfg; |
52c34561 | 55 | void __iomem *mem_addr; |
261b3e1f | 56 | int irq; |
ba9cdd0e | 57 | enum mei_pg_state pg_state; |
bb9f4d26 | 58 | bool d0i3_supported; |
8c8d964c | 59 | u8 hbuf_depth; |
261e071a | 60 | int (*read_fws)(const struct mei_device *dev, int where, u32 *val); |
52c34561 | 61 | }; |
66ef5ea9 | 62 | |
52c34561 TW |
63 | #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw) |
64 | ||
f5ac3c49 TW |
65 | /** |
66 | * enum mei_cfg_idx - indices to platform specific configurations. | |
67 | * | |
68 | * Note: has to be synchronized with mei_cfg_list[] | |
69 | * | |
70 | * @MEI_ME_UNDEF_CFG: Lower sentinel. | |
71 | * @MEI_ME_ICH_CFG: I/O Controller Hub legacy devices. | |
72 | * @MEI_ME_ICH10_CFG: I/O Controller Hub platforms Gen10 | |
f8204f0d AU |
73 | * @MEI_ME_PCH6_CFG: Platform Controller Hub platforms (Gen6). |
74 | * @MEI_ME_PCH7_CFG: Platform Controller Hub platforms (Gen7). | |
f5ac3c49 TW |
75 | * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations |
76 | * with quirk for Node Manager exclusion. | |
77 | * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer | |
78 | * client platforms. | |
79 | * @MEI_ME_PCH8_SPS_CFG: Platform Controller Hub Gen8 and newer | |
80 | * servers platforms with quirk for | |
81 | * SPS firmware exclusion. | |
7026a5fd | 82 | * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer |
d76bc820 TW |
83 | * @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 and newer |
84 | * servers platforms with quirk for | |
85 | * SPS firmware exclusion. | |
52f6efdf | 86 | * @MEI_ME_PCH15_CFG: Platform Controller Hub Gen15 and newer |
f5ac3c49 TW |
87 | * @MEI_ME_NUM_CFG: Upper Sentinel. |
88 | */ | |
89 | enum mei_cfg_idx { | |
90 | MEI_ME_UNDEF_CFG, | |
91 | MEI_ME_ICH_CFG, | |
92 | MEI_ME_ICH10_CFG, | |
f8204f0d AU |
93 | MEI_ME_PCH6_CFG, |
94 | MEI_ME_PCH7_CFG, | |
f5ac3c49 TW |
95 | MEI_ME_PCH_CPT_PBG_CFG, |
96 | MEI_ME_PCH8_CFG, | |
97 | MEI_ME_PCH8_SPS_CFG, | |
7026a5fd | 98 | MEI_ME_PCH12_CFG, |
d76bc820 | 99 | MEI_ME_PCH12_SPS_CFG, |
52f6efdf | 100 | MEI_ME_PCH15_CFG, |
f5ac3c49 TW |
101 | MEI_ME_NUM_CFG, |
102 | }; | |
103 | ||
104 | const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx); | |
8d929d48 | 105 | |
907b471c | 106 | struct mei_device *mei_me_dev_init(struct device *parent, |
8d929d48 | 107 | const struct mei_cfg *cfg); |
66ef5ea9 | 108 | |
2d1995fc AU |
109 | int mei_me_pg_enter_sync(struct mei_device *dev); |
110 | int mei_me_pg_exit_sync(struct mei_device *dev); | |
ba9cdd0e | 111 | |
06ecd645 TW |
112 | irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id); |
113 | irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id); | |
114 | ||
9dc64d6a | 115 | #endif /* _MEI_INTERFACE_H_ */ |