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1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | #ifndef __CPU_AT32AP_ATMEL_MCI_H__ | |
23 | #define __CPU_AT32AP_ATMEL_MCI_H__ | |
24 | ||
25 | /* Atmel MultiMedia Card Interface (MCI) registers */ | |
26 | #define MMCI_CR 0x0000 | |
27 | #define MMCI_MR 0x0004 | |
28 | #define MMCI_DTOR 0x0008 | |
29 | #define MMCI_SDCR 0x000c | |
30 | #define MMCI_ARGR 0x0010 | |
31 | #define MMCI_CMDR 0x0014 | |
32 | #define MMCI_RSPR 0x0020 | |
33 | #define MMCI_RSPR1 0x0024 | |
34 | #define MMCI_RSPR2 0x0028 | |
35 | #define MMCI_RSPR3 0x002c | |
36 | #define MMCI_RDR 0x0030 | |
37 | #define MMCI_TDR 0x0034 | |
38 | #define MMCI_SR 0x0040 | |
39 | #define MMCI_IER 0x0044 | |
40 | #define MMCI_IDR 0x0048 | |
41 | #define MMCI_IMR 0x004c | |
42 | ||
43 | /* Bitfields in CR */ | |
44 | #define MMCI_MCIEN_OFFSET 0 | |
45 | #define MMCI_MCIEN_SIZE 1 | |
46 | #define MMCI_MCIDIS_OFFSET 1 | |
47 | #define MMCI_MCIDIS_SIZE 1 | |
48 | #define MMCI_PWSEN_OFFSET 2 | |
49 | #define MMCI_PWSEN_SIZE 1 | |
50 | #define MMCI_PWSDIS_OFFSET 3 | |
51 | #define MMCI_PWSDIS_SIZE 1 | |
52 | #define MMCI_SWRST_OFFSET 7 | |
53 | #define MMCI_SWRST_SIZE 1 | |
54 | ||
55 | /* Bitfields in MR */ | |
56 | #define MMCI_CLKDIV_OFFSET 0 | |
57 | #define MMCI_CLKDIV_SIZE 8 | |
58 | #define MMCI_PWSDIV_OFFSET 8 | |
59 | #define MMCI_PWSDIV_SIZE 3 | |
f0d1246e HS |
60 | #define MMCI_RDPROOF_OFFSET 11 |
61 | #define MMCI_RDPROOF_SIZE 1 | |
62 | #define MMCI_WRPROOF_OFFSET 12 | |
63 | #define MMCI_WRPROOF_SIZE 1 | |
fc26c97b HS |
64 | #define MMCI_PDCPADV_OFFSET 14 |
65 | #define MMCI_PDCPADV_SIZE 1 | |
66 | #define MMCI_PDCMODE_OFFSET 15 | |
67 | #define MMCI_PDCMODE_SIZE 1 | |
68 | #define MMCI_BLKLEN_OFFSET 16 | |
69 | #define MMCI_BLKLEN_SIZE 16 | |
70 | ||
71 | /* Bitfields in DTOR */ | |
72 | #define MMCI_DTOCYC_OFFSET 0 | |
73 | #define MMCI_DTOCYC_SIZE 4 | |
74 | #define MMCI_DTOMUL_OFFSET 4 | |
75 | #define MMCI_DTOMUL_SIZE 3 | |
76 | ||
77 | /* Bitfields in SDCR */ | |
78 | #define MMCI_SCDSEL_OFFSET 0 | |
79 | #define MMCI_SCDSEL_SIZE 4 | |
80 | #define MMCI_SCDBUS_OFFSET 7 | |
81 | #define MMCI_SCDBUS_SIZE 1 | |
82 | ||
83 | /* Bitfields in ARGR */ | |
84 | #define MMCI_ARG_OFFSET 0 | |
85 | #define MMCI_ARG_SIZE 32 | |
86 | ||
87 | /* Bitfields in CMDR */ | |
88 | #define MMCI_CMDNB_OFFSET 0 | |
89 | #define MMCI_CMDNB_SIZE 6 | |
90 | #define MMCI_RSPTYP_OFFSET 6 | |
91 | #define MMCI_RSPTYP_SIZE 2 | |
92 | #define MMCI_SPCMD_OFFSET 8 | |
93 | #define MMCI_SPCMD_SIZE 3 | |
94 | #define MMCI_OPDCMD_OFFSET 11 | |
95 | #define MMCI_OPDCMD_SIZE 1 | |
96 | #define MMCI_MAXLAT_OFFSET 12 | |
97 | #define MMCI_MAXLAT_SIZE 1 | |
98 | #define MMCI_TRCMD_OFFSET 16 | |
99 | #define MMCI_TRCMD_SIZE 2 | |
100 | #define MMCI_TRDIR_OFFSET 18 | |
101 | #define MMCI_TRDIR_SIZE 1 | |
102 | #define MMCI_TRTYP_OFFSET 19 | |
103 | #define MMCI_TRTYP_SIZE 2 | |
104 | ||
105 | /* Bitfields in RSPRx */ | |
106 | #define MMCI_RSP_OFFSET 0 | |
107 | #define MMCI_RSP_SIZE 32 | |
108 | ||
109 | /* Bitfields in SR/IER/IDR/IMR */ | |
110 | #define MMCI_CMDRDY_OFFSET 0 | |
111 | #define MMCI_CMDRDY_SIZE 1 | |
112 | #define MMCI_RXRDY_OFFSET 1 | |
113 | #define MMCI_RXRDY_SIZE 1 | |
114 | #define MMCI_TXRDY_OFFSET 2 | |
115 | #define MMCI_TXRDY_SIZE 1 | |
116 | #define MMCI_BLKE_OFFSET 3 | |
117 | #define MMCI_BLKE_SIZE 1 | |
118 | #define MMCI_DTIP_OFFSET 4 | |
119 | #define MMCI_DTIP_SIZE 1 | |
120 | #define MMCI_NOTBUSY_OFFSET 5 | |
121 | #define MMCI_NOTBUSY_SIZE 1 | |
122 | #define MMCI_ENDRX_OFFSET 6 | |
123 | #define MMCI_ENDRX_SIZE 1 | |
124 | #define MMCI_ENDTX_OFFSET 7 | |
125 | #define MMCI_ENDTX_SIZE 1 | |
126 | #define MMCI_RXBUFF_OFFSET 14 | |
127 | #define MMCI_RXBUFF_SIZE 1 | |
128 | #define MMCI_TXBUFE_OFFSET 15 | |
129 | #define MMCI_TXBUFE_SIZE 1 | |
130 | #define MMCI_RINDE_OFFSET 16 | |
131 | #define MMCI_RINDE_SIZE 1 | |
132 | #define MMCI_RDIRE_OFFSET 17 | |
133 | #define MMCI_RDIRE_SIZE 1 | |
134 | #define MMCI_RCRCE_OFFSET 18 | |
135 | #define MMCI_RCRCE_SIZE 1 | |
136 | #define MMCI_RENDE_OFFSET 19 | |
137 | #define MMCI_RENDE_SIZE 1 | |
138 | #define MMCI_RTOE_OFFSET 20 | |
139 | #define MMCI_RTOE_SIZE 1 | |
140 | #define MMCI_DCRCE_OFFSET 21 | |
141 | #define MMCI_DCRCE_SIZE 1 | |
142 | #define MMCI_DTOE_OFFSET 22 | |
143 | #define MMCI_DTOE_SIZE 1 | |
144 | #define MMCI_OVRE_OFFSET 30 | |
145 | #define MMCI_OVRE_SIZE 1 | |
146 | #define MMCI_UNRE_OFFSET 31 | |
147 | #define MMCI_UNRE_SIZE 1 | |
148 | ||
149 | /* Constants for DTOMUL */ | |
150 | #define MMCI_DTOMUL_1_CYCLE 0 | |
151 | #define MMCI_DTOMUL_16_CYCLES 1 | |
152 | #define MMCI_DTOMUL_128_CYCLES 2 | |
153 | #define MMCI_DTOMUL_256_CYCLES 3 | |
154 | #define MMCI_DTOMUL_1024_CYCLES 4 | |
155 | #define MMCI_DTOMUL_4096_CYCLES 5 | |
156 | #define MMCI_DTOMUL_65536_CYCLES 6 | |
157 | #define MMCI_DTOMUL_1048576_CYCLES 7 | |
158 | ||
159 | /* Constants for RSPTYP */ | |
160 | #define MMCI_RSPTYP_NO_RESP 0 | |
161 | #define MMCI_RSPTYP_48_BIT_RESP 1 | |
162 | #define MMCI_RSPTYP_136_BIT_RESP 2 | |
163 | ||
164 | /* Constants for SPCMD */ | |
165 | #define MMCI_SPCMD_NO_SPEC_CMD 0 | |
166 | #define MMCI_SPCMD_INIT_CMD 1 | |
167 | #define MMCI_SPCMD_SYNC_CMD 2 | |
168 | #define MMCI_SPCMD_INT_CMD 4 | |
169 | #define MMCI_SPCMD_INT_RESP 5 | |
170 | ||
171 | /* Constants for TRCMD */ | |
172 | #define MMCI_TRCMD_NO_TRANS 0 | |
173 | #define MMCI_TRCMD_START_TRANS 1 | |
174 | #define MMCI_TRCMD_STOP_TRANS 2 | |
175 | ||
176 | /* Constants for TRTYP */ | |
177 | #define MMCI_TRTYP_BLOCK 0 | |
178 | #define MMCI_TRTYP_MULTI_BLOCK 1 | |
179 | #define MMCI_TRTYP_STREAM 2 | |
180 | ||
181 | /* Bit manipulation macros */ | |
182 | #define MMCI_BIT(name) \ | |
183 | (1 << MMCI_##name##_OFFSET) | |
184 | #define MMCI_BF(name,value) \ | |
185 | (((value) & ((1 << MMCI_##name##_SIZE) - 1)) \ | |
186 | << MMCI_##name##_OFFSET) | |
187 | #define MMCI_BFEXT(name,value) \ | |
188 | (((value) >> MMCI_##name##_OFFSET)\ | |
189 | & ((1 << MMCI_##name##_SIZE) - 1)) | |
190 | #define MMCI_BFINS(name,value,old) \ | |
191 | (((old) & ~(((1 << MMCI_##name##_SIZE) - 1) \ | |
192 | << MMCI_##name##_OFFSET)) \ | |
193 | | MMCI_BF(name,value)) | |
194 | ||
195 | /* Register access macros */ | |
196 | #define mmci_readl(reg) \ | |
197 | readl((void *)MMCI_BASE + MMCI_##reg) | |
198 | #define mmci_writel(reg,value) \ | |
199 | writel((value), (void *)MMCI_BASE + MMCI_##reg) | |
200 | ||
201 | #endif /* __CPU_AT32AP_ATMEL_MCI_H__ */ |