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c8a73a26 AG |
1 | /* |
2 | * bcm2835 sdhost driver. | |
3 | * | |
4 | * The 2835 has two SD controllers: The Arasan sdhci controller | |
5 | * (supported by the iproc driver) and a custom sdhost controller | |
6 | * (supported by this driver). | |
7 | * | |
8 | * The sdhci controller supports both sdcard and sdio. The sdhost | |
9 | * controller supports the sdcard only, but has better performance. | |
10 | * Also note that the rpi3 has sdio wifi, so driving the sdcard with | |
11 | * the sdhost controller allows to use the sdhci controller for wifi | |
12 | * support. | |
13 | * | |
14 | * The configuration is done by devicetree via pin muxing. Both | |
15 | * SD controller are available on the same pins (2 pin groups = pin 22 | |
16 | * to 27 + pin 48 to 53). So it's possible to use both SD controllers | |
17 | * at the same time with different pin groups. | |
18 | * | |
19 | * This code was ported to U-Boot by | |
20 | * Alexander Graf <agraf@suse.de> | |
21 | * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by | |
22 | * Phil Elwell <phil@raspberrypi.org> | |
23 | * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd. | |
24 | * which is based on | |
25 | * mmc-bcm2835.c by Gellert Weisz | |
26 | * which is, in turn, based on | |
27 | * sdhci-bcm2708.c by Broadcom | |
28 | * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko | |
29 | * sdhci.c and sdhci-pci.c by Pierre Ossman | |
30 | * | |
31 | * SPDX-License-Identifier: GPL-2.0 | |
32 | */ | |
33 | #include <clk.h> | |
34 | #include <common.h> | |
35 | #include <dm.h> | |
36 | #include <mmc.h> | |
37 | #include <asm/arch/msg.h> | |
38 | #include <asm/unaligned.h> | |
39 | #include <linux/compat.h> | |
40 | #include <linux/io.h> | |
41 | #include <linux/iopoll.h> | |
42 | #include <linux/sizes.h> | |
43 | #include <mach/gpio.h> | |
44 | #include <power/regulator.h> | |
45 | ||
46 | DECLARE_GLOBAL_DATA_PTR; | |
47 | ||
48 | #define msleep(a) udelay(a * 1000) | |
49 | ||
50 | #define SDCMD 0x00 /* Command to SD card - 16 R/W */ | |
51 | #define SDARG 0x04 /* Argument to SD card - 32 R/W */ | |
52 | #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ | |
53 | #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ | |
54 | #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ | |
55 | #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ | |
56 | #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ | |
57 | #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ | |
58 | #define SDHSTS 0x20 /* SD host status - 11 R/W */ | |
59 | #define SDVDD 0x30 /* SD card power control - 1 R/W */ | |
60 | #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ | |
61 | #define SDHCFG 0x38 /* Host configuration - 2 R/W */ | |
62 | #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ | |
63 | #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ | |
64 | #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ | |
65 | ||
66 | #define SDCMD_NEW_FLAG 0x8000 | |
67 | #define SDCMD_FAIL_FLAG 0x4000 | |
68 | #define SDCMD_BUSYWAIT 0x800 | |
69 | #define SDCMD_NO_RESPONSE 0x400 | |
70 | #define SDCMD_LONG_RESPONSE 0x200 | |
71 | #define SDCMD_WRITE_CMD 0x80 | |
72 | #define SDCMD_READ_CMD 0x40 | |
73 | #define SDCMD_CMD_MASK 0x3f | |
74 | ||
75 | #define SDCDIV_MAX_CDIV 0x7ff | |
76 | ||
77 | #define SDHSTS_BUSY_IRPT 0x400 | |
78 | #define SDHSTS_BLOCK_IRPT 0x200 | |
79 | #define SDHSTS_SDIO_IRPT 0x100 | |
80 | #define SDHSTS_REW_TIME_OUT 0x80 | |
81 | #define SDHSTS_CMD_TIME_OUT 0x40 | |
82 | #define SDHSTS_CRC16_ERROR 0x20 | |
83 | #define SDHSTS_CRC7_ERROR 0x10 | |
84 | #define SDHSTS_FIFO_ERROR 0x08 | |
85 | #define SDHSTS_DATA_FLAG 0x01 | |
86 | ||
87 | #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \ | |
88 | SDHSTS_BLOCK_IRPT | \ | |
89 | SDHSTS_SDIO_IRPT | \ | |
90 | SDHSTS_REW_TIME_OUT | \ | |
91 | SDHSTS_CMD_TIME_OUT | \ | |
92 | SDHSTS_CRC16_ERROR | \ | |
93 | SDHSTS_CRC7_ERROR | \ | |
94 | SDHSTS_FIFO_ERROR) | |
95 | ||
96 | #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \ | |
97 | SDHSTS_CRC16_ERROR | \ | |
98 | SDHSTS_REW_TIME_OUT | \ | |
99 | SDHSTS_FIFO_ERROR) | |
100 | ||
101 | #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \ | |
102 | SDHSTS_TRANSFER_ERROR_MASK) | |
103 | ||
104 | #define SDHCFG_BUSY_IRPT_EN BIT(10) | |
105 | #define SDHCFG_BLOCK_IRPT_EN BIT(8) | |
106 | #define SDHCFG_SDIO_IRPT_EN BIT(5) | |
107 | #define SDHCFG_DATA_IRPT_EN BIT(4) | |
108 | #define SDHCFG_SLOW_CARD BIT(3) | |
109 | #define SDHCFG_WIDE_EXT_BUS BIT(2) | |
110 | #define SDHCFG_WIDE_INT_BUS BIT(1) | |
111 | #define SDHCFG_REL_CMD_LINE BIT(0) | |
112 | ||
113 | #define SDVDD_POWER_OFF 0 | |
114 | #define SDVDD_POWER_ON 1 | |
115 | ||
116 | #define SDEDM_FORCE_DATA_MODE BIT(19) | |
117 | #define SDEDM_CLOCK_PULSE BIT(20) | |
118 | #define SDEDM_BYPASS BIT(21) | |
119 | ||
120 | #define SDEDM_FIFO_FILL_SHIFT 4 | |
121 | #define SDEDM_FIFO_FILL_MASK 0x1f | |
122 | static u32 edm_fifo_fill(u32 edm) | |
123 | { | |
124 | return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK; | |
125 | } | |
126 | ||
127 | #define SDEDM_WRITE_THRESHOLD_SHIFT 9 | |
128 | #define SDEDM_READ_THRESHOLD_SHIFT 14 | |
129 | #define SDEDM_THRESHOLD_MASK 0x1f | |
130 | ||
131 | #define SDEDM_FSM_MASK 0xf | |
132 | #define SDEDM_FSM_IDENTMODE 0x0 | |
133 | #define SDEDM_FSM_DATAMODE 0x1 | |
134 | #define SDEDM_FSM_READDATA 0x2 | |
135 | #define SDEDM_FSM_WRITEDATA 0x3 | |
136 | #define SDEDM_FSM_READWAIT 0x4 | |
137 | #define SDEDM_FSM_READCRC 0x5 | |
138 | #define SDEDM_FSM_WRITECRC 0x6 | |
139 | #define SDEDM_FSM_WRITEWAIT1 0x7 | |
140 | #define SDEDM_FSM_POWERDOWN 0x8 | |
141 | #define SDEDM_FSM_POWERUP 0x9 | |
142 | #define SDEDM_FSM_WRITESTART1 0xa | |
143 | #define SDEDM_FSM_WRITESTART2 0xb | |
144 | #define SDEDM_FSM_GENPULSES 0xc | |
145 | #define SDEDM_FSM_WRITEWAIT2 0xd | |
146 | #define SDEDM_FSM_STARTPOWDOWN 0xf | |
147 | ||
148 | #define SDDATA_FIFO_WORDS 16 | |
149 | ||
150 | #define FIFO_READ_THRESHOLD 4 | |
151 | #define FIFO_WRITE_THRESHOLD 4 | |
152 | #define SDDATA_FIFO_PIO_BURST 8 | |
153 | ||
154 | #define SDHST_TIMEOUT_MAX_USEC 100000 | |
155 | ||
156 | struct bcm2835_plat { | |
157 | struct mmc_config cfg; | |
158 | struct mmc mmc; | |
159 | }; | |
160 | ||
161 | struct bcm2835_host { | |
162 | void __iomem *ioaddr; | |
163 | u32 phys_addr; | |
164 | ||
165 | int clock; /* Current clock speed */ | |
166 | unsigned int max_clk; /* Max possible freq */ | |
167 | unsigned int blocks; /* remaining PIO blocks */ | |
168 | int irq; /* Device IRQ */ | |
169 | ||
170 | u32 ns_per_fifo_word; | |
171 | ||
172 | /* cached registers */ | |
173 | u32 hcfg; | |
174 | u32 cdiv; | |
175 | ||
176 | struct mmc_cmd *cmd; /* Current command */ | |
177 | struct mmc_data *data; /* Current data request */ | |
178 | bool data_complete:1;/* Data finished before cmd */ | |
179 | bool use_busy:1; /* Wait for busy interrupt */ | |
180 | bool wait_data_complete:1; /* Wait for data */ | |
181 | ||
182 | /* for threaded irq handler */ | |
183 | bool irq_block; | |
184 | bool irq_busy; | |
185 | bool irq_data; | |
186 | ||
187 | struct udevice *dev; | |
188 | struct mmc *mmc; | |
189 | struct bcm2835_plat *plat; | |
190 | }; | |
191 | ||
192 | static void bcm2835_dumpregs(struct bcm2835_host *host) | |
193 | { | |
194 | dev_dbg(dev, "=========== REGISTER DUMP ===========\n"); | |
195 | dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD)); | |
196 | dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG)); | |
197 | dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT)); | |
198 | dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); | |
199 | dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0)); | |
200 | dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1)); | |
201 | dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2)); | |
202 | dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3)); | |
203 | dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS)); | |
204 | dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD)); | |
205 | dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM)); | |
206 | dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG)); | |
207 | dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT)); | |
208 | dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC)); | |
209 | dev_dbg(dev, "===========================================\n"); | |
210 | } | |
211 | ||
212 | static void bcm2835_reset_internal(struct bcm2835_host *host) | |
213 | { | |
214 | u32 temp; | |
215 | ||
216 | writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); | |
217 | writel(0, host->ioaddr + SDCMD); | |
218 | writel(0, host->ioaddr + SDARG); | |
219 | /* Set timeout to a big enough value so we don't hit it */ | |
220 | writel(0xf00000, host->ioaddr + SDTOUT); | |
221 | writel(0, host->ioaddr + SDCDIV); | |
222 | /* Clear status register */ | |
223 | writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS); | |
224 | writel(0, host->ioaddr + SDHCFG); | |
225 | writel(0, host->ioaddr + SDHBCT); | |
226 | writel(0, host->ioaddr + SDHBLC); | |
227 | ||
228 | /* Limit fifo usage due to silicon bug */ | |
229 | temp = readl(host->ioaddr + SDEDM); | |
230 | temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) | | |
231 | (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT)); | |
232 | temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) | | |
233 | (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT); | |
234 | writel(temp, host->ioaddr + SDEDM); | |
235 | /* Wait for FIFO threshold to populate */ | |
236 | msleep(20); | |
237 | writel(SDVDD_POWER_ON, host->ioaddr + SDVDD); | |
238 | /* Wait for all components to go through power on cycle */ | |
239 | msleep(20); | |
240 | host->clock = 0; | |
241 | writel(host->hcfg, host->ioaddr + SDHCFG); | |
242 | writel(host->cdiv, host->ioaddr + SDCDIV); | |
243 | } | |
244 | ||
245 | static int bcm2835_finish_command(struct bcm2835_host *host); | |
246 | ||
247 | static void bcm2835_wait_transfer_complete(struct bcm2835_host *host) | |
248 | { | |
249 | int timediff; | |
250 | u32 alternate_idle; | |
251 | ||
252 | alternate_idle = (host->data->flags & MMC_DATA_READ) ? | |
253 | SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1; | |
254 | ||
255 | timediff = 0; | |
256 | ||
257 | while (1) { | |
258 | u32 edm, fsm; | |
259 | ||
260 | edm = readl(host->ioaddr + SDEDM); | |
261 | fsm = edm & SDEDM_FSM_MASK; | |
262 | ||
263 | if ((fsm == SDEDM_FSM_IDENTMODE) || | |
264 | (fsm == SDEDM_FSM_DATAMODE)) | |
265 | break; | |
266 | if (fsm == alternate_idle) { | |
267 | writel(edm | SDEDM_FORCE_DATA_MODE, | |
268 | host->ioaddr + SDEDM); | |
269 | break; | |
270 | } | |
271 | ||
272 | /* Error out after 100000 register reads (~1s) */ | |
273 | if (timediff++ == 100000) { | |
274 | dev_err(host->dev, | |
275 | "wait_transfer_complete - still waiting after %d retries\n", | |
276 | timediff); | |
277 | bcm2835_dumpregs(host); | |
278 | return; | |
279 | } | |
280 | } | |
281 | } | |
282 | ||
283 | static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read) | |
284 | { | |
285 | struct mmc_data *data = host->data; | |
286 | size_t blksize = data->blocksize; | |
287 | int copy_words; | |
288 | u32 hsts = 0; | |
289 | u32 *buf; | |
290 | ||
291 | if (blksize % sizeof(u32)) | |
292 | return -EINVAL; | |
293 | ||
294 | buf = is_read ? (u32 *)data->dest : (u32 *)data->src; | |
295 | ||
296 | if (is_read) | |
297 | data->dest += blksize; | |
298 | else | |
299 | data->src += blksize; | |
300 | ||
301 | copy_words = blksize / sizeof(u32); | |
302 | ||
303 | /* | |
304 | * Copy all contents from/to the FIFO as far as it reaches, | |
305 | * then wait for it to fill/empty again and rewind. | |
306 | */ | |
307 | while (copy_words) { | |
308 | int burst_words, words; | |
309 | u32 edm; | |
310 | ||
311 | burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words); | |
312 | edm = readl(host->ioaddr + SDEDM); | |
313 | if (is_read) | |
314 | words = edm_fifo_fill(edm); | |
315 | else | |
316 | words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm); | |
317 | ||
318 | if (words < burst_words) { | |
319 | int fsm_state = (edm & SDEDM_FSM_MASK); | |
320 | ||
321 | if ((is_read && | |
322 | (fsm_state != SDEDM_FSM_READDATA && | |
323 | fsm_state != SDEDM_FSM_READWAIT && | |
324 | fsm_state != SDEDM_FSM_READCRC)) || | |
325 | (!is_read && | |
326 | (fsm_state != SDEDM_FSM_WRITEDATA && | |
327 | fsm_state != SDEDM_FSM_WRITESTART1 && | |
328 | fsm_state != SDEDM_FSM_WRITESTART2))) { | |
329 | hsts = readl(host->ioaddr + SDHSTS); | |
330 | printf("fsm %x, hsts %08x\n", fsm_state, hsts); | |
331 | if (hsts & SDHSTS_ERROR_MASK) | |
332 | break; | |
333 | } | |
334 | ||
335 | continue; | |
336 | } else if (words > copy_words) { | |
337 | words = copy_words; | |
338 | } | |
339 | ||
340 | copy_words -= words; | |
341 | ||
342 | /* Copy current chunk to/from the FIFO */ | |
343 | while (words) { | |
344 | if (is_read) | |
345 | *(buf++) = readl(host->ioaddr + SDDATA); | |
346 | else | |
347 | writel(*(buf++), host->ioaddr + SDDATA); | |
348 | words--; | |
349 | } | |
350 | } | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
355 | static int bcm2835_transfer_pio(struct bcm2835_host *host) | |
356 | { | |
357 | u32 sdhsts; | |
358 | bool is_read; | |
359 | int ret = 0; | |
360 | ||
361 | is_read = (host->data->flags & MMC_DATA_READ) != 0; | |
362 | ret = bcm2835_transfer_block_pio(host, is_read); | |
363 | ||
364 | if (host->wait_data_complete) | |
365 | bcm2835_wait_transfer_complete(host); | |
366 | ||
367 | sdhsts = readl(host->ioaddr + SDHSTS); | |
368 | if (sdhsts & (SDHSTS_CRC16_ERROR | | |
369 | SDHSTS_CRC7_ERROR | | |
370 | SDHSTS_FIFO_ERROR)) { | |
371 | printf("%s transfer error - HSTS %08x\n", | |
372 | is_read ? "read" : "write", sdhsts); | |
373 | ret = -EILSEQ; | |
374 | } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | | |
375 | SDHSTS_REW_TIME_OUT))) { | |
376 | printf("%s timeout error - HSTS %08x\n", | |
377 | is_read ? "read" : "write", sdhsts); | |
378 | ret = -ETIMEDOUT; | |
379 | } | |
380 | ||
381 | return ret; | |
382 | } | |
383 | ||
384 | static void bcm2835_set_transfer_irqs(struct bcm2835_host *host) | |
385 | { | |
386 | u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN | | |
387 | SDHCFG_BUSY_IRPT_EN; | |
388 | ||
389 | host->hcfg = (host->hcfg & ~all_irqs) | | |
390 | SDHCFG_DATA_IRPT_EN | | |
391 | SDHCFG_BUSY_IRPT_EN; | |
392 | ||
393 | writel(host->hcfg, host->ioaddr + SDHCFG); | |
394 | } | |
395 | ||
396 | static | |
397 | void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd, | |
398 | struct mmc_data *data) | |
399 | { | |
400 | WARN_ON(host->data); | |
401 | ||
402 | host->data = data; | |
403 | if (!data) | |
404 | return; | |
405 | ||
406 | host->wait_data_complete = cmd->cmdidx != MMC_CMD_READ_MULTIPLE_BLOCK; | |
407 | host->data_complete = false; | |
408 | ||
409 | /* Use PIO */ | |
410 | host->blocks = data->blocks; | |
411 | ||
412 | bcm2835_set_transfer_irqs(host); | |
413 | ||
414 | writel(data->blocksize, host->ioaddr + SDHBCT); | |
415 | writel(data->blocks, host->ioaddr + SDHBLC); | |
416 | } | |
417 | ||
418 | static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host) | |
419 | { | |
420 | u32 value; | |
421 | int ret; | |
422 | int timeout_us = SDHST_TIMEOUT_MAX_USEC; | |
423 | ||
424 | ret = readl_poll_timeout(host->ioaddr + SDCMD, value, | |
425 | !(value & SDCMD_NEW_FLAG), timeout_us); | |
426 | if (ret == -ETIMEDOUT) | |
427 | printf("%s: timeout (%d us)\n", __func__, timeout_us); | |
428 | ||
429 | return value; | |
430 | } | |
431 | ||
432 | static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd, | |
433 | struct mmc_data *data) | |
434 | { | |
435 | u32 sdcmd, sdhsts; | |
436 | ||
437 | WARN_ON(host->cmd); | |
438 | ||
439 | if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) { | |
440 | printf("unsupported response type!\n"); | |
441 | return -EINVAL; | |
442 | } | |
443 | ||
444 | sdcmd = bcm2835_read_wait_sdcmd(host); | |
445 | if (sdcmd & SDCMD_NEW_FLAG) { | |
446 | printf("previous command never completed.\n"); | |
447 | bcm2835_dumpregs(host); | |
448 | return -EBUSY; | |
449 | } | |
450 | ||
451 | host->cmd = cmd; | |
452 | ||
453 | /* Clear any error flags */ | |
454 | sdhsts = readl(host->ioaddr + SDHSTS); | |
455 | if (sdhsts & SDHSTS_ERROR_MASK) | |
456 | writel(sdhsts, host->ioaddr + SDHSTS); | |
457 | ||
458 | bcm2835_prepare_data(host, cmd, data); | |
459 | ||
460 | writel(cmd->cmdarg, host->ioaddr + SDARG); | |
461 | ||
462 | sdcmd = cmd->cmdidx & SDCMD_CMD_MASK; | |
463 | ||
464 | host->use_busy = false; | |
465 | if (!(cmd->resp_type & MMC_RSP_PRESENT)) { | |
466 | sdcmd |= SDCMD_NO_RESPONSE; | |
467 | } else { | |
468 | if (cmd->resp_type & MMC_RSP_136) | |
469 | sdcmd |= SDCMD_LONG_RESPONSE; | |
470 | if (cmd->resp_type & MMC_RSP_BUSY) { | |
471 | sdcmd |= SDCMD_BUSYWAIT; | |
472 | host->use_busy = true; | |
473 | } | |
474 | } | |
475 | ||
476 | if (data) { | |
477 | if (data->flags & MMC_DATA_WRITE) | |
478 | sdcmd |= SDCMD_WRITE_CMD; | |
479 | if (data->flags & MMC_DATA_READ) | |
480 | sdcmd |= SDCMD_READ_CMD; | |
481 | } | |
482 | ||
483 | writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD); | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | static int bcm2835_transfer_complete(struct bcm2835_host *host) | |
489 | { | |
490 | int ret = 0; | |
491 | ||
492 | WARN_ON(!host->data_complete); | |
493 | ||
494 | host->data = NULL; | |
495 | ||
496 | return ret; | |
497 | } | |
498 | ||
499 | static void bcm2835_finish_data(struct bcm2835_host *host) | |
500 | { | |
501 | host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); | |
502 | writel(host->hcfg, host->ioaddr + SDHCFG); | |
503 | ||
504 | host->data_complete = true; | |
505 | ||
506 | if (host->cmd) { | |
507 | /* Data managed to finish before the | |
508 | * command completed. Make sure we do | |
509 | * things in the proper order. | |
510 | */ | |
511 | dev_dbg(dev, "Finished early - HSTS %08x\n", | |
512 | readl(host->ioaddr + SDHSTS)); | |
513 | } else { | |
514 | bcm2835_transfer_complete(host); | |
515 | } | |
516 | } | |
517 | ||
518 | static int bcm2835_finish_command(struct bcm2835_host *host) | |
519 | { | |
520 | struct mmc_cmd *cmd = host->cmd; | |
521 | u32 sdcmd; | |
522 | int ret = 0; | |
523 | ||
524 | sdcmd = bcm2835_read_wait_sdcmd(host); | |
525 | ||
526 | /* Check for errors */ | |
527 | if (sdcmd & SDCMD_NEW_FLAG) { | |
528 | printf("command never completed.\n"); | |
529 | bcm2835_dumpregs(host); | |
530 | return -EIO; | |
531 | } else if (sdcmd & SDCMD_FAIL_FLAG) { | |
532 | u32 sdhsts = readl(host->ioaddr + SDHSTS); | |
533 | ||
534 | /* Clear the errors */ | |
535 | writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS); | |
536 | ||
537 | if (!(sdhsts & SDHSTS_CRC7_ERROR) || | |
538 | (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) { | |
539 | if (sdhsts & SDHSTS_CMD_TIME_OUT) { | |
540 | ret = -ETIMEDOUT; | |
541 | } else { | |
542 | printf("unexpected command %d error\n", | |
543 | host->cmd->cmdidx); | |
544 | bcm2835_dumpregs(host); | |
545 | ret = -EILSEQ; | |
546 | } | |
547 | ||
548 | return ret; | |
549 | } | |
550 | } | |
551 | ||
552 | if (cmd->resp_type & MMC_RSP_PRESENT) { | |
553 | if (cmd->resp_type & MMC_RSP_136) { | |
554 | int i; | |
555 | ||
556 | for (i = 0; i < 4; i++) { | |
557 | cmd->response[3 - i] = | |
558 | readl(host->ioaddr + SDRSP0 + i * 4); | |
559 | } | |
560 | } else { | |
561 | cmd->response[0] = readl(host->ioaddr + SDRSP0); | |
562 | } | |
563 | } | |
564 | ||
565 | /* Processed actual command. */ | |
566 | host->cmd = NULL; | |
567 | if (host->data && host->data_complete) | |
568 | ret = bcm2835_transfer_complete(host); | |
569 | ||
570 | return ret; | |
571 | } | |
572 | ||
573 | static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask) | |
574 | { | |
575 | int ret = -EINVAL; | |
576 | ||
577 | if (!(intmask & SDHSTS_ERROR_MASK)) | |
578 | return 0; | |
579 | ||
580 | if (!host->cmd) | |
581 | return -EINVAL; | |
582 | ||
583 | printf("sdhost_busy_irq: intmask %08x\n", intmask); | |
584 | if (intmask & SDHSTS_CRC7_ERROR) { | |
585 | ret = -EILSEQ; | |
586 | } else if (intmask & (SDHSTS_CRC16_ERROR | | |
587 | SDHSTS_FIFO_ERROR)) { | |
588 | ret = -EILSEQ; | |
589 | } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) { | |
590 | ret = -ETIMEDOUT; | |
591 | } | |
592 | bcm2835_dumpregs(host); | |
593 | return ret; | |
594 | } | |
595 | ||
596 | static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask) | |
597 | { | |
598 | int ret = 0; | |
599 | ||
600 | if (!host->data) | |
601 | return 0; | |
602 | if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR)) | |
603 | ret = -EILSEQ; | |
604 | if (intmask & SDHSTS_REW_TIME_OUT) | |
605 | ret = -ETIMEDOUT; | |
606 | ||
607 | if (ret) | |
608 | printf("%s:%d %d\n", __func__, __LINE__, ret); | |
609 | ||
610 | return ret; | |
611 | } | |
612 | ||
613 | static void bcm2835_busy_irq(struct bcm2835_host *host) | |
614 | { | |
615 | if (WARN_ON(!host->cmd)) { | |
616 | bcm2835_dumpregs(host); | |
617 | return; | |
618 | } | |
619 | ||
620 | if (WARN_ON(!host->use_busy)) { | |
621 | bcm2835_dumpregs(host); | |
622 | return; | |
623 | } | |
624 | host->use_busy = false; | |
625 | ||
626 | bcm2835_finish_command(host); | |
627 | } | |
628 | ||
629 | static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask) | |
630 | { | |
631 | int ret; | |
632 | ||
633 | /* | |
634 | * There are no dedicated data/space available interrupt | |
635 | * status bits, so it is necessary to use the single shared | |
636 | * data/space available FIFO status bits. It is therefore not | |
637 | * an error to get here when there is no data transfer in | |
638 | * progress. | |
639 | */ | |
640 | if (!host->data) | |
641 | return; | |
642 | ||
643 | ret = bcm2835_check_data_error(host, intmask); | |
644 | if (ret) | |
645 | goto finished; | |
646 | ||
647 | if (host->data->flags & MMC_DATA_WRITE) { | |
648 | /* Use the block interrupt for writes after the first block */ | |
649 | host->hcfg &= ~(SDHCFG_DATA_IRPT_EN); | |
650 | host->hcfg |= SDHCFG_BLOCK_IRPT_EN; | |
651 | writel(host->hcfg, host->ioaddr + SDHCFG); | |
652 | bcm2835_transfer_pio(host); | |
653 | } else { | |
654 | bcm2835_transfer_pio(host); | |
655 | host->blocks--; | |
656 | if ((host->blocks == 0)) | |
657 | goto finished; | |
658 | } | |
659 | return; | |
660 | ||
661 | finished: | |
662 | host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); | |
663 | writel(host->hcfg, host->ioaddr + SDHCFG); | |
664 | } | |
665 | ||
666 | static void bcm2835_data_threaded_irq(struct bcm2835_host *host) | |
667 | { | |
668 | if (!host->data) | |
669 | return; | |
670 | if ((host->blocks == 0)) | |
671 | bcm2835_finish_data(host); | |
672 | } | |
673 | ||
674 | static void bcm2835_block_irq(struct bcm2835_host *host) | |
675 | { | |
676 | if (WARN_ON(!host->data)) { | |
677 | bcm2835_dumpregs(host); | |
678 | return; | |
679 | } | |
680 | ||
681 | WARN_ON(!host->blocks); | |
682 | if ((--host->blocks == 0)) | |
683 | bcm2835_finish_data(host); | |
684 | else | |
685 | bcm2835_transfer_pio(host); | |
686 | } | |
687 | ||
688 | static irqreturn_t bcm2835_irq(int irq, void *dev_id) | |
689 | { | |
690 | irqreturn_t result = IRQ_NONE; | |
691 | struct bcm2835_host *host = dev_id; | |
692 | u32 intmask; | |
693 | ||
694 | intmask = readl(host->ioaddr + SDHSTS); | |
695 | ||
696 | writel(SDHSTS_BUSY_IRPT | | |
697 | SDHSTS_BLOCK_IRPT | | |
698 | SDHSTS_SDIO_IRPT | | |
699 | SDHSTS_DATA_FLAG, | |
700 | host->ioaddr + SDHSTS); | |
701 | ||
702 | if (intmask & SDHSTS_BLOCK_IRPT) { | |
703 | bcm2835_check_data_error(host, intmask); | |
704 | host->irq_block = true; | |
705 | result = IRQ_WAKE_THREAD; | |
706 | } | |
707 | ||
708 | if (intmask & SDHSTS_BUSY_IRPT) { | |
709 | if (!bcm2835_check_cmd_error(host, intmask)) { | |
710 | host->irq_busy = true; | |
711 | result = IRQ_WAKE_THREAD; | |
712 | } else { | |
713 | result = IRQ_HANDLED; | |
714 | } | |
715 | } | |
716 | ||
717 | /* There is no true data interrupt status bit, so it is | |
718 | * necessary to qualify the data flag with the interrupt | |
719 | * enable bit. | |
720 | */ | |
721 | if ((intmask & SDHSTS_DATA_FLAG) && | |
722 | (host->hcfg & SDHCFG_DATA_IRPT_EN)) { | |
723 | bcm2835_data_irq(host, intmask); | |
724 | host->irq_data = true; | |
725 | result = IRQ_WAKE_THREAD; | |
726 | } | |
727 | ||
728 | return result; | |
729 | } | |
730 | ||
731 | static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id) | |
732 | { | |
733 | struct bcm2835_host *host = dev_id; | |
734 | ||
735 | if (host->irq_block) { | |
736 | host->irq_block = false; | |
737 | bcm2835_block_irq(host); | |
738 | } | |
739 | ||
740 | if (host->irq_busy) { | |
741 | host->irq_busy = false; | |
742 | bcm2835_busy_irq(host); | |
743 | } | |
744 | ||
745 | if (host->irq_data) { | |
746 | host->irq_data = false; | |
747 | bcm2835_data_threaded_irq(host); | |
748 | } | |
749 | ||
750 | return IRQ_HANDLED; | |
751 | } | |
752 | ||
753 | static void bcm2835_irq_poll(struct bcm2835_host *host) | |
754 | { | |
755 | u32 intmask; | |
756 | ||
757 | while (1) { | |
758 | intmask = readl(host->ioaddr + SDHSTS); | |
759 | if (intmask & (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | | |
760 | SDHSTS_SDIO_IRPT | SDHSTS_DATA_FLAG)) { | |
761 | bcm2835_irq(0, host); | |
762 | bcm2835_threaded_irq(0, host); | |
763 | return; | |
764 | } | |
765 | } | |
766 | } | |
767 | ||
768 | static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock) | |
769 | { | |
770 | int div; | |
771 | ||
772 | /* The SDCDIV register has 11 bits, and holds (div - 2). But | |
773 | * in data mode the max is 50MHz wihout a minimum, and only | |
774 | * the bottom 3 bits are used. Since the switch over is | |
775 | * automatic (unless we have marked the card as slow...), | |
776 | * chosen values have to make sense in both modes. Ident mode | |
777 | * must be 100-400KHz, so can range check the requested | |
778 | * clock. CMD15 must be used to return to data mode, so this | |
779 | * can be monitored. | |
780 | * | |
781 | * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz | |
782 | * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz | |
783 | * | |
784 | * 623->400KHz/27.8MHz | |
785 | * reset value (507)->491159/50MHz | |
786 | * | |
787 | * BUT, the 3-bit clock divisor in data mode is too small if | |
788 | * the core clock is higher than 250MHz, so instead use the | |
789 | * SLOW_CARD configuration bit to force the use of the ident | |
790 | * clock divisor at all times. | |
791 | */ | |
792 | ||
793 | if (clock < 100000) { | |
794 | /* Can't stop the clock, but make it as slow as possible | |
795 | * to show willing | |
796 | */ | |
797 | host->cdiv = SDCDIV_MAX_CDIV; | |
798 | writel(host->cdiv, host->ioaddr + SDCDIV); | |
799 | return; | |
800 | } | |
801 | ||
802 | div = host->max_clk / clock; | |
803 | if (div < 2) | |
804 | div = 2; | |
805 | if ((host->max_clk / div) > clock) | |
806 | div++; | |
807 | div -= 2; | |
808 | ||
809 | if (div > SDCDIV_MAX_CDIV) | |
810 | div = SDCDIV_MAX_CDIV; | |
811 | ||
812 | clock = host->max_clk / (div + 2); | |
813 | host->mmc->clock = clock; | |
814 | ||
815 | /* Calibrate some delays */ | |
816 | ||
817 | host->ns_per_fifo_word = (1000000000 / clock) * | |
818 | ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32); | |
819 | ||
820 | host->cdiv = div; | |
821 | writel(host->cdiv, host->ioaddr + SDCDIV); | |
822 | ||
823 | /* Set the timeout to 500ms */ | |
824 | writel(host->mmc->clock / 2, host->ioaddr + SDTOUT); | |
825 | } | |
826 | ||
827 | static inline int is_power_of_2(u64 x) | |
828 | { | |
829 | return !(x & (x - 1)); | |
830 | } | |
831 | ||
832 | static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, | |
833 | struct mmc_data *data) | |
834 | { | |
835 | struct bcm2835_host *host = dev_get_priv(dev); | |
836 | u32 edm, fsm; | |
837 | int ret = 0; | |
838 | ||
839 | if (data && !is_power_of_2(data->blocksize)) { | |
840 | printf("unsupported block size (%d bytes)\n", data->blocksize); | |
841 | ||
842 | if (cmd) | |
843 | return -EINVAL; | |
844 | } | |
845 | ||
846 | edm = readl(host->ioaddr + SDEDM); | |
847 | fsm = edm & SDEDM_FSM_MASK; | |
848 | ||
849 | if ((fsm != SDEDM_FSM_IDENTMODE) && | |
850 | (fsm != SDEDM_FSM_DATAMODE) && | |
851 | (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) { | |
852 | printf("previous command (%d) not complete (EDM %08x)\n", | |
853 | readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm); | |
854 | bcm2835_dumpregs(host); | |
855 | ||
856 | if (cmd) | |
857 | return -EILSEQ; | |
858 | ||
859 | return 0; | |
860 | } | |
861 | ||
862 | if (cmd) { | |
863 | ret = bcm2835_send_command(host, cmd, data); | |
864 | if (!ret && !host->use_busy) | |
865 | ret = bcm2835_finish_command(host); | |
866 | } | |
867 | ||
868 | /* Wait for completion of busy signal or data transfer */ | |
869 | while (host->use_busy || host->data) | |
870 | bcm2835_irq_poll(host); | |
871 | ||
872 | return ret; | |
873 | } | |
874 | ||
875 | static int bcm2835_set_ios(struct udevice *dev) | |
876 | { | |
877 | struct bcm2835_host *host = dev_get_priv(dev); | |
878 | struct mmc *mmc = mmc_get_mmc_dev(dev); | |
879 | ||
880 | if (!mmc->clock || mmc->clock != host->clock) { | |
881 | bcm2835_set_clock(host, mmc->clock); | |
882 | host->clock = mmc->clock; | |
883 | } | |
884 | ||
885 | /* set bus width */ | |
886 | host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; | |
887 | if (mmc->bus_width == 4) | |
888 | host->hcfg |= SDHCFG_WIDE_EXT_BUS; | |
889 | ||
890 | host->hcfg |= SDHCFG_WIDE_INT_BUS; | |
891 | ||
892 | /* Disable clever clock switching, to cope with fast core clocks */ | |
893 | host->hcfg |= SDHCFG_SLOW_CARD; | |
894 | ||
895 | writel(host->hcfg, host->ioaddr + SDHCFG); | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
900 | static void bcm2835_add_host(struct bcm2835_host *host) | |
901 | { | |
902 | struct mmc_config *cfg = &host->plat->cfg; | |
903 | ||
904 | cfg->f_max = host->max_clk; | |
905 | cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV; | |
906 | cfg->b_max = 65535; | |
907 | ||
908 | dev_dbg(dev, "f_max %d, f_min %d\n", | |
909 | cfg->f_max, cfg->f_min); | |
910 | ||
911 | /* host controller capabilities */ | |
912 | cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz; | |
913 | ||
914 | /* report supported voltage ranges */ | |
915 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; | |
916 | ||
917 | /* Set interrupt enables */ | |
918 | host->hcfg = SDHCFG_BUSY_IRPT_EN; | |
919 | ||
920 | bcm2835_reset_internal(host); | |
921 | } | |
922 | ||
923 | static int bcm2835_probe(struct udevice *dev) | |
924 | { | |
925 | struct bcm2835_plat *plat = dev_get_platdata(dev); | |
926 | struct bcm2835_host *host = dev_get_priv(dev); | |
927 | struct mmc *mmc = mmc_get_mmc_dev(dev); | |
928 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); | |
929 | ||
930 | host->dev = dev; | |
931 | host->mmc = mmc; | |
932 | host->plat = plat; | |
933 | upriv->mmc = &plat->mmc; | |
934 | plat->cfg.name = dev->name; | |
935 | ||
936 | host->phys_addr = devfdt_get_addr(dev); | |
937 | if (host->phys_addr == FDT_ADDR_T_NONE) | |
938 | return -EINVAL; | |
939 | ||
940 | host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256); | |
941 | if (!host->ioaddr) | |
942 | return -ENOMEM; | |
943 | ||
944 | host->max_clk = bcm2835_get_mmc_clock(); | |
945 | ||
946 | bcm2835_add_host(host); | |
947 | ||
948 | dev_dbg(dev, "%s -> OK\n", __func__); | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
953 | static const struct udevice_id bcm2835_match[] = { | |
954 | { .compatible = "brcm,bcm2835-sdhost" }, | |
955 | { } | |
956 | }; | |
957 | ||
958 | static const struct dm_mmc_ops bcm2835_ops = { | |
959 | .send_cmd = bcm2835_send_cmd, | |
960 | .set_ios = bcm2835_set_ios, | |
961 | }; | |
962 | ||
963 | static int bcm2835_bind(struct udevice *dev) | |
964 | { | |
965 | struct bcm2835_plat *plat = dev_get_platdata(dev); | |
966 | ||
967 | return mmc_bind(dev, &plat->mmc, &plat->cfg); | |
968 | } | |
969 | ||
970 | U_BOOT_DRIVER(bcm2835_sdhost) = { | |
971 | .name = "bcm2835-sdhost", | |
972 | .id = UCLASS_MMC, | |
973 | .of_match = bcm2835_match, | |
974 | .bind = bcm2835_bind, | |
975 | .probe = bcm2835_probe, | |
976 | .priv_auto_alloc_size = sizeof(struct bcm2835_host), | |
977 | .platdata_auto_alloc_size = sizeof(struct bcm2835_plat), | |
978 | .ops = &bcm2835_ops, | |
979 | }; |