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716ebf43 CC |
1 | /* |
2 | * Driver for Blackfin on-chip SDH controller | |
3 | * | |
e54c8209 | 4 | * Copyright (c) 2008-2009 Analog Devices Inc. |
716ebf43 CC |
5 | * |
6 | * Licensed under the GPL-2 or later. | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
10 | #include <malloc.h> | |
11 | #include <part.h> | |
12 | #include <mmc.h> | |
13 | ||
14 | #include <asm/io.h> | |
15 | #include <asm/errno.h> | |
16 | #include <asm/byteorder.h> | |
17 | #include <asm/blackfin.h> | |
130fbeb1 | 18 | #include <asm/clock.h> |
a87589fc | 19 | #include <asm/portmux.h> |
716ebf43 CC |
20 | #include <asm/mach-common/bits/sdh.h> |
21 | #include <asm/mach-common/bits/dma.h> | |
22 | ||
187f32fa | 23 | #if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF60x__) |
716ebf43 CC |
24 | # define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL |
25 | # define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL | |
26 | # define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT | |
27 | # define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND | |
28 | # define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0 | |
29 | # define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1 | |
30 | # define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2 | |
31 | # define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3 | |
32 | # define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER | |
33 | # define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH | |
34 | # define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL | |
35 | # define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL | |
36 | # define bfin_read_SDH_STATUS bfin_read_RSI_STATUS | |
37 | # define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL | |
38 | # define bfin_read_SDH_CFG bfin_read_RSI_CONFIG | |
39 | # define bfin_write_SDH_CFG bfin_write_RSI_CONFIG | |
187f32fa SZ |
40 | # if defined(__ADSPBF60x__) |
41 | # define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ | |
42 | # define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ | |
43 | # define bfin_write_DMA_START_ADDR bfin_write_DMA10_START_ADDR | |
44 | # define bfin_write_DMA_X_COUNT bfin_write_DMA10_X_COUNT | |
45 | # define bfin_write_DMA_X_MODIFY bfin_write_DMA10_X_MODIFY | |
46 | # define bfin_write_DMA_CONFIG bfin_write_DMA10_CONFIG | |
47 | # else | |
48 | # define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL | |
49 | # define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL | |
716ebf43 CC |
50 | # define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR |
51 | # define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT | |
52 | # define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY | |
53 | # define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG | |
187f32fa | 54 | # endif |
a87589fc MF |
55 | # define PORTMUX_PINS \ |
56 | { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 } | |
716ebf43 CC |
57 | #elif defined(__ADSPBF54x__) |
58 | # define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR | |
59 | # define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT | |
60 | # define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY | |
61 | # define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG | |
a87589fc MF |
62 | # define PORTMUX_PINS \ |
63 | { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 } | |
716ebf43 CC |
64 | #else |
65 | # error no support for this proc yet | |
66 | #endif | |
67 | ||
716ebf43 | 68 | static int |
e54c8209 | 69 | sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) |
716ebf43 | 70 | { |
6815f540 | 71 | unsigned int status, timeout; |
e54c8209 CC |
72 | int cmd = mmc_cmd->cmdidx; |
73 | int flags = mmc_cmd->resp_type; | |
74 | int arg = mmc_cmd->cmdarg; | |
6815f540 MF |
75 | int ret; |
76 | u16 sdh_cmd; | |
716ebf43 | 77 | |
6815f540 | 78 | sdh_cmd = cmd | CMD_E; |
716ebf43 CC |
79 | if (flags & MMC_RSP_PRESENT) |
80 | sdh_cmd |= CMD_RSP; | |
716ebf43 CC |
81 | if (flags & MMC_RSP_136) |
82 | sdh_cmd |= CMD_L_RSP; | |
187f32fa SZ |
83 | #ifdef RSI_BLKSZ |
84 | sdh_cmd |= CMD_DATA0_BUSY; | |
85 | #endif | |
716ebf43 CC |
86 | |
87 | bfin_write_SDH_ARGUMENT(arg); | |
6815f540 | 88 | bfin_write_SDH_COMMAND(sdh_cmd); |
716ebf43 CC |
89 | |
90 | /* wait for a while */ | |
6815f540 | 91 | timeout = 0; |
716ebf43 | 92 | do { |
6815f540 MF |
93 | if (++timeout > 1000000) { |
94 | status = CMD_TIME_OUT; | |
95 | break; | |
96 | } | |
716ebf43 CC |
97 | udelay(1); |
98 | status = bfin_read_SDH_STATUS(); | |
99 | } while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | | |
100 | CMD_CRC_FAIL))); | |
101 | ||
102 | if (flags & MMC_RSP_PRESENT) { | |
e54c8209 | 103 | mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0(); |
716ebf43 | 104 | if (flags & MMC_RSP_136) { |
e54c8209 CC |
105 | mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1(); |
106 | mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2(); | |
107 | mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3(); | |
716ebf43 CC |
108 | } |
109 | } | |
110 | ||
e54c8209 | 111 | if (status & CMD_TIME_OUT) |
6815f540 | 112 | ret = TIMEOUT; |
e54c8209 | 113 | else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC) |
6815f540 MF |
114 | ret = COMM_ERR; |
115 | else | |
116 | ret = 0; | |
e54c8209 | 117 | |
716ebf43 CC |
118 | bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | |
119 | CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT); | |
187f32fa SZ |
120 | #ifdef RSI_BLKSZ |
121 | /* wait till card ready */ | |
122 | while (!(bfin_read_RSI_ESTAT() & SD_CARD_READY)) | |
123 | continue; | |
124 | bfin_write_RSI_ESTAT(SD_CARD_READY); | |
125 | #endif | |
6815f540 | 126 | |
716ebf43 CC |
127 | return ret; |
128 | } | |
129 | ||
e54c8209 CC |
130 | /* set data for single block transfer */ |
131 | static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data) | |
716ebf43 | 132 | { |
e54c8209 CC |
133 | u16 data_ctl = 0; |
134 | u16 dma_cfg = 0; | |
21a50374 | 135 | unsigned long data_size = data->blocksize * data->blocks; |
716ebf43 | 136 | |
e54c8209 CC |
137 | /* Don't support write yet. */ |
138 | if (data->flags & MMC_DATA_WRITE) | |
139 | return UNUSABLE_ERR; | |
187f32fa | 140 | #ifndef RSI_BLKSZ |
21a50374 | 141 | data_ctl |= ((ffs(data_size) - 1) << 4); |
187f32fa SZ |
142 | #else |
143 | bfin_write_SDH_BLK_SIZE(data_size); | |
144 | #endif | |
716ebf43 CC |
145 | data_ctl |= DTX_DIR; |
146 | bfin_write_SDH_DATA_CTL(data_ctl); | |
187f32fa | 147 | dma_cfg = WDSIZE_32 | PSIZE_32 | RESTART | WNR | DMAEN; |
716ebf43 | 148 | |
1fd2d792 | 149 | bfin_write_SDH_DATA_TIMER(-1); |
716ebf43 | 150 | |
e54c8209 | 151 | blackfin_dcache_flush_invalidate_range(data->dest, |
21a50374 | 152 | data->dest + data_size); |
e54c8209 CC |
153 | /* configure DMA */ |
154 | bfin_write_DMA_START_ADDR(data->dest); | |
21a50374 | 155 | bfin_write_DMA_X_COUNT(data_size / 4); |
e54c8209 CC |
156 | bfin_write_DMA_X_MODIFY(4); |
157 | bfin_write_DMA_CONFIG(dma_cfg); | |
21a50374 | 158 | bfin_write_SDH_DATA_LGTH(data_size); |
e54c8209 CC |
159 | /* kick off transfer */ |
160 | bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E); | |
716ebf43 | 161 | |
187f32fa | 162 | return 0; |
716ebf43 CC |
163 | } |
164 | ||
e54c8209 CC |
165 | |
166 | static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd, | |
167 | struct mmc_data *data) | |
716ebf43 | 168 | { |
e54c8209 CC |
169 | u32 status; |
170 | int ret = 0; | |
716ebf43 | 171 | |
187f32fa SZ |
172 | if (data) { |
173 | ret = sdh_setup_data(mmc, data); | |
174 | if (ret) | |
175 | return ret; | |
176 | } | |
177 | ||
e54c8209 CC |
178 | ret = sdh_send_cmd(mmc, cmd); |
179 | if (ret) { | |
187f32fa SZ |
180 | bfin_write_SDH_COMMAND(0); |
181 | bfin_write_DMA_CONFIG(0); | |
182 | bfin_write_SDH_DATA_CTL(0); | |
183 | SSYNC(); | |
e54c8209 CC |
184 | printf("sending CMD%d failed\n", cmd->cmdidx); |
185 | return ret; | |
186 | } | |
187f32fa | 187 | |
e54c8209 | 188 | if (data) { |
716ebf43 CC |
189 | do { |
190 | udelay(1); | |
191 | status = bfin_read_SDH_STATUS(); | |
e54c8209 | 192 | } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN))); |
716ebf43 | 193 | |
e54c8209 CC |
194 | if (status & DAT_TIME_OUT) { |
195 | bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT); | |
196 | ret |= TIMEOUT; | |
197 | } else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) { | |
198 | bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT); | |
199 | ret |= COMM_ERR; | |
200 | } else | |
716ebf43 | 201 | bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT); |
e54c8209 CC |
202 | |
203 | if (ret) { | |
204 | printf("tranfering data failed\n"); | |
205 | return ret; | |
716ebf43 CC |
206 | } |
207 | } | |
e54c8209 | 208 | return 0; |
716ebf43 CC |
209 | } |
210 | ||
e54c8209 | 211 | static void sdh_set_clk(unsigned long clk) |
716ebf43 | 212 | { |
e54c8209 CC |
213 | unsigned long sys_clk; |
214 | unsigned long clk_div; | |
215 | u16 clk_ctl = 0; | |
216 | ||
217 | clk_ctl = bfin_read_SDH_CLK_CTL(); | |
218 | if (clk) { | |
219 | /* setting SD_CLK */ | |
220 | sys_clk = get_sclk(); | |
221 | bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E); | |
222 | if (sys_clk % (2 * clk) == 0) | |
223 | clk_div = sys_clk / (2 * clk) - 1; | |
224 | else | |
225 | clk_div = sys_clk / (2 * clk); | |
226 | ||
227 | if (clk_div > 0xff) | |
228 | clk_div = 0xff; | |
229 | clk_ctl |= (clk_div & 0xff); | |
230 | clk_ctl |= CLK_E; | |
231 | bfin_write_SDH_CLK_CTL(clk_ctl); | |
232 | } else | |
233 | bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E); | |
716ebf43 CC |
234 | } |
235 | ||
e54c8209 | 236 | static void bfin_sdh_set_ios(struct mmc *mmc) |
716ebf43 | 237 | { |
e54c8209 CC |
238 | u16 cfg = 0; |
239 | u16 clk_ctl = 0; | |
240 | ||
93bfd616 | 241 | if (mmc_bus_width(mmc) == 4) { |
e54c8209 | 242 | cfg = bfin_read_SDH_CFG(); |
187f32fa SZ |
243 | #ifndef RSI_BLKSZ |
244 | cfg &= ~PD_SDDAT3; | |
245 | #endif | |
246 | cfg |= PUP_SDDAT3; | |
e54c8209 | 247 | bfin_write_SDH_CFG(cfg); |
187f32fa | 248 | clk_ctl |= WIDE_BUS_4; |
716ebf43 | 249 | } |
e54c8209 CC |
250 | bfin_write_SDH_CLK_CTL(clk_ctl); |
251 | sdh_set_clk(mmc->clock); | |
716ebf43 CC |
252 | } |
253 | ||
e54c8209 | 254 | static int bfin_sdh_init(struct mmc *mmc) |
716ebf43 | 255 | { |
a87589fc | 256 | const unsigned short pins[] = PORTMUX_PINS; |
187f32fa | 257 | int ret; |
a87589fc MF |
258 | |
259 | /* Initialize sdh controller */ | |
187f32fa SZ |
260 | ret = peripheral_request_list(pins, "bfin_sdh"); |
261 | if (ret < 0) | |
262 | return ret; | |
716ebf43 CC |
263 | #if defined(__ADSPBF54x__) |
264 | bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1); | |
716ebf43 CC |
265 | #endif |
266 | bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN); | |
267 | /* Disable card detect pin */ | |
268 | bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60); | |
187f32fa SZ |
269 | #ifndef RSI_BLKSZ |
270 | bfin_write_SDH_PWR_CTL(PWR_ON | ROD_CTL); | |
271 | #else | |
272 | bfin_write_SDH_CFG(bfin_read_SDH_CFG() | PWR_ON); | |
273 | #endif | |
716ebf43 CC |
274 | return 0; |
275 | } | |
276 | ||
ab769f22 PA |
277 | static const struct mmc_ops bfin_mmc_ops = { |
278 | .send_cmd = bfin_sdh_request, | |
279 | .set_ios = bfin_sdh_set_ios, | |
280 | .init = bfin_sdh_init, | |
281 | }; | |
e54c8209 | 282 | |
93bfd616 PA |
283 | static struct mmc_config bfin_mmc_cfg = { |
284 | .name = "Blackfin SDH", | |
285 | .ops = &bfin_mmc_ops, | |
286 | .host_caps = MMC_MODE_4BIT, | |
287 | .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, | |
288 | .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, | |
289 | }; | |
290 | ||
e54c8209 | 291 | int bfin_mmc_init(bd_t *bis) |
716ebf43 | 292 | { |
93bfd616 | 293 | struct mmc *mmc; |
e54c8209 | 294 | |
93bfd616 PA |
295 | bfin_mmc_cfg.f_max = get_sclk(); |
296 | bfin_mmc_cfg.f_min = bfin_mmc_cfg.f_max >> 9; | |
8feafcc4 | 297 | |
93bfd616 PA |
298 | mmc = mmc_create(&bfin_mmc_cfg, NULL); |
299 | if (mmc == NULL) | |
300 | return -1; | |
e54c8209 | 301 | |
716ebf43 CC |
302 | return 0; |
303 | } |