[people/ms/u-boot.git] / drivers / mmc / dw_mmc.c

/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Jaehoon Chung <jh80.chung@samsung.com>
 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <bouncebuf.h>
#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <memalign.h>
#include <mmc.h>
#include <dwmmc.h>

#define PAGE_SIZE 4096

static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
{
	unsigned long timeout = 1000;
	u32 ctrl;

	dwmci_writel(host, DWMCI_CTRL, value);

	while (timeout--) {
		ctrl = dwmci_readl(host, DWMCI_CTRL);
		if (!(ctrl & DWMCI_RESET_ALL))
			return 1;
	}
	return 0;
}

static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
		u32 desc0, u32 desc1, u32 desc2)
{
	struct dwmci_idmac *desc = idmac;

	desc->flags = desc0;
	desc->cnt = desc1;
	desc->addr = desc2;
	desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
}

static void dwmci_prepare_data(struct dwmci_host *host,
			       struct mmc_data *data,
			       struct dwmci_idmac *cur_idmac,
			       void *bounce_buffer)
{
	unsigned long ctrl;
	unsigned int i = 0, flags, cnt, blk_cnt;
	ulong data_start, data_end;


	blk_cnt = data->blocks;

	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);

	data_start = (ulong)cur_idmac;
	dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);

	do {
		flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
		flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
		if (blk_cnt <= 8) {
			flags |= DWMCI_IDMAC_LD;
			cnt = data->blocksize * blk_cnt;
		} else
			cnt = data->blocksize * 8;

		dwmci_set_idma_desc(cur_idmac, flags, cnt,
				    (ulong)bounce_buffer + (i * PAGE_SIZE));

		if (blk_cnt <= 8)
			break;
		blk_cnt -= 8;
		cur_idmac++;
		i++;
	} while(1);

	data_end = (ulong)cur_idmac;
	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);

	ctrl = dwmci_readl(host, DWMCI_CTRL);
	ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
	dwmci_writel(host, DWMCI_CTRL, ctrl);

	ctrl = dwmci_readl(host, DWMCI_BMOD);
	ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
	dwmci_writel(host, DWMCI_BMOD, ctrl);

	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
}

static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
{
	int ret = 0;
	u32 timeout = 240000;
	u32 mask, size, i, len = 0;
	u32 *buf = NULL;
	ulong start = get_timer(0);
	u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
			    RX_WMARK_SHIFT) + 1) * 2;

	size = data->blocksize * data->blocks / 4;
	if (data->flags == MMC_DATA_READ)
		buf = (unsigned int *)data->dest;
	else
		buf = (unsigned int *)data->src;

	for (;;) {
		mask = dwmci_readl(host, DWMCI_RINTSTS);
		/* Error during data transfer. */
		if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
			debug("%s: DATA ERROR!\n", __func__);
			ret = -EINVAL;
			break;
		}

		if (host->fifo_mode && size) {
			if (data->flags == MMC_DATA_READ) {
				if ((dwmci_readl(host, DWMCI_RINTSTS) &
				     DWMCI_INTMSK_RXDR)) {
					len = dwmci_readl(host, DWMCI_STATUS);
					len = (len >> DWMCI_FIFO_SHIFT) &
						    DWMCI_FIFO_MASK;
					for (i = 0; i < len; i++)
						*buf++ =
						dwmci_readl(host, DWMCI_DATA);
					dwmci_writel(host, DWMCI_RINTSTS,
						     DWMCI_INTMSK_RXDR);
				}
			} else {
				if ((dwmci_readl(host, DWMCI_RINTSTS) &
				     DWMCI_INTMSK_TXDR)) {
					len = dwmci_readl(host, DWMCI_STATUS);
					len = fifo_depth - ((len >>
						   DWMCI_FIFO_SHIFT) &
						   DWMCI_FIFO_MASK);
					for (i = 0; i < len; i++)
						dwmci_writel(host, DWMCI_DATA,
							     *buf++);
					dwmci_writel(host, DWMCI_RINTSTS,
						     DWMCI_INTMSK_TXDR);
				}
			}
			size = size > len ? (size - len) : 0;
		}

		/* Data arrived correctly. */
		if (mask & DWMCI_INTMSK_DTO) {
			ret = 0;
			break;
		}

		/* Check for timeout. */
		if (get_timer(start) > timeout) {
			debug("%s: Timeout waiting for data!\n",
			      __func__);
			ret = TIMEOUT;
			break;
		}
	}

	dwmci_writel(host, DWMCI_RINTSTS, mask);

	return ret;
}

static int dwmci_set_transfer_mode(struct dwmci_host *host,
		struct mmc_data *data)
{
	unsigned long mode;

	mode = DWMCI_CMD_DATA_EXP;
	if (data->flags & MMC_DATA_WRITE)
		mode |= DWMCI_CMD_RW;

	return mode;
}

#ifdef CONFIG_DM_MMC_OPS
static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
		   struct mmc_data *data)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
		struct mmc_data *data)
{
#endif
	struct dwmci_host *host = mmc->priv;
	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
				 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
	int ret = 0, flags = 0, i;
	unsigned int timeout = 500;
	u32 retry = 100000;
	u32 mask, ctrl;
	ulong start = get_timer(0);
	struct bounce_buffer bbstate;

	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
		if (get_timer(start) > timeout) {
			debug("%s: Timeout on data busy\n", __func__);
			return TIMEOUT;
		}
	}

	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);

	if (data) {
		if (host->fifo_mode) {
			dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
			dwmci_writel(host, DWMCI_BYTCNT,
				     data->blocksize * data->blocks);
			dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
		} else {
			if (data->flags == MMC_DATA_READ) {
				bounce_buffer_start(&bbstate, (void*)data->dest,
						data->blocksize *
						data->blocks, GEN_BB_WRITE);
			} else {
				bounce_buffer_start(&bbstate, (void*)data->src,
						data->blocksize *
						data->blocks, GEN_BB_READ);
			}
			dwmci_prepare_data(host, data, cur_idmac,
					   bbstate.bounce_buffer);
		}
	}

	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);

	if (data)
		flags = dwmci_set_transfer_mode(host, data);

	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
		return -1;

	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		flags |= DWMCI_CMD_ABORT_STOP;
	else
		flags |= DWMCI_CMD_PRV_DAT_WAIT;

	if (cmd->resp_type & MMC_RSP_PRESENT) {
		flags |= DWMCI_CMD_RESP_EXP;
		if (cmd->resp_type & MMC_RSP_136)
			flags |= DWMCI_CMD_RESP_LENGTH;
	}

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= DWMCI_CMD_CHECK_CRC;

	flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);

	debug("Sending CMD%d\n",cmd->cmdidx);

	dwmci_writel(host, DWMCI_CMD, flags);

	for (i = 0; i < retry; i++) {
		mask = dwmci_readl(host, DWMCI_RINTSTS);
		if (mask & DWMCI_INTMSK_CDONE) {
			if (!data)
				dwmci_writel(host, DWMCI_RINTSTS, mask);
			break;
		}
	}

	if (i == retry) {
		debug("%s: Timeout.\n", __func__);
		return TIMEOUT;
	}

	if (mask & DWMCI_INTMSK_RTO) {
		/*
		 * Timeout here is not necessarily fatal. (e)MMC cards
		 * will splat here when they receive CMD55 as they do
		 * not support this command and that is exactly the way
		 * to tell them apart from SD cards. Thus, this output
		 * below shall be debug(). eMMC cards also do not favor
		 * CMD8, please keep that in mind.
		 */
		debug("%s: Response Timeout.\n", __func__);
		return TIMEOUT;
	} else if (mask & DWMCI_INTMSK_RE) {
		debug("%s: Response Error.\n", __func__);
		return -EIO;
	}


	if (cmd->resp_type & MMC_RSP_PRESENT) {
		if (cmd->resp_type & MMC_RSP_136) {
			cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
			cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
			cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
			cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
		} else {
			cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
		}
	}

	if (data) {
		ret = dwmci_data_transfer(host, data);

		/* only dma mode need it */
		if (!host->fifo_mode) {
			ctrl = dwmci_readl(host, DWMCI_CTRL);
			ctrl &= ~(DWMCI_DMA_EN);
			dwmci_writel(host, DWMCI_CTRL, ctrl);
			bounce_buffer_stop(&bbstate);
		}
	}

	udelay(100);

	return ret;
}

static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
{
	u32 div, status;
	int timeout = 10000;
	unsigned long sclk;

	if ((freq == host->clock) || (freq == 0))
		return 0;
	/*
	 * If host->get_mmc_clk isn't defined,
	 * then assume that host->bus_hz is source clock value.
	 * host->bus_hz should be set by user.
	 */
	if (host->get_mmc_clk)
		sclk = host->get_mmc_clk(host, freq);
	else if (host->bus_hz)
		sclk = host->bus_hz;
	else {
		debug("%s: Didn't get source clock value.\n", __func__);
		return -EINVAL;
	}

	if (sclk == freq)
		div = 0;	/* bypass mode */
	else
		div = DIV_ROUND_UP(sclk, 2 * freq);

	dwmci_writel(host, DWMCI_CLKENA, 0);
	dwmci_writel(host, DWMCI_CLKSRC, 0);

	dwmci_writel(host, DWMCI_CLKDIV, div);
	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);

	do {
		status = dwmci_readl(host, DWMCI_CMD);
		if (timeout-- < 0) {
			debug("%s: Timeout!\n", __func__);
			return -ETIMEDOUT;
		}
	} while (status & DWMCI_CMD_START);

	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
			DWMCI_CLKEN_LOW_PWR);

	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);

	timeout = 10000;
	do {
		status = dwmci_readl(host, DWMCI_CMD);
		if (timeout-- < 0) {
			debug("%s: Timeout!\n", __func__);
			return -ETIMEDOUT;
		}
	} while (status & DWMCI_CMD_START);

	host->clock = freq;

	return 0;
}

#ifdef CONFIG_DM_MMC_OPS
static int dwmci_set_ios(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
static void dwmci_set_ios(struct mmc *mmc)
{
#endif
	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
	u32 ctype, regs;

	debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);

	dwmci_setup_bus(host, mmc->clock);
	switch (mmc->bus_width) {
	case 8:
		ctype = DWMCI_CTYPE_8BIT;
		break;
	case 4:
		ctype = DWMCI_CTYPE_4BIT;
		break;
	default:
		ctype = DWMCI_CTYPE_1BIT;
		break;
	}

	dwmci_writel(host, DWMCI_CTYPE, ctype);

	regs = dwmci_readl(host, DWMCI_UHS_REG);
	if (mmc->ddr_mode)
		regs |= DWMCI_DDR_MODE;
	else
		regs &= ~DWMCI_DDR_MODE;

	dwmci_writel(host, DWMCI_UHS_REG, regs);

	if (host->clksel)
		host->clksel(host);
#ifdef CONFIG_DM_MMC_OPS
	return 0;
#endif
}

static int dwmci_init(struct mmc *mmc)
{
	struct dwmci_host *host = mmc->priv;

	if (host->board_init)
		host->board_init(host);

	dwmci_writel(host, DWMCI_PWREN, 1);

	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
		debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
		return -EIO;
	}

	/* Enumerate at 400KHz */
	dwmci_setup_bus(host, mmc->cfg->f_min);

	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
	dwmci_writel(host, DWMCI_INTMASK, 0);

	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);

	dwmci_writel(host, DWMCI_IDINTEN, 0);
	dwmci_writel(host, DWMCI_BMOD, 1);

	if (!host->fifoth_val) {
		uint32_t fifo_size;

		fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
		fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
		host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
				TX_WMARK(fifo_size / 2);
	}
	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);

	dwmci_writel(host, DWMCI_CLKENA, 0);
	dwmci_writel(host, DWMCI_CLKSRC, 0);

	return 0;
}

#ifdef CONFIG_DM_MMC_OPS
int dwmci_probe(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);

	return dwmci_init(mmc);
}

const struct dm_mmc_ops dm_dwmci_ops = {
	.send_cmd	= dwmci_send_cmd,
	.set_ios	= dwmci_set_ios,
};

#else
static const struct mmc_ops dwmci_ops = {
	.send_cmd	= dwmci_send_cmd,
	.set_ios	= dwmci_set_ios,
	.init		= dwmci_init,
};
#endif

void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
		     uint caps, u32 max_clk, u32 min_clk)
{
	cfg->name = name;
#ifndef CONFIG_DM_MMC_OPS
	cfg->ops = &dwmci_ops;
#endif
	cfg->f_min = min_clk;
	cfg->f_max = max_clk;

	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;

	cfg->host_caps = caps;

	if (buswidth == 8) {
		cfg->host_caps |= MMC_MODE_8BIT;
		cfg->host_caps &= ~MMC_MODE_4BIT;
	} else {
		cfg->host_caps |= MMC_MODE_4BIT;
		cfg->host_caps &= ~MMC_MODE_8BIT;
	}
	cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;

	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
}

#ifdef CONFIG_BLK
int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
{
	return mmc_bind(dev, mmc, cfg);
}
#else
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
{
	dwmci_setup_cfg(&host->cfg, host->name, host->buswidth, host->caps,
			max_clk, min_clk);

	host->mmc = mmc_create(&host->cfg, host);
	if (host->mmc == NULL)
		return -1;

	return 0;
}
#endif
Commit	Line	Data
757bff49 JC	1	/*
	2	* (C) Copyright 2012 SAMSUNG Electronics
	3	* Jaehoon Chung <jh80.chung@samsung.com>
	4	* Rajeshawari Shinde <rajeshwari.s@samsung.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
757bff49 JC	7	*/
757bff49 JC	8
2a7a210e	9	#include <bouncebuf.h>
757bff49	10	#include <common.h>
1c87ffe8	11	#include <errno.h>
757bff49	12	#include <malloc.h>
cf92e05c	13	#include <memalign.h>
757bff49 JC	14	#include <mmc.h>
757bff49 JC	15	#include <dwmmc.h>
757bff49 JC	16
	17	#define PAGE_SIZE 4096
	18
	19	static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
	20	{
	21	unsigned long timeout = 1000;
	22	u32 ctrl;
	23
	24	dwmci_writel(host, DWMCI_CTRL, value);
	25
	26	while (timeout--) {
	27	ctrl = dwmci_readl(host, DWMCI_CTRL);
	28	if (!(ctrl & DWMCI_RESET_ALL))
	29	return 1;
	30	}
	31	return 0;
	32	}
	33
	34	static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
	35	u32 desc0, u32 desc1, u32 desc2)
	36	{
	37	struct dwmci_idmac *desc = idmac;
	38
	39	desc->flags = desc0;
	40	desc->cnt = desc1;
	41	desc->addr = desc2;
41f7be3c	42	desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
757bff49 JC	43	}
	44
	45	static void dwmci_prepare_data(struct dwmci_host *host,
2a7a210e AB	46	struct mmc_data *data,
	47	struct dwmci_idmac *cur_idmac,
	48	void *bounce_buffer)
757bff49 JC	49	{
	50	unsigned long ctrl;
	51	unsigned int i = 0, flags, cnt, blk_cnt;
2a7a210e	52	ulong data_start, data_end;
757bff49 JC	53
	54
	55	blk_cnt = data->blocks;
	56
	57	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
	58
	59	data_start = (ulong)cur_idmac;
41f7be3c	60	dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
757bff49	61
757bff49 JC	62	do {
	63	flags = DWMCI_IDMAC_OWN \| DWMCI_IDMAC_CH ;
	64	flags \|= (i == 0) ? DWMCI_IDMAC_FS : 0;
	65	if (blk_cnt <= 8) {
	66	flags \|= DWMCI_IDMAC_LD;
	67	cnt = data->blocksize * blk_cnt;
	68	} else
	69	cnt = data->blocksize * 8;
	70
	71	dwmci_set_idma_desc(cur_idmac, flags, cnt,
41f7be3c	72	(ulong)bounce_buffer + (i * PAGE_SIZE));
757bff49	73
21bd5761	74	if (blk_cnt <= 8)
757bff49 JC	75	break;
	76	blk_cnt -= 8;
	77	cur_idmac++;
	78	i++;
	79	} while(1);
	80
	81	data_end = (ulong)cur_idmac;
	82	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
	83
	84	ctrl = dwmci_readl(host, DWMCI_CTRL);
	85	ctrl \|= DWMCI_IDMAC_EN \| DWMCI_DMA_EN;
	86	dwmci_writel(host, DWMCI_CTRL, ctrl);
	87
	88	ctrl = dwmci_readl(host, DWMCI_BMOD);
	89	ctrl \|= DWMCI_BMOD_IDMAC_FB \| DWMCI_BMOD_IDMAC_EN;
	90	dwmci_writel(host, DWMCI_BMOD, ctrl);
	91
	92	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	93	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
	94	}
	95
a65f51b9	96	static int dwmci_data_transfer(struct dwmci_host host, struct mmc_data data)
f382eb83	97	{
f382eb83	98	int ret = 0;
a65f51b9	99	u32 timeout = 240000;
	100	u32 mask, size, i, len = 0;
	101	u32 *buf = NULL;
f382eb83	102	ulong start = get_timer(0);
a65f51b9	103	u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
	104	RX_WMARK_SHIFT) + 1) * 2;
	105
	106	size = data->blocksize * data->blocks / 4;
	107	if (data->flags == MMC_DATA_READ)
	108	buf = (unsigned int *)data->dest;
	109	else
	110	buf = (unsigned int *)data->src;
f382eb83	111
	112	for (;;) {
	113	mask = dwmci_readl(host, DWMCI_RINTSTS);
	114	/* Error during data transfer. */
	115	if (mask & (DWMCI_DATA_ERR \| DWMCI_DATA_TOUT)) {
	116	debug("%s: DATA ERROR!\n", __func__);
	117	ret = -EINVAL;
	118	break;
	119	}
	120
a65f51b9	121	if (host->fifo_mode && size) {
a65f51b9	122	if (data->flags == MMC_DATA_READ) {
ca2ec9ad	123	if ((dwmci_readl(host, DWMCI_RINTSTS) &
a65f51b9	124	DWMCI_INTMSK_RXDR)) {
	125	len = dwmci_readl(host, DWMCI_STATUS);
	126	len = (len >> DWMCI_FIFO_SHIFT) &
	127	DWMCI_FIFO_MASK;
	128	for (i = 0; i < len; i++)
	129	*buf++ =
	130	dwmci_readl(host, DWMCI_DATA);
	131	dwmci_writel(host, DWMCI_RINTSTS,
	132	DWMCI_INTMSK_RXDR);
	133	}
	134	} else {
ca2ec9ad	135	if ((dwmci_readl(host, DWMCI_RINTSTS) &
a65f51b9	136	DWMCI_INTMSK_TXDR)) {
	137	len = dwmci_readl(host, DWMCI_STATUS);
	138	len = fifo_depth - ((len >>
	139	DWMCI_FIFO_SHIFT) &
	140	DWMCI_FIFO_MASK);
	141	for (i = 0; i < len; i++)
	142	dwmci_writel(host, DWMCI_DATA,
	143	*buf++);
	144	dwmci_writel(host, DWMCI_RINTSTS,
	145	DWMCI_INTMSK_TXDR);
	146	}
	147	}
	148	size = size > len ? (size - len) : 0;
	149	}
	150
f382eb83	151	/* Data arrived correctly. */
	152	if (mask & DWMCI_INTMSK_DTO) {
	153	ret = 0;
	154	break;
	155	}
	156
	157	/* Check for timeout. */
	158	if (get_timer(start) > timeout) {
	159	debug("%s: Timeout waiting for data!\n",
	160	__func__);
	161	ret = TIMEOUT;
	162	break;
	163	}
	164	}
	165
	166	dwmci_writel(host, DWMCI_RINTSTS, mask);
	167
	168	return ret;
	169	}
	170
757bff49 JC	171	static int dwmci_set_transfer_mode(struct dwmci_host *host,
	172	struct mmc_data *data)
	173	{
	174	unsigned long mode;
	175
	176	mode = DWMCI_CMD_DATA_EXP;
	177	if (data->flags & MMC_DATA_WRITE)
	178	mode \|= DWMCI_CMD_RW;
	179
	180	return mode;
	181	}
	182
691272fe	183	#ifdef CONFIG_DM_MMC_OPS
5628347f	184	static int dwmci_send_cmd(struct udevice dev, struct mmc_cmd cmd,
691272fe SG	185	struct mmc_data *data)
	186	{
	187	struct mmc *mmc = mmc_get_mmc_dev(dev);
	188	#else
757bff49 JC	189	static int dwmci_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
	190	struct mmc_data *data)
	191	{
691272fe	192	#endif
93bfd616	193	struct dwmci_host *host = mmc->priv;
2136d226	194	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
21bd5761	195	data ? DIV_ROUND_UP(data->blocks, 8) : 0);
9042d974	196	int ret = 0, flags = 0, i;
02ebd42c	197	unsigned int timeout = 500;
9b5b8b6e	198	u32 retry = 100000;
757bff49	199	u32 mask, ctrl;
9c50e35f	200	ulong start = get_timer(0);
2a7a210e	201	struct bounce_buffer bbstate;
757bff49 JC	202
757bff49 JC	203	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
9c50e35f	204	if (get_timer(start) > timeout) {
1c87ffe8	205	debug("%s: Timeout on data busy\n", __func__);
757bff49 JC	206	return TIMEOUT;
757bff49 JC	207	}
757bff49 JC	208	}
	209
	210	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
	211
2a7a210e	212	if (data) {
a65f51b9	213	if (host->fifo_mode) {
	214	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	215	dwmci_writel(host, DWMCI_BYTCNT,
	216	data->blocksize * data->blocks);
	217	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
2a7a210e	218	} else {
a65f51b9	219	if (data->flags == MMC_DATA_READ) {
	220	bounce_buffer_start(&bbstate, (void*)data->dest,
	221	data->blocksize *
	222	data->blocks, GEN_BB_WRITE);
	223	} else {
	224	bounce_buffer_start(&bbstate, (void*)data->src,
	225	data->blocksize *
	226	data->blocks, GEN_BB_READ);
	227	}
	228	dwmci_prepare_data(host, data, cur_idmac,
	229	bbstate.bounce_buffer);
2a7a210e	230	}
2a7a210e	231	}
757bff49	232
757bff49 JC	233	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
	234
	235	if (data)
	236	flags = dwmci_set_transfer_mode(host, data);
	237
	238	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
	239	return -1;
	240
	241	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	242	flags \|= DWMCI_CMD_ABORT_STOP;
	243	else
	244	flags \|= DWMCI_CMD_PRV_DAT_WAIT;
	245
	246	if (cmd->resp_type & MMC_RSP_PRESENT) {
	247	flags \|= DWMCI_CMD_RESP_EXP;
	248	if (cmd->resp_type & MMC_RSP_136)
	249	flags \|= DWMCI_CMD_RESP_LENGTH;
	250	}
	251
	252	if (cmd->resp_type & MMC_RSP_CRC)
	253	flags \|= DWMCI_CMD_CHECK_CRC;
	254
	255	flags \|= (cmd->cmdidx \| DWMCI_CMD_START \| DWMCI_CMD_USE_HOLD_REG);
	256
	257	debug("Sending CMD%d\n",cmd->cmdidx);
	258
	259	dwmci_writel(host, DWMCI_CMD, flags);
	260
	261	for (i = 0; i < retry; i++) {
	262	mask = dwmci_readl(host, DWMCI_RINTSTS);
	263	if (mask & DWMCI_INTMSK_CDONE) {
	264	if (!data)
	265	dwmci_writel(host, DWMCI_RINTSTS, mask);
	266	break;
	267	}
	268	}
	269
f33c9305	270	if (i == retry) {
1c87ffe8	271	debug("%s: Timeout.\n", __func__);
757bff49	272	return TIMEOUT;
f33c9305	273	}
757bff49 JC	274
757bff49 JC	275	if (mask & DWMCI_INTMSK_RTO) {
f33c9305 PM	276	/*
	277	* Timeout here is not necessarily fatal. (e)MMC cards
	278	* will splat here when they receive CMD55 as they do
	279	* not support this command and that is exactly the way
	280	* to tell them apart from SD cards. Thus, this output
	281	* below shall be debug(). eMMC cards also do not favor
	282	* CMD8, please keep that in mind.
	283	*/
	284	debug("%s: Response Timeout.\n", __func__);
757bff49 JC	285	return TIMEOUT;
757bff49 JC	286	} else if (mask & DWMCI_INTMSK_RE) {
1c87ffe8 SG	287	debug("%s: Response Error.\n", __func__);
1c87ffe8 SG	288	return -EIO;
757bff49 JC	289	}
	290
	291
	292	if (cmd->resp_type & MMC_RSP_PRESENT) {
	293	if (cmd->resp_type & MMC_RSP_136) {
	294	cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
	295	cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
	296	cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
	297	cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
	298	} else {
	299	cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
	300	}
	301	}
	302
	303	if (data) {
a65f51b9	304	ret = dwmci_data_transfer(host, data);
	305
	306	/* only dma mode need it */
	307	if (!host->fifo_mode) {
	308	ctrl = dwmci_readl(host, DWMCI_CTRL);
	309	ctrl &= ~(DWMCI_DMA_EN);
	310	dwmci_writel(host, DWMCI_CTRL, ctrl);
	311	bounce_buffer_stop(&bbstate);
	312	}
757bff49 JC	313	}
	314
	315	udelay(100);
	316
9042d974	317	return ret;
757bff49 JC	318	}
	319
	320	static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
	321	{
	322	u32 div, status;
	323	int timeout = 10000;
	324	unsigned long sclk;
	325
9c50e35f	326	if ((freq == host->clock) \|\| (freq == 0))
757bff49	327	return 0;
757bff49	328	/*
f33c9305	329	* If host->get_mmc_clk isn't defined,
757bff49	330	* then assume that host->bus_hz is source clock value.
f33c9305	331	* host->bus_hz should be set by user.
757bff49	332	*/
b44fe83a	333	if (host->get_mmc_clk)
e3563f2e	334	sclk = host->get_mmc_clk(host, freq);
757bff49 JC	335	else if (host->bus_hz)
	336	sclk = host->bus_hz;
	337	else {
1c87ffe8	338	debug("%s: Didn't get source clock value.\n", __func__);
757bff49 JC	339	return -EINVAL;
	340	}
	341
6ace153d CLS	342	if (sclk == freq)
	343	div = 0; /* bypass mode */
	344	else
	345	div = DIV_ROUND_UP(sclk, 2 * freq);
757bff49 JC	346
	347	dwmci_writel(host, DWMCI_CLKENA, 0);
	348	dwmci_writel(host, DWMCI_CLKSRC, 0);
	349
	350	dwmci_writel(host, DWMCI_CLKDIV, div);
	351	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
	352	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
	353
	354	do {
	355	status = dwmci_readl(host, DWMCI_CMD);
	356	if (timeout-- < 0) {
1c87ffe8	357	debug("%s: Timeout!\n", __func__);
757bff49 JC	358	return -ETIMEDOUT;
	359	}
	360	} while (status & DWMCI_CMD_START);
	361
	362	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE \|
	363	DWMCI_CLKEN_LOW_PWR);
	364
	365	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
	366	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
	367
	368	timeout = 10000;
	369	do {
	370	status = dwmci_readl(host, DWMCI_CMD);
	371	if (timeout-- < 0) {
1c87ffe8	372	debug("%s: Timeout!\n", __func__);
757bff49 JC	373	return -ETIMEDOUT;
	374	}
	375	} while (status & DWMCI_CMD_START);
	376
	377	host->clock = freq;
	378
	379	return 0;
	380	}
	381
691272fe	382	#ifdef CONFIG_DM_MMC_OPS
5628347f	383	static int dwmci_set_ios(struct udevice *dev)
691272fe SG	384	{
	385	struct mmc *mmc = mmc_get_mmc_dev(dev);
	386	#else
757bff49 JC	387	static void dwmci_set_ios(struct mmc *mmc)
757bff49 JC	388	{
691272fe	389	#endif
045bdcd0 JC	390	struct dwmci_host host = (struct dwmci_host )mmc->priv;
045bdcd0 JC	391	u32 ctype, regs;
757bff49	392
f33c9305	393	debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
757bff49 JC	394
	395	dwmci_setup_bus(host, mmc->clock);
	396	switch (mmc->bus_width) {
	397	case 8:
	398	ctype = DWMCI_CTYPE_8BIT;
	399	break;
	400	case 4:
	401	ctype = DWMCI_CTYPE_4BIT;
	402	break;
	403	default:
	404	ctype = DWMCI_CTYPE_1BIT;
	405	break;
	406	}
	407
	408	dwmci_writel(host, DWMCI_CTYPE, ctype);
	409
045bdcd0	410	regs = dwmci_readl(host, DWMCI_UHS_REG);
2b8a9692	411	if (mmc->ddr_mode)
045bdcd0 JC	412	regs \|= DWMCI_DDR_MODE;
045bdcd0 JC	413	else
afc9e2b5	414	regs &= ~DWMCI_DDR_MODE;
045bdcd0 JC	415
	416	dwmci_writel(host, DWMCI_UHS_REG, regs);
	417
757bff49 JC	418	if (host->clksel)
757bff49 JC	419	host->clksel(host);
691272fe SG	420	#ifdef CONFIG_DM_MMC_OPS
	421	return 0;
	422	#endif
757bff49 JC	423	}
	424
	425	static int dwmci_init(struct mmc *mmc)
	426	{
93bfd616	427	struct dwmci_host *host = mmc->priv;
757bff49	428
18ab6755 JC	429	if (host->board_init)
18ab6755 JC	430	host->board_init(host);
6f0b7caa	431
757bff49 JC	432	dwmci_writel(host, DWMCI_PWREN, 1);
	433
	434	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
1c87ffe8 SG	435	debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
1c87ffe8 SG	436	return -EIO;
757bff49 JC	437	}
757bff49 JC	438
9c50e35f	439	/* Enumerate at 400KHz */
93bfd616	440	dwmci_setup_bus(host, mmc->cfg->f_min);
9c50e35f	441
757bff49 JC	442	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
	443	dwmci_writel(host, DWMCI_INTMASK, 0);
	444
	445	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
	446
	447	dwmci_writel(host, DWMCI_IDINTEN, 0);
	448	dwmci_writel(host, DWMCI_BMOD, 1);
	449
760177df SG	450	if (!host->fifoth_val) {
	451	uint32_t fifo_size;
	452
	453	fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
	454	fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
	455	host->fifoth_val = MSIZE(0x2) \| RX_WMARK(fifo_size / 2 - 1) \|
	456	TX_WMARK(fifo_size / 2);
9c50e35f	457	}
760177df	458	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
757bff49 JC	459
	460	dwmci_writel(host, DWMCI_CLKENA, 0);
	461	dwmci_writel(host, DWMCI_CLKSRC, 0);
	462
	463	return 0;
	464	}
	465
691272fe SG	466	#ifdef CONFIG_DM_MMC_OPS
	467	int dwmci_probe(struct udevice *dev)
	468	{
	469	struct mmc *mmc = mmc_get_mmc_dev(dev);
	470
	471	return dwmci_init(mmc);
	472	}
	473
	474	const struct dm_mmc_ops dm_dwmci_ops = {
	475	.send_cmd = dwmci_send_cmd,
	476	.set_ios = dwmci_set_ios,
	477	};
	478
	479	#else
ab769f22 PA	480	static const struct mmc_ops dwmci_ops = {
	481	.send_cmd = dwmci_send_cmd,
	482	.set_ios = dwmci_set_ios,
	483	.init = dwmci_init,
	484	};
691272fe	485	#endif
ab769f22	486
5e6ff810 SG	487	void dwmci_setup_cfg(struct mmc_config cfg, const char name, int buswidth,
5e6ff810 SG	488	uint caps, u32 max_clk, u32 min_clk)
757bff49	489	{
5e6ff810	490	cfg->name = name;
691272fe	491	#ifndef CONFIG_DM_MMC_OPS
5e6ff810	492	cfg->ops = &dwmci_ops;
691272fe	493	#endif
5e6ff810 SG	494	cfg->f_min = min_clk;
5e6ff810 SG	495	cfg->f_max = max_clk;
757bff49	496
5e6ff810	497	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
757bff49	498
5e6ff810	499	cfg->host_caps = caps;
757bff49	500
5e6ff810 SG	501	if (buswidth == 8) {
	502	cfg->host_caps \|= MMC_MODE_8BIT;
	503	cfg->host_caps &= ~MMC_MODE_4BIT;
757bff49	504	} else {
5e6ff810 SG	505	cfg->host_caps \|= MMC_MODE_4BIT;
5e6ff810 SG	506	cfg->host_caps &= ~MMC_MODE_8BIT;
757bff49	507	}
5e6ff810 SG	508	cfg->host_caps \|= MMC_MODE_HS \| MMC_MODE_HS_52MHz;
	509
	510	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
	511	}
93bfd616	512
5e6ff810 SG	513	#ifdef CONFIG_BLK
	514	int dwmci_bind(struct udevice dev, struct mmc mmc, struct mmc_config *cfg)
	515	{
	516	return mmc_bind(dev, mmc, cfg);
	517	}
	518	#else
	519	int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
	520	{
	521	dwmci_setup_cfg(&host->cfg, host->name, host->buswidth, host->caps,
	522	max_clk, min_clk);
757bff49	523
93bfd616 PA	524	host->mmc = mmc_create(&host->cfg, host);
	525	if (host->mmc == NULL)
	526	return -1;
757bff49	527
93bfd616	528	return 0;
757bff49	529	}
5e6ff810	530	#endif