[thirdparty/u-boot.git] / drivers / mmc / dw_mmc.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Jaehoon Chung <jh80.chung@samsung.com>
 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
 */

#include <bouncebuf.h>
#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <memalign.h>
#include <mmc.h>
#include <dwmmc.h>

#define PAGE_SIZE 4096

static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
{
	unsigned long timeout = 1000;
	u32 ctrl;

	dwmci_writel(host, DWMCI_CTRL, value);

	while (timeout--) {
		ctrl = dwmci_readl(host, DWMCI_CTRL);
		if (!(ctrl & DWMCI_RESET_ALL))
			return 1;
	}
	return 0;
}

static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
		u32 desc0, u32 desc1, u32 desc2)
{
	struct dwmci_idmac *desc = idmac;

	desc->flags = desc0;
	desc->cnt = desc1;
	desc->addr = desc2;
	desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
}

static void dwmci_prepare_data(struct dwmci_host *host,
			       struct mmc_data *data,
			       struct dwmci_idmac *cur_idmac,
			       void *bounce_buffer)
{
	unsigned long ctrl;
	unsigned int i = 0, flags, cnt, blk_cnt;
	ulong data_start, data_end;


	blk_cnt = data->blocks;

	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);

	data_start = (ulong)cur_idmac;
	dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);

	do {
		flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
		flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
		if (blk_cnt <= 8) {
			flags |= DWMCI_IDMAC_LD;
			cnt = data->blocksize * blk_cnt;
		} else
			cnt = data->blocksize * 8;

		dwmci_set_idma_desc(cur_idmac, flags, cnt,
				    (ulong)bounce_buffer + (i * PAGE_SIZE));

		if (blk_cnt <= 8)
			break;
		blk_cnt -= 8;
		cur_idmac++;
		i++;
	} while(1);

	data_end = (ulong)cur_idmac;
	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);

	ctrl = dwmci_readl(host, DWMCI_CTRL);
	ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
	dwmci_writel(host, DWMCI_CTRL, ctrl);

	ctrl = dwmci_readl(host, DWMCI_BMOD);
	ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
	dwmci_writel(host, DWMCI_BMOD, ctrl);

	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
}

static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
{
	int ret = 0;
	u32 timeout = 240000;
	u32 mask, size, i, len = 0;
	u32 *buf = NULL;
	ulong start = get_timer(0);
	u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
			    RX_WMARK_SHIFT) + 1) * 2;

	size = data->blocksize * data->blocks / 4;
	if (data->flags == MMC_DATA_READ)
		buf = (unsigned int *)data->dest;
	else
		buf = (unsigned int *)data->src;

	for (;;) {
		mask = dwmci_readl(host, DWMCI_RINTSTS);
		/* Error during data transfer. */
		if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
			debug("%s: DATA ERROR!\n", __func__);
			ret = -EINVAL;
			break;
		}

		if (host->fifo_mode && size) {
			len = 0;
			if (data->flags == MMC_DATA_READ &&
			    (mask & DWMCI_INTMSK_RXDR)) {
				while (size) {
					len = dwmci_readl(host, DWMCI_STATUS);
					len = (len >> DWMCI_FIFO_SHIFT) &
						    DWMCI_FIFO_MASK;
					len = min(size, len);
					for (i = 0; i < len; i++)
						*buf++ =
						dwmci_readl(host, DWMCI_DATA);
					size = size > len ? (size - len) : 0;
				}
				dwmci_writel(host, DWMCI_RINTSTS,
					     DWMCI_INTMSK_RXDR);
			} else if (data->flags == MMC_DATA_WRITE &&
				   (mask & DWMCI_INTMSK_TXDR)) {
				while (size) {
					len = dwmci_readl(host, DWMCI_STATUS);
					len = fifo_depth - ((len >>
						   DWMCI_FIFO_SHIFT) &
						   DWMCI_FIFO_MASK);
					len = min(size, len);
					for (i = 0; i < len; i++)
						dwmci_writel(host, DWMCI_DATA,
							     *buf++);
					size = size > len ? (size - len) : 0;
				}
				dwmci_writel(host, DWMCI_RINTSTS,
					     DWMCI_INTMSK_TXDR);
			}
		}

		/* Data arrived correctly. */
		if (mask & DWMCI_INTMSK_DTO) {
			ret = 0;
			break;
		}

		/* Check for timeout. */
		if (get_timer(start) > timeout) {
			debug("%s: Timeout waiting for data!\n",
			      __func__);
			ret = -ETIMEDOUT;
			break;
		}
	}

	dwmci_writel(host, DWMCI_RINTSTS, mask);

	return ret;
}

static int dwmci_set_transfer_mode(struct dwmci_host *host,
		struct mmc_data *data)
{
	unsigned long mode;

	mode = DWMCI_CMD_DATA_EXP;
	if (data->flags & MMC_DATA_WRITE)
		mode |= DWMCI_CMD_RW;

	return mode;
}

#ifdef CONFIG_DM_MMC
static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
		   struct mmc_data *data)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
		struct mmc_data *data)
{
#endif
	struct dwmci_host *host = mmc->priv;
	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
				 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
	int ret = 0, flags = 0, i;
	unsigned int timeout = 500;
	u32 retry = 100000;
	u32 mask, ctrl;
	ulong start = get_timer(0);
	struct bounce_buffer bbstate;

	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
		if (get_timer(start) > timeout) {
			debug("%s: Timeout on data busy\n", __func__);
			return -ETIMEDOUT;
		}
	}

	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);

	if (data) {
		if (host->fifo_mode) {
			dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
			dwmci_writel(host, DWMCI_BYTCNT,
				     data->blocksize * data->blocks);
			dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
		} else {
			if (data->flags == MMC_DATA_READ) {
				bounce_buffer_start(&bbstate, (void*)data->dest,
						data->blocksize *
						data->blocks, GEN_BB_WRITE);
			} else {
				bounce_buffer_start(&bbstate, (void*)data->src,
						data->blocksize *
						data->blocks, GEN_BB_READ);
			}
			dwmci_prepare_data(host, data, cur_idmac,
					   bbstate.bounce_buffer);
		}
	}

	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);

	if (data)
		flags = dwmci_set_transfer_mode(host, data);

	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
		return -1;

	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		flags |= DWMCI_CMD_ABORT_STOP;
	else
		flags |= DWMCI_CMD_PRV_DAT_WAIT;

	if (cmd->resp_type & MMC_RSP_PRESENT) {
		flags |= DWMCI_CMD_RESP_EXP;
		if (cmd->resp_type & MMC_RSP_136)
			flags |= DWMCI_CMD_RESP_LENGTH;
	}

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= DWMCI_CMD_CHECK_CRC;

	flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);

	debug("Sending CMD%d\n",cmd->cmdidx);

	dwmci_writel(host, DWMCI_CMD, flags);

	for (i = 0; i < retry; i++) {
		mask = dwmci_readl(host, DWMCI_RINTSTS);
		if (mask & DWMCI_INTMSK_CDONE) {
			if (!data)
				dwmci_writel(host, DWMCI_RINTSTS, mask);
			break;
		}
	}

	if (i == retry) {
		debug("%s: Timeout.\n", __func__);
		return -ETIMEDOUT;
	}

	if (mask & DWMCI_INTMSK_RTO) {
		/*
		 * Timeout here is not necessarily fatal. (e)MMC cards
		 * will splat here when they receive CMD55 as they do
		 * not support this command and that is exactly the way
		 * to tell them apart from SD cards. Thus, this output
		 * below shall be debug(). eMMC cards also do not favor
		 * CMD8, please keep that in mind.
		 */
		debug("%s: Response Timeout.\n", __func__);
		return -ETIMEDOUT;
	} else if (mask & DWMCI_INTMSK_RE) {
		debug("%s: Response Error.\n", __func__);
		return -EIO;
	}


	if (cmd->resp_type & MMC_RSP_PRESENT) {
		if (cmd->resp_type & MMC_RSP_136) {
			cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
			cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
			cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
			cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
		} else {
			cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
		}
	}

	if (data) {
		ret = dwmci_data_transfer(host, data);

		/* only dma mode need it */
		if (!host->fifo_mode) {
			ctrl = dwmci_readl(host, DWMCI_CTRL);
			ctrl &= ~(DWMCI_DMA_EN);
			dwmci_writel(host, DWMCI_CTRL, ctrl);
			bounce_buffer_stop(&bbstate);
		}
	}

	udelay(100);

	return ret;
}

static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
{
	u32 div, status;
	int timeout = 10000;
	unsigned long sclk;

	if ((freq == host->clock) || (freq == 0))
		return 0;
	/*
	 * If host->get_mmc_clk isn't defined,
	 * then assume that host->bus_hz is source clock value.
	 * host->bus_hz should be set by user.
	 */
	if (host->get_mmc_clk)
		sclk = host->get_mmc_clk(host, freq);
	else if (host->bus_hz)
		sclk = host->bus_hz;
	else {
		debug("%s: Didn't get source clock value.\n", __func__);
		return -EINVAL;
	}

	if (sclk == freq)
		div = 0;	/* bypass mode */
	else
		div = DIV_ROUND_UP(sclk, 2 * freq);

	dwmci_writel(host, DWMCI_CLKENA, 0);
	dwmci_writel(host, DWMCI_CLKSRC, 0);

	dwmci_writel(host, DWMCI_CLKDIV, div);
	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);

	do {
		status = dwmci_readl(host, DWMCI_CMD);
		if (timeout-- < 0) {
			debug("%s: Timeout!\n", __func__);
			return -ETIMEDOUT;
		}
	} while (status & DWMCI_CMD_START);

	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
			DWMCI_CLKEN_LOW_PWR);

	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);

	timeout = 10000;
	do {
		status = dwmci_readl(host, DWMCI_CMD);
		if (timeout-- < 0) {
			debug("%s: Timeout!\n", __func__);
			return -ETIMEDOUT;
		}
	} while (status & DWMCI_CMD_START);

	host->clock = freq;

	return 0;
}

#ifdef CONFIG_DM_MMC
static int dwmci_set_ios(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
static int dwmci_set_ios(struct mmc *mmc)
{
#endif
	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
	u32 ctype, regs;

	debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);

	dwmci_setup_bus(host, mmc->clock);
	switch (mmc->bus_width) {
	case 8:
		ctype = DWMCI_CTYPE_8BIT;
		break;
	case 4:
		ctype = DWMCI_CTYPE_4BIT;
		break;
	default:
		ctype = DWMCI_CTYPE_1BIT;
		break;
	}

	dwmci_writel(host, DWMCI_CTYPE, ctype);

	regs = dwmci_readl(host, DWMCI_UHS_REG);
	if (mmc->ddr_mode)
		regs |= DWMCI_DDR_MODE;
	else
		regs &= ~DWMCI_DDR_MODE;

	dwmci_writel(host, DWMCI_UHS_REG, regs);

	if (host->clksel)
		host->clksel(host);

	return 0;
}

static int dwmci_init(struct mmc *mmc)
{
	struct dwmci_host *host = mmc->priv;

	if (host->board_init)
		host->board_init(host);

	dwmci_writel(host, DWMCI_PWREN, 1);

	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
		debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
		return -EIO;
	}

	/* Enumerate at 400KHz */
	dwmci_setup_bus(host, mmc->cfg->f_min);

	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
	dwmci_writel(host, DWMCI_INTMASK, 0);

	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);

	dwmci_writel(host, DWMCI_IDINTEN, 0);
	dwmci_writel(host, DWMCI_BMOD, 1);

	if (!host->fifoth_val) {
		uint32_t fifo_size;

		fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
		fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
		host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
				TX_WMARK(fifo_size / 2);
	}
	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);

	dwmci_writel(host, DWMCI_CLKENA, 0);
	dwmci_writel(host, DWMCI_CLKSRC, 0);

	return 0;
}

#ifdef CONFIG_DM_MMC
int dwmci_probe(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);

	return dwmci_init(mmc);
}

const struct dm_mmc_ops dm_dwmci_ops = {
	.send_cmd	= dwmci_send_cmd,
	.set_ios	= dwmci_set_ios,
};

#else
static const struct mmc_ops dwmci_ops = {
	.send_cmd	= dwmci_send_cmd,
	.set_ios	= dwmci_set_ios,
	.init		= dwmci_init,
};
#endif

void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
		u32 max_clk, u32 min_clk)
{
	cfg->name = host->name;
#ifndef CONFIG_DM_MMC
	cfg->ops = &dwmci_ops;
#endif
	cfg->f_min = min_clk;
	cfg->f_max = max_clk;

	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;

	cfg->host_caps = host->caps;

	if (host->buswidth == 8) {
		cfg->host_caps |= MMC_MODE_8BIT;
		cfg->host_caps &= ~MMC_MODE_4BIT;
	} else {
		cfg->host_caps |= MMC_MODE_4BIT;
		cfg->host_caps &= ~MMC_MODE_8BIT;
	}
	cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;

	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
}

#ifdef CONFIG_BLK
int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
{
	return mmc_bind(dev, mmc, cfg);
}
#else
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
{
	dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);

	host->mmc = mmc_create(&host->cfg, host);
	if (host->mmc == NULL)
		return -1;

	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
757bff49 JC	2	/*
	3	* (C) Copyright 2012 SAMSUNG Electronics
	4	* Jaehoon Chung <jh80.chung@samsung.com>
	5	* Rajeshawari Shinde <rajeshwari.s@samsung.com>
757bff49 JC	6	*/
757bff49 JC	7
2a7a210e	8	#include <bouncebuf.h>
757bff49	9	#include <common.h>
1c87ffe8	10	#include <errno.h>
757bff49	11	#include <malloc.h>
cf92e05c	12	#include <memalign.h>
757bff49 JC	13	#include <mmc.h>
757bff49 JC	14	#include <dwmmc.h>
757bff49 JC	15
	16	#define PAGE_SIZE 4096
	17
	18	static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
	19	{
	20	unsigned long timeout = 1000;
	21	u32 ctrl;
	22
	23	dwmci_writel(host, DWMCI_CTRL, value);
	24
	25	while (timeout--) {
	26	ctrl = dwmci_readl(host, DWMCI_CTRL);
	27	if (!(ctrl & DWMCI_RESET_ALL))
	28	return 1;
	29	}
	30	return 0;
	31	}
	32
	33	static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
	34	u32 desc0, u32 desc1, u32 desc2)
	35	{
	36	struct dwmci_idmac *desc = idmac;
	37
	38	desc->flags = desc0;
	39	desc->cnt = desc1;
	40	desc->addr = desc2;
41f7be3c	41	desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
757bff49 JC	42	}
	43
	44	static void dwmci_prepare_data(struct dwmci_host *host,
2a7a210e AB	45	struct mmc_data *data,
	46	struct dwmci_idmac *cur_idmac,
	47	void *bounce_buffer)
757bff49 JC	48	{
	49	unsigned long ctrl;
	50	unsigned int i = 0, flags, cnt, blk_cnt;
2a7a210e	51	ulong data_start, data_end;
757bff49 JC	52
	53
	54	blk_cnt = data->blocks;
	55
	56	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
	57
	58	data_start = (ulong)cur_idmac;
41f7be3c	59	dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
757bff49	60
757bff49 JC	61	do {
	62	flags = DWMCI_IDMAC_OWN \| DWMCI_IDMAC_CH ;
	63	flags \|= (i == 0) ? DWMCI_IDMAC_FS : 0;
	64	if (blk_cnt <= 8) {
	65	flags \|= DWMCI_IDMAC_LD;
	66	cnt = data->blocksize * blk_cnt;
	67	} else
	68	cnt = data->blocksize * 8;
	69
	70	dwmci_set_idma_desc(cur_idmac, flags, cnt,
41f7be3c	71	(ulong)bounce_buffer + (i * PAGE_SIZE));
757bff49	72
21bd5761	73	if (blk_cnt <= 8)
757bff49 JC	74	break;
	75	blk_cnt -= 8;
	76	cur_idmac++;
	77	i++;
	78	} while(1);
	79
	80	data_end = (ulong)cur_idmac;
	81	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
	82
	83	ctrl = dwmci_readl(host, DWMCI_CTRL);
	84	ctrl \|= DWMCI_IDMAC_EN \| DWMCI_DMA_EN;
	85	dwmci_writel(host, DWMCI_CTRL, ctrl);
	86
	87	ctrl = dwmci_readl(host, DWMCI_BMOD);
	88	ctrl \|= DWMCI_BMOD_IDMAC_FB \| DWMCI_BMOD_IDMAC_EN;
	89	dwmci_writel(host, DWMCI_BMOD, ctrl);
	90
	91	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	92	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
	93	}
	94
a65f51b9	95	static int dwmci_data_transfer(struct dwmci_host host, struct mmc_data data)
f382eb83	96	{
f382eb83	97	int ret = 0;
a65f51b9	98	u32 timeout = 240000;
	99	u32 mask, size, i, len = 0;
	100	u32 *buf = NULL;
f382eb83	101	ulong start = get_timer(0);
a65f51b9	102	u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
	103	RX_WMARK_SHIFT) + 1) * 2;
	104
	105	size = data->blocksize * data->blocks / 4;
	106	if (data->flags == MMC_DATA_READ)
	107	buf = (unsigned int *)data->dest;
	108	else
	109	buf = (unsigned int *)data->src;
f382eb83	110
	111	for (;;) {
	112	mask = dwmci_readl(host, DWMCI_RINTSTS);
	113	/* Error during data transfer. */
	114	if (mask & (DWMCI_DATA_ERR \| DWMCI_DATA_TOUT)) {
	115	debug("%s: DATA ERROR!\n", __func__);
	116	ret = -EINVAL;
	117	break;
	118	}
	119
a65f51b9	120	if (host->fifo_mode && size) {
720724d0	121	len = 0;
2b429033 JC	122	if (data->flags == MMC_DATA_READ &&
	123	(mask & DWMCI_INTMSK_RXDR)) {
	124	while (size) {
a65f51b9	125	len = dwmci_readl(host, DWMCI_STATUS);
	126	len = (len >> DWMCI_FIFO_SHIFT) &
	127	DWMCI_FIFO_MASK;
2990e07a	128	len = min(size, len);
a65f51b9	129	for (i = 0; i < len; i++)
	130	*buf++ =
	131	dwmci_readl(host, DWMCI_DATA);
2b429033	132	size = size > len ? (size - len) : 0;
a65f51b9	133	}
2b429033 JC	134	dwmci_writel(host, DWMCI_RINTSTS,
	135	DWMCI_INTMSK_RXDR);
	136	} else if (data->flags == MMC_DATA_WRITE &&
	137	(mask & DWMCI_INTMSK_TXDR)) {
	138	while (size) {
a65f51b9	139	len = dwmci_readl(host, DWMCI_STATUS);
	140	len = fifo_depth - ((len >>
	141	DWMCI_FIFO_SHIFT) &
	142	DWMCI_FIFO_MASK);
2990e07a	143	len = min(size, len);
a65f51b9	144	for (i = 0; i < len; i++)
	145	dwmci_writel(host, DWMCI_DATA,
	146	*buf++);
2b429033	147	size = size > len ? (size - len) : 0;
a65f51b9	148	}
2b429033 JC	149	dwmci_writel(host, DWMCI_RINTSTS,
2b429033 JC	150	DWMCI_INTMSK_TXDR);
a65f51b9	151	}
a65f51b9	152	}
a65f51b9	153
f382eb83	154	/* Data arrived correctly. */
	155	if (mask & DWMCI_INTMSK_DTO) {
	156	ret = 0;
	157	break;
	158	}
	159
	160	/* Check for timeout. */
	161	if (get_timer(start) > timeout) {
	162	debug("%s: Timeout waiting for data!\n",
	163	__func__);
915ffa52	164	ret = -ETIMEDOUT;
f382eb83	165	break;
	166	}
	167	}
	168
	169	dwmci_writel(host, DWMCI_RINTSTS, mask);
	170
	171	return ret;
	172	}
	173
757bff49 JC	174	static int dwmci_set_transfer_mode(struct dwmci_host *host,
	175	struct mmc_data *data)
	176	{
	177	unsigned long mode;
	178
	179	mode = DWMCI_CMD_DATA_EXP;
	180	if (data->flags & MMC_DATA_WRITE)
	181	mode \|= DWMCI_CMD_RW;
	182
	183	return mode;
	184	}
	185
e7881d85	186	#ifdef CONFIG_DM_MMC
5628347f	187	static int dwmci_send_cmd(struct udevice dev, struct mmc_cmd cmd,
691272fe SG	188	struct mmc_data *data)
	189	{
	190	struct mmc *mmc = mmc_get_mmc_dev(dev);
	191	#else
757bff49 JC	192	static int dwmci_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
	193	struct mmc_data *data)
	194	{
691272fe	195	#endif
93bfd616	196	struct dwmci_host *host = mmc->priv;
2136d226	197	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
21bd5761	198	data ? DIV_ROUND_UP(data->blocks, 8) : 0);
9042d974	199	int ret = 0, flags = 0, i;
02ebd42c	200	unsigned int timeout = 500;
9b5b8b6e	201	u32 retry = 100000;
757bff49	202	u32 mask, ctrl;
9c50e35f	203	ulong start = get_timer(0);
2a7a210e	204	struct bounce_buffer bbstate;
757bff49 JC	205
757bff49 JC	206	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
9c50e35f	207	if (get_timer(start) > timeout) {
1c87ffe8	208	debug("%s: Timeout on data busy\n", __func__);
915ffa52	209	return -ETIMEDOUT;
757bff49	210	}
757bff49 JC	211	}
	212
	213	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
	214
2a7a210e	215	if (data) {
a65f51b9	216	if (host->fifo_mode) {
	217	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	218	dwmci_writel(host, DWMCI_BYTCNT,
	219	data->blocksize * data->blocks);
	220	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
2a7a210e	221	} else {
a65f51b9	222	if (data->flags == MMC_DATA_READ) {
	223	bounce_buffer_start(&bbstate, (void*)data->dest,
	224	data->blocksize *
	225	data->blocks, GEN_BB_WRITE);
	226	} else {
	227	bounce_buffer_start(&bbstate, (void*)data->src,
	228	data->blocksize *
	229	data->blocks, GEN_BB_READ);
	230	}
	231	dwmci_prepare_data(host, data, cur_idmac,
	232	bbstate.bounce_buffer);
2a7a210e	233	}
2a7a210e	234	}
757bff49	235
757bff49 JC	236	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
	237
	238	if (data)
	239	flags = dwmci_set_transfer_mode(host, data);
	240
	241	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
	242	return -1;
	243
	244	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	245	flags \|= DWMCI_CMD_ABORT_STOP;
	246	else
	247	flags \|= DWMCI_CMD_PRV_DAT_WAIT;
	248
	249	if (cmd->resp_type & MMC_RSP_PRESENT) {
	250	flags \|= DWMCI_CMD_RESP_EXP;
	251	if (cmd->resp_type & MMC_RSP_136)
	252	flags \|= DWMCI_CMD_RESP_LENGTH;
	253	}
	254
	255	if (cmd->resp_type & MMC_RSP_CRC)
	256	flags \|= DWMCI_CMD_CHECK_CRC;
	257
	258	flags \|= (cmd->cmdidx \| DWMCI_CMD_START \| DWMCI_CMD_USE_HOLD_REG);
	259
	260	debug("Sending CMD%d\n",cmd->cmdidx);
	261
	262	dwmci_writel(host, DWMCI_CMD, flags);
	263
	264	for (i = 0; i < retry; i++) {
	265	mask = dwmci_readl(host, DWMCI_RINTSTS);
	266	if (mask & DWMCI_INTMSK_CDONE) {
	267	if (!data)
	268	dwmci_writel(host, DWMCI_RINTSTS, mask);
	269	break;
	270	}
	271	}
	272
f33c9305	273	if (i == retry) {
1c87ffe8	274	debug("%s: Timeout.\n", __func__);
915ffa52	275	return -ETIMEDOUT;
f33c9305	276	}
757bff49 JC	277
757bff49 JC	278	if (mask & DWMCI_INTMSK_RTO) {
f33c9305 PM	279	/*
	280	* Timeout here is not necessarily fatal. (e)MMC cards
	281	* will splat here when they receive CMD55 as they do
	282	* not support this command and that is exactly the way
	283	* to tell them apart from SD cards. Thus, this output
	284	* below shall be debug(). eMMC cards also do not favor
	285	* CMD8, please keep that in mind.
	286	*/
	287	debug("%s: Response Timeout.\n", __func__);
915ffa52	288	return -ETIMEDOUT;
757bff49	289	} else if (mask & DWMCI_INTMSK_RE) {
1c87ffe8 SG	290	debug("%s: Response Error.\n", __func__);
1c87ffe8 SG	291	return -EIO;
757bff49 JC	292	}
	293
	294
	295	if (cmd->resp_type & MMC_RSP_PRESENT) {
	296	if (cmd->resp_type & MMC_RSP_136) {
	297	cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
	298	cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
	299	cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
	300	cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
	301	} else {
	302	cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
	303	}
	304	}
	305
	306	if (data) {
a65f51b9	307	ret = dwmci_data_transfer(host, data);
	308
	309	/* only dma mode need it */
	310	if (!host->fifo_mode) {
	311	ctrl = dwmci_readl(host, DWMCI_CTRL);
	312	ctrl &= ~(DWMCI_DMA_EN);
	313	dwmci_writel(host, DWMCI_CTRL, ctrl);
	314	bounce_buffer_stop(&bbstate);
	315	}
757bff49 JC	316	}
	317
	318	udelay(100);
	319
9042d974	320	return ret;
757bff49 JC	321	}
	322
	323	static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
	324	{
	325	u32 div, status;
	326	int timeout = 10000;
	327	unsigned long sclk;
	328
9c50e35f	329	if ((freq == host->clock) \|\| (freq == 0))
757bff49	330	return 0;
757bff49	331	/*
f33c9305	332	* If host->get_mmc_clk isn't defined,
757bff49	333	* then assume that host->bus_hz is source clock value.
f33c9305	334	* host->bus_hz should be set by user.
757bff49	335	*/
b44fe83a	336	if (host->get_mmc_clk)
e3563f2e	337	sclk = host->get_mmc_clk(host, freq);
757bff49 JC	338	else if (host->bus_hz)
	339	sclk = host->bus_hz;
	340	else {
1c87ffe8	341	debug("%s: Didn't get source clock value.\n", __func__);
757bff49 JC	342	return -EINVAL;
	343	}
	344
6ace153d CLS	345	if (sclk == freq)
	346	div = 0; /* bypass mode */
	347	else
	348	div = DIV_ROUND_UP(sclk, 2 * freq);
757bff49 JC	349
	350	dwmci_writel(host, DWMCI_CLKENA, 0);
	351	dwmci_writel(host, DWMCI_CLKSRC, 0);
	352
	353	dwmci_writel(host, DWMCI_CLKDIV, div);
	354	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
	355	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
	356
	357	do {
	358	status = dwmci_readl(host, DWMCI_CMD);
	359	if (timeout-- < 0) {
1c87ffe8	360	debug("%s: Timeout!\n", __func__);
757bff49 JC	361	return -ETIMEDOUT;
	362	}
	363	} while (status & DWMCI_CMD_START);
	364
	365	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE \|
	366	DWMCI_CLKEN_LOW_PWR);
	367
	368	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
	369	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
	370
	371	timeout = 10000;
	372	do {
	373	status = dwmci_readl(host, DWMCI_CMD);
	374	if (timeout-- < 0) {
1c87ffe8	375	debug("%s: Timeout!\n", __func__);
757bff49 JC	376	return -ETIMEDOUT;
	377	}
	378	} while (status & DWMCI_CMD_START);
	379
	380	host->clock = freq;
	381
	382	return 0;
	383	}
	384
e7881d85	385	#ifdef CONFIG_DM_MMC
5628347f	386	static int dwmci_set_ios(struct udevice *dev)
691272fe SG	387	{
	388	struct mmc *mmc = mmc_get_mmc_dev(dev);
	389	#else
07b0b9c0	390	static int dwmci_set_ios(struct mmc *mmc)
757bff49	391	{
691272fe	392	#endif
045bdcd0 JC	393	struct dwmci_host host = (struct dwmci_host )mmc->priv;
045bdcd0 JC	394	u32 ctype, regs;
757bff49	395
f33c9305	396	debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
757bff49 JC	397
	398	dwmci_setup_bus(host, mmc->clock);
	399	switch (mmc->bus_width) {
	400	case 8:
	401	ctype = DWMCI_CTYPE_8BIT;
	402	break;
	403	case 4:
	404	ctype = DWMCI_CTYPE_4BIT;
	405	break;
	406	default:
	407	ctype = DWMCI_CTYPE_1BIT;
	408	break;
	409	}
	410
	411	dwmci_writel(host, DWMCI_CTYPE, ctype);
	412
045bdcd0	413	regs = dwmci_readl(host, DWMCI_UHS_REG);
2b8a9692	414	if (mmc->ddr_mode)
045bdcd0 JC	415	regs \|= DWMCI_DDR_MODE;
045bdcd0 JC	416	else
afc9e2b5	417	regs &= ~DWMCI_DDR_MODE;
045bdcd0 JC	418
	419	dwmci_writel(host, DWMCI_UHS_REG, regs);
	420
757bff49 JC	421	if (host->clksel)
757bff49 JC	422	host->clksel(host);
07b0b9c0	423
691272fe	424	return 0;
757bff49 JC	425	}
	426
	427	static int dwmci_init(struct mmc *mmc)
	428	{
93bfd616	429	struct dwmci_host *host = mmc->priv;
757bff49	430
18ab6755 JC	431	if (host->board_init)
18ab6755 JC	432	host->board_init(host);
6f0b7caa	433
757bff49 JC	434	dwmci_writel(host, DWMCI_PWREN, 1);
	435
	436	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
1c87ffe8 SG	437	debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
1c87ffe8 SG	438	return -EIO;
757bff49 JC	439	}
757bff49 JC	440
9c50e35f	441	/* Enumerate at 400KHz */
93bfd616	442	dwmci_setup_bus(host, mmc->cfg->f_min);
9c50e35f	443
757bff49 JC	444	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
	445	dwmci_writel(host, DWMCI_INTMASK, 0);
	446
	447	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
	448
	449	dwmci_writel(host, DWMCI_IDINTEN, 0);
	450	dwmci_writel(host, DWMCI_BMOD, 1);
	451
760177df SG	452	if (!host->fifoth_val) {
	453	uint32_t fifo_size;
	454
	455	fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
	456	fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
	457	host->fifoth_val = MSIZE(0x2) \| RX_WMARK(fifo_size / 2 - 1) \|
	458	TX_WMARK(fifo_size / 2);
9c50e35f	459	}
760177df	460	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
757bff49 JC	461
	462	dwmci_writel(host, DWMCI_CLKENA, 0);
	463	dwmci_writel(host, DWMCI_CLKSRC, 0);
	464
	465	return 0;
	466	}
	467
e7881d85	468	#ifdef CONFIG_DM_MMC
691272fe SG	469	int dwmci_probe(struct udevice *dev)
	470	{
	471	struct mmc *mmc = mmc_get_mmc_dev(dev);
	472
	473	return dwmci_init(mmc);
	474	}
	475
	476	const struct dm_mmc_ops dm_dwmci_ops = {
	477	.send_cmd = dwmci_send_cmd,
	478	.set_ios = dwmci_set_ios,
	479	};
	480
	481	#else
ab769f22 PA	482	static const struct mmc_ops dwmci_ops = {
	483	.send_cmd = dwmci_send_cmd,
	484	.set_ios = dwmci_set_ios,
	485	.init = dwmci_init,
	486	};
691272fe	487	#endif
ab769f22	488
e5113c33 JC	489	void dwmci_setup_cfg(struct mmc_config cfg, struct dwmci_host host,
e5113c33 JC	490	u32 max_clk, u32 min_clk)
757bff49	491	{
e5113c33	492	cfg->name = host->name;
e7881d85	493	#ifndef CONFIG_DM_MMC
5e6ff810	494	cfg->ops = &dwmci_ops;
691272fe	495	#endif
5e6ff810 SG	496	cfg->f_min = min_clk;
5e6ff810 SG	497	cfg->f_max = max_clk;
757bff49	498
5e6ff810	499	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
757bff49	500
e5113c33	501	cfg->host_caps = host->caps;
757bff49	502
e5113c33	503	if (host->buswidth == 8) {
5e6ff810 SG	504	cfg->host_caps \|= MMC_MODE_8BIT;
5e6ff810 SG	505	cfg->host_caps &= ~MMC_MODE_4BIT;
757bff49	506	} else {
5e6ff810 SG	507	cfg->host_caps \|= MMC_MODE_4BIT;
5e6ff810 SG	508	cfg->host_caps &= ~MMC_MODE_8BIT;
757bff49	509	}
5e6ff810 SG	510	cfg->host_caps \|= MMC_MODE_HS \| MMC_MODE_HS_52MHz;
	511
	512	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
	513	}
93bfd616	514
5e6ff810 SG	515	#ifdef CONFIG_BLK
	516	int dwmci_bind(struct udevice dev, struct mmc mmc, struct mmc_config *cfg)
	517	{
	518	return mmc_bind(dev, mmc, cfg);
	519	}
	520	#else
	521	int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
	522	{
e5113c33	523	dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
757bff49	524
93bfd616 PA	525	host->mmc = mmc_create(&host->cfg, host);
	526	if (host->mmc == NULL)
	527	return -1;
757bff49	528
93bfd616	529	return 0;
757bff49	530	}
5e6ff810	531	#endif