[people/ms/u-boot.git] / drivers / mmc / dw_mmc.c

/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Jaehoon Chung <jh80.chung@samsung.com>
 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,  MA 02111-1307 USA
 *
 */

#include <common.h>
#include <malloc.h>
#include <mmc.h>
#include <dwmmc.h>
#include <asm/arch/clk.h>
#include <asm-generic/errno.h>

#define PAGE_SIZE 4096

static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
{
	unsigned long timeout = 1000;
	u32 ctrl;

	dwmci_writel(host, DWMCI_CTRL, value);

	while (timeout--) {
		ctrl = dwmci_readl(host, DWMCI_CTRL);
		if (!(ctrl & DWMCI_RESET_ALL))
			return 1;
	}
	return 0;
}

static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
		u32 desc0, u32 desc1, u32 desc2)
{
	struct dwmci_idmac *desc = idmac;

	desc->flags = desc0;
	desc->cnt = desc1;
	desc->addr = desc2;
	desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
}

static void dwmci_prepare_data(struct dwmci_host *host,
		struct mmc_data *data)
{
	unsigned long ctrl;
	unsigned int i = 0, flags, cnt, blk_cnt;
	ulong data_start, data_end, start_addr;
	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, data->blocks);


	blk_cnt = data->blocks;

	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);

	data_start = (ulong)cur_idmac;
	dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);

	if (data->flags == MMC_DATA_READ)
		start_addr = (unsigned int)data->dest;
	else
		start_addr = (unsigned int)data->src;

	do {
		flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
		flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
		if (blk_cnt <= 8) {
			flags |= DWMCI_IDMAC_LD;
			cnt = data->blocksize * blk_cnt;
		} else
			cnt = data->blocksize * 8;

		dwmci_set_idma_desc(cur_idmac, flags, cnt,
				start_addr + (i * PAGE_SIZE));

		if(blk_cnt < 8)
			break;
		blk_cnt -= 8;
		cur_idmac++;
		i++;
	} while(1);

	data_end = (ulong)cur_idmac;
	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);

	ctrl = dwmci_readl(host, DWMCI_CTRL);
	ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
	dwmci_writel(host, DWMCI_CTRL, ctrl);

	ctrl = dwmci_readl(host, DWMCI_BMOD);
	ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
	dwmci_writel(host, DWMCI_BMOD, ctrl);

	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
}

static int dwmci_set_transfer_mode(struct dwmci_host *host,
		struct mmc_data *data)
{
	unsigned long mode;

	mode = DWMCI_CMD_DATA_EXP;
	if (data->flags & MMC_DATA_WRITE)
		mode |= DWMCI_CMD_RW;

	return mode;
}

static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
		struct mmc_data *data)
{
	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
	int flags = 0, i;
	unsigned int timeout = 100000;
	u32 retry = 10000;
	u32 mask, ctrl;
	ulong start = get_timer(0);

	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
		if (get_timer(start) > timeout) {
			printf("Timeout on data busy\n");
			return TIMEOUT;
		}
	}

	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);

	if (data)
		dwmci_prepare_data(host, data);

	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);

	if (data)
		flags = dwmci_set_transfer_mode(host, data);

	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
		return -1;

	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		flags |= DWMCI_CMD_ABORT_STOP;
	else
		flags |= DWMCI_CMD_PRV_DAT_WAIT;

	if (cmd->resp_type & MMC_RSP_PRESENT) {
		flags |= DWMCI_CMD_RESP_EXP;
		if (cmd->resp_type & MMC_RSP_136)
			flags |= DWMCI_CMD_RESP_LENGTH;
	}

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= DWMCI_CMD_CHECK_CRC;

	flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);

	debug("Sending CMD%d\n",cmd->cmdidx);

	dwmci_writel(host, DWMCI_CMD, flags);

	for (i = 0; i < retry; i++) {
		mask = dwmci_readl(host, DWMCI_RINTSTS);
		if (mask & DWMCI_INTMSK_CDONE) {
			if (!data)
				dwmci_writel(host, DWMCI_RINTSTS, mask);
			break;
		}
	}

	if (i == retry)
		return TIMEOUT;

	if (mask & DWMCI_INTMSK_RTO) {
		debug("Response Timeout..\n");
		return TIMEOUT;
	} else if (mask & DWMCI_INTMSK_RE) {
		debug("Response Error..\n");
		return -1;
	}


	if (cmd->resp_type & MMC_RSP_PRESENT) {
		if (cmd->resp_type & MMC_RSP_136) {
			cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
			cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
			cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
			cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
		} else {
			cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
		}
	}

	if (data) {
		do {
			mask = dwmci_readl(host, DWMCI_RINTSTS);
			if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
				debug("DATA ERROR!\n");
				return -1;
			}
		} while (!(mask & DWMCI_INTMSK_DTO));

		dwmci_writel(host, DWMCI_RINTSTS, mask);

		ctrl = dwmci_readl(host, DWMCI_CTRL);
		ctrl &= ~(DWMCI_DMA_EN);
		dwmci_writel(host, DWMCI_CTRL, ctrl);
	}

	udelay(100);

	return 0;
}

static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
{
	u32 div, status;
	int timeout = 10000;
	unsigned long sclk;

	if ((freq == host->clock) || (freq == 0))
		return 0;
	/*
	 * If host->mmc_clk didn't define,
	 * then assume that host->bus_hz is source clock value.
	 * host->bus_hz should be set from user.
	 */
	if (host->mmc_clk)
		sclk = host->mmc_clk(host->dev_index);
	else if (host->bus_hz)
		sclk = host->bus_hz;
	else {
		printf("Didn't get source clock value..\n");
		return -EINVAL;
	}

	div = DIV_ROUND_UP(sclk, 2 * freq);

	dwmci_writel(host, DWMCI_CLKENA, 0);
	dwmci_writel(host, DWMCI_CLKSRC, 0);

	dwmci_writel(host, DWMCI_CLKDIV, div);
	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);

	do {
		status = dwmci_readl(host, DWMCI_CMD);
		if (timeout-- < 0) {
			printf("TIMEOUT error!!\n");
			return -ETIMEDOUT;
		}
	} while (status & DWMCI_CMD_START);

	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
			DWMCI_CLKEN_LOW_PWR);

	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);

	timeout = 10000;
	do {
		status = dwmci_readl(host, DWMCI_CMD);
		if (timeout-- < 0) {
			printf("TIMEOUT error!!\n");
			return -ETIMEDOUT;
		}
	} while (status & DWMCI_CMD_START);

	host->clock = freq;

	return 0;
}

static void dwmci_set_ios(struct mmc *mmc)
{
	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
	u32 ctype;

	debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);

	dwmci_setup_bus(host, mmc->clock);
	switch (mmc->bus_width) {
	case 8:
		ctype = DWMCI_CTYPE_8BIT;
		break;
	case 4:
		ctype = DWMCI_CTYPE_4BIT;
		break;
	default:
		ctype = DWMCI_CTYPE_1BIT;
		break;
	}

	dwmci_writel(host, DWMCI_CTYPE, ctype);

	if (host->clksel)
		host->clksel(host);
}

static int dwmci_init(struct mmc *mmc)
{
	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
	u32 fifo_size, fifoth_val;

	dwmci_writel(host, DWMCI_PWREN, 1);

	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
		debug("%s[%d] Fail-reset!!\n",__func__,__LINE__);
		return -1;
	}

	/* Enumerate at 400KHz */
	dwmci_setup_bus(host, mmc->f_min);

	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
	dwmci_writel(host, DWMCI_INTMASK, 0);

	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);

	dwmci_writel(host, DWMCI_IDINTEN, 0);
	dwmci_writel(host, DWMCI_BMOD, 1);

	fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
	fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
	if (host->fifoth_val) {
		fifoth_val = host->fifoth_val;
	} else {
		fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
			TX_WMARK(fifo_size / 2);
	}
	dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);

	dwmci_writel(host, DWMCI_CLKENA, 0);
	dwmci_writel(host, DWMCI_CLKSRC, 0);

	return 0;
}

int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
{
	struct mmc *mmc;
	int err = 0;

	mmc = malloc(sizeof(struct mmc));
	if (!mmc) {
		printf("mmc malloc fail!\n");
		return -1;
	}

	mmc->priv = host;
	host->mmc = mmc;

	sprintf(mmc->name, "%s", host->name);
	mmc->send_cmd = dwmci_send_cmd;
	mmc->set_ios = dwmci_set_ios;
	mmc->init = dwmci_init;
	mmc->f_min = min_clk;
	mmc->f_max = max_clk;

	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;

	mmc->host_caps = host->caps;

	if (host->buswidth == 8) {
		mmc->host_caps |= MMC_MODE_8BIT;
		mmc->host_caps &= ~MMC_MODE_4BIT;
	} else {
		mmc->host_caps |= MMC_MODE_4BIT;
		mmc->host_caps &= ~MMC_MODE_8BIT;
	}
	mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;

	err = mmc_register(mmc);

	return err;
}
Commit	Line	Data
757bff49 JC	1	/*
	2	* (C) Copyright 2012 SAMSUNG Electronics
	3	* Jaehoon Chung <jh80.chung@samsung.com>
	4	* Rajeshawari Shinde <rajeshwari.s@samsung.com>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*
	20	*/
	21
	22	#include <common.h>
	23	#include <malloc.h>
	24	#include <mmc.h>
	25	#include <dwmmc.h>
	26	#include <asm/arch/clk.h>
	27	#include <asm-generic/errno.h>
	28
	29	#define PAGE_SIZE 4096
	30
	31	static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
	32	{
	33	unsigned long timeout = 1000;
	34	u32 ctrl;
	35
	36	dwmci_writel(host, DWMCI_CTRL, value);
	37
	38	while (timeout--) {
	39	ctrl = dwmci_readl(host, DWMCI_CTRL);
	40	if (!(ctrl & DWMCI_RESET_ALL))
	41	return 1;
	42	}
	43	return 0;
	44	}
	45
	46	static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
	47	u32 desc0, u32 desc1, u32 desc2)
	48	{
	49	struct dwmci_idmac *desc = idmac;
	50
	51	desc->flags = desc0;
	52	desc->cnt = desc1;
	53	desc->addr = desc2;
	54	desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
	55	}
	56
	57	static void dwmci_prepare_data(struct dwmci_host *host,
	58	struct mmc_data *data)
	59	{
	60	unsigned long ctrl;
	61	unsigned int i = 0, flags, cnt, blk_cnt;
	62	ulong data_start, data_end, start_addr;
	63	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, data->blocks);
	64
65
66	blk_cnt = data->blocks;
67
68	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
69
70	data_start = (ulong)cur_idmac;
71	dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
72
73	if (data->flags == MMC_DATA_READ)
74	start_addr = (unsigned int)data->dest;
75	else
76	start_addr = (unsigned int)data->src;
77
78	do {
79	flags = DWMCI_IDMAC_OWN \| DWMCI_IDMAC_CH ;
80	flags \|= (i == 0) ? DWMCI_IDMAC_FS : 0;
81	if (blk_cnt <= 8) {
82	flags \|= DWMCI_IDMAC_LD;
83	cnt = data->blocksize * blk_cnt;
84	} else
85	cnt = data->blocksize * 8;
86
87	dwmci_set_idma_desc(cur_idmac, flags, cnt,
88	start_addr + (i * PAGE_SIZE));
89
90	if(blk_cnt < 8)
91	break;
92	blk_cnt -= 8;
93	cur_idmac++;
94	i++;
95	} while(1);
96
97	data_end = (ulong)cur_idmac;
98	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
99
100	ctrl = dwmci_readl(host, DWMCI_CTRL);
101	ctrl \|= DWMCI_IDMAC_EN \| DWMCI_DMA_EN;
102	dwmci_writel(host, DWMCI_CTRL, ctrl);
103
104	ctrl = dwmci_readl(host, DWMCI_BMOD);
105	ctrl \|= DWMCI_BMOD_IDMAC_FB \| DWMCI_BMOD_IDMAC_EN;
106	dwmci_writel(host, DWMCI_BMOD, ctrl);
107
108	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
109	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
110	}
111
112	static int dwmci_set_transfer_mode(struct dwmci_host *host,
113	struct mmc_data *data)
114	{
115	unsigned long mode;
116
117	mode = DWMCI_CMD_DATA_EXP;
118	if (data->flags & MMC_DATA_WRITE)
119	mode \|= DWMCI_CMD_RW;
120
121	return mode;
122	}
123
124	static int dwmci_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
125	struct mmc_data *data)
126	{
127	struct dwmci_host host = (struct dwmci_host )mmc->priv;
128	int flags = 0, i;
129	unsigned int timeout = 100000;
130	u32 retry = 10000;
131	u32 mask, ctrl;
9c50e35f	132	ulong start = get_timer(0);
757bff49 JC	133
757bff49 JC	134	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
9c50e35f	135	if (get_timer(start) > timeout) {
757bff49 JC	136	printf("Timeout on data busy\n");
	137	return TIMEOUT;
	138	}
757bff49 JC	139	}
	140
	141	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
	142
	143	if (data)
	144	dwmci_prepare_data(host, data);
	145
757bff49 JC	146	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
	147
	148	if (data)
	149	flags = dwmci_set_transfer_mode(host, data);
	150
	151	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
	152	return -1;
	153
	154	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	155	flags \|= DWMCI_CMD_ABORT_STOP;
	156	else
	157	flags \|= DWMCI_CMD_PRV_DAT_WAIT;
	158
	159	if (cmd->resp_type & MMC_RSP_PRESENT) {
	160	flags \|= DWMCI_CMD_RESP_EXP;
	161	if (cmd->resp_type & MMC_RSP_136)
	162	flags \|= DWMCI_CMD_RESP_LENGTH;
	163	}
	164
	165	if (cmd->resp_type & MMC_RSP_CRC)
	166	flags \|= DWMCI_CMD_CHECK_CRC;
	167
	168	flags \|= (cmd->cmdidx \| DWMCI_CMD_START \| DWMCI_CMD_USE_HOLD_REG);
	169
	170	debug("Sending CMD%d\n",cmd->cmdidx);
	171
	172	dwmci_writel(host, DWMCI_CMD, flags);
	173
	174	for (i = 0; i < retry; i++) {
	175	mask = dwmci_readl(host, DWMCI_RINTSTS);
	176	if (mask & DWMCI_INTMSK_CDONE) {
	177	if (!data)
	178	dwmci_writel(host, DWMCI_RINTSTS, mask);
	179	break;
	180	}
	181	}
	182
	183	if (i == retry)
	184	return TIMEOUT;
	185
	186	if (mask & DWMCI_INTMSK_RTO) {
	187	debug("Response Timeout..\n");
	188	return TIMEOUT;
	189	} else if (mask & DWMCI_INTMSK_RE) {
	190	debug("Response Error..\n");
	191	return -1;
	192	}
	193
	194
	195	if (cmd->resp_type & MMC_RSP_PRESENT) {
	196	if (cmd->resp_type & MMC_RSP_136) {
	197	cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
	198	cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
	199	cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
	200	cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
	201	} else {
	202	cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
	203	}
	204	}
	205
	206	if (data) {
	207	do {
	208	mask = dwmci_readl(host, DWMCI_RINTSTS);
	209	if (mask & (DWMCI_DATA_ERR \| DWMCI_DATA_TOUT)) {
210	debug("DATA ERROR!\n");
211	return -1;
212	}
213	} while (!(mask & DWMCI_INTMSK_DTO));
214
215	dwmci_writel(host, DWMCI_RINTSTS, mask);
216
217	ctrl = dwmci_readl(host, DWMCI_CTRL);
218	ctrl &= ~(DWMCI_DMA_EN);
219	dwmci_writel(host, DWMCI_CTRL, ctrl);
220	}
221
222	udelay(100);
223
224	return 0;
225	}
226
227	static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
228	{
229	u32 div, status;
230	int timeout = 10000;
231	unsigned long sclk;
232
9c50e35f	233	if ((freq == host->clock) \|\| (freq == 0))
757bff49	234	return 0;
757bff49 JC	235	/*
	236	* If host->mmc_clk didn't define,
	237	* then assume that host->bus_hz is source clock value.
	238	* host->bus_hz should be set from user.
	239	*/
	240	if (host->mmc_clk)
	241	sclk = host->mmc_clk(host->dev_index);
	242	else if (host->bus_hz)
	243	sclk = host->bus_hz;
	244	else {
	245	printf("Didn't get source clock value..\n");
	246	return -EINVAL;
	247	}
	248
	249	div = DIV_ROUND_UP(sclk, 2 * freq);
	250
	251	dwmci_writel(host, DWMCI_CLKENA, 0);
	252	dwmci_writel(host, DWMCI_CLKSRC, 0);
	253
	254	dwmci_writel(host, DWMCI_CLKDIV, div);
	255	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
	256	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
	257
	258	do {
	259	status = dwmci_readl(host, DWMCI_CMD);
	260	if (timeout-- < 0) {
	261	printf("TIMEOUT error!!\n");
	262	return -ETIMEDOUT;
	263	}
	264	} while (status & DWMCI_CMD_START);
	265
	266	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE \|
	267	DWMCI_CLKEN_LOW_PWR);
	268
	269	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
	270	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
	271
	272	timeout = 10000;
	273	do {
	274	status = dwmci_readl(host, DWMCI_CMD);
	275	if (timeout-- < 0) {
	276	printf("TIMEOUT error!!\n");
	277	return -ETIMEDOUT;
	278	}
	279	} while (status & DWMCI_CMD_START);
	280
	281	host->clock = freq;
	282
	283	return 0;
	284	}
	285
	286	static void dwmci_set_ios(struct mmc *mmc)
	287	{
	288	struct dwmci_host host = (struct dwmci_host )mmc->priv;
	289	u32 ctype;
	290
	291	debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
	292
	293	dwmci_setup_bus(host, mmc->clock);
	294	switch (mmc->bus_width) {
	295	case 8:
	296	ctype = DWMCI_CTYPE_8BIT;
	297	break;
	298	case 4:
299	ctype = DWMCI_CTYPE_4BIT;
300	break;
301	default:
302	ctype = DWMCI_CTYPE_1BIT;
303	break;
304	}
305
306	dwmci_writel(host, DWMCI_CTYPE, ctype);
307
308	if (host->clksel)
309	host->clksel(host);
310	}
311
312	static int dwmci_init(struct mmc *mmc)
313	{
314	struct dwmci_host host = (struct dwmci_host )mmc->priv;
315	u32 fifo_size, fifoth_val;
316
317	dwmci_writel(host, DWMCI_PWREN, 1);
318
319	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
320	debug("%s[%d] Fail-reset!!\n",__func__,__LINE__);
321	return -1;
322	}
323
9c50e35f A	324	/* Enumerate at 400KHz */
	325	dwmci_setup_bus(host, mmc->f_min);
	326
757bff49 JC	327	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
	328	dwmci_writel(host, DWMCI_INTMASK, 0);
	329
	330	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
	331
	332	dwmci_writel(host, DWMCI_IDINTEN, 0);
	333	dwmci_writel(host, DWMCI_BMOD, 1);
	334
	335	fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
9c50e35f A	336	fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
9c50e35f A	337	if (host->fifoth_val) {
757bff49	338	fifoth_val = host->fifoth_val;
9c50e35f A	339	} else {
	340	fifoth_val = MSIZE(0x2) \| RX_WMARK(fifo_size / 2 - 1) \|
	341	TX_WMARK(fifo_size / 2);
	342	}
757bff49 JC	343	dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
	344
	345	dwmci_writel(host, DWMCI_CLKENA, 0);
	346	dwmci_writel(host, DWMCI_CLKSRC, 0);
	347
	348	return 0;
	349	}
	350
	351	int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
	352	{
	353	struct mmc *mmc;
	354	int err = 0;
	355
	356	mmc = malloc(sizeof(struct mmc));
	357	if (!mmc) {
	358	printf("mmc malloc fail!\n");
	359	return -1;
	360	}
	361
	362	mmc->priv = host;
	363	host->mmc = mmc;
	364
	365	sprintf(mmc->name, "%s", host->name);
	366	mmc->send_cmd = dwmci_send_cmd;
	367	mmc->set_ios = dwmci_set_ios;
	368	mmc->init = dwmci_init;
	369	mmc->f_min = min_clk;
	370	mmc->f_max = max_clk;
	371
	372	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
	373
	374	mmc->host_caps = host->caps;
	375
	376	if (host->buswidth == 8) {
	377	mmc->host_caps \|= MMC_MODE_8BIT;
	378	mmc->host_caps &= ~MMC_MODE_4BIT;
	379	} else {
	380	mmc->host_caps \|= MMC_MODE_4BIT;
	381	mmc->host_caps &= ~MMC_MODE_8BIT;
	382	}
	383	mmc->host_caps \|= MMC_MODE_HS \| MMC_MODE_HS_52MHz \| MMC_MODE_HC;
	384
	385	err = mmc_register(mmc);
	386
	387	return err;
	388	}