[people/ms/u-boot.git] / drivers / mmc / dw_mmc.c

/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Jaehoon Chung <jh80.chung@samsung.com>
 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <bouncebuf.h>
#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <memalign.h>
#include <mmc.h>
#include <dwmmc.h>
#include <asm-generic/errno.h>

#define PAGE_SIZE 4096

static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
{
	unsigned long timeout = 1000;
	u32 ctrl;

	dwmci_writel(host, DWMCI_CTRL, value);

	while (timeout--) {
		ctrl = dwmci_readl(host, DWMCI_CTRL);
		if (!(ctrl & DWMCI_RESET_ALL))
			return 1;
	}
	return 0;
}

static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
		u32 desc0, u32 desc1, u32 desc2)
{
	struct dwmci_idmac *desc = idmac;

	desc->flags = desc0;
	desc->cnt = desc1;
	desc->addr = desc2;
	desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
}

static void dwmci_prepare_data(struct dwmci_host *host,
			       struct mmc_data *data,
			       struct dwmci_idmac *cur_idmac,
			       void *bounce_buffer)
{
	unsigned long ctrl;
	unsigned int i = 0, flags, cnt, blk_cnt;
	ulong data_start, data_end;


	blk_cnt = data->blocks;

	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);

	data_start = (ulong)cur_idmac;
	dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);

	do {
		flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
		flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
		if (blk_cnt <= 8) {
			flags |= DWMCI_IDMAC_LD;
			cnt = data->blocksize * blk_cnt;
		} else
			cnt = data->blocksize * 8;

		dwmci_set_idma_desc(cur_idmac, flags, cnt,
				    (ulong)bounce_buffer + (i * PAGE_SIZE));

		if (blk_cnt <= 8)
			break;
		blk_cnt -= 8;
		cur_idmac++;
		i++;
	} while(1);

	data_end = (ulong)cur_idmac;
	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);

	ctrl = dwmci_readl(host, DWMCI_CTRL);
	ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
	dwmci_writel(host, DWMCI_CTRL, ctrl);

	ctrl = dwmci_readl(host, DWMCI_BMOD);
	ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
	dwmci_writel(host, DWMCI_BMOD, ctrl);

	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
}

static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
{
	int ret = 0;
	u32 timeout = 240000;
	u32 mask, size, i, len = 0;
	u32 *buf = NULL;
	ulong start = get_timer(0);
	u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
			    RX_WMARK_SHIFT) + 1) * 2;

	size = data->blocksize * data->blocks / 4;
	if (data->flags == MMC_DATA_READ)
		buf = (unsigned int *)data->dest;
	else
		buf = (unsigned int *)data->src;

	for (;;) {
		mask = dwmci_readl(host, DWMCI_RINTSTS);
		/* Error during data transfer. */
		if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
			debug("%s: DATA ERROR!\n", __func__);
			ret = -EINVAL;
			break;
		}

		if (host->fifo_mode && size) {
			if (data->flags == MMC_DATA_READ) {
				if ((dwmci_readl(host, DWMCI_RINTSTS) &&
				     DWMCI_INTMSK_RXDR)) {
					len = dwmci_readl(host, DWMCI_STATUS);
					len = (len >> DWMCI_FIFO_SHIFT) &
						    DWMCI_FIFO_MASK;
					for (i = 0; i < len; i++)
						*buf++ =
						dwmci_readl(host, DWMCI_DATA);
					dwmci_writel(host, DWMCI_RINTSTS,
						     DWMCI_INTMSK_RXDR);
				}
			} else {
				if ((dwmci_readl(host, DWMCI_RINTSTS) &&
				     DWMCI_INTMSK_TXDR)) {
					len = dwmci_readl(host, DWMCI_STATUS);
					len = fifo_depth - ((len >>
						   DWMCI_FIFO_SHIFT) &
						   DWMCI_FIFO_MASK);
					for (i = 0; i < len; i++)
						dwmci_writel(host, DWMCI_DATA,
							     *buf++);
					dwmci_writel(host, DWMCI_RINTSTS,
						     DWMCI_INTMSK_TXDR);
				}
			}
			size = size > len ? (size - len) : 0;
		}

		/* Data arrived correctly. */
		if (mask & DWMCI_INTMSK_DTO) {
			ret = 0;
			break;
		}

		/* Check for timeout. */
		if (get_timer(start) > timeout) {
			debug("%s: Timeout waiting for data!\n",
			      __func__);
			ret = TIMEOUT;
			break;
		}
	}

	dwmci_writel(host, DWMCI_RINTSTS, mask);

	return ret;
}

static int dwmci_set_transfer_mode(struct dwmci_host *host,
		struct mmc_data *data)
{
	unsigned long mode;

	mode = DWMCI_CMD_DATA_EXP;
	if (data->flags & MMC_DATA_WRITE)
		mode |= DWMCI_CMD_RW;

	return mode;
}

static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
		struct mmc_data *data)
{
	struct dwmci_host *host = mmc->priv;
	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
				 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
	int ret = 0, flags = 0, i;
	unsigned int timeout = 100000;
	u32 retry = 100000;
	u32 mask, ctrl;
	ulong start = get_timer(0);
	struct bounce_buffer bbstate;

	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
		if (get_timer(start) > timeout) {
			debug("%s: Timeout on data busy\n", __func__);
			return TIMEOUT;
		}
	}

	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);

	if (data) {
		if (host->fifo_mode) {
			dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
			dwmci_writel(host, DWMCI_BYTCNT,
				     data->blocksize * data->blocks);
			dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
		} else {
			if (data->flags == MMC_DATA_READ) {
				bounce_buffer_start(&bbstate, (void*)data->dest,
						data->blocksize *
						data->blocks, GEN_BB_WRITE);
			} else {
				bounce_buffer_start(&bbstate, (void*)data->src,
						data->blocksize *
						data->blocks, GEN_BB_READ);
			}
			dwmci_prepare_data(host, data, cur_idmac,
					   bbstate.bounce_buffer);
		}
	}

	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);

	if (data)
		flags = dwmci_set_transfer_mode(host, data);

	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
		return -1;

	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		flags |= DWMCI_CMD_ABORT_STOP;
	else
		flags |= DWMCI_CMD_PRV_DAT_WAIT;

	if (cmd->resp_type & MMC_RSP_PRESENT) {
		flags |= DWMCI_CMD_RESP_EXP;
		if (cmd->resp_type & MMC_RSP_136)
			flags |= DWMCI_CMD_RESP_LENGTH;
	}

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= DWMCI_CMD_CHECK_CRC;

	flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);

	debug("Sending CMD%d\n",cmd->cmdidx);

	dwmci_writel(host, DWMCI_CMD, flags);

	for (i = 0; i < retry; i++) {
		mask = dwmci_readl(host, DWMCI_RINTSTS);
		if (mask & DWMCI_INTMSK_CDONE) {
			if (!data)
				dwmci_writel(host, DWMCI_RINTSTS, mask);
			break;
		}
	}

	if (i == retry) {
		debug("%s: Timeout.\n", __func__);
		return TIMEOUT;
	}

	if (mask & DWMCI_INTMSK_RTO) {
		/*
		 * Timeout here is not necessarily fatal. (e)MMC cards
		 * will splat here when they receive CMD55 as they do
		 * not support this command and that is exactly the way
		 * to tell them apart from SD cards. Thus, this output
		 * below shall be debug(). eMMC cards also do not favor
		 * CMD8, please keep that in mind.
		 */
		debug("%s: Response Timeout.\n", __func__);
		return TIMEOUT;
	} else if (mask & DWMCI_INTMSK_RE) {
		debug("%s: Response Error.\n", __func__);
		return -EIO;
	}


	if (cmd->resp_type & MMC_RSP_PRESENT) {
		if (cmd->resp_type & MMC_RSP_136) {
			cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
			cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
			cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
			cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
		} else {
			cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
		}
	}

	if (data) {
		ret = dwmci_data_transfer(host, data);

		/* only dma mode need it */
		if (!host->fifo_mode) {
			ctrl = dwmci_readl(host, DWMCI_CTRL);
			ctrl &= ~(DWMCI_DMA_EN);
			dwmci_writel(host, DWMCI_CTRL, ctrl);
			bounce_buffer_stop(&bbstate);
		}
	}

	udelay(100);

	return ret;
}

static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
{
	u32 div, status;
	int timeout = 10000;
	unsigned long sclk;

	if ((freq == host->clock) || (freq == 0))
		return 0;
	/*
	 * If host->get_mmc_clk isn't defined,
	 * then assume that host->bus_hz is source clock value.
	 * host->bus_hz should be set by user.
	 */
	if (host->get_mmc_clk)
		sclk = host->get_mmc_clk(host, freq);
	else if (host->bus_hz)
		sclk = host->bus_hz;
	else {
		debug("%s: Didn't get source clock value.\n", __func__);
		return -EINVAL;
	}

	if (sclk == freq)
		div = 0;	/* bypass mode */
	else
		div = DIV_ROUND_UP(sclk, 2 * freq);

	dwmci_writel(host, DWMCI_CLKENA, 0);
	dwmci_writel(host, DWMCI_CLKSRC, 0);

	dwmci_writel(host, DWMCI_CLKDIV, div);
	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);

	do {
		status = dwmci_readl(host, DWMCI_CMD);
		if (timeout-- < 0) {
			debug("%s: Timeout!\n", __func__);
			return -ETIMEDOUT;
		}
	} while (status & DWMCI_CMD_START);

	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
			DWMCI_CLKEN_LOW_PWR);

	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);

	timeout = 10000;
	do {
		status = dwmci_readl(host, DWMCI_CMD);
		if (timeout-- < 0) {
			debug("%s: Timeout!\n", __func__);
			return -ETIMEDOUT;
		}
	} while (status & DWMCI_CMD_START);

	host->clock = freq;

	return 0;
}

static void dwmci_set_ios(struct mmc *mmc)
{
	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
	u32 ctype, regs;

	debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);

	dwmci_setup_bus(host, mmc->clock);
	switch (mmc->bus_width) {
	case 8:
		ctype = DWMCI_CTYPE_8BIT;
		break;
	case 4:
		ctype = DWMCI_CTYPE_4BIT;
		break;
	default:
		ctype = DWMCI_CTYPE_1BIT;
		break;
	}

	dwmci_writel(host, DWMCI_CTYPE, ctype);

	regs = dwmci_readl(host, DWMCI_UHS_REG);
	if (mmc->ddr_mode)
		regs |= DWMCI_DDR_MODE;
	else
		regs &= ~DWMCI_DDR_MODE;

	dwmci_writel(host, DWMCI_UHS_REG, regs);

	if (host->clksel)
		host->clksel(host);
}

static int dwmci_init(struct mmc *mmc)
{
	struct dwmci_host *host = mmc->priv;

	if (host->board_init)
		host->board_init(host);

	dwmci_writel(host, DWMCI_PWREN, 1);

	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
		debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
		return -EIO;
	}

	/* Enumerate at 400KHz */
	dwmci_setup_bus(host, mmc->cfg->f_min);

	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
	dwmci_writel(host, DWMCI_INTMASK, 0);

	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);

	dwmci_writel(host, DWMCI_IDINTEN, 0);
	dwmci_writel(host, DWMCI_BMOD, 1);

	if (!host->fifoth_val) {
		uint32_t fifo_size;

		fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
		fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
		host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
				TX_WMARK(fifo_size / 2);
	}
	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);

	dwmci_writel(host, DWMCI_CLKENA, 0);
	dwmci_writel(host, DWMCI_CLKSRC, 0);

	return 0;
}

static const struct mmc_ops dwmci_ops = {
	.send_cmd	= dwmci_send_cmd,
	.set_ios	= dwmci_set_ios,
	.init		= dwmci_init,
};

int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
{
	host->cfg.name = host->name;
	host->cfg.ops = &dwmci_ops;
	host->cfg.f_min = min_clk;
	host->cfg.f_max = max_clk;

	host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;

	host->cfg.host_caps = host->caps;

	if (host->buswidth == 8) {
		host->cfg.host_caps |= MMC_MODE_8BIT;
		host->cfg.host_caps &= ~MMC_MODE_4BIT;
	} else {
		host->cfg.host_caps |= MMC_MODE_4BIT;
		host->cfg.host_caps &= ~MMC_MODE_8BIT;
	}
	host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;

	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

	host->mmc = mmc_create(&host->cfg, host);
	if (host->mmc == NULL)
		return -1;

	return 0;
}
Commit	Line	Data
757bff49 JC	1	/*
	2	* (C) Copyright 2012 SAMSUNG Electronics
	3	* Jaehoon Chung <jh80.chung@samsung.com>
	4	* Rajeshawari Shinde <rajeshwari.s@samsung.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
757bff49 JC	7	*/
757bff49 JC	8
2a7a210e	9	#include <bouncebuf.h>
757bff49	10	#include <common.h>
1c87ffe8	11	#include <errno.h>
757bff49	12	#include <malloc.h>
cf92e05c	13	#include <memalign.h>
757bff49 JC	14	#include <mmc.h>
757bff49 JC	15	#include <dwmmc.h>
757bff49 JC	16	#include <asm-generic/errno.h>
	17
	18	#define PAGE_SIZE 4096
	19
	20	static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
	21	{
	22	unsigned long timeout = 1000;
	23	u32 ctrl;
	24
	25	dwmci_writel(host, DWMCI_CTRL, value);
	26
	27	while (timeout--) {
	28	ctrl = dwmci_readl(host, DWMCI_CTRL);
	29	if (!(ctrl & DWMCI_RESET_ALL))
	30	return 1;
	31	}
	32	return 0;
	33	}
	34
	35	static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
	36	u32 desc0, u32 desc1, u32 desc2)
	37	{
	38	struct dwmci_idmac *desc = idmac;
	39
	40	desc->flags = desc0;
	41	desc->cnt = desc1;
	42	desc->addr = desc2;
41f7be3c	43	desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
757bff49 JC	44	}
	45
	46	static void dwmci_prepare_data(struct dwmci_host *host,
2a7a210e AB	47	struct mmc_data *data,
	48	struct dwmci_idmac *cur_idmac,
	49	void *bounce_buffer)
757bff49 JC	50	{
	51	unsigned long ctrl;
	52	unsigned int i = 0, flags, cnt, blk_cnt;
2a7a210e	53	ulong data_start, data_end;
757bff49 JC	54
	55
	56	blk_cnt = data->blocks;
	57
	58	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
	59
	60	data_start = (ulong)cur_idmac;
41f7be3c	61	dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
757bff49	62
757bff49 JC	63	do {
	64	flags = DWMCI_IDMAC_OWN \| DWMCI_IDMAC_CH ;
	65	flags \|= (i == 0) ? DWMCI_IDMAC_FS : 0;
	66	if (blk_cnt <= 8) {
	67	flags \|= DWMCI_IDMAC_LD;
	68	cnt = data->blocksize * blk_cnt;
	69	} else
	70	cnt = data->blocksize * 8;
	71
	72	dwmci_set_idma_desc(cur_idmac, flags, cnt,
41f7be3c	73	(ulong)bounce_buffer + (i * PAGE_SIZE));
757bff49	74
21bd5761	75	if (blk_cnt <= 8)
757bff49 JC	76	break;
	77	blk_cnt -= 8;
	78	cur_idmac++;
	79	i++;
	80	} while(1);
	81
	82	data_end = (ulong)cur_idmac;
	83	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
	84
	85	ctrl = dwmci_readl(host, DWMCI_CTRL);
	86	ctrl \|= DWMCI_IDMAC_EN \| DWMCI_DMA_EN;
	87	dwmci_writel(host, DWMCI_CTRL, ctrl);
	88
	89	ctrl = dwmci_readl(host, DWMCI_BMOD);
	90	ctrl \|= DWMCI_BMOD_IDMAC_FB \| DWMCI_BMOD_IDMAC_EN;
	91	dwmci_writel(host, DWMCI_BMOD, ctrl);
	92
	93	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	94	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
	95	}
	96
a65f51b9	97	static int dwmci_data_transfer(struct dwmci_host host, struct mmc_data data)
f382eb83	98	{
f382eb83	99	int ret = 0;
a65f51b9	100	u32 timeout = 240000;
	101	u32 mask, size, i, len = 0;
	102	u32 *buf = NULL;
f382eb83	103	ulong start = get_timer(0);
a65f51b9	104	u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
	105	RX_WMARK_SHIFT) + 1) * 2;
	106
	107	size = data->blocksize * data->blocks / 4;
	108	if (data->flags == MMC_DATA_READ)
	109	buf = (unsigned int *)data->dest;
	110	else
	111	buf = (unsigned int *)data->src;
f382eb83	112
	113	for (;;) {
	114	mask = dwmci_readl(host, DWMCI_RINTSTS);
	115	/* Error during data transfer. */
	116	if (mask & (DWMCI_DATA_ERR \| DWMCI_DATA_TOUT)) {
	117	debug("%s: DATA ERROR!\n", __func__);
	118	ret = -EINVAL;
	119	break;
	120	}
	121
a65f51b9	122	if (host->fifo_mode && size) {
	123	if (data->flags == MMC_DATA_READ) {
	124	if ((dwmci_readl(host, DWMCI_RINTSTS) &&
	125	DWMCI_INTMSK_RXDR)) {
	126	len = dwmci_readl(host, DWMCI_STATUS);
	127	len = (len >> DWMCI_FIFO_SHIFT) &
	128	DWMCI_FIFO_MASK;
	129	for (i = 0; i < len; i++)
	130	*buf++ =
	131	dwmci_readl(host, DWMCI_DATA);
	132	dwmci_writel(host, DWMCI_RINTSTS,
	133	DWMCI_INTMSK_RXDR);
	134	}
	135	} else {
	136	if ((dwmci_readl(host, DWMCI_RINTSTS) &&
	137	DWMCI_INTMSK_TXDR)) {
	138	len = dwmci_readl(host, DWMCI_STATUS);
	139	len = fifo_depth - ((len >>
	140	DWMCI_FIFO_SHIFT) &
	141	DWMCI_FIFO_MASK);
	142	for (i = 0; i < len; i++)
	143	dwmci_writel(host, DWMCI_DATA,
	144	*buf++);
	145	dwmci_writel(host, DWMCI_RINTSTS,
	146	DWMCI_INTMSK_TXDR);
	147	}
	148	}
	149	size = size > len ? (size - len) : 0;
	150	}
	151
f382eb83	152	/* Data arrived correctly. */
	153	if (mask & DWMCI_INTMSK_DTO) {
	154	ret = 0;
	155	break;
	156	}
	157
	158	/* Check for timeout. */
	159	if (get_timer(start) > timeout) {
	160	debug("%s: Timeout waiting for data!\n",
	161	__func__);
	162	ret = TIMEOUT;
	163	break;
	164	}
	165	}
	166
	167	dwmci_writel(host, DWMCI_RINTSTS, mask);
	168
	169	return ret;
	170	}
	171
757bff49 JC	172	static int dwmci_set_transfer_mode(struct dwmci_host *host,
	173	struct mmc_data *data)
	174	{
	175	unsigned long mode;
	176
	177	mode = DWMCI_CMD_DATA_EXP;
	178	if (data->flags & MMC_DATA_WRITE)
	179	mode \|= DWMCI_CMD_RW;
	180
	181	return mode;
	182	}
	183
	184	static int dwmci_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
	185	struct mmc_data *data)
	186	{
93bfd616	187	struct dwmci_host *host = mmc->priv;
2136d226	188	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
21bd5761	189	data ? DIV_ROUND_UP(data->blocks, 8) : 0);
9042d974	190	int ret = 0, flags = 0, i;
757bff49	191	unsigned int timeout = 100000;
9b5b8b6e	192	u32 retry = 100000;
757bff49	193	u32 mask, ctrl;
9c50e35f	194	ulong start = get_timer(0);
2a7a210e	195	struct bounce_buffer bbstate;
757bff49 JC	196
757bff49 JC	197	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
9c50e35f	198	if (get_timer(start) > timeout) {
1c87ffe8	199	debug("%s: Timeout on data busy\n", __func__);
757bff49 JC	200	return TIMEOUT;
757bff49 JC	201	}
757bff49 JC	202	}
	203
	204	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
	205
2a7a210e	206	if (data) {
a65f51b9	207	if (host->fifo_mode) {
	208	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	209	dwmci_writel(host, DWMCI_BYTCNT,
	210	data->blocksize * data->blocks);
	211	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
2a7a210e	212	} else {
a65f51b9	213	if (data->flags == MMC_DATA_READ) {
	214	bounce_buffer_start(&bbstate, (void*)data->dest,
	215	data->blocksize *
	216	data->blocks, GEN_BB_WRITE);
	217	} else {
	218	bounce_buffer_start(&bbstate, (void*)data->src,
	219	data->blocksize *
	220	data->blocks, GEN_BB_READ);
	221	}
	222	dwmci_prepare_data(host, data, cur_idmac,
	223	bbstate.bounce_buffer);
2a7a210e	224	}
2a7a210e	225	}
757bff49	226
757bff49 JC	227	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
	228
	229	if (data)
	230	flags = dwmci_set_transfer_mode(host, data);
	231
	232	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
	233	return -1;
	234
	235	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	236	flags \|= DWMCI_CMD_ABORT_STOP;
	237	else
	238	flags \|= DWMCI_CMD_PRV_DAT_WAIT;
	239
	240	if (cmd->resp_type & MMC_RSP_PRESENT) {
	241	flags \|= DWMCI_CMD_RESP_EXP;
	242	if (cmd->resp_type & MMC_RSP_136)
	243	flags \|= DWMCI_CMD_RESP_LENGTH;
	244	}
	245
	246	if (cmd->resp_type & MMC_RSP_CRC)
	247	flags \|= DWMCI_CMD_CHECK_CRC;
	248
	249	flags \|= (cmd->cmdidx \| DWMCI_CMD_START \| DWMCI_CMD_USE_HOLD_REG);
	250
	251	debug("Sending CMD%d\n",cmd->cmdidx);
	252
	253	dwmci_writel(host, DWMCI_CMD, flags);
	254
	255	for (i = 0; i < retry; i++) {
	256	mask = dwmci_readl(host, DWMCI_RINTSTS);
	257	if (mask & DWMCI_INTMSK_CDONE) {
	258	if (!data)
	259	dwmci_writel(host, DWMCI_RINTSTS, mask);
	260	break;
	261	}
	262	}
	263
f33c9305	264	if (i == retry) {
1c87ffe8	265	debug("%s: Timeout.\n", __func__);
757bff49	266	return TIMEOUT;
f33c9305	267	}
757bff49 JC	268
757bff49 JC	269	if (mask & DWMCI_INTMSK_RTO) {
f33c9305 PM	270	/*
	271	* Timeout here is not necessarily fatal. (e)MMC cards
	272	* will splat here when they receive CMD55 as they do
	273	* not support this command and that is exactly the way
	274	* to tell them apart from SD cards. Thus, this output
	275	* below shall be debug(). eMMC cards also do not favor
	276	* CMD8, please keep that in mind.
	277	*/
	278	debug("%s: Response Timeout.\n", __func__);
757bff49 JC	279	return TIMEOUT;
757bff49 JC	280	} else if (mask & DWMCI_INTMSK_RE) {
1c87ffe8 SG	281	debug("%s: Response Error.\n", __func__);
1c87ffe8 SG	282	return -EIO;
757bff49 JC	283	}
	284
	285
	286	if (cmd->resp_type & MMC_RSP_PRESENT) {
	287	if (cmd->resp_type & MMC_RSP_136) {
	288	cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
	289	cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
	290	cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
	291	cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
	292	} else {
	293	cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
	294	}
	295	}
	296
	297	if (data) {
a65f51b9	298	ret = dwmci_data_transfer(host, data);
	299
	300	/* only dma mode need it */
	301	if (!host->fifo_mode) {
	302	ctrl = dwmci_readl(host, DWMCI_CTRL);
	303	ctrl &= ~(DWMCI_DMA_EN);
	304	dwmci_writel(host, DWMCI_CTRL, ctrl);
	305	bounce_buffer_stop(&bbstate);
	306	}
757bff49 JC	307	}
	308
	309	udelay(100);
	310
9042d974	311	return ret;
757bff49 JC	312	}
	313
	314	static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
	315	{
	316	u32 div, status;
	317	int timeout = 10000;
	318	unsigned long sclk;
	319
9c50e35f	320	if ((freq == host->clock) \|\| (freq == 0))
757bff49	321	return 0;
757bff49	322	/*
f33c9305	323	* If host->get_mmc_clk isn't defined,
757bff49	324	* then assume that host->bus_hz is source clock value.
f33c9305	325	* host->bus_hz should be set by user.
757bff49	326	*/
b44fe83a	327	if (host->get_mmc_clk)
e3563f2e	328	sclk = host->get_mmc_clk(host, freq);
757bff49 JC	329	else if (host->bus_hz)
	330	sclk = host->bus_hz;
	331	else {
1c87ffe8	332	debug("%s: Didn't get source clock value.\n", __func__);
757bff49 JC	333	return -EINVAL;
	334	}
	335
6ace153d CLS	336	if (sclk == freq)
	337	div = 0; /* bypass mode */
	338	else
	339	div = DIV_ROUND_UP(sclk, 2 * freq);
757bff49 JC	340
	341	dwmci_writel(host, DWMCI_CLKENA, 0);
	342	dwmci_writel(host, DWMCI_CLKSRC, 0);
	343
	344	dwmci_writel(host, DWMCI_CLKDIV, div);
	345	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
	346	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
	347
	348	do {
	349	status = dwmci_readl(host, DWMCI_CMD);
	350	if (timeout-- < 0) {
1c87ffe8	351	debug("%s: Timeout!\n", __func__);
757bff49 JC	352	return -ETIMEDOUT;
	353	}
	354	} while (status & DWMCI_CMD_START);
	355
	356	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE \|
	357	DWMCI_CLKEN_LOW_PWR);
	358
	359	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
	360	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
	361
	362	timeout = 10000;
	363	do {
	364	status = dwmci_readl(host, DWMCI_CMD);
	365	if (timeout-- < 0) {
1c87ffe8	366	debug("%s: Timeout!\n", __func__);
757bff49 JC	367	return -ETIMEDOUT;
	368	}
	369	} while (status & DWMCI_CMD_START);
	370
	371	host->clock = freq;
	372
	373	return 0;
	374	}
	375
	376	static void dwmci_set_ios(struct mmc *mmc)
	377	{
045bdcd0 JC	378	struct dwmci_host host = (struct dwmci_host )mmc->priv;
045bdcd0 JC	379	u32 ctype, regs;
757bff49	380
f33c9305	381	debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
757bff49 JC	382
	383	dwmci_setup_bus(host, mmc->clock);
	384	switch (mmc->bus_width) {
	385	case 8:
	386	ctype = DWMCI_CTYPE_8BIT;
	387	break;
	388	case 4:
	389	ctype = DWMCI_CTYPE_4BIT;
	390	break;
	391	default:
	392	ctype = DWMCI_CTYPE_1BIT;
	393	break;
	394	}
	395
	396	dwmci_writel(host, DWMCI_CTYPE, ctype);
	397
045bdcd0	398	regs = dwmci_readl(host, DWMCI_UHS_REG);
2b8a9692	399	if (mmc->ddr_mode)
045bdcd0 JC	400	regs \|= DWMCI_DDR_MODE;
045bdcd0 JC	401	else
afc9e2b5	402	regs &= ~DWMCI_DDR_MODE;
045bdcd0 JC	403
	404	dwmci_writel(host, DWMCI_UHS_REG, regs);
	405
757bff49 JC	406	if (host->clksel)
	407	host->clksel(host);
	408	}
	409
	410	static int dwmci_init(struct mmc *mmc)
	411	{
93bfd616	412	struct dwmci_host *host = mmc->priv;
757bff49	413
18ab6755 JC	414	if (host->board_init)
18ab6755 JC	415	host->board_init(host);
6f0b7caa	416
757bff49 JC	417	dwmci_writel(host, DWMCI_PWREN, 1);
	418
	419	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
1c87ffe8 SG	420	debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
1c87ffe8 SG	421	return -EIO;
757bff49 JC	422	}
757bff49 JC	423
9c50e35f	424	/* Enumerate at 400KHz */
93bfd616	425	dwmci_setup_bus(host, mmc->cfg->f_min);
9c50e35f	426
757bff49 JC	427	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
	428	dwmci_writel(host, DWMCI_INTMASK, 0);
	429
	430	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
	431
	432	dwmci_writel(host, DWMCI_IDINTEN, 0);
	433	dwmci_writel(host, DWMCI_BMOD, 1);
	434
760177df SG	435	if (!host->fifoth_val) {
	436	uint32_t fifo_size;
	437
	438	fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
	439	fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
	440	host->fifoth_val = MSIZE(0x2) \| RX_WMARK(fifo_size / 2 - 1) \|
	441	TX_WMARK(fifo_size / 2);
9c50e35f	442	}
760177df	443	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
757bff49 JC	444
	445	dwmci_writel(host, DWMCI_CLKENA, 0);
	446	dwmci_writel(host, DWMCI_CLKSRC, 0);
	447
	448	return 0;
	449	}
	450
ab769f22 PA	451	static const struct mmc_ops dwmci_ops = {
	452	.send_cmd = dwmci_send_cmd,
	453	.set_ios = dwmci_set_ios,
	454	.init = dwmci_init,
	455	};
	456
757bff49 JC	457	int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
757bff49 JC	458	{
93bfd616 PA	459	host->cfg.name = host->name;
	460	host->cfg.ops = &dwmci_ops;
	461	host->cfg.f_min = min_clk;
	462	host->cfg.f_max = max_clk;
757bff49	463
93bfd616	464	host->cfg.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
757bff49	465
93bfd616	466	host->cfg.host_caps = host->caps;
757bff49 JC	467
757bff49 JC	468	if (host->buswidth == 8) {
93bfd616 PA	469	host->cfg.host_caps \|= MMC_MODE_8BIT;
93bfd616 PA	470	host->cfg.host_caps &= ~MMC_MODE_4BIT;
757bff49	471	} else {
93bfd616 PA	472	host->cfg.host_caps \|= MMC_MODE_4BIT;
93bfd616 PA	473	host->cfg.host_caps &= ~MMC_MODE_8BIT;
757bff49	474	}
5a20397b	475	host->cfg.host_caps \|= MMC_MODE_HS \| MMC_MODE_HS_52MHz;
93bfd616 PA	476
93bfd616 PA	477	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
757bff49	478
93bfd616 PA	479	host->mmc = mmc_create(&host->cfg, host);
	480	if (host->mmc == NULL)
	481	return -1;
757bff49	482
93bfd616	483	return 0;
757bff49	484	}