[people/ms/u-boot.git] / drivers / mmc / exynos_dw_mmc.c

/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Jaehoon Chung <jh80.chung@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dwmmc.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/pinmux.h>

#define	DWMMC_MAX_CH_NUM		4
#define	DWMMC_MAX_FREQ			52000000
#define	DWMMC_MIN_FREQ			400000
#define	DWMMC_MMC0_CLKSEL_VAL		0x03030001
#define	DWMMC_MMC2_CLKSEL_VAL		0x03020001

/*
 * Function used as callback function to initialise the
 * CLKSEL register for every mmc channel.
 */
static void exynos_dwmci_clksel(struct dwmci_host *host)
{
	dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
}

unsigned int exynos_dwmci_get_clk(int dev_index)
{
	return get_mmc_clk(dev_index);
}

/*
 * This function adds the mmc channel to be registered with mmc core.
 * index -	mmc channel number.
 * regbase -	register base address of mmc channel specified in 'index'.
 * bus_width -	operating bus width of mmc channel specified in 'index'.
 * clksel -	value to be written into CLKSEL register in case of FDT.
 *		NULL in case od non-FDT.
 */
int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
{
	struct dwmci_host *host = NULL;
	unsigned int div;
	unsigned long freq, sclk;
	host = malloc(sizeof(struct dwmci_host));
	if (!host) {
		printf("dwmci_host malloc fail!\n");
		return 1;
	}
	/* request mmc clock vlaue of 52MHz.  */
	freq = 52000000;
	sclk = get_mmc_clk(index);
	div = DIV_ROUND_UP(sclk, freq);
	/* set the clock divisor for mmc */
	set_mmc_clk(index, div);

	host->name = "EXYNOS DWMMC";
	host->ioaddr = (void *)regbase;
	host->buswidth = bus_width;
#ifdef CONFIG_EXYNOS5420
	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
#endif

	if (clksel) {
		host->clksel_val = clksel;
	} else {
		if (0 == index)
			host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
		if (2 == index)
			host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
	}

	host->clksel = exynos_dwmci_clksel;
	host->dev_index = index;
	host->get_mmc_clk = exynos_dwmci_get_clk;
	/* Add the mmc channel to be registered with mmc core */
	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
		debug("dwmmc%d registration failed\n", index);
		return -1;
	}
	return 0;
}

#ifdef CONFIG_OF_CONTROL
int exynos_dwmmc_init(const void *blob)
{
	int index, bus_width;
	int node_list[DWMMC_MAX_CH_NUM];
	int err = 0, dev_id, flag, count, i;
	u32 clksel_val, base, timing[3];

	count = fdtdec_find_aliases_for_id(blob, "mmc",
				COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
				DWMMC_MAX_CH_NUM);

	for (i = 0; i < count; i++) {
		int node = node_list[i];

		if (node <= 0)
			continue;

		/* Extract device id for each mmc channel */
		dev_id = pinmux_decode_periph_id(blob, node);

		/* Get the bus width from the device node */
		bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
		if (bus_width <= 0) {
			debug("DWMMC: Can't get bus-width\n");
			return -1;
		}
		if (8 == bus_width)
			flag = PINMUX_FLAG_8BIT_MODE;
		else
			flag = PINMUX_FLAG_NONE;

		/* config pinmux for each mmc channel */
		err = exynos_pinmux_config(dev_id, flag);
		if (err) {
			debug("DWMMC not configured\n");
			return err;
		}

		index = dev_id - PERIPH_ID_SDMMC0;

		/* Get the base address from the device node */
		base = fdtdec_get_addr(blob, node, "reg");
		if (!base) {
			debug("DWMMC: Can't get base address\n");
			return -1;
		}
		/* Extract the timing info from the node */
		err = fdtdec_get_int_array(blob, node, "samsung,timing",
					timing, 3);
		if (err) {
			debug("Can't get sdr-timings for divider\n");
			return -1;
		}

		clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
				DWMCI_SET_DRV_CLK(timing[1]) |
				DWMCI_SET_DIV_RATIO(timing[2]));
		/* Initialise each mmc channel */
		err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
		if (err)
			debug("dwmmc Channel-%d init failed\n", index);
	}
	return 0;
}
#endif
Commit	Line	Data
d0ebbb8d JC	1	/*
	2	* (C) Copyright 2012 SAMSUNG Electronics
	3	* Jaehoon Chung <jh80.chung@samsung.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
d0ebbb8d JC	6	*/
	7
	8	#include <common.h>
d0ebbb8d	9	#include <dwmmc.h>
a082a2dd A	10	#include <fdtdec.h>
	11	#include <libfdt.h>
	12	#include <malloc.h>
d0ebbb8d JC	13	#include <asm/arch/dwmmc.h>
d0ebbb8d JC	14	#include <asm/arch/clk.h>
a082a2dd	15	#include <asm/arch/pinmux.h>
d0ebbb8d	16
a082a2dd A	17	#define DWMMC_MAX_CH_NUM 4
	18	#define DWMMC_MAX_FREQ 52000000
	19	#define DWMMC_MIN_FREQ 400000
	20	#define DWMMC_MMC0_CLKSEL_VAL 0x03030001
	21	#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
d0ebbb8d	22
a082a2dd A	23	/*
	24	* Function used as callback function to initialise the
	25	* CLKSEL register for every mmc channel.
	26	*/
d0ebbb8d JC	27	static void exynos_dwmci_clksel(struct dwmci_host *host)
d0ebbb8d JC	28	{
a082a2dd A	29	dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
a082a2dd A	30	}
d0ebbb8d	31
a082a2dd A	32	unsigned int exynos_dwmci_get_clk(int dev_index)
	33	{
	34	return get_mmc_clk(dev_index);
d0ebbb8d JC	35	}
d0ebbb8d JC	36
a082a2dd A	37	/*
	38	* This function adds the mmc channel to be registered with mmc core.
	39	* index - mmc channel number.
	40	* regbase - register base address of mmc channel specified in 'index'.
	41	* bus_width - operating bus width of mmc channel specified in 'index'.
	42	* clksel - value to be written into CLKSEL register in case of FDT.
	43	* NULL in case od non-FDT.
	44	*/
	45	int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
d0ebbb8d JC	46	{
d0ebbb8d JC	47	struct dwmci_host *host = NULL;
a082a2dd A	48	unsigned int div;
a082a2dd A	49	unsigned long freq, sclk;
d0ebbb8d JC	50	host = malloc(sizeof(struct dwmci_host));
	51	if (!host) {
	52	printf("dwmci_host malloc fail!\n");
	53	return 1;
	54	}
a082a2dd A	55	/* request mmc clock vlaue of 52MHz. */
	56	freq = 52000000;
	57	sclk = get_mmc_clk(index);
	58	div = DIV_ROUND_UP(sclk, freq);
	59	/* set the clock divisor for mmc */
	60	set_mmc_clk(index, div);
d0ebbb8d	61
a082a2dd	62	host->name = "EXYNOS DWMMC";
d0ebbb8d JC	63	host->ioaddr = (void *)regbase;
d0ebbb8d JC	64	host->buswidth = bus_width;
6f0b7caa RS	65	#ifdef CONFIG_EXYNOS5420
	66	host->quirks = DWMCI_QUIRK_DISABLE_SMU;
	67	#endif
a082a2dd A	68
	69	if (clksel) {
	70	host->clksel_val = clksel;
	71	} else {
	72	if (0 == index)
	73	host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
	74	if (2 == index)
	75	host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
	76	}
	77
d0ebbb8d JC	78	host->clksel = exynos_dwmci_clksel;
d0ebbb8d JC	79	host->dev_index = index;
b44fe83a	80	host->get_mmc_clk = exynos_dwmci_get_clk;
a082a2dd A	81	/* Add the mmc channel to be registered with mmc core */
	82	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
	83	debug("dwmmc%d registration failed\n", index);
	84	return -1;
	85	}
	86	return 0;
	87	}
	88
	89	#ifdef CONFIG_OF_CONTROL
	90	int exynos_dwmmc_init(const void *blob)
	91	{
	92	int index, bus_width;
	93	int node_list[DWMMC_MAX_CH_NUM];
	94	int err = 0, dev_id, flag, count, i;
	95	u32 clksel_val, base, timing[3];
	96
	97	count = fdtdec_find_aliases_for_id(blob, "mmc",
	98	COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
	99	DWMMC_MAX_CH_NUM);
	100
	101	for (i = 0; i < count; i++) {
	102	int node = node_list[i];
	103
	104	if (node <= 0)
	105	continue;
d0ebbb8d	106
a082a2dd A	107	/* Extract device id for each mmc channel */
a082a2dd A	108	dev_id = pinmux_decode_periph_id(blob, node);
d0ebbb8d	109
a082a2dd A	110	/* Get the bus width from the device node */
	111	bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
	112	if (bus_width <= 0) {
	113	debug("DWMMC: Can't get bus-width\n");
	114	return -1;
	115	}
	116	if (8 == bus_width)
	117	flag = PINMUX_FLAG_8BIT_MODE;
	118	else
	119	flag = PINMUX_FLAG_NONE;
	120
	121	/* config pinmux for each mmc channel */
	122	err = exynos_pinmux_config(dev_id, flag);
	123	if (err) {
	124	debug("DWMMC not configured\n");
	125	return err;
	126	}
	127
	128	index = dev_id - PERIPH_ID_SDMMC0;
	129
	130	/* Get the base address from the device node */
	131	base = fdtdec_get_addr(blob, node, "reg");
	132	if (!base) {
	133	debug("DWMMC: Can't get base address\n");
	134	return -1;
	135	}
	136	/* Extract the timing info from the node */
	137	err = fdtdec_get_int_array(blob, node, "samsung,timing",
	138	timing, 3);
	139	if (err) {
	140	debug("Can't get sdr-timings for divider\n");
	141	return -1;
	142	}
	143
	144	clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) \|
	145	DWMCI_SET_DRV_CLK(timing[1]) \|
	146	DWMCI_SET_DIV_RATIO(timing[2]));
	147	/* Initialise each mmc channel */
	148	err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
	149	if (err)
	150	debug("dwmmc Channel-%d init failed\n", index);
	151	}
d0ebbb8d JC	152	return 0;
d0ebbb8d JC	153	}
a082a2dd	154	#endif