[people/ms/u-boot.git] / drivers / mmc / fsl_esdhc.c

/*
 * Copyright 2007, Freescale Semiconductor, Inc
 * Andy Fleming
 *
 * Based vaguely on the pxa mmc code:
 * (C) Copyright 2003
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <command.h>
#include <hwconfig.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fdt_support.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

struct fsl_esdhc {
	uint	dsaddr;
	uint	blkattr;
	uint	cmdarg;
	uint	xfertyp;
	uint	cmdrsp0;
	uint	cmdrsp1;
	uint	cmdrsp2;
	uint	cmdrsp3;
	uint	datport;
	uint	prsstat;
	uint	proctl;
	uint	sysctl;
	uint	irqstat;
	uint	irqstaten;
	uint	irqsigen;
	uint	autoc12err;
	uint	hostcapblt;
	uint	wml;
	char	reserved1[8];
	uint	fevt;
	char	reserved2[168];
	uint	hostver;
	char	reserved3[780];
	uint	scr;
};

/* Return the XFERTYP flags for a given command and data packet */
uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
{
	uint xfertyp = 0;

	if (data) {
		xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN;

		if (data->blocks > 1) {
			xfertyp |= XFERTYP_MSBSEL;
			xfertyp |= XFERTYP_BCEN;
		}

		if (data->flags & MMC_DATA_READ)
			xfertyp |= XFERTYP_DTDSEL;
	}

	if (cmd->resp_type & MMC_RSP_CRC)
		xfertyp |= XFERTYP_CCCEN;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		xfertyp |= XFERTYP_CICEN;
	if (cmd->resp_type & MMC_RSP_136)
		xfertyp |= XFERTYP_RSPTYP_136;
	else if (cmd->resp_type & MMC_RSP_BUSY)
		xfertyp |= XFERTYP_RSPTYP_48_BUSY;
	else if (cmd->resp_type & MMC_RSP_PRESENT)
		xfertyp |= XFERTYP_RSPTYP_48;

	return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
}

static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
{
	uint wml_value;
	int timeout;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;

	wml_value = data->blocksize/4;

	if (data->flags & MMC_DATA_READ) {
		if (wml_value > 0x10)
			wml_value = 0x10;

		wml_value = 0x100000 | wml_value;

		esdhc_write32(&regs->dsaddr, (u32)data->dest);
	} else {
		if (wml_value > 0x80)
			wml_value = 0x80;
		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
			printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
			return TIMEOUT;
		}
		wml_value = wml_value << 16 | 0x10;
		esdhc_write32(&regs->dsaddr, (u32)data->src);
	}

	esdhc_write32(&regs->wml, wml_value);

	esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);

	/* Calculate the timeout period for data transactions */
	timeout = fls(mmc->tran_speed/10) - 1;
	timeout -= 13;

	if (timeout > 14)
		timeout = 14;

	if (timeout < 0)
		timeout = 0;

	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);

	return 0;
}


/*
 * Sends a command out on the bus.  Takes the mmc pointer,
 * a command pointer, and an optional data pointer.
 */
static int
esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
	uint	xfertyp;
	uint	irqstat;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;

	esdhc_write32(&regs->irqstat, -1);

	sync();

	/* Wait for the bus to be idle */
	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
		;

	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
		;

	/* Wait at least 8 SD clock cycles before the next command */
	/*
	 * Note: This is way more than 8 cycles, but 1ms seems to
	 * resolve timing issues with some cards
	 */
	udelay(1000);

	/* Set up for a data transfer if we have one */
	if (data) {
		int err;

		err = esdhc_setup_data(mmc, data);
		if(err)
			return err;
	}

	/* Figure out the transfer arguments */
	xfertyp = esdhc_xfertyp(cmd, data);

	/* Send the command */
	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
	esdhc_write32(&regs->xfertyp, xfertyp);

	/* Wait for the command to complete */
	while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
		;

	irqstat = esdhc_read32(&regs->irqstat);
	esdhc_write32(&regs->irqstat, irqstat);

	if (irqstat & CMD_ERR)
		return COMM_ERR;

	if (irqstat & IRQSTAT_CTOE)
		return TIMEOUT;

	/* Copy the response to the response buffer */
	if (cmd->resp_type & MMC_RSP_136) {
		u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;

		cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
		cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
		cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
		cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
		cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
		cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
		cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
		cmd->response[3] = (cmdrsp0 << 8);
	} else
		cmd->response[0] = esdhc_read32(&regs->cmdrsp0);

	/* Wait until all of the blocks are transferred */
	if (data) {
		do {
			irqstat = esdhc_read32(&regs->irqstat);

			if (irqstat & DATA_ERR)
				return COMM_ERR;

			if (irqstat & IRQSTAT_DTOE)
				return TIMEOUT;
		} while (!(irqstat & IRQSTAT_TC) &&
				(esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
	}

	esdhc_write32(&regs->irqstat, -1);

	return 0;
}

void set_sysctl(struct mmc *mmc, uint clock)
{
	int sdhc_clk = gd->sdhc_clk;
	int div, pre_div;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	uint clk;

	if (clock < mmc->f_min)
		clock = mmc->f_min;

	if (sdhc_clk / 16 > clock) {
		for (pre_div = 2; pre_div < 256; pre_div *= 2)
			if ((sdhc_clk / pre_div) <= (clock * 16))
				break;
	} else
		pre_div = 2;

	for (div = 1; div <= 16; div++)
		if ((sdhc_clk / (div * pre_div)) <= clock)
			break;

	pre_div >>= 1;
	div -= 1;

	clk = (pre_div << 8) | (div << 4);

	/* On imx the clock must be stopped before changing frequency */
	if (cfg->clk_enable)
		esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);

	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);

	udelay(10000);

	clk = SYSCTL_PEREN;
	/* On imx systems the clock must be explicitely enabled */
	if (cfg->clk_enable)
		clk |= SYSCTL_CKEN;

	esdhc_setbits32(&regs->sysctl, clk);
}

static void esdhc_set_ios(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;

	/* Set the clock speed */
	set_sysctl(mmc, mmc->clock);

	/* Set the bus width */
	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);

	if (mmc->bus_width == 4)
		esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
	else if (mmc->bus_width == 8)
		esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);

}

static int esdhc_init(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	int timeout = 1000;
	int ret = 0;
	u8 card_absent;

	/* Enable cache snooping */
	if (cfg && !cfg->no_snoop)
		esdhc_write32(&regs->scr, 0x00000040);

	/* Reset the entire host controller */
	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);

	/* Wait until the controller is available */
	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
		udelay(1000);

	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);

	/* Set the initial clock speed */
	set_sysctl(mmc, 400000);

	/* Disable the BRR and BWR bits in IRQSTAT */
	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);

	/* Put the PROCTL reg back to the default */
	esdhc_write32(&regs->proctl, PROCTL_INIT);

	/* Set timout to the maximum value */
	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);

	/* Check if there is a callback for detecting the card */
	if (board_mmc_getcd(&card_absent, mmc)) {
		timeout = 1000;
		while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) &&
				--timeout)
			udelay(1000);

		if (timeout <= 0)
			ret = NO_CARD_ERR;
	} else {
		if (card_absent)
			ret = NO_CARD_ERR;
	}

	return ret;
}

int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
	struct fsl_esdhc *regs;
	struct mmc *mmc;
	u32 caps;

	if (!cfg)
		return -1;

	mmc = malloc(sizeof(struct mmc));

	sprintf(mmc->name, "FSL_ESDHC");
	regs = (struct fsl_esdhc *)cfg->esdhc_base;

	mmc->priv = cfg;
	mmc->send_cmd = esdhc_send_cmd;
	mmc->set_ios = esdhc_set_ios;
	mmc->init = esdhc_init;

	caps = regs->hostcapblt;

	if (caps & ESDHC_HOSTCAPBLT_VS18)
		mmc->voltages |= MMC_VDD_165_195;
	if (caps & ESDHC_HOSTCAPBLT_VS30)
		mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
	if (caps & ESDHC_HOSTCAPBLT_VS33)
		mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;

	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;

	if (caps & ESDHC_HOSTCAPBLT_HSS)
		mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;

	mmc->f_min = 400000;
	mmc->f_max = MIN(gd->sdhc_clk, 50000000);

	mmc_register(mmc);

	return 0;
}

int fsl_esdhc_mmc_init(bd_t *bis)
{
	struct fsl_esdhc_cfg *cfg;

	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
	return fsl_esdhc_initialize(bis, cfg);
}

#ifdef CONFIG_OF_LIBFDT
void fdt_fixup_esdhc(void *blob, bd_t *bd)
{
	const char *compat = "fsl,esdhc";
	const char *status = "okay";

	if (!hwconfig("esdhc")) {
		status = "disabled";
		goto out;
	}

	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
			       gd->sdhc_clk, 1);
out:
	do_fixup_by_compat(blob, compat, "status", status,
			   strlen(status) + 1, 1);
}
#endif
Commit	Line	Data
50586ef2 AF	1	/*
	2	* Copyright 2007, Freescale Semiconductor, Inc
	3	* Andy Fleming
	4	*
	5	* Based vaguely on the pxa mmc code:
	6	* (C) Copyright 2003
	7	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <config.h>
	29	#include <common.h>
	30	#include <command.h>
b33433a6	31	#include <hwconfig.h>
50586ef2 AF	32	#include <mmc.h>
	33	#include <part.h>
	34	#include <malloc.h>
	35	#include <mmc.h>
	36	#include <fsl_esdhc.h>
b33433a6	37	#include <fdt_support.h>
50586ef2 AF	38	#include <asm/io.h>
50586ef2 AF	39
50586ef2 AF	40	DECLARE_GLOBAL_DATA_PTR;
	41
	42	struct fsl_esdhc {
	43	uint dsaddr;
	44	uint blkattr;
	45	uint cmdarg;
	46	uint xfertyp;
	47	uint cmdrsp0;
	48	uint cmdrsp1;
	49	uint cmdrsp2;
	50	uint cmdrsp3;
	51	uint datport;
	52	uint prsstat;
	53	uint proctl;
	54	uint sysctl;
	55	uint irqstat;
	56	uint irqstaten;
	57	uint irqsigen;
	58	uint autoc12err;
	59	uint hostcapblt;
	60	uint wml;
	61	char reserved1[8];
	62	uint fevt;
	63	char reserved2[168];
	64	uint hostver;
	65	char reserved3[780];
	66	uint scr;
	67	};
	68
	69	/* Return the XFERTYP flags for a given command and data packet */
	70	uint esdhc_xfertyp(struct mmc_cmd cmd, struct mmc_data data)
	71	{
	72	uint xfertyp = 0;
	73
	74	if (data) {
	75	xfertyp \|= XFERTYP_DPSEL \| XFERTYP_DMAEN;
	76
	77	if (data->blocks > 1) {
	78	xfertyp \|= XFERTYP_MSBSEL;
	79	xfertyp \|= XFERTYP_BCEN;
	80	}
	81
	82	if (data->flags & MMC_DATA_READ)
	83	xfertyp \|= XFERTYP_DTDSEL;
	84	}
	85
	86	if (cmd->resp_type & MMC_RSP_CRC)
	87	xfertyp \|= XFERTYP_CCCEN;
	88	if (cmd->resp_type & MMC_RSP_OPCODE)
	89	xfertyp \|= XFERTYP_CICEN;
	90	if (cmd->resp_type & MMC_RSP_136)
	91	xfertyp \|= XFERTYP_RSPTYP_136;
	92	else if (cmd->resp_type & MMC_RSP_BUSY)
	93	xfertyp \|= XFERTYP_RSPTYP_48_BUSY;
	94	else if (cmd->resp_type & MMC_RSP_PRESENT)
	95	xfertyp \|= XFERTYP_RSPTYP_48;
	96
	97	return XFERTYP_CMD(cmd->cmdidx) \| xfertyp;
	98	}
	99
	100	static int esdhc_setup_data(struct mmc mmc, struct mmc_data data)
	101	{
	102	uint wml_value;
	103	int timeout;
c67bee14 SB	104	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	105	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2 AF	106
	107	wml_value = data->blocksize/4;
	108
	109	if (data->flags & MMC_DATA_READ) {
	110	if (wml_value > 0x10)
	111	wml_value = 0x10;
	112
	113	wml_value = 0x100000 \| wml_value;
	114
c67bee14	115	esdhc_write32(&regs->dsaddr, (u32)data->dest);
50586ef2 AF	116	} else {
	117	if (wml_value > 0x80)
	118	wml_value = 0x80;
c67bee14	119	if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
50586ef2 AF	120	printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
	121	return TIMEOUT;
	122	}
	123	wml_value = wml_value << 16 \| 0x10;
c67bee14	124	esdhc_write32(&regs->dsaddr, (u32)data->src);
50586ef2 AF	125	}
50586ef2 AF	126
c67bee14	127	esdhc_write32(&regs->wml, wml_value);
50586ef2	128
c67bee14	129	esdhc_write32(&regs->blkattr, data->blocks << 16 \| data->blocksize);
50586ef2 AF	130
50586ef2 AF	131	/* Calculate the timeout period for data transactions */
c67bee14	132	timeout = fls(mmc->tran_speed/10) - 1;
50586ef2 AF	133	timeout -= 13;
	134
	135	if (timeout > 14)
	136	timeout = 14;
	137
	138	if (timeout < 0)
	139	timeout = 0;
	140
c67bee14	141	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
50586ef2 AF	142
	143	return 0;
	144	}
	145
	146
	147	/*
	148	* Sends a command out on the bus. Takes the mmc pointer,
	149	* a command pointer, and an optional data pointer.
	150	*/
	151	static int
	152	esdhc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)
	153	{
	154	uint xfertyp;
	155	uint irqstat;
c67bee14 SB	156	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	157	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2	158
c67bee14	159	esdhc_write32(&regs->irqstat, -1);
50586ef2 AF	160
	161	sync();
	162
	163	/* Wait for the bus to be idle */
c67bee14 SB	164	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) \|\|
	165	(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
	166	;
50586ef2	167
c67bee14 SB	168	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
c67bee14 SB	169	;
50586ef2 AF	170
	171	/* Wait at least 8 SD clock cycles before the next command */
	172	/*
	173	* Note: This is way more than 8 cycles, but 1ms seems to
	174	* resolve timing issues with some cards
	175	*/
	176	udelay(1000);
	177
	178	/* Set up for a data transfer if we have one */
	179	if (data) {
	180	int err;
	181
	182	err = esdhc_setup_data(mmc, data);
	183	if(err)
	184	return err;
	185	}
	186
	187	/* Figure out the transfer arguments */
	188	xfertyp = esdhc_xfertyp(cmd, data);
	189
	190	/* Send the command */
c67bee14 SB	191	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
c67bee14 SB	192	esdhc_write32(&regs->xfertyp, xfertyp);
50586ef2 AF	193
50586ef2 AF	194	/* Wait for the command to complete */
c67bee14 SB	195	while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
c67bee14 SB	196	;
50586ef2	197
c67bee14 SB	198	irqstat = esdhc_read32(&regs->irqstat);
c67bee14 SB	199	esdhc_write32(&regs->irqstat, irqstat);
50586ef2 AF	200
	201	if (irqstat & CMD_ERR)
	202	return COMM_ERR;
	203
	204	if (irqstat & IRQSTAT_CTOE)
	205	return TIMEOUT;
	206
	207	/* Copy the response to the response buffer */
	208	if (cmd->resp_type & MMC_RSP_136) {
	209	u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
	210
c67bee14 SB	211	cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
	212	cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
	213	cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
	214	cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
998be3dd RV	215	cmd->response[0] = (cmdrsp3 << 8) \| (cmdrsp2 >> 24);
	216	cmd->response[1] = (cmdrsp2 << 8) \| (cmdrsp1 >> 24);
	217	cmd->response[2] = (cmdrsp1 << 8) \| (cmdrsp0 >> 24);
	218	cmd->response[3] = (cmdrsp0 << 8);
50586ef2	219	} else
c67bee14	220	cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
50586ef2 AF	221
	222	/* Wait until all of the blocks are transferred */
	223	if (data) {
	224	do {
c67bee14	225	irqstat = esdhc_read32(&regs->irqstat);
50586ef2 AF	226
	227	if (irqstat & DATA_ERR)
	228	return COMM_ERR;
	229
	230	if (irqstat & IRQSTAT_DTOE)
	231	return TIMEOUT;
	232	} while (!(irqstat & IRQSTAT_TC) &&
c67bee14	233	(esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
50586ef2 AF	234	}
50586ef2 AF	235
c67bee14	236	esdhc_write32(&regs->irqstat, -1);
50586ef2 AF	237
	238	return 0;
	239	}
	240
	241	void set_sysctl(struct mmc *mmc, uint clock)
	242	{
	243	int sdhc_clk = gd->sdhc_clk;
	244	int div, pre_div;
c67bee14 SB	245	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	246	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2 AF	247	uint clk;
50586ef2 AF	248
c67bee14 SB	249	if (clock < mmc->f_min)
	250	clock = mmc->f_min;
	251
50586ef2 AF	252	if (sdhc_clk / 16 > clock) {
	253	for (pre_div = 2; pre_div < 256; pre_div *= 2)
	254	if ((sdhc_clk / pre_div) <= (clock * 16))
	255	break;
	256	} else
	257	pre_div = 2;
	258
	259	for (div = 1; div <= 16; div++)
	260	if ((sdhc_clk / (div * pre_div)) <= clock)
	261	break;
	262
	263	pre_div >>= 1;
	264	div -= 1;
	265
	266	clk = (pre_div << 8) \| (div << 4);
	267
c67bee14 SB	268	/* On imx the clock must be stopped before changing frequency */
	269	if (cfg->clk_enable)
	270	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
	271
	272	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
50586ef2 AF	273
	274	udelay(10000);
	275
c67bee14 SB	276	clk = SYSCTL_PEREN;
	277	/* On imx systems the clock must be explicitely enabled */
	278	if (cfg->clk_enable)
	279	clk \|= SYSCTL_CKEN;
	280
	281	esdhc_setbits32(&regs->sysctl, clk);
50586ef2 AF	282	}
	283
	284	static void esdhc_set_ios(struct mmc *mmc)
	285	{
c67bee14 SB	286	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	287	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2 AF	288
	289	/* Set the clock speed */
	290	set_sysctl(mmc, mmc->clock);
	291
	292	/* Set the bus width */
c67bee14	293	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 \| PROCTL_DTW_8);
50586ef2 AF	294
50586ef2 AF	295	if (mmc->bus_width == 4)
c67bee14	296	esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
50586ef2	297	else if (mmc->bus_width == 8)
c67bee14 SB	298	esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
c67bee14 SB	299
50586ef2 AF	300	}
	301
	302	static int esdhc_init(struct mmc *mmc)
	303	{
c67bee14 SB	304	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	305	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2	306	int timeout = 1000;
c67bee14 SB	307	int ret = 0;
c67bee14 SB	308	u8 card_absent;
50586ef2 AF	309
50586ef2 AF	310	/* Enable cache snooping */
c67bee14 SB	311	if (cfg && !cfg->no_snoop)
	312	esdhc_write32(&regs->scr, 0x00000040);
	313
	314	/* Reset the entire host controller */
	315	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
	316
	317	/* Wait until the controller is available */
	318	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
	319	udelay(1000);
50586ef2	320
c67bee14	321	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN \| SYSCTL_IPGEN);
50586ef2 AF	322
	323	/* Set the initial clock speed */
	324	set_sysctl(mmc, 400000);
	325
	326	/* Disable the BRR and BWR bits in IRQSTAT */
c67bee14	327	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR \| IRQSTATEN_BWR);
50586ef2 AF	328
50586ef2 AF	329	/* Put the PROCTL reg back to the default */
c67bee14	330	esdhc_write32(&regs->proctl, PROCTL_INIT);
50586ef2	331
c67bee14 SB	332	/* Set timout to the maximum value */
c67bee14 SB	333	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
50586ef2	334
c67bee14 SB	335	/* Check if there is a callback for detecting the card */
	336	if (board_mmc_getcd(&card_absent, mmc)) {
	337	timeout = 1000;
	338	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) &&
	339	--timeout)
	340	udelay(1000);
50586ef2	341
c67bee14 SB	342	if (timeout <= 0)
	343	ret = NO_CARD_ERR;
	344	} else {
	345	if (card_absent)
	346	ret = NO_CARD_ERR;
	347	}
	348
	349	return ret;
50586ef2 AF	350	}
50586ef2 AF	351
c67bee14	352	int fsl_esdhc_initialize(bd_t bis, struct fsl_esdhc_cfg cfg)
50586ef2	353	{
c67bee14	354	struct fsl_esdhc *regs;
50586ef2 AF	355	struct mmc *mmc;
	356	u32 caps;
	357
c67bee14 SB	358	if (!cfg)
	359	return -1;
	360
50586ef2 AF	361	mmc = malloc(sizeof(struct mmc));
	362
	363	sprintf(mmc->name, "FSL_ESDHC");
c67bee14 SB	364	regs = (struct fsl_esdhc *)cfg->esdhc_base;
	365
	366	mmc->priv = cfg;
50586ef2 AF	367	mmc->send_cmd = esdhc_send_cmd;
	368	mmc->set_ios = esdhc_set_ios;
	369	mmc->init = esdhc_init;
	370
	371	caps = regs->hostcapblt;
	372
	373	if (caps & ESDHC_HOSTCAPBLT_VS18)
	374	mmc->voltages \|= MMC_VDD_165_195;
	375	if (caps & ESDHC_HOSTCAPBLT_VS30)
	376	mmc->voltages \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
	377	if (caps & ESDHC_HOSTCAPBLT_VS33)
	378	mmc->voltages \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
	379
	380	mmc->host_caps = MMC_MODE_4BIT \| MMC_MODE_8BIT;
	381
	382	if (caps & ESDHC_HOSTCAPBLT_HSS)
	383	mmc->host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS;
	384
	385	mmc->f_min = 400000;
	386	mmc->f_max = MIN(gd->sdhc_clk, 50000000);
	387
	388	mmc_register(mmc);
	389
	390	return 0;
	391	}
	392
	393	int fsl_esdhc_mmc_init(bd_t *bis)
	394	{
c67bee14 SB	395	struct fsl_esdhc_cfg *cfg;
	396
	397	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
	398	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
	399	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
	400	return fsl_esdhc_initialize(bis, cfg);
50586ef2	401	}
b33433a6	402
c67bee14	403	#ifdef CONFIG_OF_LIBFDT
b33433a6 AV	404	void fdt_fixup_esdhc(void blob, bd_t bd)
	405	{
	406	const char *compat = "fsl,esdhc";
	407	const char *status = "okay";
	408
	409	if (!hwconfig("esdhc")) {
	410	status = "disabled";
	411	goto out;
	412	}
	413
	414	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
	415	gd->sdhc_clk, 1);
	416	out:
	417	do_fixup_by_compat(blob, compat, "status", status,
	418	strlen(status) + 1, 1);
	419	}
c67bee14	420	#endif