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[thirdparty/u-boot.git] / drivers / mmc / fsl_esdhc_imx.c
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fa33d207
YL		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
5 * Andy Fleming
6 * Yangbo Lu <yangbo.lu@nxp.com>
7 *
8 * Based vaguely on the pxa mmc code:
9 * (C) Copyright 2003
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
11 */
12
13#include <config.h>
14#include <common.h>
15#include <command.h>
16#include <clk.h>
1eb69ae4 17#include <cpu_func.h>
fa33d207
YL		 18#include <errno.h>
19#include <hwconfig.h>
20#include <mmc.h>
21#include <part.h>
90526e9f 22#include <asm/cache.h>
336d4615 23#include <dm/device_compat.h>
61b29b82 24#include <linux/err.h>
fa33d207
YL		 25#include <power/regulator.h>
26#include <malloc.h>
27#include <fsl_esdhc_imx.h>
28#include <fdt_support.h>
29#include <asm/io.h>
30#include <dm.h>
31#include <asm-generic/gpio.h>
32#include <dm/pinctrl.h>
33
34#if !CONFIG_IS_ENABLED(BLK)
35#include "mmc_private.h"
36#endif
37
38DECLARE_GLOBAL_DATA_PTR;
39
40#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
41 IRQSTATEN_CINT | \
42 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
43 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
44 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
45 IRQSTATEN_DINT)
46#define MAX_TUNING_LOOP 40
47#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
48
49struct fsl_esdhc {
50 uint dsaddr; /* SDMA system address register */
51 uint blkattr; /* Block attributes register */
52 uint cmdarg; /* Command argument register */
53 uint xfertyp; /* Transfer type register */
54 uint cmdrsp0; /* Command response 0 register */
55 uint cmdrsp1; /* Command response 1 register */
56 uint cmdrsp2; /* Command response 2 register */
57 uint cmdrsp3; /* Command response 3 register */
58 uint datport; /* Buffer data port register */
59 uint prsstat; /* Present state register */
60 uint proctl; /* Protocol control register */
61 uint sysctl; /* System Control Register */
62 uint irqstat; /* Interrupt status register */
63 uint irqstaten; /* Interrupt status enable register */
64 uint irqsigen; /* Interrupt signal enable register */
65 uint autoc12err; /* Auto CMD error status register */
66 uint hostcapblt; /* Host controller capabilities register */
67 uint wml; /* Watermark level register */
68 uint mixctrl; /* For USDHC */
69 char reserved1[4]; /* reserved */
70 uint fevt; /* Force event register */
71 uint admaes; /* ADMA error status register */
72 uint adsaddr; /* ADMA system address register */
73 char reserved2[4];
74 uint dllctrl;
75 uint dllstat;
76 uint clktunectrlstatus;
77 char reserved3[4];
78 uint strobe_dllctrl;
79 uint strobe_dllstat;
80 char reserved4[72];
81 uint vendorspec;
82 uint mmcboot;
83 uint vendorspec2;
6a63a873 84 uint tuning_ctrl; /* on i.MX6/7/8/RT */
fa33d207
YL		 85 char reserved5[44];
86 uint hostver; /* Host controller version register */
87 char reserved6[4]; /* reserved */
88 uint dmaerraddr; /* DMA error address register */
89 char reserved7[4]; /* reserved */
90 uint dmaerrattr; /* DMA error attribute register */
91 char reserved8[4]; /* reserved */
92 uint hostcapblt2; /* Host controller capabilities register 2 */
93 char reserved9[8]; /* reserved */
94 uint tcr; /* Tuning control register */
95 char reserved10[28]; /* reserved */
96 uint sddirctl; /* SD direction control register */
97 char reserved11[712];/* reserved */
98 uint scr; /* eSDHC control register */
99};
100
101struct fsl_esdhc_plat {
102 struct mmc_config cfg;
103 struct mmc mmc;
104};
105
106struct esdhc_soc_data {
107 u32 flags;
fa33d207
YL		 108};
109
110/**
111 * struct fsl_esdhc_priv
112 *
113 * @esdhc_regs: registers of the sdhc controller
114 * @sdhc_clk: Current clk of the sdhc controller
115 * @bus_width: bus width, 1bit, 4bit or 8bit
116 * @cfg: mmc config
117 * @mmc: mmc
118 * Following is used when Driver Model is enabled for MMC
119 * @dev: pointer for the device
120 * @non_removable: 0: removable; 1: non-removable
29230f38 121 * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
fa33d207
YL		 122 * @wp_enable: 1: enable checking wp; 0: no check
123 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
124 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
125 * @caps: controller capabilities
126 * @tuning_step: tuning step setting in tuning_ctrl register
127 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
128 * @strobe_dll_delay_target: settings in strobe_dllctrl
129 * @signal_voltage: indicating the current voltage
130 * @cd_gpio: gpio for card detection
131 * @wp_gpio: gpio for write protection
132 */
133struct fsl_esdhc_priv {
134 struct fsl_esdhc *esdhc_regs;
135 unsigned int sdhc_clk;
136 struct clk per_clk;
137 unsigned int clock;
138 unsigned int mode;
139 unsigned int bus_width;
140#if !CONFIG_IS_ENABLED(BLK)
141 struct mmc *mmc;
142#endif
143 struct udevice *dev;
144 int non_removable;
29230f38 145 int broken_cd;
fa33d207
YL		 146 int wp_enable;
147 int vs18_enable;
148 u32 flags;
149 u32 caps;
150 u32 tuning_step;
151 u32 tuning_start_tap;
152 u32 strobe_dll_delay_target;
153 u32 signal_voltage;
82771716 154#if CONFIG_IS_ENABLED(DM_REGULATOR)
fa33d207
YL		 155 struct udevice *vqmmc_dev;
156 struct udevice *vmmc_dev;
157#endif
bcee8d67 158#if CONFIG_IS_ENABLED(DM_GPIO)
fa33d207
YL		 159 struct gpio_desc cd_gpio;
160 struct gpio_desc wp_gpio;
161#endif
162};
163
164/* Return the XFERTYP flags for a given command and data packet */
165static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
166{
167 uint xfertyp = 0;
168
169 if (data) {
170 xfertyp |= XFERTYP_DPSEL;
171#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
172 xfertyp |= XFERTYP_DMAEN;
173#endif
174 if (data->blocks > 1) {
175 xfertyp |= XFERTYP_MSBSEL;
176 xfertyp |= XFERTYP_BCEN;
177#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
178 xfertyp |= XFERTYP_AC12EN;
179#endif
180 }
181
182 if (data->flags & MMC_DATA_READ)
183 xfertyp |= XFERTYP_DTDSEL;
184 }
185
186 if (cmd->resp_type & MMC_RSP_CRC)
187 xfertyp |= XFERTYP_CCCEN;
188 if (cmd->resp_type & MMC_RSP_OPCODE)
189 xfertyp |= XFERTYP_CICEN;
190 if (cmd->resp_type & MMC_RSP_136)
191 xfertyp |= XFERTYP_RSPTYP_136;
192 else if (cmd->resp_type & MMC_RSP_BUSY)
193 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
194 else if (cmd->resp_type & MMC_RSP_PRESENT)
195 xfertyp |= XFERTYP_RSPTYP_48;
196
197 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
198 xfertyp |= XFERTYP_CMDTYP_ABORT;
199
200 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
201}
202
203#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
204/*
205 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
206 */
207static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
208 struct mmc_data *data)
209{
210 struct fsl_esdhc *regs = priv->esdhc_regs;
211 uint blocks;
212 char *buffer;
213 uint databuf;
214 uint size;
215 uint irqstat;
216 ulong start;
217
218 if (data->flags & MMC_DATA_READ) {
219 blocks = data->blocks;
220 buffer = data->dest;
221 while (blocks) {
222 start = get_timer(0);
223 size = data->blocksize;
224 irqstat = esdhc_read32(&regs->irqstat);
225 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
226 if (get_timer(start) > PIO_TIMEOUT) {
227 printf("\nData Read Failed in PIO Mode.");
228 return;
229 }
230 }
231 while (size && (!(irqstat & IRQSTAT_TC))) {
232 udelay(100); /* Wait before last byte transfer complete */
233 irqstat = esdhc_read32(&regs->irqstat);
234 databuf = in_le32(&regs->datport);
235 *((uint *)buffer) = databuf;
236 buffer += 4;
237 size -= 4;
238 }
239 blocks--;
240 }
241 } else {
242 blocks = data->blocks;
243 buffer = (char *)data->src;
244 while (blocks) {
245 start = get_timer(0);
246 size = data->blocksize;
247 irqstat = esdhc_read32(&regs->irqstat);
248 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
249 if (get_timer(start) > PIO_TIMEOUT) {
250 printf("\nData Write Failed in PIO Mode.");
251 return;
252 }
253 }
254 while (size && (!(irqstat & IRQSTAT_TC))) {
255 udelay(100); /* Wait before last byte transfer complete */
256 databuf = *((uint *)buffer);
257 buffer += 4;
258 size -= 4;
259 irqstat = esdhc_read32(&regs->irqstat);
260 out_le32(&regs->datport, databuf);
261 }
262 blocks--;
263 }
264 }
265}
266#endif
267
268static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
269 struct mmc_data *data)
270{
271 int timeout;
272 struct fsl_esdhc *regs = priv->esdhc_regs;
5053da2e 273#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
fa33d207
YL		 274 dma_addr_t addr;
275#endif
276 uint wml_value;
277
278 wml_value = data->blocksize/4;
279
280 if (data->flags & MMC_DATA_READ) {
281 if (wml_value > WML_RD_WML_MAX)
282 wml_value = WML_RD_WML_MAX_VAL;
283
284 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
285#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
5053da2e 286#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
fa33d207
YL		 287 addr = virt_to_phys((void *)(data->dest));
288 if (upper_32_bits(addr))
289 printf("Error found for upper 32 bits\n");
290 else
291 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
292#else
293 esdhc_write32(&regs->dsaddr, (u32)data->dest);
294#endif
295#endif
296 } else {
297#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
298 flush_dcache_range((ulong)data->src,
299 (ulong)data->src+data->blocks
300 *data->blocksize);
301#endif
302 if (wml_value > WML_WR_WML_MAX)
303 wml_value = WML_WR_WML_MAX_VAL;
304 if (priv->wp_enable) {
305 if ((esdhc_read32(&regs->prsstat) &
306 PRSSTAT_WPSPL) == 0) {
307 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
308 return -ETIMEDOUT;
309 }
310 } else {
bcee8d67
SG		 311#if CONFIG_IS_ENABLED(DM_GPIO)
312 if (dm_gpio_is_valid(&priv->wp_gpio) &&
313 dm_gpio_get_value(&priv->wp_gpio)) {
fa33d207
YL		 314 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
315 return -ETIMEDOUT;
316 }
317#endif
318 }
319
320 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
321 wml_value << 16);
322#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
5053da2e 323#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
fa33d207
YL		 324 addr = virt_to_phys((void *)(data->src));
325 if (upper_32_bits(addr))
326 printf("Error found for upper 32 bits\n");
327 else
328 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
329#else
330 esdhc_write32(&regs->dsaddr, (u32)data->src);
331#endif
332#endif
333 }
334
335 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
336
337 /* Calculate the timeout period for data transactions */
338 /*
339 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
340 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
341 * So, Number of SD Clock cycles for 0.25sec should be minimum
342 * (SD Clock/sec * 0.25 sec) SD Clock cycles
343 * = (mmc->clock * 1/4) SD Clock cycles
344 * As 1) >= 2)
345 * => (2^(timeout+13)) >= mmc->clock * 1/4
346 * Taking log2 both the sides
347 * => timeout + 13 >= log2(mmc->clock/4)
348 * Rounding up to next power of 2
349 * => timeout + 13 = log2(mmc->clock/4) + 1
350 * => timeout + 13 = fls(mmc->clock/4)
351 *
352 * However, the MMC spec "It is strongly recommended for hosts to
353 * implement more than 500ms timeout value even if the card
354 * indicates the 250ms maximum busy length." Even the previous
355 * value of 300ms is known to be insufficient for some cards.
356 * So, we use
357 * => timeout + 13 = fls(mmc->clock/2)
358 */
359 timeout = fls(mmc->clock/2);
360 timeout -= 13;
361
362 if (timeout > 14)
363 timeout = 14;
364
365 if (timeout < 0)
366 timeout = 0;
367
368#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
369 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
370 timeout++;
371#endif
372
373#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
374 timeout = 0xE;
375#endif
376 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
377
378 return 0;
379}
380
381static void check_and_invalidate_dcache_range
382 (struct mmc_cmd *cmd,
383 struct mmc_data *data) {
384 unsigned start = 0;
385 unsigned end = 0;
386 unsigned size = roundup(ARCH_DMA_MINALIGN,
387 data->blocks*data->blocksize);
5053da2e 388#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
fa33d207
YL		 389 dma_addr_t addr;
390
391 addr = virt_to_phys((void *)(data->dest));
392 if (upper_32_bits(addr))
393 printf("Error found for upper 32 bits\n");
394 else
395 start = lower_32_bits(addr);
396#else
397 start = (unsigned)data->dest;
398#endif
399 end = start + size;
400 invalidate_dcache_range(start, end);
401}
402
403#ifdef CONFIG_MCF5441x
404/*
405 * Swaps 32-bit words to little-endian byte order.
406 */
407static inline void sd_swap_dma_buff(struct mmc_data *data)
408{
409 int i, size = data->blocksize >> 2;
410 u32 *buffer = (u32 *)data->dest;
411 u32 sw;
412
413 while (data->blocks--) {
414 for (i = 0; i < size; i++) {
415 sw = __sw32(*buffer);
416 *buffer++ = sw;
417 }
418 }
419}
420#endif
421
422/*
423 * Sends a command out on the bus. Takes the mmc pointer,
424 * a command pointer, and an optional data pointer.
425 */
426static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
427 struct mmc_cmd *cmd, struct mmc_data *data)
428{
429 int err = 0;
430 uint xfertyp;
431 uint irqstat;
432 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
433 struct fsl_esdhc *regs = priv->esdhc_regs;
434 unsigned long start;
435
436#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
437 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
438 return 0;
439#endif
440
441 esdhc_write32(&regs->irqstat, -1);
442
443 sync();
444
445 /* Wait for the bus to be idle */
446 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
447 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
448 ;
449
450 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
451 ;
452
453 /* Wait at least 8 SD clock cycles before the next command */
454 /*
455 * Note: This is way more than 8 cycles, but 1ms seems to
456 * resolve timing issues with some cards
457 */
458 udelay(1000);
459
460 /* Set up for a data transfer if we have one */
461 if (data) {
462 err = esdhc_setup_data(priv, mmc, data);
463 if(err)
464 return err;
465
466 if (data->flags & MMC_DATA_READ)
467 check_and_invalidate_dcache_range(cmd, data);
468 }
469
470 /* Figure out the transfer arguments */
471 xfertyp = esdhc_xfertyp(cmd, data);
472
473 /* Mask all irqs */
474 esdhc_write32(&regs->irqsigen, 0);
475
476 /* Send the command */
477 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
478#if defined(CONFIG_FSL_USDHC)
479 esdhc_write32(&regs->mixctrl,
480 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
481 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
482 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
483#else
484 esdhc_write32(&regs->xfertyp, xfertyp);
485#endif
486
487 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
488 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
489 flags = IRQSTAT_BRR;
490
491 /* Wait for the command to complete */
492 start = get_timer(0);
493 while (!(esdhc_read32(&regs->irqstat) & flags)) {
494 if (get_timer(start) > 1000) {
495 err = -ETIMEDOUT;
496 goto out;
497 }
498 }
499
500 irqstat = esdhc_read32(&regs->irqstat);
501
502 if (irqstat & CMD_ERR) {
503 err = -ECOMM;
504 goto out;
505 }
506
507 if (irqstat & IRQSTAT_CTOE) {
508 err = -ETIMEDOUT;
509 goto out;
510 }
511
512 /* Switch voltage to 1.8V if CMD11 succeeded */
513 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
514 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
515
516 printf("Run CMD11 1.8V switch\n");
517 /* Sleep for 5 ms - max time for card to switch to 1.8V */
518 udelay(5000);
519 }
520
521 /* Workaround for ESDHC errata ENGcm03648 */
522 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
356f782c 523 int timeout = 50000;
fa33d207 524
356f782c 525 /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
fa33d207
YL		 526 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
527 PRSSTAT_DAT0)) {
528 udelay(100);
529 timeout--;
530 }
531
532 if (timeout <= 0) {
533 printf("Timeout waiting for DAT0 to go high!\n");
534 err = -ETIMEDOUT;
535 goto out;
536 }
537 }
538
539 /* Copy the response to the response buffer */
540 if (cmd->resp_type & MMC_RSP_136) {
541 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
542
543 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
544 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
545 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
546 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
547 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
548 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
549 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
550 cmd->response[3] = (cmdrsp0 << 8);
551 } else
552 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
553
554 /* Wait until all of the blocks are transferred */
555 if (data) {
556#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
557 esdhc_pio_read_write(priv, data);
558#else
559 flags = DATA_COMPLETE;
560 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
561 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
562 flags = IRQSTAT_BRR;
563 }
564
565 do {
566 irqstat = esdhc_read32(&regs->irqstat);
567
568 if (irqstat & IRQSTAT_DTOE) {
569 err = -ETIMEDOUT;
570 goto out;
571 }
572
573 if (irqstat & DATA_ERR) {
574 err = -ECOMM;
575 goto out;
576 }
577 } while ((irqstat & flags) != flags);
578
579 /*
580 * Need invalidate the dcache here again to avoid any
581 * cache-fill during the DMA operations such as the
582 * speculative pre-fetching etc.
583 */
584 if (data->flags & MMC_DATA_READ) {
585 check_and_invalidate_dcache_range(cmd, data);
586#ifdef CONFIG_MCF5441x
587 sd_swap_dma_buff(data);
588#endif
589 }
590#endif
591 }
592
593out:
594 /* Reset CMD and DATA portions on error */
595 if (err) {
596 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
597 SYSCTL_RSTC);
598 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
599 ;
600
601 if (data) {
602 esdhc_write32(&regs->sysctl,
603 esdhc_read32(&regs->sysctl) |
604 SYSCTL_RSTD);
605 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
606 ;
607 }
608
609 /* If this was CMD11, then notify that power cycle is needed */
610 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
611 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
612 }
613
614 esdhc_write32(&regs->irqstat, -1);
615
616 return err;
617}
618
619static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
620{
621 struct fsl_esdhc *regs = priv->esdhc_regs;
622 int div = 1;
623#ifdef ARCH_MXC
624#ifdef CONFIG_MX53
625 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
626 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
627#else
628 int pre_div = 1;
629#endif
630#else
631 int pre_div = 2;
632#endif
633 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
634 int sdhc_clk = priv->sdhc_clk;
635 uint clk;
636
fa33d207
YL		 637 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
638 pre_div *= 2;
639
640 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
641 div++;
642
643 pre_div >>= 1;
644 div -= 1;
645
646 clk = (pre_div << 8) | (div << 4);
647
648#ifdef CONFIG_FSL_USDHC
649 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
650#else
651 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
652#endif
653
654 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
655
656 udelay(10000);
657
658#ifdef CONFIG_FSL_USDHC
659 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
660#else
661 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
662#endif
663
664 priv->clock = clock;
665}
666
fa33d207
YL		 667#ifdef MMC_SUPPORTS_TUNING
668static int esdhc_change_pinstate(struct udevice *dev)
669{
670 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
671 int ret;
672
673 switch (priv->mode) {
674 case UHS_SDR50:
675 case UHS_DDR50:
676 ret = pinctrl_select_state(dev, "state_100mhz");
677 break;
678 case UHS_SDR104:
679 case MMC_HS_200:
680 case MMC_HS_400:
e9c22552 681 case MMC_HS_400_ES:
fa33d207
YL		 682 ret = pinctrl_select_state(dev, "state_200mhz");
683 break;
684 default:
685 ret = pinctrl_select_state(dev, "default");
686 break;
687 }
688
689 if (ret)
690 printf("%s %d error\n", __func__, priv->mode);
691
692 return ret;
693}
694
695static void esdhc_reset_tuning(struct mmc *mmc)
696{
697 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
698 struct fsl_esdhc *regs = priv->esdhc_regs;
699
700 if (priv->flags & ESDHC_FLAG_USDHC) {
701 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
702 esdhc_clrbits32(&regs->autoc12err,
703 MIX_CTRL_SMPCLK_SEL |
704 MIX_CTRL_EXE_TUNE);
705 }
706 }
707}
708
709static void esdhc_set_strobe_dll(struct mmc *mmc)
710{
711 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
712 struct fsl_esdhc *regs = priv->esdhc_regs;
713 u32 val;
714
715 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
716 writel(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl);
717
718 /*
719 * enable strobe dll ctrl and adjust the delay target
720 * for the uSDHC loopback read clock
721 */
722 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
723 (priv->strobe_dll_delay_target <<
724 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
725 writel(val, &regs->strobe_dllctrl);
726 /* wait 1us to make sure strobe dll status register stable */
727 mdelay(1);
728 val = readl(&regs->strobe_dllstat);
729 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
730 pr_warn("HS400 strobe DLL status REF not lock!\n");
731 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
732 pr_warn("HS400 strobe DLL status SLV not lock!\n");
733 }
734}
735
736static int esdhc_set_timing(struct mmc *mmc)
737{
738 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
739 struct fsl_esdhc *regs = priv->esdhc_regs;
740 u32 mixctrl;
741
742 mixctrl = readl(&regs->mixctrl);
743 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
744
745 switch (mmc->selected_mode) {
746 case MMC_LEGACY:
fa33d207
YL		 747 esdhc_reset_tuning(mmc);
748 writel(mixctrl, &regs->mixctrl);
749 break;
750 case MMC_HS_400:
e9c22552 751 case MMC_HS_400_ES:
fa33d207
YL		 752 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
753 writel(mixctrl, &regs->mixctrl);
754 esdhc_set_strobe_dll(mmc);
755 break;
756 case MMC_HS:
757 case MMC_HS_52:
758 case MMC_HS_200:
759 case SD_HS:
760 case UHS_SDR12:
761 case UHS_SDR25:
762 case UHS_SDR50:
763 case UHS_SDR104:
764 writel(mixctrl, &regs->mixctrl);
765 break;
766 case UHS_DDR50:
767 case MMC_DDR_52:
768 mixctrl |= MIX_CTRL_DDREN;
769 writel(mixctrl, &regs->mixctrl);
770 break;
771 default:
772 printf("Not supported %d\n", mmc->selected_mode);
773 return -EINVAL;
774 }
775
776 priv->mode = mmc->selected_mode;
777
778 return esdhc_change_pinstate(mmc->dev);
779}
780
781static int esdhc_set_voltage(struct mmc *mmc)
782{
783 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
784 struct fsl_esdhc *regs = priv->esdhc_regs;
785 int ret;
786
787 priv->signal_voltage = mmc->signal_voltage;
788 switch (mmc->signal_voltage) {
789 case MMC_SIGNAL_VOLTAGE_330:
790 if (priv->vs18_enable)
791 return -EIO;
792#if CONFIG_IS_ENABLED(DM_REGULATOR)
793 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
794 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
795 if (ret) {
796 printf("Setting to 3.3V error");
797 return -EIO;
798 }
799 /* Wait for 5ms */
800 mdelay(5);
801 }
802#endif
803
804 esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
805 if (!(esdhc_read32(&regs->vendorspec) &
806 ESDHC_VENDORSPEC_VSELECT))
807 return 0;
808
809 return -EAGAIN;
810 case MMC_SIGNAL_VOLTAGE_180:
811#if CONFIG_IS_ENABLED(DM_REGULATOR)
812 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
813 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
814 if (ret) {
815 printf("Setting to 1.8V error");
816 return -EIO;
817 }
818 }
819#endif
820 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
821 if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
822 return 0;
823
824 return -EAGAIN;
825 case MMC_SIGNAL_VOLTAGE_120:
826 return -ENOTSUPP;
827 default:
828 return 0;
829 }
830}
831
832static void esdhc_stop_tuning(struct mmc *mmc)
833{
834 struct mmc_cmd cmd;
835
836 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
837 cmd.cmdarg = 0;
838 cmd.resp_type = MMC_RSP_R1b;
839
840 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
841}
842
843static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
844{
845 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
846 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
847 struct fsl_esdhc *regs = priv->esdhc_regs;
848 struct mmc *mmc = &plat->mmc;
849 u32 irqstaten = readl(&regs->irqstaten);
850 u32 irqsigen = readl(&regs->irqsigen);
851 int i, ret = -ETIMEDOUT;
852 u32 val, mixctrl;
853
854 /* clock tuning is not needed for upto 52MHz */
855 if (mmc->clock <= 52000000)
856 return 0;
857
858 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
859 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
860 val = readl(&regs->autoc12err);
861 mixctrl = readl(&regs->mixctrl);
862 val &= ~MIX_CTRL_SMPCLK_SEL;
863 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
864
865 val |= MIX_CTRL_EXE_TUNE;
866 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
867
868 writel(val, &regs->autoc12err);
869 writel(mixctrl, &regs->mixctrl);
870 }
871
872 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
873 mixctrl = readl(&regs->mixctrl);
874 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
875 writel(mixctrl, &regs->mixctrl);
876
877 writel(IRQSTATEN_BRR, &regs->irqstaten);
878 writel(IRQSTATEN_BRR, &regs->irqsigen);
879
880 /*
881 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
882 * of loops reaches 40 times.
883 */
884 for (i = 0; i < MAX_TUNING_LOOP; i++) {
885 u32 ctrl;
886
887 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
888 if (mmc->bus_width == 8)
889 writel(0x7080, &regs->blkattr);
890 else if (mmc->bus_width == 4)
891 writel(0x7040, &regs->blkattr);
892 } else {
893 writel(0x7040, &regs->blkattr);
894 }
895
896 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
897 val = readl(&regs->mixctrl);
898 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
899 writel(val, &regs->mixctrl);
900
901 /* We are using STD tuning, no need to check return value */
902 mmc_send_tuning(mmc, opcode, NULL);
903
904 ctrl = readl(&regs->autoc12err);
905 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
906 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
907 /*
908 * need to wait some time, make sure sd/mmc fininsh
909 * send out tuning data, otherwise, the sd/mmc can't
910 * response to any command when the card still out
911 * put the tuning data.
912 */
913 mdelay(1);
914 ret = 0;
915 break;
916 }
917
918 /* Add 1ms delay for SD and eMMC */
919 mdelay(1);
920 }
921
922 writel(irqstaten, &regs->irqstaten);
923 writel(irqsigen, &regs->irqsigen);
924
925 esdhc_stop_tuning(mmc);
926
927 return ret;
928}
929#endif
930
931static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
932{
933 struct fsl_esdhc *regs = priv->esdhc_regs;
934 int ret __maybe_unused;
1d01c984 935 u32 clock;
fa33d207 936
fa33d207 937 /* Set the clock speed */
1d01c984
PF		 938 clock = mmc->clock;
939 if (clock < mmc->cfg->f_min)
940 clock = mmc->cfg->f_min;
941
942 if (priv->clock != clock)
943 set_sysctl(priv, mmc, clock);
fa33d207
YL		 944
945#ifdef MMC_SUPPORTS_TUNING
946 if (mmc->clk_disable) {
947#ifdef CONFIG_FSL_USDHC
948 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
949#else
950 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
951#endif
952 } else {
953#ifdef CONFIG_FSL_USDHC
954 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
955 VENDORSPEC_CKEN);
956#else
957 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
958#endif
959 }
960
961 if (priv->mode != mmc->selected_mode) {
962 ret = esdhc_set_timing(mmc);
963 if (ret) {
964 printf("esdhc_set_timing error %d\n", ret);
965 return ret;
966 }
967 }
968
969 if (priv->signal_voltage != mmc->signal_voltage) {
970 ret = esdhc_set_voltage(mmc);
971 if (ret) {
972 printf("esdhc_set_voltage error %d\n", ret);
973 return ret;
974 }
975 }
976#endif
977
978 /* Set the bus width */
979 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
980
981 if (mmc->bus_width == 4)
982 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
983 else if (mmc->bus_width == 8)
984 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
985
986 return 0;
987}
988
989static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
990{
991 struct fsl_esdhc *regs = priv->esdhc_regs;
992 ulong start;
993
994 /* Reset the entire host controller */
995 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
996
997 /* Wait until the controller is available */
998 start = get_timer(0);
999 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
1000 if (get_timer(start) > 1000)
1001 return -ETIMEDOUT;
1002 }
1003
1004#if defined(CONFIG_FSL_USDHC)
1005 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1006 esdhc_write32(&regs->mmcboot, 0x0);
1007 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1008 esdhc_write32(&regs->mixctrl, 0x0);
1009 esdhc_write32(&regs->clktunectrlstatus, 0x0);
1010
1011 /* Put VEND_SPEC to default value */
1012 if (priv->vs18_enable)
1013 esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
1014 ESDHC_VENDORSPEC_VSELECT));
1015 else
1016 esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
1017
1018 /* Disable DLL_CTRL delay line */
1019 esdhc_write32(&regs->dllctrl, 0x0);
1020#endif
1021
1022#ifndef ARCH_MXC
1023 /* Enable cache snooping */
1024 esdhc_write32(&regs->scr, 0x00000040);
1025#endif
1026
1027#ifndef CONFIG_FSL_USDHC
1028 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1029#else
1030 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1031#endif
1032
1033 /* Set the initial clock speed */
1034 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1035
1036 /* Disable the BRR and BWR bits in IRQSTAT */
1037 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1038
1039#ifdef CONFIG_MCF5441x
1040 esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
1041#else
1042 /* Put the PROCTL reg back to the default */
1043 esdhc_write32(&regs->proctl, PROCTL_INIT);
1044#endif
1045
1046 /* Set timout to the maximum value */
1047 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1048
1049 return 0;
1050}
1051
1052static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1053{
1054 struct fsl_esdhc *regs = priv->esdhc_regs;
1055 int timeout = 1000;
1056
1057#ifdef CONFIG_ESDHC_DETECT_QUIRK
1058 if (CONFIG_ESDHC_DETECT_QUIRK)
1059 return 1;
1060#endif
1061
1062#if CONFIG_IS_ENABLED(DM_MMC)
1063 if (priv->non_removable)
1064 return 1;
29230f38
FE		 1065
1066 if (priv->broken_cd)
1067 return 1;
bcee8d67 1068#if CONFIG_IS_ENABLED(DM_GPIO)
fa33d207
YL		 1069 if (dm_gpio_is_valid(&priv->cd_gpio))
1070 return dm_gpio_get_value(&priv->cd_gpio);
1071#endif
1072#endif
1073
1074 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
1075 udelay(1000);
1076
1077 return timeout > 0;
1078}
1079
1080static int esdhc_reset(struct fsl_esdhc *regs)
1081{
1082 ulong start;
1083
1084 /* reset the controller */
1085 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
1086
1087 /* hardware clears the bit when it is done */
1088 start = get_timer(0);
1089 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
1090 if (get_timer(start) > 100) {
1091 printf("MMC/SD: Reset never completed.\n");
1092 return -ETIMEDOUT;
1093 }
1094 }
1095
1096 return 0;
1097}
1098
1099#if !CONFIG_IS_ENABLED(DM_MMC)
1100static int esdhc_getcd(struct mmc *mmc)
1101{
1102 struct fsl_esdhc_priv *priv = mmc->priv;
1103
1104 return esdhc_getcd_common(priv);
1105}
1106
1107static int esdhc_init(struct mmc *mmc)
1108{
1109 struct fsl_esdhc_priv *priv = mmc->priv;
1110
1111 return esdhc_init_common(priv, mmc);
1112}
1113
1114static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1115 struct mmc_data *data)
1116{
1117 struct fsl_esdhc_priv *priv = mmc->priv;
1118
1119 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1120}
1121
1122static int esdhc_set_ios(struct mmc *mmc)
1123{
1124 struct fsl_esdhc_priv *priv = mmc->priv;
1125
1126 return esdhc_set_ios_common(priv, mmc);
1127}
1128
1129static const struct mmc_ops esdhc_ops = {
1130 .getcd = esdhc_getcd,
1131 .init = esdhc_init,
1132 .send_cmd = esdhc_send_cmd,
1133 .set_ios = esdhc_set_ios,
1134};
1135#endif
1136
1137static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1138 struct fsl_esdhc_plat *plat)
1139{
1140 struct mmc_config *cfg;
1141 struct fsl_esdhc *regs;
1142 u32 caps, voltage_caps;
1143 int ret;
1144
1145 if (!priv)
1146 return -EINVAL;
1147
1148 regs = priv->esdhc_regs;
1149
1150 /* First reset the eSDHC controller */
1151 ret = esdhc_reset(regs);
1152 if (ret)
1153 return ret;
1154
1155#ifdef CONFIG_MCF5441x
1156 /* ColdFire, using SDHC_DATA[3] for card detection */
1157 esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
1158#endif
1159
1160#ifndef CONFIG_FSL_USDHC
1161 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1162 | SYSCTL_IPGEN | SYSCTL_CKEN);
1163 /* Clearing tuning bits in case ROM has set it already */
1164 esdhc_write32(&regs->mixctrl, 0);
1165 esdhc_write32(&regs->autoc12err, 0);
1166 esdhc_write32(&regs->clktunectrlstatus, 0);
1167#else
1168 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
1169 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1170#endif
1171
1172 if (priv->vs18_enable)
1173 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1174
1175 writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
1176 cfg = &plat->cfg;
1177#ifndef CONFIG_DM_MMC
1178 memset(cfg, '\0', sizeof(*cfg));
1179#endif
1180
1181 voltage_caps = 0;
1182 caps = esdhc_read32(&regs->hostcapblt);
1183
1184#ifdef CONFIG_MCF5441x
1185 /*
1186 * MCF5441x RM declares in more points that sdhc clock speed must
1187 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1188 * from host capabilities.
1189 */
1190 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1191#endif
1192
1193#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1194 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1195 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1196#endif
1197
1198/* T4240 host controller capabilities register should have VS33 bit */
1199#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1200 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1201#endif
1202
1203 if (caps & ESDHC_HOSTCAPBLT_VS18)
1204 voltage_caps |= MMC_VDD_165_195;
1205 if (caps & ESDHC_HOSTCAPBLT_VS30)
1206 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1207 if (caps & ESDHC_HOSTCAPBLT_VS33)
1208 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1209
1210 cfg->name = "FSL_SDHC";
1211#if !CONFIG_IS_ENABLED(DM_MMC)
1212 cfg->ops = &esdhc_ops;
1213#endif
1214#ifdef CONFIG_SYS_SD_VOLTAGE
1215 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1216#else
1217 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1218#endif
1219 if ((cfg->voltages & voltage_caps) == 0) {
1220 printf("voltage not supported by controller\n");
1221 return -1;
1222 }
1223
1224 if (priv->bus_width == 8)
1225 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1226 else if (priv->bus_width == 4)
1227 cfg->host_caps = MMC_MODE_4BIT;
1228
1229 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1230#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1231 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1232#endif
1233
1234 if (priv->bus_width > 0) {
1235 if (priv->bus_width < 8)
1236 cfg->host_caps &= ~MMC_MODE_8BIT;
1237 if (priv->bus_width < 4)
1238 cfg->host_caps &= ~MMC_MODE_4BIT;
1239 }
1240
1241 if (caps & ESDHC_HOSTCAPBLT_HSS)
1242 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1243
1244#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1245 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1246 cfg->host_caps &= ~MMC_MODE_8BIT;
1247#endif
1248
1249 cfg->host_caps |= priv->caps;
1250
1251 cfg->f_min = 400000;
1252 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1253
1254 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1255
1256 writel(0, &regs->dllctrl);
1257 if (priv->flags & ESDHC_FLAG_USDHC) {
1258 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1259 u32 val = readl(&regs->tuning_ctrl);
1260
1261 val |= ESDHC_STD_TUNING_EN;
1262 val &= ~ESDHC_TUNING_START_TAP_MASK;
1263 val |= priv->tuning_start_tap;
1264 val &= ~ESDHC_TUNING_STEP_MASK;
1265 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1266 writel(val, &regs->tuning_ctrl);
1267 }
1268 }
1269
1270 return 0;
1271}
1272
1273#if !CONFIG_IS_ENABLED(DM_MMC)
1274static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1275 struct fsl_esdhc_priv *priv)
1276{
1277 if (!cfg || !priv)
1278 return -EINVAL;
1279
1280 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1281 priv->bus_width = cfg->max_bus_width;
1282 priv->sdhc_clk = cfg->sdhc_clk;
1283 priv->wp_enable = cfg->wp_enable;
1284 priv->vs18_enable = cfg->vs18_enable;
1285
1286 return 0;
1287};
1288
1289int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1290{
1291 struct fsl_esdhc_plat *plat;
1292 struct fsl_esdhc_priv *priv;
1293 struct mmc *mmc;
1294 int ret;
1295
1296 if (!cfg)
1297 return -EINVAL;
1298
1299 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1300 if (!priv)
1301 return -ENOMEM;
1302 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1303 if (!plat) {
1304 free(priv);
1305 return -ENOMEM;
1306 }
1307
1308 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1309 if (ret) {
1310 debug("%s xlate failure\n", __func__);
1311 free(plat);
1312 free(priv);
1313 return ret;
1314 }
1315
1316 ret = fsl_esdhc_init(priv, plat);
1317 if (ret) {
1318 debug("%s init failure\n", __func__);
1319 free(plat);
1320 free(priv);
1321 return ret;
1322 }
1323
1324 mmc = mmc_create(&plat->cfg, priv);
1325 if (!mmc)
1326 return -EIO;
1327
1328 priv->mmc = mmc;
1329
1330 return 0;
1331}
1332
1333int fsl_esdhc_mmc_init(bd_t *bis)
1334{
1335 struct fsl_esdhc_cfg *cfg;
1336
1337 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1338 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1339 cfg->sdhc_clk = gd->arch.sdhc_clk;
1340 return fsl_esdhc_initialize(bis, cfg);
1341}
1342#endif
1343
fa33d207
YL		 1344#ifdef CONFIG_OF_LIBFDT
1345__weak int esdhc_status_fixup(void *blob, const char *compat)
1346{
1347#ifdef CONFIG_FSL_ESDHC_PIN_MUX
1348 if (!hwconfig("esdhc")) {
1349 do_fixup_by_compat(blob, compat, "status", "disabled",
1350 sizeof("disabled"), 1);
1351 return 1;
1352 }
1353#endif
1354 return 0;
1355}
1356
1357void fdt_fixup_esdhc(void *blob, bd_t *bd)
1358{
1359 const char *compat = "fsl,esdhc";
1360
1361 if (esdhc_status_fixup(blob, compat))
1362 return;
1363
fa33d207
YL		 1364 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1365 gd->arch.sdhc_clk, 1);
fa33d207
YL		 1366}
1367#endif
1368
1369#if CONFIG_IS_ENABLED(DM_MMC)
fa33d207 1370#include <asm/arch/clock.h>
fa33d207
YL		 1371__weak void init_clk_usdhc(u32 index)
1372{
1373}
1374
1375static int fsl_esdhc_probe(struct udevice *dev)
1376{
1377 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1378 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1379 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1380 const void *fdt = gd->fdt_blob;
1381 int node = dev_of_offset(dev);
1382 struct esdhc_soc_data *data =
1383 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1384#if CONFIG_IS_ENABLED(DM_REGULATOR)
1385 struct udevice *vqmmc_dev;
1386#endif
1387 fdt_addr_t addr;
1388 unsigned int val;
1389 struct mmc *mmc;
1390#if !CONFIG_IS_ENABLED(BLK)
1391 struct blk_desc *bdesc;
1392#endif
1393 int ret;
1394
1395 addr = dev_read_addr(dev);
1396 if (addr == FDT_ADDR_T_NONE)
1397 return -EINVAL;
fa33d207 1398 priv->esdhc_regs = (struct fsl_esdhc *)addr;
fa33d207
YL		 1399 priv->dev = dev;
1400 priv->mode = -1;
b0155ac6 1401 if (data)
fa33d207 1402 priv->flags = data->flags;
fa33d207
YL		 1403
1404 val = dev_read_u32_default(dev, "bus-width", -1);
1405 if (val == 8)
1406 priv->bus_width = 8;
1407 else if (val == 4)
1408 priv->bus_width = 4;
1409 else
1410 priv->bus_width = 1;
1411
1412 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1413 priv->tuning_step = val;
1414 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1415 ESDHC_TUNING_START_TAP_DEFAULT);
1416 priv->tuning_start_tap = val;
1417 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1418 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1419 priv->strobe_dll_delay_target = val;
1420
29230f38
FE		 1421 if (dev_read_bool(dev, "broken-cd"))
1422 priv->broken_cd = 1;
1423
fa33d207
YL		 1424 if (dev_read_bool(dev, "non-removable")) {
1425 priv->non_removable = 1;
1426 } else {
1427 priv->non_removable = 0;
bcee8d67 1428#if CONFIG_IS_ENABLED(DM_GPIO)
fa33d207
YL		 1429 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1430 GPIOD_IS_IN);
1431#endif
1432 }
1433
1434 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1435 priv->wp_enable = 1;
1436 } else {
1437 priv->wp_enable = 0;
bcee8d67 1438#if CONFIG_IS_ENABLED(DM_GPIO)
fa33d207
YL		 1439 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1440 GPIOD_IS_IN);
1441#endif
1442 }
1443
1444 priv->vs18_enable = 0;
1445
1446#if CONFIG_IS_ENABLED(DM_REGULATOR)
1447 /*
1448 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1449 * otherwise, emmc will work abnormally.
1450 */
1451 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1452 if (ret) {
1453 dev_dbg(dev, "no vqmmc-supply\n");
1454 } else {
1455 ret = regulator_set_enable(vqmmc_dev, true);
1456 if (ret) {
1457 dev_err(dev, "fail to enable vqmmc-supply\n");
1458 return ret;
1459 }
1460
1461 if (regulator_get_value(vqmmc_dev) == 1800000)
1462 priv->vs18_enable = 1;
1463 }
1464#endif
1465
fa33d207
YL		 1466 /*
1467 * TODO:
1468 * Because lack of clk driver, if SDHC clk is not enabled,
1469 * need to enable it first before this driver is invoked.
1470 *
1471 * we use MXC_ESDHC_CLK to get clk freq.
1472 * If one would like to make this function work,
1473 * the aliases should be provided in dts as this:
1474 *
1475 * aliases {
1476 * mmc0 = &usdhc1;
1477 * mmc1 = &usdhc2;
1478 * mmc2 = &usdhc3;
1479 * mmc3 = &usdhc4;
1480 * };
1481 * Then if your board only supports mmc2 and mmc3, but we can
1482 * correctly get the seq as 2 and 3, then let mxc_get_clock
1483 * work as expected.
1484 */
1485
1486 init_clk_usdhc(dev->seq);
1487
a820bedc
GB		 1488#if CONFIG_IS_ENABLED(CLK)
1489 /* Assigned clock already set clock */
1490 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1491 if (ret) {
1492 printf("Failed to get per_clk\n");
1493 return ret;
1494 }
1495 ret = clk_enable(&priv->per_clk);
1496 if (ret) {
1497 printf("Failed to enable per_clk\n");
1498 return ret;
1499 }
fa33d207 1500
a820bedc
GB		 1501 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1502#else
1503 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1504 if (priv->sdhc_clk <= 0) {
1505 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1506 return -EINVAL;
fa33d207 1507 }
a820bedc 1508#endif
fa33d207
YL		 1509
1510 ret = fsl_esdhc_init(priv, plat);
1511 if (ret) {
1512 dev_err(dev, "fsl_esdhc_init failure\n");
1513 return ret;
1514 }
1515
b0155ac6
PF		 1516 ret = mmc_of_parse(dev, &plat->cfg);
1517 if (ret)
1518 return ret;
1519
fa33d207
YL		 1520 mmc = &plat->mmc;
1521 mmc->cfg = &plat->cfg;
1522 mmc->dev = dev;
1523#if !CONFIG_IS_ENABLED(BLK)
1524 mmc->priv = priv;
1525
1526 /* Setup dsr related values */
1527 mmc->dsr_imp = 0;
1528 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1529 /* Setup the universal parts of the block interface just once */
1530 bdesc = mmc_get_blk_desc(mmc);
1531 bdesc->if_type = IF_TYPE_MMC;
1532 bdesc->removable = 1;
1533 bdesc->devnum = mmc_get_next_devnum();
1534 bdesc->block_read = mmc_bread;
1535 bdesc->block_write = mmc_bwrite;
1536 bdesc->block_erase = mmc_berase;
1537
1538 /* setup initial part type */
1539 bdesc->part_type = mmc->cfg->part_type;
1540 mmc_list_add(mmc);
1541#endif
1542
1543 upriv->mmc = mmc;
1544
1545 return esdhc_init_common(priv, mmc);
1546}
1547
1548#if CONFIG_IS_ENABLED(DM_MMC)
1549static int fsl_esdhc_get_cd(struct udevice *dev)
1550{
1551 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1552
1553 return esdhc_getcd_common(priv);
1554}
1555
1556static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1557 struct mmc_data *data)
1558{
1559 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1560 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1561
1562 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1563}
1564
1565static int fsl_esdhc_set_ios(struct udevice *dev)
1566{
1567 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1568 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1569
1570 return esdhc_set_ios_common(priv, &plat->mmc);
1571}
1572
e9c22552
PF		 1573#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1574static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
1575{
1576 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1577 struct fsl_esdhc *regs = priv->esdhc_regs;
1578 u32 m;
1579
1580 m = readl(&regs->mixctrl);
1581 m |= MIX_CTRL_HS400_ES;
1582 writel(m, &regs->mixctrl);
1583
1584 return 0;
1585}
1586#endif
1587
fa33d207
YL		 1588static const struct dm_mmc_ops fsl_esdhc_ops = {
1589 .get_cd = fsl_esdhc_get_cd,
1590 .send_cmd = fsl_esdhc_send_cmd,
1591 .set_ios = fsl_esdhc_set_ios,
1592#ifdef MMC_SUPPORTS_TUNING
1593 .execute_tuning = fsl_esdhc_execute_tuning,
1594#endif
e9c22552
PF		 1595#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1596 .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
1597#endif
fa33d207
YL		 1598};
1599#endif
1600
1601static struct esdhc_soc_data usdhc_imx7d_data = {
1602 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1603 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1604 | ESDHC_FLAG_HS400,
fa33d207
YL		 1605};
1606
609ba125
PF		 1607static struct esdhc_soc_data usdhc_imx8qm_data = {
1608 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
1609 ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
1610 ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
1611};
1612
fa33d207
YL		 1613static const struct udevice_id fsl_esdhc_ids[] = {
1614 { .compatible = "fsl,imx53-esdhc", },
1615 { .compatible = "fsl,imx6ul-usdhc", },
1616 { .compatible = "fsl,imx6sx-usdhc", },
1617 { .compatible = "fsl,imx6sl-usdhc", },
1618 { .compatible = "fsl,imx6q-usdhc", },
1619 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1620 { .compatible = "fsl,imx7ulp-usdhc", },
609ba125 1621 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
f65d0841
PF		 1622 { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1623 { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1624 { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
6a63a873 1625 { .compatible = "fsl,imxrt-usdhc", },
fa33d207
YL		 1626 { .compatible = "fsl,esdhc", },
1627 { /* sentinel */ }
1628};
1629
1630#if CONFIG_IS_ENABLED(BLK)
1631static int fsl_esdhc_bind(struct udevice *dev)
1632{
1633 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1634
1635 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1636}
1637#endif
1638
1639U_BOOT_DRIVER(fsl_esdhc) = {
1640 .name = "fsl-esdhc-mmc",
1641 .id = UCLASS_MMC,
1642 .of_match = fsl_esdhc_ids,
1643 .ops = &fsl_esdhc_ops,
1644#if CONFIG_IS_ENABLED(BLK)
1645 .bind = fsl_esdhc_bind,
1646#endif
1647 .probe = fsl_esdhc_probe,
1648 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1649 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
1650};
1651#endif
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