[thirdparty/u-boot.git] / drivers / mmc / jz_mmc.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Ingenic JZ MMC driver
 *
 * Copyright (c) 2013 Imagination Technologies
 * Author: Paul Burton <paul.burton@imgtec.com>
 */

#include <common.h>
#include <malloc.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/unaligned.h>
#include <errno.h>
#include <dm/device_compat.h>
#include <mach/jz4780.h>
#include <wait_bit.h>

/* Registers */
#define MSC_STRPCL			0x000
#define MSC_STAT			0x004
#define MSC_CLKRT			0x008
#define MSC_CMDAT			0x00c
#define MSC_RESTO			0x010
#define MSC_RDTO			0x014
#define MSC_BLKLEN			0x018
#define MSC_NOB				0x01c
#define MSC_SNOB			0x020
#define MSC_IMASK			0x024
#define MSC_IREG			0x028
#define MSC_CMD				0x02c
#define MSC_ARG				0x030
#define MSC_RES				0x034
#define MSC_RXFIFO			0x038
#define MSC_TXFIFO			0x03c
#define MSC_LPM				0x040
#define MSC_DMAC			0x044
#define MSC_DMANDA			0x048
#define MSC_DMADA			0x04c
#define MSC_DMALEN			0x050
#define MSC_DMACMD			0x054
#define MSC_CTRL2			0x058
#define MSC_RTCNT			0x05c
#define MSC_DBG				0x0fc

/* MSC Clock and Control Register (MSC_STRPCL) */
#define MSC_STRPCL_EXIT_MULTIPLE	BIT(7)
#define MSC_STRPCL_EXIT_TRANSFER	BIT(6)
#define MSC_STRPCL_START_READWAIT	BIT(5)
#define MSC_STRPCL_STOP_READWAIT	BIT(4)
#define MSC_STRPCL_RESET		BIT(3)
#define MSC_STRPCL_START_OP		BIT(2)
#define MSC_STRPCL_CLOCK_CONTROL_STOP	BIT(0)
#define MSC_STRPCL_CLOCK_CONTROL_START	BIT(1)

/* MSC Status Register (MSC_STAT) */
#define MSC_STAT_AUTO_CMD_DONE		BIT(31)
#define MSC_STAT_IS_RESETTING		BIT(15)
#define MSC_STAT_SDIO_INT_ACTIVE	BIT(14)
#define MSC_STAT_PRG_DONE		BIT(13)
#define MSC_STAT_DATA_TRAN_DONE		BIT(12)
#define MSC_STAT_END_CMD_RES		BIT(11)
#define MSC_STAT_DATA_FIFO_AFULL	BIT(10)
#define MSC_STAT_IS_READWAIT		BIT(9)
#define MSC_STAT_CLK_EN			BIT(8)
#define MSC_STAT_DATA_FIFO_FULL		BIT(7)
#define MSC_STAT_DATA_FIFO_EMPTY	BIT(6)
#define MSC_STAT_CRC_RES_ERR		BIT(5)
#define MSC_STAT_CRC_READ_ERROR		BIT(4)
#define MSC_STAT_CRC_WRITE_ERROR	BIT(2)
#define MSC_STAT_CRC_WRITE_ERROR_NOSTS	BIT(4)
#define MSC_STAT_TIME_OUT_RES		BIT(1)
#define MSC_STAT_TIME_OUT_READ		BIT(0)

/* MSC Bus Clock Control Register (MSC_CLKRT) */
#define MSC_CLKRT_CLK_RATE_MASK		0x7

/* MSC Command Sequence Control Register (MSC_CMDAT) */
#define MSC_CMDAT_IO_ABORT		BIT(11)
#define MSC_CMDAT_BUS_WIDTH_1BIT	(0x0 << 9)
#define MSC_CMDAT_BUS_WIDTH_4BIT	(0x2 << 9)
#define MSC_CMDAT_DMA_EN		BIT(8)
#define MSC_CMDAT_INIT			BIT(7)
#define MSC_CMDAT_BUSY			BIT(6)
#define MSC_CMDAT_STREAM_BLOCK		BIT(5)
#define MSC_CMDAT_WRITE			BIT(4)
#define MSC_CMDAT_DATA_EN		BIT(3)
#define MSC_CMDAT_RESPONSE_MASK		(0x7 << 0)
#define MSC_CMDAT_RESPONSE_NONE		(0x0 << 0) /* No response */
#define MSC_CMDAT_RESPONSE_R1		(0x1 << 0) /* Format R1 and R1b */
#define MSC_CMDAT_RESPONSE_R2		(0x2 << 0) /* Format R2 */
#define MSC_CMDAT_RESPONSE_R3		(0x3 << 0) /* Format R3 */
#define MSC_CMDAT_RESPONSE_R4		(0x4 << 0) /* Format R4 */
#define MSC_CMDAT_RESPONSE_R5		(0x5 << 0) /* Format R5 */
#define MSC_CMDAT_RESPONSE_R6		(0x6 << 0) /* Format R6 */

/* MSC Interrupts Mask Register (MSC_IMASK) */
#define MSC_IMASK_TIME_OUT_RES		BIT(9)
#define MSC_IMASK_TIME_OUT_READ		BIT(8)
#define MSC_IMASK_SDIO			BIT(7)
#define MSC_IMASK_TXFIFO_WR_REQ		BIT(6)
#define MSC_IMASK_RXFIFO_RD_REQ		BIT(5)
#define MSC_IMASK_END_CMD_RES		BIT(2)
#define MSC_IMASK_PRG_DONE		BIT(1)
#define MSC_IMASK_DATA_TRAN_DONE	BIT(0)

/* MSC Interrupts Status Register (MSC_IREG) */
#define MSC_IREG_TIME_OUT_RES		BIT(9)
#define MSC_IREG_TIME_OUT_READ		BIT(8)
#define MSC_IREG_SDIO			BIT(7)
#define MSC_IREG_TXFIFO_WR_REQ		BIT(6)
#define MSC_IREG_RXFIFO_RD_REQ		BIT(5)
#define MSC_IREG_END_CMD_RES		BIT(2)
#define MSC_IREG_PRG_DONE		BIT(1)
#define MSC_IREG_DATA_TRAN_DONE		BIT(0)

struct jz_mmc_plat {
	struct mmc_config cfg;
	struct mmc mmc;
};

struct jz_mmc_priv {
	void __iomem		*regs;
	u32			flags;
/* priv flags */
#define JZ_MMC_BUS_WIDTH_MASK	0x3
#define JZ_MMC_BUS_WIDTH_1	0x0
#define JZ_MMC_BUS_WIDTH_4	0x2
#define JZ_MMC_BUS_WIDTH_8	0x3
#define JZ_MMC_SENT_INIT	BIT(2)
};

static int jz_mmc_clock_rate(void)
{
	return 24000000;
}

#if CONFIG_IS_ENABLED(MMC_WRITE)
static inline void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
{
	int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
	const void *buf = data->src;

	while (sz--) {
		u32 val = get_unaligned_le32(buf);

		wait_for_bit_le32(priv->regs + MSC_IREG,
				  MSC_IREG_TXFIFO_WR_REQ,
				  true, 10000, false);
		writel(val, priv->regs + MSC_TXFIFO);
		buf += 4;
	}
}
#else
static void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
{}
#endif

static inline int jz_mmc_read_data(struct jz_mmc_priv *priv, struct mmc_data *data)
{
	int sz = data->blocks * data->blocksize;
	void *buf = data->dest;
	u32 stat, val;

	do {
		stat = readl(priv->regs + MSC_STAT);

		if (stat & MSC_STAT_TIME_OUT_READ)
			return -ETIMEDOUT;
		if (stat & MSC_STAT_CRC_READ_ERROR)
			return -EINVAL;
		if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
			udelay(10);
			continue;
		}
		do {
			val = readl(priv->regs + MSC_RXFIFO);
			if (sz == 1)
				*(u8 *)buf = (u8)val;
			else if (sz == 2)
				put_unaligned_le16(val, buf);
			else if (sz >= 4)
				put_unaligned_le32(val, buf);
			buf += 4;
			sz -= 4;
			stat = readl(priv->regs + MSC_STAT);
		} while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
	} while (!(stat & MSC_STAT_DATA_TRAN_DONE));
	return 0;
}

static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
			   struct mmc_cmd *cmd, struct mmc_data *data)
{
	u32 stat, mask, cmdat = 0;
	int i, ret;

	/* stop the clock */
	writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
	ret = wait_for_bit_le32(priv->regs + MSC_STAT,
				MSC_STAT_CLK_EN, false, 10000, false);
	if (ret)
		return ret;

	writel(0, priv->regs + MSC_DMAC);

	/* setup command */
	writel(cmd->cmdidx, priv->regs + MSC_CMD);
	writel(cmd->cmdarg, priv->regs + MSC_ARG);

	if (data) {
		/* setup data */
		cmdat |= MSC_CMDAT_DATA_EN;
		if (data->flags & MMC_DATA_WRITE)
			cmdat |= MSC_CMDAT_WRITE;

		writel(data->blocks, priv->regs + MSC_NOB);
		writel(data->blocksize, priv->regs + MSC_BLKLEN);
	} else {
		writel(0, priv->regs + MSC_NOB);
		writel(0, priv->regs + MSC_BLKLEN);
	}

	/* setup response */
	switch (cmd->resp_type) {
	case MMC_RSP_NONE:
		break;
	case MMC_RSP_R1:
	case MMC_RSP_R1b:
		cmdat |= MSC_CMDAT_RESPONSE_R1;
		break;
	case MMC_RSP_R2:
		cmdat |= MSC_CMDAT_RESPONSE_R2;
		break;
	case MMC_RSP_R3:
		cmdat |= MSC_CMDAT_RESPONSE_R3;
		break;
	default:
		break;
	}

	if (cmd->resp_type & MMC_RSP_BUSY)
		cmdat |= MSC_CMDAT_BUSY;

	/* set init for the first command only */
	if (!(priv->flags & JZ_MMC_SENT_INIT)) {
		cmdat |= MSC_CMDAT_INIT;
		priv->flags |= JZ_MMC_SENT_INIT;
	}

	cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;

	/* write the data setup */
	writel(cmdat, priv->regs + MSC_CMDAT);

	/* unmask interrupts */
	mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES);
	if (data) {
		mask &= ~MSC_IMASK_DATA_TRAN_DONE;
		if (data->flags & MMC_DATA_WRITE) {
			mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
		} else {
			mask &= ~(MSC_IMASK_RXFIFO_RD_REQ |
				  MSC_IMASK_TIME_OUT_READ);
		}
	}
	writel(mask, priv->regs + MSC_IMASK);

	/* clear interrupts */
	writel(0xffffffff, priv->regs + MSC_IREG);

	/* start the command (& the clock) */
	writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START,
	       priv->regs + MSC_STRPCL);

	/* wait for completion */
	for (i = 0; i < 100; i++) {
		stat = readl(priv->regs + MSC_IREG);
		stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES;
		if (stat)
			break;
		mdelay(1);
	}
	writel(stat, priv->regs + MSC_IREG);
	if (stat & MSC_IREG_TIME_OUT_RES)
		return -ETIMEDOUT;

	if (cmd->resp_type & MMC_RSP_PRESENT) {
		/* read the response */
		if (cmd->resp_type & MMC_RSP_136) {
			u16 a, b, c, i;

			a = readw(priv->regs + MSC_RES);
			for (i = 0; i < 4; i++) {
				b = readw(priv->regs + MSC_RES);
				c = readw(priv->regs + MSC_RES);
				cmd->response[i] =
					(a << 24) | (b << 8) | (c >> 8);
				a = c;
			}
		} else {
			cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
			cmd->response[0] |= readw(priv->regs + MSC_RES) << 8;
			cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
		}
	}
	if (data) {
		if (data->flags & MMC_DATA_WRITE)
			jz_mmc_write_data(priv, data);
		else if (data->flags & MMC_DATA_READ) {
			ret = jz_mmc_read_data(priv, data);
			if (ret)
				return ret;
		}
	}

	return 0;
}

static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv)
{
	u32 real_rate = jz_mmc_clock_rate();
	u8 clk_div = 0;

	/* calculate clock divide */
	while ((real_rate > mmc->clock) && (clk_div < 7)) {
		real_rate >>= 1;
		clk_div++;
	}
	writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);

	/* set the bus width for the next command */
	priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
	if (mmc->bus_width == 8)
		priv->flags |= JZ_MMC_BUS_WIDTH_8;
	else if (mmc->bus_width == 4)
		priv->flags |= JZ_MMC_BUS_WIDTH_4;
	else
		priv->flags |= JZ_MMC_BUS_WIDTH_1;

	return 0;
}

static int jz_mmc_core_init(struct mmc *mmc)
{
	struct jz_mmc_priv *priv = mmc->priv;
	int ret;

	/* Reset */
	writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
	ret = wait_for_bit_le32(priv->regs + MSC_STAT,
				MSC_STAT_IS_RESETTING, false, 10000, false);
	if (ret)
		return ret;

	/* Maximum timeouts */
	writel(0xffff, priv->regs + MSC_RESTO);
	writel(0xffffffff, priv->regs + MSC_RDTO);

	/* Enable low power mode */
	writel(0x1, priv->regs + MSC_LPM);

	return 0;
}

#if !CONFIG_IS_ENABLED(DM_MMC)

static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
				  struct mmc_data *data)
{
	struct jz_mmc_priv *priv = mmc->priv;

	return jz_mmc_send_cmd(mmc, priv, cmd, data);
}

static int jz_mmc_legacy_set_ios(struct mmc *mmc)
{
	struct jz_mmc_priv *priv = mmc->priv;

	return jz_mmc_set_ios(mmc, priv);
};

static const struct mmc_ops jz_msc_ops = {
	.send_cmd	= jz_mmc_legacy_send_cmd,
	.set_ios	= jz_mmc_legacy_set_ios,
	.init		= jz_mmc_core_init,
};

static struct jz_mmc_priv jz_mmc_priv_static;
static struct jz_mmc_plat jz_mmc_plat_static = {
	.cfg = {
		.name = "MSC",
		.ops = &jz_msc_ops,

		.voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
			    MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
			    MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36,
		.host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,

		.f_min = 375000,
		.f_max = 48000000,
		.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
	},
};

int jz_mmc_init(void __iomem *base)
{
	struct mmc *mmc;

	jz_mmc_priv_static.regs = base;

	mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);

	return mmc ? 0 : -ENODEV;
}

#else /* CONFIG_DM_MMC */

#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;

static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
			      struct mmc_data *data)
{
	struct jz_mmc_priv *priv = dev_get_priv(dev);
	struct mmc *mmc = mmc_get_mmc_dev(dev);

	return jz_mmc_send_cmd(mmc, priv, cmd, data);
}

static int jz_mmc_dm_set_ios(struct udevice *dev)
{
	struct jz_mmc_priv *priv = dev_get_priv(dev);
	struct mmc *mmc = mmc_get_mmc_dev(dev);

	return jz_mmc_set_ios(mmc, priv);
};

static const struct dm_mmc_ops jz_msc_ops = {
	.send_cmd	= jz_mmc_dm_send_cmd,
	.set_ios	= jz_mmc_dm_set_ios,
};

static int jz_mmc_ofdata_to_platdata(struct udevice *dev)
{
	struct jz_mmc_priv *priv = dev_get_priv(dev);
	struct jz_mmc_plat *plat = dev_get_platdata(dev);
	struct mmc_config *cfg;
	int ret;

	priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);
	cfg = &plat->cfg;

	cfg->name = "MSC";
	cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;

	ret = mmc_of_parse(dev, cfg);
	if (ret < 0) {
		dev_err(dev, "failed to parse host caps\n");
		return ret;
	}

	cfg->f_min = 400000;
	cfg->f_max = 52000000;

	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;

	return 0;
}

static int jz_mmc_bind(struct udevice *dev)
{
	struct jz_mmc_plat *plat = dev_get_platdata(dev);

	return mmc_bind(dev, &plat->mmc, &plat->cfg);
}

static int jz_mmc_probe(struct udevice *dev)
{
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct jz_mmc_priv *priv = dev_get_priv(dev);
	struct jz_mmc_plat *plat = dev_get_platdata(dev);

	plat->mmc.priv = priv;
	upriv->mmc = &plat->mmc;
	return jz_mmc_core_init(&plat->mmc);
}

static const struct udevice_id jz_mmc_ids[] = {
	{ .compatible = "ingenic,jz4780-mmc" },
	{ }
};

U_BOOT_DRIVER(jz_mmc_drv) = {
	.name			= "jz_mmc",
	.id			= UCLASS_MMC,
	.of_match		= jz_mmc_ids,
	.ofdata_to_platdata	= jz_mmc_ofdata_to_platdata,
	.bind			= jz_mmc_bind,
	.probe			= jz_mmc_probe,
	.priv_auto_alloc_size	= sizeof(struct jz_mmc_priv),
	.platdata_auto_alloc_size = sizeof(struct jz_mmc_plat),
	.ops			= &jz_msc_ops,
};
#endif /* CONFIG_DM_MMC */
Commit	Line	Data
d7727139 PB	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Ingenic JZ MMC driver
	4	*
	5	* Copyright (c) 2013 Imagination Technologies
	6	* Author: Paul Burton <paul.burton@imgtec.com>
	7	*/
	8
	9	#include <common.h>
	10	#include <malloc.h>
	11	#include <mmc.h>
	12	#include <asm/io.h>
	13	#include <asm/unaligned.h>
	14	#include <errno.h>
336d4615	15	#include <dm/device_compat.h>
d7727139 PB	16	#include <mach/jz4780.h>
	17	#include <wait_bit.h>
	18
	19	/* Registers */
	20	#define MSC_STRPCL 0x000
	21	#define MSC_STAT 0x004
	22	#define MSC_CLKRT 0x008
	23	#define MSC_CMDAT 0x00c
	24	#define MSC_RESTO 0x010
	25	#define MSC_RDTO 0x014
	26	#define MSC_BLKLEN 0x018
	27	#define MSC_NOB 0x01c
	28	#define MSC_SNOB 0x020
	29	#define MSC_IMASK 0x024
	30	#define MSC_IREG 0x028
	31	#define MSC_CMD 0x02c
	32	#define MSC_ARG 0x030
	33	#define MSC_RES 0x034
	34	#define MSC_RXFIFO 0x038
	35	#define MSC_TXFIFO 0x03c
	36	#define MSC_LPM 0x040
	37	#define MSC_DMAC 0x044
	38	#define MSC_DMANDA 0x048
	39	#define MSC_DMADA 0x04c
	40	#define MSC_DMALEN 0x050
	41	#define MSC_DMACMD 0x054
	42	#define MSC_CTRL2 0x058
	43	#define MSC_RTCNT 0x05c
	44	#define MSC_DBG 0x0fc
	45
	46	/* MSC Clock and Control Register (MSC_STRPCL) */
	47	#define MSC_STRPCL_EXIT_MULTIPLE BIT(7)
	48	#define MSC_STRPCL_EXIT_TRANSFER BIT(6)
	49	#define MSC_STRPCL_START_READWAIT BIT(5)
	50	#define MSC_STRPCL_STOP_READWAIT BIT(4)
	51	#define MSC_STRPCL_RESET BIT(3)
	52	#define MSC_STRPCL_START_OP BIT(2)
	53	#define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0)
	54	#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
	55
	56	/* MSC Status Register (MSC_STAT) */
	57	#define MSC_STAT_AUTO_CMD_DONE BIT(31)
	58	#define MSC_STAT_IS_RESETTING BIT(15)
	59	#define MSC_STAT_SDIO_INT_ACTIVE BIT(14)
	60	#define MSC_STAT_PRG_DONE BIT(13)
	61	#define MSC_STAT_DATA_TRAN_DONE BIT(12)
	62	#define MSC_STAT_END_CMD_RES BIT(11)
	63	#define MSC_STAT_DATA_FIFO_AFULL BIT(10)
	64	#define MSC_STAT_IS_READWAIT BIT(9)
	65	#define MSC_STAT_CLK_EN BIT(8)
	66	#define MSC_STAT_DATA_FIFO_FULL BIT(7)
	67	#define MSC_STAT_DATA_FIFO_EMPTY BIT(6)
	68	#define MSC_STAT_CRC_RES_ERR BIT(5)
	69	#define MSC_STAT_CRC_READ_ERROR BIT(4)
	70	#define MSC_STAT_CRC_WRITE_ERROR BIT(2)
	71	#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
	72	#define MSC_STAT_TIME_OUT_RES BIT(1)
	73	#define MSC_STAT_TIME_OUT_READ BIT(0)
	74
	75	/* MSC Bus Clock Control Register (MSC_CLKRT) */
	76	#define MSC_CLKRT_CLK_RATE_MASK 0x7
	77
	78	/* MSC Command Sequence Control Register (MSC_CMDAT) */
	79	#define MSC_CMDAT_IO_ABORT BIT(11)
80	#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9)
81	#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9)
82	#define MSC_CMDAT_DMA_EN BIT(8)
83	#define MSC_CMDAT_INIT BIT(7)
84	#define MSC_CMDAT_BUSY BIT(6)
85	#define MSC_CMDAT_STREAM_BLOCK BIT(5)
86	#define MSC_CMDAT_WRITE BIT(4)
87	#define MSC_CMDAT_DATA_EN BIT(3)
88	#define MSC_CMDAT_RESPONSE_MASK (0x7 << 0)
89	#define MSC_CMDAT_RESPONSE_NONE (0x0 << 0) /* No response */
90	#define MSC_CMDAT_RESPONSE_R1 (0x1 << 0) /* Format R1 and R1b */
91	#define MSC_CMDAT_RESPONSE_R2 (0x2 << 0) /* Format R2 */
92	#define MSC_CMDAT_RESPONSE_R3 (0x3 << 0) /* Format R3 */
93	#define MSC_CMDAT_RESPONSE_R4 (0x4 << 0) /* Format R4 */
94	#define MSC_CMDAT_RESPONSE_R5 (0x5 << 0) /* Format R5 */
95	#define MSC_CMDAT_RESPONSE_R6 (0x6 << 0) /* Format R6 */
96
97	/* MSC Interrupts Mask Register (MSC_IMASK) */
98	#define MSC_IMASK_TIME_OUT_RES BIT(9)
99	#define MSC_IMASK_TIME_OUT_READ BIT(8)
100	#define MSC_IMASK_SDIO BIT(7)
101	#define MSC_IMASK_TXFIFO_WR_REQ BIT(6)
102	#define MSC_IMASK_RXFIFO_RD_REQ BIT(5)
103	#define MSC_IMASK_END_CMD_RES BIT(2)
104	#define MSC_IMASK_PRG_DONE BIT(1)
105	#define MSC_IMASK_DATA_TRAN_DONE BIT(0)
106
107	/* MSC Interrupts Status Register (MSC_IREG) */
108	#define MSC_IREG_TIME_OUT_RES BIT(9)
109	#define MSC_IREG_TIME_OUT_READ BIT(8)
110	#define MSC_IREG_SDIO BIT(7)
111	#define MSC_IREG_TXFIFO_WR_REQ BIT(6)
112	#define MSC_IREG_RXFIFO_RD_REQ BIT(5)
113	#define MSC_IREG_END_CMD_RES BIT(2)
114	#define MSC_IREG_PRG_DONE BIT(1)
115	#define MSC_IREG_DATA_TRAN_DONE BIT(0)
116
117	struct jz_mmc_plat {
118	struct mmc_config cfg;
119	struct mmc mmc;
120	};
121
122	struct jz_mmc_priv {
123	void __iomem *regs;
124	u32 flags;
125	/* priv flags */
126	#define JZ_MMC_BUS_WIDTH_MASK 0x3
127	#define JZ_MMC_BUS_WIDTH_1 0x0
128	#define JZ_MMC_BUS_WIDTH_4 0x2
129	#define JZ_MMC_BUS_WIDTH_8 0x3
130	#define JZ_MMC_SENT_INIT BIT(2)
131	};
132
133	static int jz_mmc_clock_rate(void)
134	{
135	return 24000000;
136	}
137
82d54647 EG	138	#if CONFIG_IS_ENABLED(MMC_WRITE)
	139	static inline void jz_mmc_write_data(struct jz_mmc_priv priv, struct mmc_data data)
	140	{
	141	int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
	142	const void *buf = data->src;
	143
	144	while (sz--) {
	145	u32 val = get_unaligned_le32(buf);
	146
	147	wait_for_bit_le32(priv->regs + MSC_IREG,
	148	MSC_IREG_TXFIFO_WR_REQ,
	149	true, 10000, false);
	150	writel(val, priv->regs + MSC_TXFIFO);
	151	buf += 4;
	152	}
	153	}
	154	#else
	155	static void jz_mmc_write_data(struct jz_mmc_priv priv, struct mmc_data data)
	156	{}
	157	#endif
	158
	159	static inline int jz_mmc_read_data(struct jz_mmc_priv priv, struct mmc_data data)
	160	{
	161	int sz = data->blocks * data->blocksize;
	162	void *buf = data->dest;
	163	u32 stat, val;
	164
	165	do {
	166	stat = readl(priv->regs + MSC_STAT);
	167
	168	if (stat & MSC_STAT_TIME_OUT_READ)
	169	return -ETIMEDOUT;
	170	if (stat & MSC_STAT_CRC_READ_ERROR)
	171	return -EINVAL;
	172	if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
	173	udelay(10);
	174	continue;
	175	}
	176	do {
	177	val = readl(priv->regs + MSC_RXFIFO);
	178	if (sz == 1)
	179	(u8 )buf = (u8)val;
	180	else if (sz == 2)
	181	put_unaligned_le16(val, buf);
	182	else if (sz >= 4)
	183	put_unaligned_le32(val, buf);
	184	buf += 4;
	185	sz -= 4;
	186	stat = readl(priv->regs + MSC_STAT);
	187	} while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
	188	} while (!(stat & MSC_STAT_DATA_TRAN_DONE));
	189	return 0;
	190	}
	191
d7727139 PB	192	static int jz_mmc_send_cmd(struct mmc mmc, struct jz_mmc_priv priv,
	193	struct mmc_cmd cmd, struct mmc_data data)
	194	{
	195	u32 stat, mask, cmdat = 0;
	196	int i, ret;
	197
	198	/* stop the clock */
	199	writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
	200	ret = wait_for_bit_le32(priv->regs + MSC_STAT,
	201	MSC_STAT_CLK_EN, false, 10000, false);
	202	if (ret)
	203	return ret;
	204
	205	writel(0, priv->regs + MSC_DMAC);
	206
	207	/* setup command */
	208	writel(cmd->cmdidx, priv->regs + MSC_CMD);
	209	writel(cmd->cmdarg, priv->regs + MSC_ARG);
	210
	211	if (data) {
	212	/* setup data */
	213	cmdat \|= MSC_CMDAT_DATA_EN;
	214	if (data->flags & MMC_DATA_WRITE)
	215	cmdat \|= MSC_CMDAT_WRITE;
	216
	217	writel(data->blocks, priv->regs + MSC_NOB);
	218	writel(data->blocksize, priv->regs + MSC_BLKLEN);
	219	} else {
	220	writel(0, priv->regs + MSC_NOB);
	221	writel(0, priv->regs + MSC_BLKLEN);
	222	}
	223
	224	/* setup response */
	225	switch (cmd->resp_type) {
	226	case MMC_RSP_NONE:
	227	break;
	228	case MMC_RSP_R1:
	229	case MMC_RSP_R1b:
	230	cmdat \|= MSC_CMDAT_RESPONSE_R1;
	231	break;
	232	case MMC_RSP_R2:
	233	cmdat \|= MSC_CMDAT_RESPONSE_R2;
	234	break;
	235	case MMC_RSP_R3:
	236	cmdat \|= MSC_CMDAT_RESPONSE_R3;
	237	break;
	238	default:
	239	break;
	240	}
	241
	242	if (cmd->resp_type & MMC_RSP_BUSY)
	243	cmdat \|= MSC_CMDAT_BUSY;
	244
	245	/* set init for the first command only */
	246	if (!(priv->flags & JZ_MMC_SENT_INIT)) {
	247	cmdat \|= MSC_CMDAT_INIT;
	248	priv->flags \|= JZ_MMC_SENT_INIT;
	249	}
	250
	251	cmdat \|= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;
	252
	253	/* write the data setup */
	254	writel(cmdat, priv->regs + MSC_CMDAT);
	255
256	/* unmask interrupts */
257	mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES \| MSC_IMASK_TIME_OUT_RES);
258	if (data) {
259	mask &= ~MSC_IMASK_DATA_TRAN_DONE;
260	if (data->flags & MMC_DATA_WRITE) {
261	mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
262	} else {
263	mask &= ~(MSC_IMASK_RXFIFO_RD_REQ \|
264	MSC_IMASK_TIME_OUT_READ);
265	}
266	}
267	writel(mask, priv->regs + MSC_IMASK);
268
269	/* clear interrupts */
270	writel(0xffffffff, priv->regs + MSC_IREG);
271
272	/* start the command (& the clock) */
273	writel(MSC_STRPCL_START_OP \| MSC_STRPCL_CLOCK_CONTROL_START,
274	priv->regs + MSC_STRPCL);
275
276	/* wait for completion */
277	for (i = 0; i < 100; i++) {
278	stat = readl(priv->regs + MSC_IREG);
279	stat &= MSC_IREG_END_CMD_RES \| MSC_IREG_TIME_OUT_RES;
280	if (stat)
281	break;
282	mdelay(1);
283	}
284	writel(stat, priv->regs + MSC_IREG);
285	if (stat & MSC_IREG_TIME_OUT_RES)
286	return -ETIMEDOUT;
287
288	if (cmd->resp_type & MMC_RSP_PRESENT) {
289	/* read the response */
290	if (cmd->resp_type & MMC_RSP_136) {
291	u16 a, b, c, i;
292
293	a = readw(priv->regs + MSC_RES);
294	for (i = 0; i < 4; i++) {
295	b = readw(priv->regs + MSC_RES);
296	c = readw(priv->regs + MSC_RES);
297	cmd->response[i] =
298	(a << 24) \| (b << 8) \| (c >> 8);
299	a = c;
300	}
301	} else {
302	cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
303	cmd->response[0] \|= readw(priv->regs + MSC_RES) << 8;
304	cmd->response[0] \|= readw(priv->regs + MSC_RES) & 0xff;
305	}
306	}
82d54647 EG	307	if (data) {
	308	if (data->flags & MMC_DATA_WRITE)
	309	jz_mmc_write_data(priv, data);
	310	else if (data->flags & MMC_DATA_READ) {
	311	ret = jz_mmc_read_data(priv, data);
	312	if (ret)
	313	return ret;
d7727139	314	}
d7727139 PB	315	}
	316
	317	return 0;
	318	}
	319
	320	static int jz_mmc_set_ios(struct mmc mmc, struct jz_mmc_priv priv)
	321	{
	322	u32 real_rate = jz_mmc_clock_rate();
	323	u8 clk_div = 0;
	324
	325	/* calculate clock divide */
	326	while ((real_rate > mmc->clock) && (clk_div < 7)) {
	327	real_rate >>= 1;
	328	clk_div++;
	329	}
	330	writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);
	331
	332	/* set the bus width for the next command */
	333	priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
	334	if (mmc->bus_width == 8)
	335	priv->flags \|= JZ_MMC_BUS_WIDTH_8;
	336	else if (mmc->bus_width == 4)
	337	priv->flags \|= JZ_MMC_BUS_WIDTH_4;
	338	else
	339	priv->flags \|= JZ_MMC_BUS_WIDTH_1;
	340
	341	return 0;
	342	}
	343
	344	static int jz_mmc_core_init(struct mmc *mmc)
	345	{
	346	struct jz_mmc_priv *priv = mmc->priv;
	347	int ret;
	348
	349	/* Reset */
	350	writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
	351	ret = wait_for_bit_le32(priv->regs + MSC_STAT,
	352	MSC_STAT_IS_RESETTING, false, 10000, false);
	353	if (ret)
	354	return ret;
	355
	356	/* Maximum timeouts */
	357	writel(0xffff, priv->regs + MSC_RESTO);
	358	writel(0xffffffff, priv->regs + MSC_RDTO);
	359
	360	/* Enable low power mode */
	361	writel(0x1, priv->regs + MSC_LPM);
	362
	363	return 0;
	364	}
	365
	366	#if !CONFIG_IS_ENABLED(DM_MMC)
	367
	368	static int jz_mmc_legacy_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
	369	struct mmc_data *data)
	370	{
	371	struct jz_mmc_priv *priv = mmc->priv;
	372
	373	return jz_mmc_send_cmd(mmc, priv, cmd, data);
	374	}
	375
	376	static int jz_mmc_legacy_set_ios(struct mmc *mmc)
	377	{
	378	struct jz_mmc_priv *priv = mmc->priv;
379
380	return jz_mmc_set_ios(mmc, priv);
381	};
382
383	static const struct mmc_ops jz_msc_ops = {
384	.send_cmd = jz_mmc_legacy_send_cmd,
385	.set_ios = jz_mmc_legacy_set_ios,
386	.init = jz_mmc_core_init,
387	};
388
389	static struct jz_mmc_priv jz_mmc_priv_static;
390	static struct jz_mmc_plat jz_mmc_plat_static = {
391	.cfg = {
392	.name = "MSC",
393	.ops = &jz_msc_ops,
394
395	.voltages = MMC_VDD_27_28 \| MMC_VDD_28_29 \| MMC_VDD_29_30 \|
396	MMC_VDD_30_31 \| MMC_VDD_31_32 \| MMC_VDD_32_33 \|
397	MMC_VDD_33_34 \| MMC_VDD_34_35 \| MMC_VDD_35_36,
398	.host_caps = MMC_MODE_4BIT \| MMC_MODE_HS_52MHz \| MMC_MODE_HS,
399
400	.f_min = 375000,
401	.f_max = 48000000,
402	.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
403	},
404	};
405
406	int jz_mmc_init(void __iomem *base)
407	{
408	struct mmc *mmc;
409
410	jz_mmc_priv_static.regs = base;
411
412	mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);
413
414	return mmc ? 0 : -ENODEV;
415	}
416
417	#else /* CONFIG_DM_MMC */
418
419	#include <dm.h>
420	DECLARE_GLOBAL_DATA_PTR;
421
422	static int jz_mmc_dm_send_cmd(struct udevice dev, struct mmc_cmd cmd,
423	struct mmc_data *data)
424	{
425	struct jz_mmc_priv *priv = dev_get_priv(dev);
426	struct mmc *mmc = mmc_get_mmc_dev(dev);
427
428	return jz_mmc_send_cmd(mmc, priv, cmd, data);
429	}
430
431	static int jz_mmc_dm_set_ios(struct udevice *dev)
432	{
433	struct jz_mmc_priv *priv = dev_get_priv(dev);
434	struct mmc *mmc = mmc_get_mmc_dev(dev);
435
436	return jz_mmc_set_ios(mmc, priv);
437	};
438
439	static const struct dm_mmc_ops jz_msc_ops = {
440	.send_cmd = jz_mmc_dm_send_cmd,
441	.set_ios = jz_mmc_dm_set_ios,
442	};
443
444	static int jz_mmc_ofdata_to_platdata(struct udevice *dev)
445	{
446	struct jz_mmc_priv *priv = dev_get_priv(dev);
447	struct jz_mmc_plat *plat = dev_get_platdata(dev);
448	struct mmc_config *cfg;
449	int ret;
450
451	priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);
452	cfg = &plat->cfg;
453
454	cfg->name = "MSC";
455	cfg->host_caps = MMC_MODE_HS_52MHz \| MMC_MODE_HS;
456
457	ret = mmc_of_parse(dev, cfg);
458	if (ret < 0) {
459	dev_err(dev, "failed to parse host caps\n");
460	return ret;
461	}
462
463	cfg->f_min = 400000;
464	cfg->f_max = 52000000;
465
466	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
467	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
468
469	return 0;
470	}
471
472	static int jz_mmc_bind(struct udevice *dev)
473	{
474	struct jz_mmc_plat *plat = dev_get_platdata(dev);
475
476	return mmc_bind(dev, &plat->mmc, &plat->cfg);
477	}
478
479	static int jz_mmc_probe(struct udevice *dev)
480	{
481	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
482	struct jz_mmc_priv *priv = dev_get_priv(dev);
483	struct jz_mmc_plat *plat = dev_get_platdata(dev);
484
485	plat->mmc.priv = priv;
486	upriv->mmc = &plat->mmc;
487	return jz_mmc_core_init(&plat->mmc);
488	}
489
490	static const struct udevice_id jz_mmc_ids[] = {
491	{ .compatible = "ingenic,jz4780-mmc" },
492	{ }
493	};
494
495	U_BOOT_DRIVER(jz_mmc_drv) = {
496	.name = "jz_mmc",
497	.id = UCLASS_MMC,
498	.of_match = jz_mmc_ids,
499	.ofdata_to_platdata = jz_mmc_ofdata_to_platdata,
500	.bind = jz_mmc_bind,
501	.probe = jz_mmc_probe,
502	.priv_auto_alloc_size = sizeof(struct jz_mmc_priv),
503	.platdata_auto_alloc_size = sizeof(struct jz_mmc_plat),
504	.ops = &jz_msc_ops,
505	};
506	#endif /* CONFIG_DM_MMC */