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Merge tag 'u-boot-rockchip-20190809' of https://gitlab.denx.de/u-boot/custodians...
[thirdparty/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 2/*
3 * Copyright 2008, Freescale Semiconductor, Inc
4 * Andy Fleming
5 *
6 * Based vaguely on the Linux code
272cc70b
AF		 7 */
8
9#include <config.h>
10#include <common.h>
11#include <command.h>
8e3332e2
SS		 12#include <dm.h>
13#include <dm/device-internal.h>
d4622df3 14#include <errno.h>
272cc70b
AF		 15#include <mmc.h>
16#include <part.h>
2051aefe 17#include <power/regulator.h>
272cc70b 18#include <malloc.h>
cf92e05c 19#include <memalign.h>
272cc70b 20#include <linux/list.h>
9b1f942c 21#include <div64.h>
da61fa5f 22#include "mmc_private.h"
272cc70b 23
39320c53
JJH		 24#define DEFAULT_CMD6_TIMEOUT_MS 500
25
aff5d3c8 26static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
fb7c3beb 27static int mmc_power_cycle(struct mmc *mmc);
62d77cea 28#if !CONFIG_IS_ENABLED(MMC_TINY)
01298da3 29static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
b5b838f1
MV		 30#endif
31
e7881d85 32#if !CONFIG_IS_ENABLED(DM_MMC)
c10b85d6
JJH		 33
34static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
35{
36 return -ENOSYS;
37}
38
750121c3 39__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 40{
41 return -1;
42}
43
44int mmc_getwp(struct mmc *mmc)
45{
46 int wp;
47
48 wp = board_mmc_getwp(mmc);
49
d4e1da4e 50 if (wp < 0) {
93bfd616
PA		 51 if (mmc->cfg->ops->getwp)
52 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 53 else
54 wp = 0;
55 }
d23d8d7e
NK		 56
57 return wp;
58}
59
cee9ab7c
JH		 60__weak int board_mmc_getcd(struct mmc *mmc)
61{
11fdade2
SB		 62 return -1;
63}
8ca51e51 64#endif
11fdade2 65
c0c76eba
SG		 66#ifdef CONFIG_MMC_TRACE
67void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 68{
c0c76eba 69 printf("CMD_SEND:%d\n", cmd->cmdidx);
7d5ccb1a 70 printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
c0c76eba 71}
8635ff9e 72
c0c76eba
SG		 73void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
74{
5db2fe3a
RR		 75 int i;
76 u8 *ptr;
77
7863ce58
BM		 78 if (ret) {
79 printf("\t\tRET\t\t\t %d\n", ret);
80 } else {
81 switch (cmd->resp_type) {
82 case MMC_RSP_NONE:
83 printf("\t\tMMC_RSP_NONE\n");
84 break;
85 case MMC_RSP_R1:
7d5ccb1a 86 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
7863ce58
BM		 87 cmd->response[0]);
88 break;
89 case MMC_RSP_R1b:
7d5ccb1a 90 printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
7863ce58
BM		 91 cmd->response[0]);
92 break;
93 case MMC_RSP_R2:
7d5ccb1a 94 printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
7863ce58 95 cmd->response[0]);
7d5ccb1a 96 printf("\t\t \t\t 0x%08x \n",
7863ce58 97 cmd->response[1]);
7d5ccb1a 98 printf("\t\t \t\t 0x%08x \n",
7863ce58 99 cmd->response[2]);
7d5ccb1a 100 printf("\t\t \t\t 0x%08x \n",
7863ce58 101 cmd->response[3]);
5db2fe3a 102 printf("\n");
7863ce58
BM		 103 printf("\t\t\t\t\tDUMPING DATA\n");
104 for (i = 0; i < 4; i++) {
105 int j;
106 printf("\t\t\t\t\t%03d - ", i*4);
107 ptr = (u8 *)&cmd->response[i];
108 ptr += 3;
109 for (j = 0; j < 4; j++)
7d5ccb1a 110 printf("%02x ", *ptr--);
7863ce58
BM		 111 printf("\n");
112 }
113 break;
114 case MMC_RSP_R3:
7d5ccb1a 115 printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
7863ce58
BM		 116 cmd->response[0]);
117 break;
118 default:
119 printf("\t\tERROR MMC rsp not supported\n");
120 break;
53e8e40b 121 }
5db2fe3a 122 }
c0c76eba
SG		 123}
124
125void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
126{
127 int status;
128
129 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
130 printf("CURR STATE:%d\n", status);
131}
5db2fe3a 132#endif
c0c76eba 133
35f9e196
JJH		 134#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
135const char *mmc_mode_name(enum bus_mode mode)
136{
137 static const char *const names[] = {
138 [MMC_LEGACY] = "MMC legacy",
139 [SD_LEGACY] = "SD Legacy",
140 [MMC_HS] = "MMC High Speed (26MHz)",
141 [SD_HS] = "SD High Speed (50MHz)",
142 [UHS_SDR12] = "UHS SDR12 (25MHz)",
143 [UHS_SDR25] = "UHS SDR25 (50MHz)",
144 [UHS_SDR50] = "UHS SDR50 (100MHz)",
145 [UHS_SDR104] = "UHS SDR104 (208MHz)",
146 [UHS_DDR50] = "UHS DDR50 (50MHz)",
147 [MMC_HS_52] = "MMC High Speed (52MHz)",
148 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
149 [MMC_HS_200] = "HS200 (200MHz)",
3dd2626f 150 [MMC_HS_400] = "HS400 (200MHz)",
44acd492 151 [MMC_HS_400_ES] = "HS400ES (200MHz)",
35f9e196
JJH		 152 };
153
154 if (mode >= MMC_MODES_END)
155 return "Unknown mode";
156 else
157 return names[mode];
158}
159#endif
160
05038576
JJH		 161static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
162{
163 static const int freqs[] = {
1b313aa3 164 [MMC_LEGACY] = 25000000,
05038576
JJH		 165 [SD_LEGACY] = 25000000,
166 [MMC_HS] = 26000000,
167 [SD_HS] = 50000000,
1b313aa3
JC		 168 [MMC_HS_52] = 52000000,
169 [MMC_DDR_52] = 52000000,
05038576
JJH		 170 [UHS_SDR12] = 25000000,
171 [UHS_SDR25] = 50000000,
172 [UHS_SDR50] = 100000000,
05038576 173 [UHS_DDR50] = 50000000,
f99c2efe 174 [UHS_SDR104] = 208000000,
05038576 175 [MMC_HS_200] = 200000000,
3dd2626f 176 [MMC_HS_400] = 200000000,
44acd492 177 [MMC_HS_400_ES] = 200000000,
05038576
JJH		 178 };
179
180 if (mode == MMC_LEGACY)
181 return mmc->legacy_speed;
182 else if (mode >= MMC_MODES_END)
183 return 0;
184 else
185 return freqs[mode];
186}
187
35f9e196
JJH		 188static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
189{
190 mmc->selected_mode = mode;
05038576 191 mmc->tran_speed = mmc_mode2freq(mmc, mode);
3862b854 192 mmc->ddr_mode = mmc_is_mode_ddr(mode);
d4d64889
MY		 193 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
194 mmc->tran_speed / 1000000);
35f9e196
JJH		 195 return 0;
196}
197
e7881d85 198#if !CONFIG_IS_ENABLED(DM_MMC)
c0c76eba
SG		 199int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
200{
201 int ret;
202
203 mmmc_trace_before_send(mmc, cmd);
204 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
205 mmmc_trace_after_send(mmc, cmd, ret);
206
8635ff9e 207 return ret;
272cc70b 208}
8ca51e51 209#endif
272cc70b 210
863d1004 211int mmc_send_status(struct mmc *mmc, unsigned int *status)
5d4fc8d9
RR		 212{
213 struct mmc_cmd cmd;
d617c426 214 int err, retries = 5;
5d4fc8d9
RR		 215
216 cmd.cmdidx = MMC_CMD_SEND_STATUS;
217 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 218 if (!mmc_host_is_spi(mmc))
219 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 220
863d1004 221 while (retries--) {
5d4fc8d9 222 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426 223 if (!err) {
863d1004
JJH		 224 mmc_trace_state(mmc, &cmd);
225 *status = cmd.response[0];
226 return 0;
227 }
228 }
229 mmc_trace_state(mmc, &cmd);
230 return -ECOMM;
231}
232
233int mmc_poll_for_busy(struct mmc *mmc, int timeout)
234{
235 unsigned int status;
236 int err;
d0c221fe 237
cd0b80ec
JJH		 238 err = mmc_wait_dat0(mmc, 1, timeout);
239 if (err != -ENOSYS)
240 return err;
241
863d1004
JJH		 242 while (1) {
243 err = mmc_send_status(mmc, &status);
244 if (err)
245 return err;
246
247 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
248 (status & MMC_STATUS_CURR_STATE) !=
249 MMC_STATE_PRG)
250 break;
251
252 if (status & MMC_STATUS_MASK) {
56196826 253#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
863d1004 254 pr_err("Status Error: 0x%08x\n", status);
56196826 255#endif
863d1004
JJH		 256 return -ECOMM;
257 }
5d4fc8d9 258
1677eef4
AG		 259 if (timeout-- <= 0)
260 break;
5d4fc8d9 261
1677eef4
AG		 262 udelay(1000);
263 }
5d4fc8d9 264
5b0c942f 265 if (timeout <= 0) {
56196826 266#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 267 pr_err("Timeout waiting card ready\n");
56196826 268#endif
915ffa52 269 return -ETIMEDOUT;
5d4fc8d9
RR		 270 }
271
272 return 0;
273}
274
da61fa5f 275int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 276{
277 struct mmc_cmd cmd;
83dc4227 278 int err;
272cc70b 279
786e8f81 280 if (mmc->ddr_mode)
d22e3d46
JC		 281 return 0;
282
272cc70b
AF		 283 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
284 cmd.resp_type = MMC_RSP_R1;
285 cmd.cmdarg = len;
272cc70b 286
83dc4227
KVA		 287 err = mmc_send_cmd(mmc, &cmd, NULL);
288
289#ifdef CONFIG_MMC_QUIRKS
290 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
291 int retries = 4;
292 /*
293 * It has been seen that SET_BLOCKLEN may fail on the first
294 * attempt, let's try a few more time
295 */
296 do {
297 err = mmc_send_cmd(mmc, &cmd, NULL);
298 if (!err)
299 break;
300 } while (retries--);
301 }
302#endif
303
304 return err;
272cc70b
AF		 305}
306
f99c2efe 307#ifdef MMC_SUPPORTS_TUNING
9815e3ba
JJH		 308static const u8 tuning_blk_pattern_4bit[] = {
309 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
310 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
311 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
312 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
313 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
314 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
315 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
316 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
317};
318
319static const u8 tuning_blk_pattern_8bit[] = {
320 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
321 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
322 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
323 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
324 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
325 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
326 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
327 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
328 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
329 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
330 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
331 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
332 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
333 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
334 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
335 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
336};
337
338int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
339{
340 struct mmc_cmd cmd;
341 struct mmc_data data;
342 const u8 *tuning_block_pattern;
343 int size, err;
344
345 if (mmc->bus_width == 8) {
346 tuning_block_pattern = tuning_blk_pattern_8bit;
347 size = sizeof(tuning_blk_pattern_8bit);
348 } else if (mmc->bus_width == 4) {
349 tuning_block_pattern = tuning_blk_pattern_4bit;
350 size = sizeof(tuning_blk_pattern_4bit);
351 } else {
352 return -EINVAL;
353 }
354
355 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
356
357 cmd.cmdidx = opcode;
358 cmd.cmdarg = 0;
359 cmd.resp_type = MMC_RSP_R1;
360
361 data.dest = (void *)data_buf;
362 data.blocks = 1;
363 data.blocksize = size;
364 data.flags = MMC_DATA_READ;
365
366 err = mmc_send_cmd(mmc, &cmd, &data);
367 if (err)
368 return err;
369
370 if (memcmp(data_buf, tuning_block_pattern, size))
371 return -EIO;
372
373 return 0;
374}
f99c2efe 375#endif
9815e3ba 376
ff8fef56 377static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 378 lbaint_t blkcnt)
272cc70b
AF		 379{
380 struct mmc_cmd cmd;
381 struct mmc_data data;
382
4a1a06bc
AS		 383 if (blkcnt > 1)
384 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
385 else
386 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 387
388 if (mmc->high_capacity)
4a1a06bc 389 cmd.cmdarg = start;
272cc70b 390 else
4a1a06bc 391 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 392
393 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 394
395 data.dest = dst;
4a1a06bc 396 data.blocks = blkcnt;
272cc70b
AF		 397 data.blocksize = mmc->read_bl_len;
398 data.flags = MMC_DATA_READ;
399
4a1a06bc
AS		 400 if (mmc_send_cmd(mmc, &cmd, &data))
401 return 0;
272cc70b 402
4a1a06bc
AS		 403 if (blkcnt > 1) {
404 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
405 cmd.cmdarg = 0;
406 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 407 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 408#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 409 pr_err("mmc fail to send stop cmd\n");
56196826 410#endif
4a1a06bc
AS		 411 return 0;
412 }
272cc70b
AF		 413 }
414
4a1a06bc 415 return blkcnt;
272cc70b
AF		 416}
417
c4d660d4 418#if CONFIG_IS_ENABLED(BLK)
7dba0b93 419ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 420#else
7dba0b93
SG		 421ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
422 void *dst)
33fb211d 423#endif
272cc70b 424{
c4d660d4 425#if CONFIG_IS_ENABLED(BLK)
33fb211d
SG		 426 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
427#endif
bcce53d0 428 int dev_num = block_dev->devnum;
873cc1d7 429 int err;
4a1a06bc
AS		 430 lbaint_t cur, blocks_todo = blkcnt;
431
432 if (blkcnt == 0)
433 return 0;
272cc70b 434
4a1a06bc 435 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 436 if (!mmc)
437 return 0;
438
b5b838f1
MV		 439 if (CONFIG_IS_ENABLED(MMC_TINY))
440 err = mmc_switch_part(mmc, block_dev->hwpart);
441 else
442 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
443
873cc1d7
SW		 444 if (err < 0)
445 return 0;
446
c40fdca6 447 if ((start + blkcnt) > block_dev->lba) {
56196826 448#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420
JJH		 449 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
450 start + blkcnt, block_dev->lba);
56196826 451#endif
d2bf29e3
LW		 452 return 0;
453 }
272cc70b 454
11692991 455 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
d4d64889 456 pr_debug("%s: Failed to set blocklen\n", __func__);
272cc70b 457 return 0;
11692991 458 }
272cc70b 459
4a1a06bc 460 do {
93bfd616
PA		 461 cur = (blocks_todo > mmc->cfg->b_max) ?
462 mmc->cfg->b_max : blocks_todo;
11692991 463 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
d4d64889 464 pr_debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 465 return 0;
11692991 466 }
4a1a06bc
AS		 467 blocks_todo -= cur;
468 start += cur;
469 dst += cur * mmc->read_bl_len;
470 } while (blocks_todo > 0);
272cc70b
AF		 471
472 return blkcnt;
473}
474
fdbb873e 475static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 476{
477 struct mmc_cmd cmd;
478 int err;
479
480 udelay(1000);
481
482 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
483 cmd.cmdarg = 0;
484 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 485
486 err = mmc_send_cmd(mmc, &cmd, NULL);
487
488 if (err)
489 return err;
490
491 udelay(2000);
492
493 return 0;
494}
495
f99c2efe 496#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 497static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
498{
499 struct mmc_cmd cmd;
500 int err = 0;
501
502 /*
503 * Send CMD11 only if the request is to switch the card to
504 * 1.8V signalling.
505 */
506 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
507 return mmc_set_signal_voltage(mmc, signal_voltage);
508
509 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
510 cmd.cmdarg = 0;
511 cmd.resp_type = MMC_RSP_R1;
512
513 err = mmc_send_cmd(mmc, &cmd, NULL);
514 if (err)
515 return err;
516
517 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
518 return -EIO;
519
520 /*
521 * The card should drive cmd and dat[0:3] low immediately
522 * after the response of cmd11, but wait 100 us to be sure
523 */
524 err = mmc_wait_dat0(mmc, 0, 100);
525 if (err == -ENOSYS)
526 udelay(100);
527 else if (err)
528 return -ETIMEDOUT;
529
530 /*
531 * During a signal voltage level switch, the clock must be gated
532 * for 5 ms according to the SD spec
533 */
65117182 534 mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
c10b85d6
JJH		 535
536 err = mmc_set_signal_voltage(mmc, signal_voltage);
537 if (err)
538 return err;
539
540 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
541 mdelay(10);
65117182 542 mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
c10b85d6
JJH		 543
544 /*
545 * Failure to switch is indicated by the card holding
546 * dat[0:3] low. Wait for at least 1 ms according to spec
547 */
548 err = mmc_wait_dat0(mmc, 1, 1000);
549 if (err == -ENOSYS)
550 udelay(1000);
551 else if (err)
552 return -ETIMEDOUT;
553
554 return 0;
555}
f99c2efe 556#endif
c10b85d6
JJH		 557
558static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
272cc70b
AF		 559{
560 int timeout = 1000;
561 int err;
562 struct mmc_cmd cmd;
563
1677eef4 564 while (1) {
272cc70b
AF		 565 cmd.cmdidx = MMC_CMD_APP_CMD;
566 cmd.resp_type = MMC_RSP_R1;
567 cmd.cmdarg = 0;
272cc70b
AF		 568
569 err = mmc_send_cmd(mmc, &cmd, NULL);
570
571 if (err)
572 return err;
573
574 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
575 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 576
577 /*
578 * Most cards do not answer if some reserved bits
579 * in the ocr are set. However, Some controller
580 * can set bit 7 (reserved for low voltages), but
581 * how to manage low voltages SD card is not yet
582 * specified.
583 */
d52ebf10 584 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 585 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 586
587 if (mmc->version == SD_VERSION_2)
588 cmd.cmdarg |= OCR_HCS;
589
c10b85d6
JJH		 590 if (uhs_en)
591 cmd.cmdarg |= OCR_S18R;
592
272cc70b
AF		 593 err = mmc_send_cmd(mmc, &cmd, NULL);
594
595 if (err)
596 return err;
597
1677eef4
AG		 598 if (cmd.response[0] & OCR_BUSY)
599 break;
600
601 if (timeout-- <= 0)
915ffa52 602 return -EOPNOTSUPP;
272cc70b 603
1677eef4
AG		 604 udelay(1000);
605 }
272cc70b
AF		 606
607 if (mmc->version != SD_VERSION_2)
608 mmc->version = SD_VERSION_1_0;
609
d52ebf10
TC		 610 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
611 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
612 cmd.resp_type = MMC_RSP_R3;
613 cmd.cmdarg = 0;
d52ebf10
TC		 614
615 err = mmc_send_cmd(mmc, &cmd, NULL);
616
617 if (err)
618 return err;
619 }
620
998be3dd 621 mmc->ocr = cmd.response[0];
272cc70b 622
f99c2efe 623#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 624 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
625 == 0x41000000) {
626 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
627 if (err)
628 return err;
629 }
f99c2efe 630#endif
c10b85d6 631
272cc70b
AF		 632 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
633 mmc->rca = 0;
634
635 return 0;
636}
637
5289b535 638static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 639{
5289b535 640 struct mmc_cmd cmd;
272cc70b
AF		 641 int err;
642
5289b535
AG		 643 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
644 cmd.resp_type = MMC_RSP_R3;
645 cmd.cmdarg = 0;
5a20397b
RH		 646 if (use_arg && !mmc_host_is_spi(mmc))
647 cmd.cmdarg = OCR_HCS |
93bfd616 648 (mmc->cfg->voltages &
a626c8d4
AG		 649 (mmc->ocr & OCR_VOLTAGE_MASK)) |
650 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 651
5289b535 652 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 653 if (err)
654 return err;
5289b535 655 mmc->ocr = cmd.response[0];
e9550449
CLC		 656 return 0;
657}
658
750121c3 659static int mmc_send_op_cond(struct mmc *mmc)
e9550449 660{
e9550449
CLC		 661 int err, i;
662
272cc70b
AF		 663 /* Some cards seem to need this */
664 mmc_go_idle(mmc);
665
31cacbab 666 /* Asking to the card its capabilities */
e9550449 667 for (i = 0; i < 2; i++) {
5289b535 668 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 669 if (err)
670 return err;
cd6881b5 671
e9550449 672 /* exit if not busy (flag seems to be inverted) */
a626c8d4 673 if (mmc->ocr & OCR_BUSY)
bd47c135 674 break;
e9550449 675 }
bd47c135
AG		 676 mmc->op_cond_pending = 1;
677 return 0;
e9550449 678}
cd6881b5 679
750121c3 680static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 681{
682 struct mmc_cmd cmd;
683 int timeout = 1000;
36332b6e 684 ulong start;
e9550449 685 int err;
cd6881b5 686
e9550449 687 mmc->op_cond_pending = 0;
cc17c01f 688 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 689 /* Some cards seem to need this */
690 mmc_go_idle(mmc);
691
cc17c01f 692 start = get_timer(0);
1677eef4 693 while (1) {
cc17c01f
AG		 694 err = mmc_send_op_cond_iter(mmc, 1);
695 if (err)
696 return err;
1677eef4
AG		 697 if (mmc->ocr & OCR_BUSY)
698 break;
cc17c01f 699 if (get_timer(start) > timeout)
915ffa52 700 return -EOPNOTSUPP;
cc17c01f 701 udelay(100);
1677eef4 702 }
cc17c01f 703 }
272cc70b 704
d52ebf10
TC		 705 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
706 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
707 cmd.resp_type = MMC_RSP_R3;
708 cmd.cmdarg = 0;
d52ebf10
TC		 709
710 err = mmc_send_cmd(mmc, &cmd, NULL);
711
712 if (err)
713 return err;
a626c8d4
AG		 714
715 mmc->ocr = cmd.response[0];
d52ebf10
TC		 716 }
717
272cc70b 718 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 719
720 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 721 mmc->rca = 1;
272cc70b
AF		 722
723 return 0;
724}
725
726
fdbb873e 727static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 728{
729 struct mmc_cmd cmd;
730 struct mmc_data data;
731 int err;
732
733 /* Get the Card Status Register */
734 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
735 cmd.resp_type = MMC_RSP_R1;
736 cmd.cmdarg = 0;
272cc70b 737
cdfd1ac6 738 data.dest = (char *)ext_csd;
272cc70b 739 data.blocks = 1;
8bfa195e 740 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 741 data.flags = MMC_DATA_READ;
742
743 err = mmc_send_cmd(mmc, &cmd, &data);
744
745 return err;
746}
747
6892550c
MV		 748static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
749 bool send_status)
272cc70b 750{
bb98b8c5 751 unsigned int status, start;
272cc70b 752 struct mmc_cmd cmd;
39320c53 753 int timeout = DEFAULT_CMD6_TIMEOUT_MS;
513e00b6
JJH		 754 bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
755 (index == EXT_CSD_PART_CONF);
a9003dc6 756 int retries = 3;
5d4fc8d9 757 int ret;
272cc70b 758
39320c53
JJH		 759 if (mmc->gen_cmd6_time)
760 timeout = mmc->gen_cmd6_time * 10;
761
513e00b6
JJH		 762 if (is_part_switch && mmc->part_switch_time)
763 timeout = mmc->part_switch_time * 10;
764
272cc70b
AF		 765 cmd.cmdidx = MMC_CMD_SWITCH;
766 cmd.resp_type = MMC_RSP_R1b;
767 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 768 (index << 16) |
769 (value << 8);
272cc70b 770
bb98b8c5 771 do {
a9003dc6 772 ret = mmc_send_cmd(mmc, &cmd, NULL);
bb98b8c5 773 } while (ret && retries-- > 0);
5d4fc8d9 774
bb98b8c5
JJH		 775 if (ret)
776 return ret;
6892550c 777
bb98b8c5 778 start = get_timer(0);
a9003dc6 779
bb98b8c5
JJH		 780 /* poll dat0 for rdy/buys status */
781 ret = mmc_wait_dat0(mmc, 1, timeout);
782 if (ret && ret != -ENOSYS)
783 return ret;
5d4fc8d9 784
bb98b8c5
JJH		 785 /*
786 * In cases when not allowed to poll by using CMD13 or because we aren't
787 * capable of polling by using mmc_wait_dat0, then rely on waiting the
788 * stated timeout to be sufficient.
789 */
790 if (ret == -ENOSYS && !send_status)
791 mdelay(timeout);
792
793 /* Finally wait until the card is ready or indicates a failure
794 * to switch. It doesn't hurt to use CMD13 here even if send_status
795 * is false, because by now (after 'timeout' ms) the bus should be
796 * reliable.
797 */
798 do {
799 ret = mmc_send_status(mmc, &status);
800
801 if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
802 pr_debug("switch failed %d/%d/0x%x !\n", set, index,
803 value);
804 return -EIO;
805 }
806 if (!ret && (status & MMC_STATUS_RDY_FOR_DATA))
807 return 0;
808 udelay(100);
809 } while (get_timer(start) < timeout);
5d4fc8d9 810
bb98b8c5 811 return -ETIMEDOUT;
272cc70b
AF		 812}
813
6892550c
MV		 814int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
815{
816 return __mmc_switch(mmc, set, index, value, true);
817}
818
62d77cea 819#if !CONFIG_IS_ENABLED(MMC_TINY)
b9a2a0e2
MV		 820static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
821 bool hsdowngrade)
272cc70b 822{
272cc70b 823 int err;
3862b854
JJH		 824 int speed_bits;
825
826 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
827
828 switch (mode) {
829 case MMC_HS:
830 case MMC_HS_52:
831 case MMC_DDR_52:
832 speed_bits = EXT_CSD_TIMING_HS;
634d4849 833 break;
baef2070 834#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
634d4849
KVA		 835 case MMC_HS_200:
836 speed_bits = EXT_CSD_TIMING_HS200;
837 break;
3dd2626f
PF		 838#endif
839#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
840 case MMC_HS_400:
841 speed_bits = EXT_CSD_TIMING_HS400;
842 break;
44acd492
PF		 843#endif
844#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
845 case MMC_HS_400_ES:
846 speed_bits = EXT_CSD_TIMING_HS400;
847 break;
baef2070 848#endif
3862b854
JJH		 849 case MMC_LEGACY:
850 speed_bits = EXT_CSD_TIMING_LEGACY;
851 break;
852 default:
853 return -EINVAL;
854 }
6892550c
MV		 855
856 err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
857 speed_bits, !hsdowngrade);
3862b854
JJH		 858 if (err)
859 return err;
860
b9a2a0e2
MV		 861#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
862 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
863 /*
864 * In case the eMMC is in HS200/HS400 mode and we are downgrading
865 * to HS mode, the card clock are still running much faster than
866 * the supported HS mode clock, so we can not reliably read out
867 * Extended CSD. Reconfigure the controller to run at HS mode.
868 */
869 if (hsdowngrade) {
870 mmc_select_mode(mmc, MMC_HS);
871 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
872 }
873#endif
874
3862b854
JJH		 875 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
876 /* Now check to see that it worked */
877 err = mmc_send_ext_csd(mmc, test_csd);
878 if (err)
879 return err;
880
881 /* No high-speed support */
882 if (!test_csd[EXT_CSD_HS_TIMING])
883 return -ENOTSUPP;
884 }
885
886 return 0;
887}
888
889static int mmc_get_capabilities(struct mmc *mmc)
890{
891 u8 *ext_csd = mmc->ext_csd;
892 char cardtype;
272cc70b 893
00e446fa 894 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
272cc70b 895
d52ebf10
TC		 896 if (mmc_host_is_spi(mmc))
897 return 0;
898
272cc70b
AF		 899 /* Only version 4 supports high-speed */
900 if (mmc->version < MMC_VERSION_4)
901 return 0;
902
3862b854 903 if (!ext_csd) {
d8e3d420 904 pr_err("No ext_csd found!\n"); /* this should enver happen */
3862b854
JJH		 905 return -ENOTSUPP;
906 }
272cc70b 907
3862b854 908 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 909
3dd2626f 910 cardtype = ext_csd[EXT_CSD_CARD_TYPE];
bc1e3272 911 mmc->cardtype = cardtype;
272cc70b 912
baef2070 913#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
634d4849
KVA		 914 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
915 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
916 mmc->card_caps |= MMC_MODE_HS200;
917 }
3dd2626f 918#endif
44acd492
PF		 919#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
920 CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
3dd2626f
PF		 921 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
922 EXT_CSD_CARD_TYPE_HS400_1_8V)) {
923 mmc->card_caps |= MMC_MODE_HS400;
924 }
baef2070 925#endif
d22e3d46 926 if (cardtype & EXT_CSD_CARD_TYPE_52) {
3862b854 927 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
d22e3d46 928 mmc->card_caps |= MMC_MODE_DDR_52MHz;
3862b854 929 mmc->card_caps |= MMC_MODE_HS_52MHz;
d22e3d46 930 }
3862b854
JJH		 931 if (cardtype & EXT_CSD_CARD_TYPE_26)
932 mmc->card_caps |= MMC_MODE_HS;
272cc70b 933
44acd492
PF		 934#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
935 if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
936 (mmc->card_caps & MMC_MODE_HS400)) {
937 mmc->card_caps |= MMC_MODE_HS400_ES;
938 }
939#endif
940
272cc70b
AF		 941 return 0;
942}
62d77cea 943#endif
272cc70b 944
f866a46d
SW		 945static int mmc_set_capacity(struct mmc *mmc, int part_num)
946{
947 switch (part_num) {
948 case 0:
949 mmc->capacity = mmc->capacity_user;
950 break;
951 case 1:
952 case 2:
953 mmc->capacity = mmc->capacity_boot;
954 break;
955 case 3:
956 mmc->capacity = mmc->capacity_rpmb;
957 break;
958 case 4:
959 case 5:
960 case 6:
961 case 7:
962 mmc->capacity = mmc->capacity_gp[part_num - 4];
963 break;
964 default:
965 return -1;
966 }
967
c40fdca6 968 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 969
970 return 0;
971}
972
7dba0b93 973int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 974{
f866a46d 975 int ret;
0538477c 976 int retry = 3;
bc897b1d 977
0538477c
JJH		 978 do {
979 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
980 EXT_CSD_PART_CONF,
981 (mmc->part_config & ~PART_ACCESS_MASK)
982 | (part_num & PART_ACCESS_MASK));
983 } while (ret && retry--);
f866a46d 984
6dc93e70
PB		 985 /*
986 * Set the capacity if the switch succeeded or was intended
987 * to return to representing the raw device.
988 */
873cc1d7 989 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 990 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 991 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 992 }
6dc93e70
PB		 993
994 return ret;
bc897b1d
LW		 995}
996
cf17789e 997#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
ac9da0e0
DSC		 998int mmc_hwpart_config(struct mmc *mmc,
999 const struct mmc_hwpart_conf *conf,
1000 enum mmc_hwpart_conf_mode mode)
1001{
1002 u8 part_attrs = 0;
1003 u32 enh_size_mult;
1004 u32 enh_start_addr;
1005 u32 gp_size_mult[4];
1006 u32 max_enh_size_mult;
1007 u32 tot_enh_size_mult = 0;
8dda5b0e 1008 u8 wr_rel_set;
ac9da0e0
DSC		 1009 int i, pidx, err;
1010 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1011
1012 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1013 return -EINVAL;
1014
1015 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
d8e3d420 1016 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
ac9da0e0
DSC		 1017 return -EMEDIUMTYPE;
1018 }
1019
1020 if (!(mmc->part_support & PART_SUPPORT)) {
d8e3d420 1021 pr_err("Card does not support partitioning\n");
ac9da0e0
DSC		 1022 return -EMEDIUMTYPE;
1023 }
1024
1025 if (!mmc->hc_wp_grp_size) {
d8e3d420 1026 pr_err("Card does not define HC WP group size\n");
ac9da0e0
DSC		 1027 return -EMEDIUMTYPE;
1028 }
1029
1030 /* check partition alignment and total enhanced size */
1031 if (conf->user.enh_size) {
1032 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1033 conf->user.enh_start % mmc->hc_wp_grp_size) {
d8e3d420 1034 pr_err("User data enhanced area not HC WP group "
ac9da0e0
DSC		 1035 "size aligned\n");
1036 return -EINVAL;
1037 }
1038 part_attrs |= EXT_CSD_ENH_USR;
1039 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1040 if (mmc->high_capacity) {
1041 enh_start_addr = conf->user.enh_start;
1042 } else {
1043 enh_start_addr = (conf->user.enh_start << 9);
1044 }
1045 } else {
1046 enh_size_mult = 0;
1047 enh_start_addr = 0;
1048 }
1049 tot_enh_size_mult += enh_size_mult;
1050
1051 for (pidx = 0; pidx < 4; pidx++) {
1052 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
d8e3d420 1053 pr_err("GP%i partition not HC WP group size "
ac9da0e0
DSC		 1054 "aligned\n", pidx+1);
1055 return -EINVAL;
1056 }
1057 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1058 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1059 part_attrs |= EXT_CSD_ENH_GP(pidx);
1060 tot_enh_size_mult += gp_size_mult[pidx];
1061 }
1062 }
1063
1064 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
d8e3d420 1065 pr_err("Card does not support enhanced attribute\n");
ac9da0e0
DSC		 1066 return -EMEDIUMTYPE;
1067 }
1068
1069 err = mmc_send_ext_csd(mmc, ext_csd);
1070 if (err)
1071 return err;
1072
1073 max_enh_size_mult =
1074 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1075 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1076 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1077 if (tot_enh_size_mult > max_enh_size_mult) {
d8e3d420 1078 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
ac9da0e0
DSC		 1079 tot_enh_size_mult, max_enh_size_mult);
1080 return -EMEDIUMTYPE;
1081 }
1082
8dda5b0e
DSC		 1083 /* The default value of EXT_CSD_WR_REL_SET is device
1084 * dependent, the values can only be changed if the
1085 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1086 * changed only once and before partitioning is completed. */
1087 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1088 if (conf->user.wr_rel_change) {
1089 if (conf->user.wr_rel_set)
1090 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1091 else
1092 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1093 }
1094 for (pidx = 0; pidx < 4; pidx++) {
1095 if (conf->gp_part[pidx].wr_rel_change) {
1096 if (conf->gp_part[pidx].wr_rel_set)
1097 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1098 else
1099 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1100 }
1101 }
1102
1103 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1104 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1105 puts("Card does not support host controlled partition write "
1106 "reliability settings\n");
1107 return -EMEDIUMTYPE;
1108 }
1109
ac9da0e0
DSC		 1110 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1111 EXT_CSD_PARTITION_SETTING_COMPLETED) {
d8e3d420 1112 pr_err("Card already partitioned\n");
ac9da0e0
DSC		 1113 return -EPERM;
1114 }
1115
1116 if (mode == MMC_HWPART_CONF_CHECK)
1117 return 0;
1118
1119 /* Partitioning requires high-capacity size definitions */
1120 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1121 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1122 EXT_CSD_ERASE_GROUP_DEF, 1);
1123
1124 if (err)
1125 return err;
1126
1127 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1128
1129 /* update erase group size to be high-capacity */
1130 mmc->erase_grp_size =
1131 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1132
1133 }
1134
1135 /* all OK, write the configuration */
1136 for (i = 0; i < 4; i++) {
1137 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1138 EXT_CSD_ENH_START_ADDR+i,
1139 (enh_start_addr >> (i*8)) & 0xFF);
1140 if (err)
1141 return err;
1142 }
1143 for (i = 0; i < 3; i++) {
1144 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1145 EXT_CSD_ENH_SIZE_MULT+i,
1146 (enh_size_mult >> (i*8)) & 0xFF);
1147 if (err)
1148 return err;
1149 }
1150 for (pidx = 0; pidx < 4; pidx++) {
1151 for (i = 0; i < 3; i++) {
1152 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1153 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1154 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1155 if (err)
1156 return err;
1157 }
1158 }
1159 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1160 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1161 if (err)
1162 return err;
1163
1164 if (mode == MMC_HWPART_CONF_SET)
1165 return 0;
1166
8dda5b0e
DSC		 1167 /* The WR_REL_SET is a write-once register but shall be
1168 * written before setting PART_SETTING_COMPLETED. As it is
1169 * write-once we can only write it when completing the
1170 * partitioning. */
1171 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1172 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1173 EXT_CSD_WR_REL_SET, wr_rel_set);
1174 if (err)
1175 return err;
1176 }
1177
ac9da0e0
DSC		 1178 /* Setting PART_SETTING_COMPLETED confirms the partition
1179 * configuration but it only becomes effective after power
1180 * cycle, so we do not adjust the partition related settings
1181 * in the mmc struct. */
1182
1183 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1184 EXT_CSD_PARTITION_SETTING,
1185 EXT_CSD_PARTITION_SETTING_COMPLETED);
1186 if (err)
1187 return err;
1188
1189 return 0;
1190}
cf17789e 1191#endif
ac9da0e0 1192
e7881d85 1193#if !CONFIG_IS_ENABLED(DM_MMC)
48972d90
TR		 1194int mmc_getcd(struct mmc *mmc)
1195{
1196 int cd;
1197
1198 cd = board_mmc_getcd(mmc);
1199
d4e1da4e 1200 if (cd < 0) {
93bfd616
PA		 1201 if (mmc->cfg->ops->getcd)
1202 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 1203 else
1204 cd = 1;
1205 }
48972d90
TR		 1206
1207 return cd;
1208}
8ca51e51 1209#endif
48972d90 1210
62d77cea 1211#if !CONFIG_IS_ENABLED(MMC_TINY)
fdbb873e 1212static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 1213{
1214 struct mmc_cmd cmd;
1215 struct mmc_data data;
1216
1217 /* Switch the frequency */
1218 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1219 cmd.resp_type = MMC_RSP_R1;
1220 cmd.cmdarg = (mode << 31) | 0xffffff;
1221 cmd.cmdarg &= ~(0xf << (group * 4));
1222 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 1223
1224 data.dest = (char *)resp;
1225 data.blocksize = 64;
1226 data.blocks = 1;
1227 data.flags = MMC_DATA_READ;
1228
1229 return mmc_send_cmd(mmc, &cmd, &data);
1230}
1231
d0c221fe 1232static int sd_get_capabilities(struct mmc *mmc)
272cc70b
AF		 1233{
1234 int err;
1235 struct mmc_cmd cmd;
18e7c8f6
SM		 1236 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1237 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
272cc70b
AF		 1238 struct mmc_data data;
1239 int timeout;
f99c2efe 1240#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6 1241 u32 sd3_bus_mode;
f99c2efe 1242#endif
272cc70b 1243
00e446fa 1244 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
272cc70b 1245
d52ebf10
TC		 1246 if (mmc_host_is_spi(mmc))
1247 return 0;
1248
272cc70b
AF		 1249 /* Read the SCR to find out if this card supports higher speeds */
1250 cmd.cmdidx = MMC_CMD_APP_CMD;
1251 cmd.resp_type = MMC_RSP_R1;
1252 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1253
1254 err = mmc_send_cmd(mmc, &cmd, NULL);
1255
1256 if (err)
1257 return err;
1258
1259 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1260 cmd.resp_type = MMC_RSP_R1;
1261 cmd.cmdarg = 0;
272cc70b
AF		 1262
1263 timeout = 3;
1264
1265retry_scr:
f781dd38 1266 data.dest = (char *)scr;
272cc70b
AF		 1267 data.blocksize = 8;
1268 data.blocks = 1;
1269 data.flags = MMC_DATA_READ;
1270
1271 err = mmc_send_cmd(mmc, &cmd, &data);
1272
1273 if (err) {
1274 if (timeout--)
1275 goto retry_scr;
1276
1277 return err;
1278 }
1279
4e3d89ba
YK		 1280 mmc->scr[0] = __be32_to_cpu(scr[0]);
1281 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 1282
1283 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 1284 case 0:
1285 mmc->version = SD_VERSION_1_0;
1286 break;
1287 case 1:
1288 mmc->version = SD_VERSION_1_10;
1289 break;
1290 case 2:
1291 mmc->version = SD_VERSION_2;
1292 if ((mmc->scr[0] >> 15) & 0x1)
1293 mmc->version = SD_VERSION_3;
1294 break;
1295 default:
1296 mmc->version = SD_VERSION_1_0;
1297 break;
272cc70b
AF		 1298 }
1299
b44c7083
AS		 1300 if (mmc->scr[0] & SD_DATA_4BIT)
1301 mmc->card_caps |= MMC_MODE_4BIT;
1302
272cc70b
AF		 1303 /* Version 1.0 doesn't support switching */
1304 if (mmc->version == SD_VERSION_1_0)
1305 return 0;
1306
1307 timeout = 4;
1308 while (timeout--) {
1309 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 1310 (u8 *)switch_status);
272cc70b
AF		 1311
1312 if (err)
1313 return err;
1314
1315 /* The high-speed function is busy. Try again */
4e3d89ba 1316 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 1317 break;
1318 }
1319
272cc70b 1320 /* If high-speed isn't supported, we return */
d0c221fe
JJH		 1321 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1322 mmc->card_caps |= MMC_CAP(SD_HS);
272cc70b 1323
f99c2efe 1324#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 1325 /* Version before 3.0 don't support UHS modes */
1326 if (mmc->version < SD_VERSION_3)
1327 return 0;
1328
1329 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1330 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1331 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1332 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1333 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1334 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1335 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1336 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1337 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1338 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1339 mmc->card_caps |= MMC_CAP(UHS_DDR50);
f99c2efe 1340#endif
c10b85d6 1341
d0c221fe
JJH		 1342 return 0;
1343}
1344
1345static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1346{
1347 int err;
1348
1349 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
c10b85d6 1350 int speed;
2c3fbf4c 1351
cf345760
MV		 1352 /* SD version 1.00 and 1.01 does not support CMD 6 */
1353 if (mmc->version == SD_VERSION_1_0)
1354 return 0;
1355
c10b85d6
JJH		 1356 switch (mode) {
1357 case SD_LEGACY:
c10b85d6
JJH		 1358 speed = UHS_SDR12_BUS_SPEED;
1359 break;
1360 case SD_HS:
baef2070
JJH		 1361 speed = HIGH_SPEED_BUS_SPEED;
1362 break;
1363#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1364 case UHS_SDR12:
1365 speed = UHS_SDR12_BUS_SPEED;
1366 break;
c10b85d6
JJH		 1367 case UHS_SDR25:
1368 speed = UHS_SDR25_BUS_SPEED;
1369 break;
1370 case UHS_SDR50:
1371 speed = UHS_SDR50_BUS_SPEED;
1372 break;
1373 case UHS_DDR50:
1374 speed = UHS_DDR50_BUS_SPEED;
1375 break;
1376 case UHS_SDR104:
1377 speed = UHS_SDR104_BUS_SPEED;
1378 break;
baef2070 1379#endif
c10b85d6
JJH		 1380 default:
1381 return -EINVAL;
1382 }
1383
1384 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
d0c221fe
JJH		 1385 if (err)
1386 return err;
1387
a0276f3e 1388 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
d0c221fe 1389 return -ENOTSUPP;
272cc70b 1390
d0c221fe
JJH		 1391 return 0;
1392}
1393
ec360e64 1394static int sd_select_bus_width(struct mmc *mmc, int w)
d0c221fe
JJH		 1395{
1396 int err;
1397 struct mmc_cmd cmd;
1398
1399 if ((w != 4) && (w != 1))
1400 return -EINVAL;
1401
1402 cmd.cmdidx = MMC_CMD_APP_CMD;
1403 cmd.resp_type = MMC_RSP_R1;
1404 cmd.cmdarg = mmc->rca << 16;
1405
1406 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b
AF		 1407 if (err)
1408 return err;
1409
d0c221fe
JJH		 1410 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1411 cmd.resp_type = MMC_RSP_R1;
1412 if (w == 4)
1413 cmd.cmdarg = 2;
1414 else if (w == 1)
1415 cmd.cmdarg = 0;
1416 err = mmc_send_cmd(mmc, &cmd, NULL);
1417 if (err)
1418 return err;
272cc70b
AF		 1419
1420 return 0;
1421}
62d77cea 1422#endif
272cc70b 1423
5b2e72f3 1424#if CONFIG_IS_ENABLED(MMC_WRITE)
3697e599
PF		 1425static int sd_read_ssr(struct mmc *mmc)
1426{
5b2e72f3
JJH		 1427 static const unsigned int sd_au_size[] = {
1428 0, SZ_16K / 512, SZ_32K / 512,
1429 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1430 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1431 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1432 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1433 SZ_64M / 512,
1434 };
3697e599
PF		 1435 int err, i;
1436 struct mmc_cmd cmd;
1437 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1438 struct mmc_data data;
1439 int timeout = 3;
1440 unsigned int au, eo, et, es;
1441
1442 cmd.cmdidx = MMC_CMD_APP_CMD;
1443 cmd.resp_type = MMC_RSP_R1;
1444 cmd.cmdarg = mmc->rca << 16;
1445
1446 err = mmc_send_cmd(mmc, &cmd, NULL);
1447 if (err)
1448 return err;
1449
1450 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1451 cmd.resp_type = MMC_RSP_R1;
1452 cmd.cmdarg = 0;
1453
1454retry_ssr:
1455 data.dest = (char *)ssr;
1456 data.blocksize = 64;
1457 data.blocks = 1;
1458 data.flags = MMC_DATA_READ;
1459
1460 err = mmc_send_cmd(mmc, &cmd, &data);
1461 if (err) {
1462 if (timeout--)
1463 goto retry_ssr;
1464
1465 return err;
1466 }
1467
1468 for (i = 0; i < 16; i++)
1469 ssr[i] = be32_to_cpu(ssr[i]);
1470
1471 au = (ssr[2] >> 12) & 0xF;
1472 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1473 mmc->ssr.au = sd_au_size[au];
1474 es = (ssr[3] >> 24) & 0xFF;
1475 es |= (ssr[2] & 0xFF) << 8;
1476 et = (ssr[3] >> 18) & 0x3F;
1477 if (es && et) {
1478 eo = (ssr[3] >> 16) & 0x3;
1479 mmc->ssr.erase_timeout = (et * 1000) / es;
1480 mmc->ssr.erase_offset = eo * 1000;
1481 }
1482 } else {
d4d64889 1483 pr_debug("Invalid Allocation Unit Size.\n");
3697e599
PF		 1484 }
1485
1486 return 0;
1487}
5b2e72f3 1488#endif
272cc70b
AF		 1489/* frequency bases */
1490/* divided by 10 to be nice to platforms without floating point */
5f837c2c 1491static const int fbase[] = {
272cc70b
AF		 1492 10000,
1493 100000,
1494 1000000,
1495 10000000,
1496};
1497
1498/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1499 * to platforms without floating point.
1500 */
61fe076f 1501static const u8 multipliers[] = {
272cc70b
AF		 1502 0, /* reserved */
1503 10,
1504 12,
1505 13,
1506 15,
1507 20,
1508 25,
1509 30,
1510 35,
1511 40,
1512 45,
1513 50,
1514 55,
1515 60,
1516 70,
1517 80,
1518};
1519
d0c221fe
JJH		 1520static inline int bus_width(uint cap)
1521{
1522 if (cap == MMC_MODE_8BIT)
1523 return 8;
1524 if (cap == MMC_MODE_4BIT)
1525 return 4;
1526 if (cap == MMC_MODE_1BIT)
1527 return 1;
d8e3d420 1528 pr_warn("invalid bus witdh capability 0x%x\n", cap);
d0c221fe
JJH		 1529 return 0;
1530}
1531
e7881d85 1532#if !CONFIG_IS_ENABLED(DM_MMC)
f99c2efe 1533#ifdef MMC_SUPPORTS_TUNING
ec841209
KVA		 1534static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1535{
1536 return -ENOTSUPP;
1537}
f99c2efe 1538#endif
ec841209 1539
2a4d212f 1540static int mmc_set_ios(struct mmc *mmc)
272cc70b 1541{
2a4d212f
KVA		 1542 int ret = 0;
1543
93bfd616 1544 if (mmc->cfg->ops->set_ios)
2a4d212f
KVA		 1545 ret = mmc->cfg->ops->set_ios(mmc);
1546
1547 return ret;
272cc70b 1548}
8ca51e51 1549#endif
272cc70b 1550
35f67820 1551int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
272cc70b 1552{
c0fafe64 1553 if (!disable) {
9546eb92
JC		 1554 if (clock > mmc->cfg->f_max)
1555 clock = mmc->cfg->f_max;
272cc70b 1556
9546eb92
JC		 1557 if (clock < mmc->cfg->f_min)
1558 clock = mmc->cfg->f_min;
1559 }
272cc70b
AF		 1560
1561 mmc->clock = clock;
35f67820 1562 mmc->clk_disable = disable;
272cc70b 1563
d2faadb5
JC		 1564 debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1565
2a4d212f 1566 return mmc_set_ios(mmc);
272cc70b
AF		 1567}
1568
2a4d212f 1569static int mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1570{
1571 mmc->bus_width = width;
1572
2a4d212f 1573 return mmc_set_ios(mmc);
272cc70b
AF		 1574}
1575
4c9d2aaa
JJH		 1576#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1577/*
1578 * helper function to display the capabilities in a human
1579 * friendly manner. The capabilities include bus width and
1580 * supported modes.
1581 */
1582void mmc_dump_capabilities(const char *text, uint caps)
1583{
1584 enum bus_mode mode;
1585
d4d64889 1586 pr_debug("%s: widths [", text);
4c9d2aaa 1587 if (caps & MMC_MODE_8BIT)
d4d64889 1588 pr_debug("8, ");
4c9d2aaa 1589 if (caps & MMC_MODE_4BIT)
d4d64889 1590 pr_debug("4, ");
d0c221fe 1591 if (caps & MMC_MODE_1BIT)
d4d64889
MY		 1592 pr_debug("1, ");
1593 pr_debug("\b\b] modes [");
4c9d2aaa
JJH		 1594 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1595 if (MMC_CAP(mode) & caps)
d4d64889
MY		 1596 pr_debug("%s, ", mmc_mode_name(mode));
1597 pr_debug("\b\b]\n");
4c9d2aaa
JJH		 1598}
1599#endif
1600
d0c221fe
JJH		 1601struct mode_width_tuning {
1602 enum bus_mode mode;
1603 uint widths;
f99c2efe 1604#ifdef MMC_SUPPORTS_TUNING
634d4849 1605 uint tuning;
f99c2efe 1606#endif
d0c221fe
JJH		 1607};
1608
f99c2efe 1609#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
bc1e3272
JJH		 1610int mmc_voltage_to_mv(enum mmc_voltage voltage)
1611{
1612 switch (voltage) {
1613 case MMC_SIGNAL_VOLTAGE_000: return 0;
1614 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1615 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1616 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1617 }
1618 return -EINVAL;
1619}
1620
aff5d3c8
KVA		 1621static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1622{
bc1e3272
JJH		 1623 int err;
1624
1625 if (mmc->signal_voltage == signal_voltage)
1626 return 0;
1627
aff5d3c8 1628 mmc->signal_voltage = signal_voltage;
bc1e3272
JJH		 1629 err = mmc_set_ios(mmc);
1630 if (err)
d4d64889 1631 pr_debug("unable to set voltage (err %d)\n", err);
bc1e3272
JJH		 1632
1633 return err;
aff5d3c8 1634}
f99c2efe
JJH		 1635#else
1636static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1637{
1638 return 0;
1639}
1640#endif
aff5d3c8 1641
62d77cea 1642#if !CONFIG_IS_ENABLED(MMC_TINY)
d0c221fe 1643static const struct mode_width_tuning sd_modes_by_pref[] = {
f99c2efe
JJH		 1644#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1645#ifdef MMC_SUPPORTS_TUNING
c10b85d6
JJH		 1646 {
1647 .mode = UHS_SDR104,
1648 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1649 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1650 },
f99c2efe 1651#endif
c10b85d6
JJH		 1652 {
1653 .mode = UHS_SDR50,
1654 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1655 },
1656 {
1657 .mode = UHS_DDR50,
1658 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1659 },
1660 {
1661 .mode = UHS_SDR25,
1662 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1663 },
f99c2efe 1664#endif
d0c221fe
JJH		 1665 {
1666 .mode = SD_HS,
1667 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1668 },
f99c2efe 1669#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 1670 {
1671 .mode = UHS_SDR12,
1672 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1673 },
f99c2efe 1674#endif
d0c221fe
JJH		 1675 {
1676 .mode = SD_LEGACY,
1677 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1678 }
1679};
1680
1681#define for_each_sd_mode_by_pref(caps, mwt) \
1682 for (mwt = sd_modes_by_pref;\
1683 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1684 mwt++) \
1685 if (caps & MMC_CAP(mwt->mode))
1686
01298da3 1687static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
8ac8a263
JJH		 1688{
1689 int err;
d0c221fe
JJH		 1690 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1691 const struct mode_width_tuning *mwt;
f99c2efe 1692#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6 1693 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
f99c2efe
JJH		 1694#else
1695 bool uhs_en = false;
1696#endif
c10b85d6
JJH		 1697 uint caps;
1698
52d241df
JJH		 1699#ifdef DEBUG
1700 mmc_dump_capabilities("sd card", card_caps);
1da8eb59 1701 mmc_dump_capabilities("host", mmc->host_caps);
52d241df 1702#endif
8ac8a263 1703
f49ff799
AP		 1704 if (mmc_host_is_spi(mmc)) {
1705 mmc_set_bus_width(mmc, 1);
1706 mmc_select_mode(mmc, SD_LEGACY);
1707 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
1708 return 0;
1709 }
1710
8ac8a263 1711 /* Restrict card's capabilities by what the host can do */
1da8eb59 1712 caps = card_caps & mmc->host_caps;
d0c221fe 1713
c10b85d6
JJH		 1714 if (!uhs_en)
1715 caps &= ~UHS_CAPS;
1716
1717 for_each_sd_mode_by_pref(caps, mwt) {
d0c221fe
JJH		 1718 uint *w;
1719
1720 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
c10b85d6 1721 if (*w & caps & mwt->widths) {
d4d64889
MY		 1722 pr_debug("trying mode %s width %d (at %d MHz)\n",
1723 mmc_mode_name(mwt->mode),
1724 bus_width(*w),
1725 mmc_mode2freq(mmc, mwt->mode) / 1000000);
d0c221fe
JJH		 1726
1727 /* configure the bus width (card + host) */
1728 err = sd_select_bus_width(mmc, bus_width(*w));
1729 if (err)
1730 goto error;
1731 mmc_set_bus_width(mmc, bus_width(*w));
1732
1733 /* configure the bus mode (card) */
1734 err = sd_set_card_speed(mmc, mwt->mode);
1735 if (err)
1736 goto error;
1737
1738 /* configure the bus mode (host) */
1739 mmc_select_mode(mmc, mwt->mode);
65117182
JC		 1740 mmc_set_clock(mmc, mmc->tran_speed,
1741 MMC_CLK_ENABLE);
d0c221fe 1742
f99c2efe 1743#ifdef MMC_SUPPORTS_TUNING
c10b85d6
JJH		 1744 /* execute tuning if needed */
1745 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1746 err = mmc_execute_tuning(mmc,
1747 mwt->tuning);
1748 if (err) {
d4d64889 1749 pr_debug("tuning failed\n");
c10b85d6
JJH		 1750 goto error;
1751 }
1752 }
f99c2efe 1753#endif
c10b85d6 1754
5b2e72f3 1755#if CONFIG_IS_ENABLED(MMC_WRITE)
d0c221fe 1756 err = sd_read_ssr(mmc);
0a4c2b09 1757 if (err)
5b2e72f3
JJH		 1758 pr_warn("unable to read ssr\n");
1759#endif
d0c221fe
JJH		 1760 if (!err)
1761 return 0;
1762
d0c221fe
JJH		 1763error:
1764 /* revert to a safer bus speed */
1765 mmc_select_mode(mmc, SD_LEGACY);
65117182
JC		 1766 mmc_set_clock(mmc, mmc->tran_speed,
1767 MMC_CLK_ENABLE);
d0c221fe
JJH		 1768 }
1769 }
8ac8a263
JJH		 1770 }
1771
d4d64889 1772 pr_err("unable to select a mode\n");
d0c221fe 1773 return -ENOTSUPP;
8ac8a263
JJH		 1774}
1775
7382e691
JJH		 1776/*
1777 * read the compare the part of ext csd that is constant.
1778 * This can be used to check that the transfer is working
1779 * as expected.
1780 */
1781static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
8ac8a263 1782{
7382e691 1783 int err;
dfda9d88 1784 const u8 *ext_csd = mmc->ext_csd;
7382e691
JJH		 1785 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1786
1de06b9f
JJH		 1787 if (mmc->version < MMC_VERSION_4)
1788 return 0;
1789
7382e691
JJH		 1790 err = mmc_send_ext_csd(mmc, test_csd);
1791 if (err)
1792 return err;
1793
1794 /* Only compare read only fields */
1795 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1796 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1797 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1798 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1799 ext_csd[EXT_CSD_REV]
1800 == test_csd[EXT_CSD_REV] &&
1801 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1802 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1803 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1804 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1805 return 0;
1806
1807 return -EBADMSG;
1808}
1809
f99c2efe 1810#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
bc1e3272
JJH		 1811static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1812 uint32_t allowed_mask)
1813{
1814 u32 card_mask = 0;
1815
1816 switch (mode) {
44acd492 1817 case MMC_HS_400_ES:
3dd2626f 1818 case MMC_HS_400:
bc1e3272 1819 case MMC_HS_200:
3dd2626f
PF		 1820 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1821 EXT_CSD_CARD_TYPE_HS400_1_8V))
bc1e3272 1822 card_mask |= MMC_SIGNAL_VOLTAGE_180;
3dd2626f
PF		 1823 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1824 EXT_CSD_CARD_TYPE_HS400_1_2V))
bc1e3272
JJH		 1825 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1826 break;
1827 case MMC_DDR_52:
1828 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1829 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1830 MMC_SIGNAL_VOLTAGE_180;
1831 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1832 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1833 break;
1834 default:
1835 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1836 break;
1837 }
1838
1839 while (card_mask & allowed_mask) {
1840 enum mmc_voltage best_match;
1841
1842 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1843 if (!mmc_set_signal_voltage(mmc, best_match))
1844 return 0;
1845
1846 allowed_mask &= ~best_match;
1847 }
1848
1849 return -ENOTSUPP;
1850}
f99c2efe
JJH		 1851#else
1852static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1853 uint32_t allowed_mask)
1854{
1855 return 0;
1856}
1857#endif
bc1e3272 1858
3862b854 1859static const struct mode_width_tuning mmc_modes_by_pref[] = {
44acd492
PF		 1860#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1861 {
1862 .mode = MMC_HS_400_ES,
1863 .widths = MMC_MODE_8BIT,
1864 },
1865#endif
3dd2626f
PF		 1866#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1867 {
1868 .mode = MMC_HS_400,
1869 .widths = MMC_MODE_8BIT,
1870 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1871 },
1872#endif
f99c2efe 1873#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
3862b854
JJH		 1874 {
1875 .mode = MMC_HS_200,
1876 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
634d4849 1877 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
3862b854 1878 },
f99c2efe 1879#endif
3862b854
JJH		 1880 {
1881 .mode = MMC_DDR_52,
1882 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1883 },
1884 {
1885 .mode = MMC_HS_52,
1886 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1887 },
1888 {
1889 .mode = MMC_HS,
1890 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1891 },
1892 {
1893 .mode = MMC_LEGACY,
1894 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1895 }
1896};
1897
1898#define for_each_mmc_mode_by_pref(caps, mwt) \
1899 for (mwt = mmc_modes_by_pref;\
1900 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1901 mwt++) \
1902 if (caps & MMC_CAP(mwt->mode))
1903
1904static const struct ext_csd_bus_width {
1905 uint cap;
1906 bool is_ddr;
1907 uint ext_csd_bits;
1908} ext_csd_bus_width[] = {
1909 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1910 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1911 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1912 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1913 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1914};
1915
3dd2626f
PF		 1916#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1917static int mmc_select_hs400(struct mmc *mmc)
1918{
1919 int err;
1920
1921 /* Set timing to HS200 for tuning */
b9a2a0e2 1922 err = mmc_set_card_speed(mmc, MMC_HS_200, false);
3dd2626f
PF		 1923 if (err)
1924 return err;
1925
1926 /* configure the bus mode (host) */
1927 mmc_select_mode(mmc, MMC_HS_200);
1928 mmc_set_clock(mmc, mmc->tran_speed, false);
1929
1930 /* execute tuning if needed */
1931 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1932 if (err) {
1933 debug("tuning failed\n");
1934 return err;
1935 }
1936
1937 /* Set back to HS */
5cf12031 1938 mmc_set_card_speed(mmc, MMC_HS, true);
3dd2626f
PF		 1939
1940 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1941 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1942 if (err)
1943 return err;
1944
b9a2a0e2 1945 err = mmc_set_card_speed(mmc, MMC_HS_400, false);
3dd2626f
PF		 1946 if (err)
1947 return err;
1948
1949 mmc_select_mode(mmc, MMC_HS_400);
1950 err = mmc_set_clock(mmc, mmc->tran_speed, false);
1951 if (err)
1952 return err;
1953
1954 return 0;
1955}
1956#else
1957static int mmc_select_hs400(struct mmc *mmc)
1958{
1959 return -ENOTSUPP;
1960}
1961#endif
1962
44acd492
PF		 1963#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1964#if !CONFIG_IS_ENABLED(DM_MMC)
1965static int mmc_set_enhanced_strobe(struct mmc *mmc)
1966{
1967 return -ENOTSUPP;
1968}
1969#endif
1970static int mmc_select_hs400es(struct mmc *mmc)
1971{
1972 int err;
1973
1974 err = mmc_set_card_speed(mmc, MMC_HS, true);
1975 if (err)
1976 return err;
1977
1978 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1979 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
1980 EXT_CSD_BUS_WIDTH_STROBE);
1981 if (err) {
1982 printf("switch to bus width for hs400 failed\n");
1983 return err;
1984 }
1985 /* TODO: driver strength */
1986 err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
1987 if (err)
1988 return err;
1989
1990 mmc_select_mode(mmc, MMC_HS_400_ES);
1991 err = mmc_set_clock(mmc, mmc->tran_speed, false);
1992 if (err)
1993 return err;
1994
1995 return mmc_set_enhanced_strobe(mmc);
1996}
1997#else
1998static int mmc_select_hs400es(struct mmc *mmc)
1999{
2000 return -ENOTSUPP;
2001}
2002#endif
2003
3862b854
JJH		 2004#define for_each_supported_width(caps, ddr, ecbv) \
2005 for (ecbv = ext_csd_bus_width;\
2006 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
2007 ecbv++) \
2008 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
2009
01298da3 2010static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
7382e691 2011{
8ac8a263 2012 int err;
3862b854
JJH		 2013 const struct mode_width_tuning *mwt;
2014 const struct ext_csd_bus_width *ecbw;
8ac8a263 2015
52d241df
JJH		 2016#ifdef DEBUG
2017 mmc_dump_capabilities("mmc", card_caps);
1da8eb59 2018 mmc_dump_capabilities("host", mmc->host_caps);
52d241df
JJH		 2019#endif
2020
f49ff799
AP		 2021 if (mmc_host_is_spi(mmc)) {
2022 mmc_set_bus_width(mmc, 1);
2023 mmc_select_mode(mmc, MMC_LEGACY);
2024 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
2025 return 0;
2026 }
2027
8ac8a263 2028 /* Restrict card's capabilities by what the host can do */
1da8eb59 2029 card_caps &= mmc->host_caps;
8ac8a263
JJH		 2030
2031 /* Only version 4 of MMC supports wider bus widths */
2032 if (mmc->version < MMC_VERSION_4)
2033 return 0;
2034
dfda9d88 2035 if (!mmc->ext_csd) {
d4d64889 2036 pr_debug("No ext_csd found!\n"); /* this should enver happen */
dfda9d88
JJH		 2037 return -ENOTSUPP;
2038 }
2039
b9a2a0e2
MV		 2040#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2041 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2042 /*
2043 * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2044 * before doing anything else, since a transition from either of
2045 * the HS200/HS400 mode directly to legacy mode is not supported.
2046 */
2047 if (mmc->selected_mode == MMC_HS_200 ||
2048 mmc->selected_mode == MMC_HS_400)
2049 mmc_set_card_speed(mmc, MMC_HS, true);
2050 else
2051#endif
2052 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
01298da3
JJH		 2053
2054 for_each_mmc_mode_by_pref(card_caps, mwt) {
2055 for_each_supported_width(card_caps & mwt->widths,
3862b854 2056 mmc_is_mode_ddr(mwt->mode), ecbw) {
bc1e3272 2057 enum mmc_voltage old_voltage;
d4d64889
MY		 2058 pr_debug("trying mode %s width %d (at %d MHz)\n",
2059 mmc_mode_name(mwt->mode),
2060 bus_width(ecbw->cap),
2061 mmc_mode2freq(mmc, mwt->mode) / 1000000);
bc1e3272
JJH		 2062 old_voltage = mmc->signal_voltage;
2063 err = mmc_set_lowest_voltage(mmc, mwt->mode,
2064 MMC_ALL_SIGNAL_VOLTAGE);
2065 if (err)
2066 continue;
2067
3862b854
JJH		 2068 /* configure the bus width (card + host) */
2069 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2070 EXT_CSD_BUS_WIDTH,
2071 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2072 if (err)
2073 goto error;
2074 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
8ac8a263 2075
3dd2626f
PF		 2076 if (mwt->mode == MMC_HS_400) {
2077 err = mmc_select_hs400(mmc);
2078 if (err) {
2079 printf("Select HS400 failed %d\n", err);
2080 goto error;
2081 }
44acd492
PF		 2082 } else if (mwt->mode == MMC_HS_400_ES) {
2083 err = mmc_select_hs400es(mmc);
2084 if (err) {
2085 printf("Select HS400ES failed %d\n",
2086 err);
2087 goto error;
2088 }
3dd2626f
PF		 2089 } else {
2090 /* configure the bus speed (card) */
b9a2a0e2 2091 err = mmc_set_card_speed(mmc, mwt->mode, false);
3862b854
JJH		 2092 if (err)
2093 goto error;
8ac8a263 2094
3dd2626f
PF		 2095 /*
2096 * configure the bus width AND the ddr mode
2097 * (card). The host side will be taken care
2098 * of in the next step
2099 */
2100 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2101 err = mmc_switch(mmc,
2102 EXT_CSD_CMD_SET_NORMAL,
2103 EXT_CSD_BUS_WIDTH,
2104 ecbw->ext_csd_bits);
2105 if (err)
2106 goto error;
2107 }
2108
2109 /* configure the bus mode (host) */
2110 mmc_select_mode(mmc, mwt->mode);
2111 mmc_set_clock(mmc, mmc->tran_speed,
2112 MMC_CLK_ENABLE);
f99c2efe 2113#ifdef MMC_SUPPORTS_TUNING
8ac8a263 2114
3dd2626f
PF		 2115 /* execute tuning if needed */
2116 if (mwt->tuning) {
2117 err = mmc_execute_tuning(mmc,
2118 mwt->tuning);
2119 if (err) {
2120 pr_debug("tuning failed\n");
2121 goto error;
2122 }
634d4849 2123 }
f99c2efe 2124#endif
3dd2626f 2125 }
634d4849 2126
3862b854
JJH		 2127 /* do a transfer to check the configuration */
2128 err = mmc_read_and_compare_ext_csd(mmc);
2129 if (!err)
2130 return 0;
2131error:
bc1e3272 2132 mmc_set_signal_voltage(mmc, old_voltage);
3862b854
JJH		 2133 /* if an error occured, revert to a safer bus mode */
2134 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2135 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2136 mmc_select_mode(mmc, MMC_LEGACY);
2137 mmc_set_bus_width(mmc, 1);
2138 }
8ac8a263
JJH		 2139 }
2140
d8e3d420 2141 pr_err("unable to select a mode\n");
8ac8a263 2142
3862b854 2143 return -ENOTSUPP;
8ac8a263 2144}
62d77cea
MV		 2145#endif
2146
2147#if CONFIG_IS_ENABLED(MMC_TINY)
2148DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2149#endif
8ac8a263 2150
dfda9d88 2151static int mmc_startup_v4(struct mmc *mmc)
c744b6f6
JJH		 2152{
2153 int err, i;
2154 u64 capacity;
2155 bool has_parts = false;
2156 bool part_completed;
58a6fb7b
JJH		 2157 static const u32 mmc_versions[] = {
2158 MMC_VERSION_4,
2159 MMC_VERSION_4_1,
2160 MMC_VERSION_4_2,
2161 MMC_VERSION_4_3,
ace1bed3 2162 MMC_VERSION_4_4,
58a6fb7b
JJH		 2163 MMC_VERSION_4_41,
2164 MMC_VERSION_4_5,
2165 MMC_VERSION_5_0,
2166 MMC_VERSION_5_1
2167 };
2168
62d77cea
MV		 2169#if CONFIG_IS_ENABLED(MMC_TINY)
2170 u8 *ext_csd = ext_csd_bkup;
2171
2172 if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2173 return 0;
2174
2175 if (!mmc->ext_csd)
2176 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2177
2178 err = mmc_send_ext_csd(mmc, ext_csd);
2179 if (err)
2180 goto error;
2181
2182 /* store the ext csd for future reference */
2183 if (!mmc->ext_csd)
2184 mmc->ext_csd = ext_csd;
2185#else
f7d5dffc 2186 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
c744b6f6
JJH		 2187
2188 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2189 return 0;
2190
2191 /* check ext_csd version and capacity */
2192 err = mmc_send_ext_csd(mmc, ext_csd);
2193 if (err)
f7d5dffc
JJH		 2194 goto error;
2195
2196 /* store the ext csd for future reference */
2197 if (!mmc->ext_csd)
2198 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2199 if (!mmc->ext_csd)
2200 return -ENOMEM;
2201 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
62d77cea 2202#endif
76584e33 2203 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
58a6fb7b
JJH		 2204 return -EINVAL;
2205
2206 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2207
2208 if (mmc->version >= MMC_VERSION_4_2) {
c744b6f6
JJH		 2209 /*
2210 * According to the JEDEC Standard, the value of
2211 * ext_csd's capacity is valid if the value is more
2212 * than 2GB
2213 */
2214 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2215 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2216 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2217 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2218 capacity *= MMC_MAX_BLOCK_LEN;
2219 if ((capacity >> 20) > 2 * 1024)
2220 mmc->capacity_user = capacity;
2221 }
2222
39320c53
JJH		 2223 if (mmc->version >= MMC_VERSION_4_5)
2224 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2225
c744b6f6
JJH		 2226 /* The partition data may be non-zero but it is only
2227 * effective if PARTITION_SETTING_COMPLETED is set in
2228 * EXT_CSD, so ignore any data if this bit is not set,
2229 * except for enabling the high-capacity group size
2230 * definition (see below).
2231 */
2232 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2233 EXT_CSD_PARTITION_SETTING_COMPLETED);
2234
513e00b6
JJH		 2235 mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
2236 /* Some eMMC set the value too low so set a minimum */
2237 if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
2238 mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
2239
c744b6f6
JJH		 2240 /* store the partition info of emmc */
2241 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2242 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2243 ext_csd[EXT_CSD_BOOT_MULT])
2244 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2245 if (part_completed &&
2246 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2247 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2248
2249 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2250
2251 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2252
2253 for (i = 0; i < 4; i++) {
2254 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2255 uint mult = (ext_csd[idx + 2] << 16) +
2256 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2257 if (mult)
2258 has_parts = true;
2259 if (!part_completed)
2260 continue;
2261 mmc->capacity_gp[i] = mult;
2262 mmc->capacity_gp[i] *=
2263 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2264 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2265 mmc->capacity_gp[i] <<= 19;
2266 }
2267
173c06df 2268#ifndef CONFIG_SPL_BUILD
c744b6f6
JJH		 2269 if (part_completed) {
2270 mmc->enh_user_size =
2271 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2272 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2273 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2274 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2275 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2276 mmc->enh_user_size <<= 19;
2277 mmc->enh_user_start =
2278 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2279 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2280 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2281 ext_csd[EXT_CSD_ENH_START_ADDR];
2282 if (mmc->high_capacity)
2283 mmc->enh_user_start <<= 9;
2284 }
173c06df 2285#endif
c744b6f6
JJH		 2286
2287 /*
2288 * Host needs to enable ERASE_GRP_DEF bit if device is
2289 * partitioned. This bit will be lost every time after a reset
2290 * or power off. This will affect erase size.
2291 */
2292 if (part_completed)
2293 has_parts = true;
2294 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2295 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2296 has_parts = true;
2297 if (has_parts) {
2298 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2299 EXT_CSD_ERASE_GROUP_DEF, 1);
2300
2301 if (err)
f7d5dffc 2302 goto error;
c744b6f6
JJH		 2303
2304 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2305 }
2306
2307 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
e6fa5a54 2308#if CONFIG_IS_ENABLED(MMC_WRITE)
c744b6f6
JJH		 2309 /* Read out group size from ext_csd */
2310 mmc->erase_grp_size =
2311 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
e6fa5a54 2312#endif
c744b6f6
JJH		 2313 /*
2314 * if high capacity and partition setting completed
2315 * SEC_COUNT is valid even if it is smaller than 2 GiB
2316 * JEDEC Standard JESD84-B45, 6.2.4
2317 */
2318 if (mmc->high_capacity && part_completed) {
2319 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2320 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2321 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2322 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2323 capacity *= MMC_MAX_BLOCK_LEN;
2324 mmc->capacity_user = capacity;
2325 }
e6fa5a54
JJH		 2326 }
2327#if CONFIG_IS_ENABLED(MMC_WRITE)
2328 else {
c744b6f6
JJH		 2329 /* Calculate the group size from the csd value. */
2330 int erase_gsz, erase_gmul;
2331
2332 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2333 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2334 mmc->erase_grp_size = (erase_gsz + 1)
2335 * (erase_gmul + 1);
2336 }
e6fa5a54 2337#endif
b7a6e2c9 2338#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
c744b6f6
JJH		 2339 mmc->hc_wp_grp_size = 1024
2340 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2341 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
b7a6e2c9 2342#endif
c744b6f6
JJH		 2343
2344 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2345
2346 return 0;
f7d5dffc
JJH		 2347error:
2348 if (mmc->ext_csd) {
62d77cea 2349#if !CONFIG_IS_ENABLED(MMC_TINY)
f7d5dffc 2350 free(mmc->ext_csd);
62d77cea 2351#endif
f7d5dffc
JJH		 2352 mmc->ext_csd = NULL;
2353 }
2354 return err;
c744b6f6
JJH		 2355}
2356
fdbb873e 2357static int mmc_startup(struct mmc *mmc)
272cc70b 2358{
f866a46d 2359 int err, i;
272cc70b 2360 uint mult, freq;
c744b6f6 2361 u64 cmult, csize;
272cc70b 2362 struct mmc_cmd cmd;
c40fdca6 2363 struct blk_desc *bdesc;
272cc70b 2364
d52ebf10
TC		 2365#ifdef CONFIG_MMC_SPI_CRC_ON
2366 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2367 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2368 cmd.resp_type = MMC_RSP_R1;
2369 cmd.cmdarg = 1;
d52ebf10 2370 err = mmc_send_cmd(mmc, &cmd, NULL);
d52ebf10
TC		 2371 if (err)
2372 return err;
2373 }
2374#endif
2375
272cc70b 2376 /* Put the Card in Identify Mode */
d52ebf10
TC		 2377 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2378 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 2379 cmd.resp_type = MMC_RSP_R2;
2380 cmd.cmdarg = 0;
272cc70b
AF		 2381
2382 err = mmc_send_cmd(mmc, &cmd, NULL);
2383
83dc4227
KVA		 2384#ifdef CONFIG_MMC_QUIRKS
2385 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2386 int retries = 4;
2387 /*
2388 * It has been seen that SEND_CID may fail on the first
2389 * attempt, let's try a few more time
2390 */
2391 do {
2392 err = mmc_send_cmd(mmc, &cmd, NULL);
2393 if (!err)
2394 break;
2395 } while (retries--);
2396 }
2397#endif
2398
272cc70b
AF		 2399 if (err)
2400 return err;
2401
2402 memcpy(mmc->cid, cmd.response, 16);
2403
2404 /*
2405 * For MMC cards, set the Relative Address.
2406 * For SD cards, get the Relatvie Address.
2407 * This also puts the cards into Standby State
2408 */
d52ebf10
TC		 2409 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2410 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2411 cmd.cmdarg = mmc->rca << 16;
2412 cmd.resp_type = MMC_RSP_R6;
272cc70b 2413
d52ebf10 2414 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2415
d52ebf10
TC		 2416 if (err)
2417 return err;
272cc70b 2418
d52ebf10
TC		 2419 if (IS_SD(mmc))
2420 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2421 }
272cc70b
AF		 2422
2423 /* Get the Card-Specific Data */
2424 cmd.cmdidx = MMC_CMD_SEND_CSD;
2425 cmd.resp_type = MMC_RSP_R2;
2426 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 2427
2428 err = mmc_send_cmd(mmc, &cmd, NULL);
2429
2430 if (err)
2431 return err;
2432
998be3dd
RV		 2433 mmc->csd[0] = cmd.response[0];
2434 mmc->csd[1] = cmd.response[1];
2435 mmc->csd[2] = cmd.response[2];
2436 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 2437
2438 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 2439 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 2440
2441 switch (version) {
53e8e40b
BM		 2442 case 0:
2443 mmc->version = MMC_VERSION_1_2;
2444 break;
2445 case 1:
2446 mmc->version = MMC_VERSION_1_4;
2447 break;
2448 case 2:
2449 mmc->version = MMC_VERSION_2_2;
2450 break;
2451 case 3:
2452 mmc->version = MMC_VERSION_3;
2453 break;
2454 case 4:
2455 mmc->version = MMC_VERSION_4;
2456 break;
2457 default:
2458 mmc->version = MMC_VERSION_1_2;
2459 break;
272cc70b
AF		 2460 }
2461 }
2462
2463 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 2464 freq = fbase[(cmd.response[0] & 0x7)];
2465 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b 2466
35f9e196 2467 mmc->legacy_speed = freq * mult;
35f9e196 2468 mmc_select_mode(mmc, MMC_LEGACY);
272cc70b 2469
ab71188c 2470 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 2471 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
e6fa5a54 2472#if CONFIG_IS_ENABLED(MMC_WRITE)
272cc70b
AF		 2473
2474 if (IS_SD(mmc))
2475 mmc->write_bl_len = mmc->read_bl_len;
2476 else
998be3dd 2477 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
e6fa5a54 2478#endif
272cc70b
AF		 2479
2480 if (mmc->high_capacity) {
2481 csize = (mmc->csd[1] & 0x3f) << 16
2482 | (mmc->csd[2] & 0xffff0000) >> 16;
2483 cmult = 8;
2484 } else {
2485 csize = (mmc->csd[1] & 0x3ff) << 2
2486 | (mmc->csd[2] & 0xc0000000) >> 30;
2487 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2488 }
2489
f866a46d
SW		 2490 mmc->capacity_user = (csize + 1) << (cmult + 2);
2491 mmc->capacity_user *= mmc->read_bl_len;
2492 mmc->capacity_boot = 0;
2493 mmc->capacity_rpmb = 0;
2494 for (i = 0; i < 4; i++)
2495 mmc->capacity_gp[i] = 0;
272cc70b 2496
8bfa195e
SG		 2497 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2498 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2499
e6fa5a54 2500#if CONFIG_IS_ENABLED(MMC_WRITE)
8bfa195e
SG		 2501 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2502 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2503#endif
272cc70b 2504
ab71188c
MN		 2505 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2506 cmd.cmdidx = MMC_CMD_SET_DSR;
2507 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2508 cmd.resp_type = MMC_RSP_NONE;
2509 if (mmc_send_cmd(mmc, &cmd, NULL))
d8e3d420 2510 pr_warn("MMC: SET_DSR failed\n");
ab71188c
MN		 2511 }
2512
272cc70b 2513 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 2514 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2515 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 2516 cmd.resp_type = MMC_RSP_R1;
d52ebf10 2517 cmd.cmdarg = mmc->rca << 16;
d52ebf10 2518 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2519
d52ebf10
TC		 2520 if (err)
2521 return err;
2522 }
272cc70b 2523
e6f99a56
LW		 2524 /*
2525 * For SD, its erase group is always one sector
2526 */
e6fa5a54 2527#if CONFIG_IS_ENABLED(MMC_WRITE)
e6f99a56 2528 mmc->erase_grp_size = 1;
e6fa5a54 2529#endif
bc897b1d 2530 mmc->part_config = MMCPART_NOAVAILABLE;
1937e5aa 2531
dfda9d88 2532 err = mmc_startup_v4(mmc);
c744b6f6
JJH		 2533 if (err)
2534 return err;
d23e2c09 2535
c40fdca6 2536 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 2537 if (err)
2538 return err;
2539
62d77cea
MV		 2540#if CONFIG_IS_ENABLED(MMC_TINY)
2541 mmc_set_clock(mmc, mmc->legacy_speed, false);
2542 mmc_select_mode(mmc, IS_SD(mmc) ? SD_LEGACY : MMC_LEGACY);
2543 mmc_set_bus_width(mmc, 1);
2544#else
01298da3
JJH		 2545 if (IS_SD(mmc)) {
2546 err = sd_get_capabilities(mmc);
2547 if (err)
2548 return err;
2549 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2550 } else {
2551 err = mmc_get_capabilities(mmc);
2552 if (err)
2553 return err;
2554 mmc_select_mode_and_width(mmc, mmc->card_caps);
2555 }
62d77cea 2556#endif
272cc70b
AF		 2557 if (err)
2558 return err;
2559
01298da3 2560 mmc->best_mode = mmc->selected_mode;
ad5fd922 2561
5af8f45c
AG		 2562 /* Fix the block length for DDR mode */
2563 if (mmc->ddr_mode) {
2564 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2565#if CONFIG_IS_ENABLED(MMC_WRITE)
5af8f45c 2566 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2567#endif
5af8f45c
AG		 2568 }
2569
272cc70b 2570 /* fill in device description */
c40fdca6
SG		 2571 bdesc = mmc_get_blk_desc(mmc);
2572 bdesc->lun = 0;
2573 bdesc->hwpart = 0;
2574 bdesc->type = 0;
2575 bdesc->blksz = mmc->read_bl_len;
2576 bdesc->log2blksz = LOG2(bdesc->blksz);
2577 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 2578#if !defined(CONFIG_SPL_BUILD) || \
2579 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2580 !defined(CONFIG_USE_TINY_PRINTF))
c40fdca6 2581 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 2582 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2583 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 2584 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 2585 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2586 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2587 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 2588 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 2589 (mmc->cid[2] >> 16) & 0xf);
56196826 2590#else
c40fdca6
SG		 2591 bdesc->vendor[0] = 0;
2592 bdesc->product[0] = 0;
2593 bdesc->revision[0] = 0;
56196826 2594#endif
272cc70b 2595
eef05fd3
AP		 2596#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2597 part_init(bdesc);
2598#endif
2599
272cc70b
AF		 2600 return 0;
2601}
2602
fdbb873e 2603static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 2604{
2605 struct mmc_cmd cmd;
2606 int err;
2607
2608 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2609 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 2610 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 2611 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 2612
2613 err = mmc_send_cmd(mmc, &cmd, NULL);
2614
2615 if (err)
2616 return err;
2617
998be3dd 2618 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 2619 return -EOPNOTSUPP;
272cc70b
AF		 2620 else
2621 mmc->version = SD_VERSION_2;
2622
2623 return 0;
2624}
2625
c4d660d4 2626#if !CONFIG_IS_ENABLED(DM_MMC)
95de9ab2
PK		 2627/* board-specific MMC power initializations. */
2628__weak void board_mmc_power_init(void)
2629{
2630}
05cbeb7c 2631#endif
95de9ab2 2632
2051aefe
PF		 2633static int mmc_power_init(struct mmc *mmc)
2634{
c4d660d4 2635#if CONFIG_IS_ENABLED(DM_MMC)
06ec045f 2636#if CONFIG_IS_ENABLED(DM_REGULATOR)
2051aefe
PF		 2637 int ret;
2638
2639 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
06ec045f
JJH		 2640 &mmc->vmmc_supply);
2641 if (ret)
d4d64889 2642 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2051aefe 2643
06ec045f
JJH		 2644 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2645 &mmc->vqmmc_supply);
2646 if (ret)
d4d64889 2647 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
fb7c3beb
KVA		 2648#endif
2649#else /* !CONFIG_DM_MMC */
2650 /*
2651 * Driver model should use a regulator, as above, rather than calling
2652 * out to board code.
2653 */
2654 board_mmc_power_init();
2655#endif
2656 return 0;
2657}
2658
2659/*
2660 * put the host in the initial state:
2661 * - turn on Vdd (card power supply)
2662 * - configure the bus width and clock to minimal values
2663 */
2664static void mmc_set_initial_state(struct mmc *mmc)
2665{
2666 int err;
2667
2668 /* First try to set 3.3V. If it fails set to 1.8V */
2669 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2670 if (err != 0)
2671 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2672 if (err != 0)
d8e3d420 2673 pr_warn("mmc: failed to set signal voltage\n");
fb7c3beb
KVA		 2674
2675 mmc_select_mode(mmc, MMC_LEGACY);
2676 mmc_set_bus_width(mmc, 1);
65117182 2677 mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
fb7c3beb 2678}
06ec045f 2679
fb7c3beb
KVA		 2680static int mmc_power_on(struct mmc *mmc)
2681{
2682#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
06ec045f 2683 if (mmc->vmmc_supply) {
fb7c3beb
KVA		 2684 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2685
06ec045f
JJH		 2686 if (ret) {
2687 puts("Error enabling VMMC supply\n");
2688 return ret;
2689 }
2051aefe 2690 }
05cbeb7c 2691#endif
fb7c3beb
KVA		 2692 return 0;
2693}
2694
2695static int mmc_power_off(struct mmc *mmc)
2696{
65117182 2697 mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
fb7c3beb
KVA		 2698#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2699 if (mmc->vmmc_supply) {
2700 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2701
2702 if (ret) {
d4d64889 2703 pr_debug("Error disabling VMMC supply\n");
fb7c3beb
KVA		 2704 return ret;
2705 }
2706 }
2051aefe
PF		 2707#endif
2708 return 0;
2709}
2710
fb7c3beb
KVA		 2711static int mmc_power_cycle(struct mmc *mmc)
2712{
2713 int ret;
2714
2715 ret = mmc_power_off(mmc);
2716 if (ret)
2717 return ret;
2718 /*
2719 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2720 * to be on the safer side.
2721 */
2722 udelay(2000);
2723 return mmc_power_on(mmc);
2724}
2725
6c09eba5 2726int mmc_get_op_cond(struct mmc *mmc)
272cc70b 2727{
c10b85d6 2728 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
afd5932b 2729 int err;
272cc70b 2730
bc897b1d
LW		 2731 if (mmc->has_init)
2732 return 0;
2733
5a8dbdc6
YL		 2734#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2735 mmc_adapter_card_type_ident();
2736#endif
2051aefe
PF		 2737 err = mmc_power_init(mmc);
2738 if (err)
2739 return err;
95de9ab2 2740
83dc4227
KVA		 2741#ifdef CONFIG_MMC_QUIRKS
2742 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2743 MMC_QUIRK_RETRY_SEND_CID;
2744#endif
2745
04a2ea24
JJH		 2746 err = mmc_power_cycle(mmc);
2747 if (err) {
2748 /*
2749 * if power cycling is not supported, we should not try
2750 * to use the UHS modes, because we wouldn't be able to
2751 * recover from an error during the UHS initialization.
2752 */
d4d64889 2753 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
04a2ea24
JJH		 2754 uhs_en = false;
2755 mmc->host_caps &= ~UHS_CAPS;
2756 err = mmc_power_on(mmc);
2757 }
fb7c3beb
KVA		 2758 if (err)
2759 return err;
2760
e7881d85 2761#if CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 2762 /* The device has already been probed ready for use */
2763#else
ab769f22 2764 /* made sure it's not NULL earlier */
93bfd616 2765 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 2766 if (err)
2767 return err;
8ca51e51 2768#endif
786e8f81 2769 mmc->ddr_mode = 0;
aff5d3c8 2770
c10b85d6 2771retry:
fb7c3beb 2772 mmc_set_initial_state(mmc);
318a7a57 2773
272cc70b
AF		 2774 /* Reset the Card */
2775 err = mmc_go_idle(mmc);
2776
2777 if (err)
2778 return err;
2779
bc897b1d 2780 /* The internal partition reset to user partition(0) at every CMD0*/
c40fdca6 2781 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 2782
272cc70b 2783 /* Test for SD version 2 */
afd5932b 2784 err = mmc_send_if_cond(mmc);
272cc70b 2785
272cc70b 2786 /* Now try to get the SD card's operating condition */
c10b85d6
JJH		 2787 err = sd_send_op_cond(mmc, uhs_en);
2788 if (err && uhs_en) {
2789 uhs_en = false;
2790 mmc_power_cycle(mmc);
2791 goto retry;
2792 }
272cc70b
AF		 2793
2794 /* If the command timed out, we check for an MMC card */
915ffa52 2795 if (err == -ETIMEDOUT) {
272cc70b
AF		 2796 err = mmc_send_op_cond(mmc);
2797
bd47c135 2798 if (err) {
56196826 2799#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 2800 pr_err("Card did not respond to voltage select!\n");
56196826 2801#endif
915ffa52 2802 return -EOPNOTSUPP;
272cc70b
AF		 2803 }
2804 }
2805
6c09eba5
JN		 2806 return err;
2807}
2808
2809int mmc_start_init(struct mmc *mmc)
2810{
2811 bool no_card;
2812 int err = 0;
2813
2814 /*
2815 * all hosts are capable of 1 bit bus-width and able to use the legacy
2816 * timings.
2817 */
2818 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2819 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2820
2821#if !defined(CONFIG_MMC_BROKEN_CD)
6c09eba5
JN		 2822 no_card = mmc_getcd(mmc) == 0;
2823#else
2824 no_card = 0;
2825#endif
2826#if !CONFIG_IS_ENABLED(DM_MMC)
fea3939d 2827 /* we pretend there's no card when init is NULL */
6c09eba5
JN		 2828 no_card = no_card || (mmc->cfg->ops->init == NULL);
2829#endif
2830 if (no_card) {
2831 mmc->has_init = 0;
2832#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2833 pr_err("MMC: no card present\n");
2834#endif
2835 return -ENOMEDIUM;
2836 }
2837
2838 err = mmc_get_op_cond(mmc);
2839
bd47c135 2840 if (!err)
e9550449
CLC		 2841 mmc->init_in_progress = 1;
2842
2843 return err;
2844}
2845
2846static int mmc_complete_init(struct mmc *mmc)
2847{
2848 int err = 0;
2849
bd47c135 2850 mmc->init_in_progress = 0;
e9550449
CLC		 2851 if (mmc->op_cond_pending)
2852 err = mmc_complete_op_cond(mmc);
2853
2854 if (!err)
2855 err = mmc_startup(mmc);
bc897b1d
LW		 2856 if (err)
2857 mmc->has_init = 0;
2858 else
2859 mmc->has_init = 1;
e9550449
CLC		 2860 return err;
2861}
2862
2863int mmc_init(struct mmc *mmc)
2864{
bd47c135 2865 int err = 0;
36332b6e 2866 __maybe_unused ulong start;
c4d660d4 2867#if CONFIG_IS_ENABLED(DM_MMC)
33fb211d 2868 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 2869
33fb211d
SG		 2870 upriv->mmc = mmc;
2871#endif
e9550449
CLC		 2872 if (mmc->has_init)
2873 return 0;
d803fea5
MZ		 2874
2875 start = get_timer(0);
2876
e9550449
CLC		 2877 if (!mmc->init_in_progress)
2878 err = mmc_start_init(mmc);
2879
bd47c135 2880 if (!err)
e9550449 2881 err = mmc_complete_init(mmc);
919b4858 2882 if (err)
d4d64889 2883 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
919b4858 2884
bc897b1d 2885 return err;
272cc70b
AF		 2886}
2887
fceea992
MV		 2888#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
2889 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2890 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2891int mmc_deinit(struct mmc *mmc)
2892{
2893 u32 caps_filtered;
2894
2895 if (!mmc->has_init)
2896 return 0;
2897
2898 if (IS_SD(mmc)) {
2899 caps_filtered = mmc->card_caps &
2900 ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
2901 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
2902 MMC_CAP(UHS_SDR104));
2903
2904 return sd_select_mode_and_width(mmc, caps_filtered);
2905 } else {
2906 caps_filtered = mmc->card_caps &
2907 ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
2908
2909 return mmc_select_mode_and_width(mmc, caps_filtered);
2910 }
2911}
2912#endif
2913
ab71188c
MN		 2914int mmc_set_dsr(struct mmc *mmc, u16 val)
2915{
2916 mmc->dsr = val;
2917 return 0;
2918}
2919
cee9ab7c
JH		 2920/* CPU-specific MMC initializations */
2921__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 2922{
2923 return -1;
2924}
2925
cee9ab7c
JH		 2926/* board-specific MMC initializations. */
2927__weak int board_mmc_init(bd_t *bis)
2928{
2929 return -1;
2930}
272cc70b 2931
e9550449
CLC		 2932void mmc_set_preinit(struct mmc *mmc, int preinit)
2933{
2934 mmc->preinit = preinit;
2935}
2936
8a856db2 2937#if CONFIG_IS_ENABLED(DM_MMC)
8e3332e2
SS		 2938static int mmc_probe(bd_t *bis)
2939{
4a1db6d8 2940 int ret, i;
8e3332e2 2941 struct uclass *uc;
4a1db6d8 2942 struct udevice *dev;
8e3332e2
SS		 2943
2944 ret = uclass_get(UCLASS_MMC, &uc);
2945 if (ret)
2946 return ret;
2947
4a1db6d8
SG		 2948 /*
2949 * Try to add them in sequence order. Really with driver model we
2950 * should allow holes, but the current MMC list does not allow that.
2951 * So if we request 0, 1, 3 we will get 0, 1, 2.
2952 */
2953 for (i = 0; ; i++) {
2954 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2955 if (ret == -ENODEV)
2956 break;
2957 }
2958 uclass_foreach_dev(dev, uc) {
2959 ret = device_probe(dev);
8e3332e2 2960 if (ret)
d8e3d420 2961 pr_err("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 2962 }
2963
2964 return 0;
2965}
2966#else
2967static int mmc_probe(bd_t *bis)
2968{
2969 if (board_mmc_init(bis) < 0)
2970 cpu_mmc_init(bis);
2971
2972 return 0;
2973}
2974#endif
e9550449 2975
272cc70b
AF		 2976int mmc_initialize(bd_t *bis)
2977{
1b26bab1 2978 static int initialized = 0;
8e3332e2 2979 int ret;
1b26bab1
DK		 2980 if (initialized) /* Avoid initializing mmc multiple times */
2981 return 0;
2982 initialized = 1;
2983
c4d660d4 2984#if !CONFIG_IS_ENABLED(BLK)
b5b838f1 2985#if !CONFIG_IS_ENABLED(MMC_TINY)
c40fdca6 2986 mmc_list_init();
b5b838f1 2987#endif
c40fdca6 2988#endif
8e3332e2
SS		 2989 ret = mmc_probe(bis);
2990 if (ret)
2991 return ret;
272cc70b 2992
bb0dc108 2993#ifndef CONFIG_SPL_BUILD
272cc70b 2994 print_mmc_devices(',');
bb0dc108 2995#endif
272cc70b 2996
c40fdca6 2997 mmc_do_preinit();
272cc70b
AF		 2998 return 0;
2999}
cd3d4880
TM		 3000
3001#ifdef CONFIG_CMD_BKOPS_ENABLE
3002int mmc_set_bkops_enable(struct mmc *mmc)
3003{
3004 int err;
3005 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
3006
3007 err = mmc_send_ext_csd(mmc, ext_csd);
3008 if (err) {
3009 puts("Could not get ext_csd register values\n");
3010 return err;
3011 }
3012
3013 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
3014 puts("Background operations not supported on device\n");
3015 return -EMEDIUMTYPE;
3016 }
3017
3018 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
3019 puts("Background operations already enabled\n");
3020 return 0;
3021 }
3022
3023 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
3024 if (err) {
3025 puts("Failed to enable manual background operations\n");
3026 return err;
3027 }
3028
3029 puts("Enabled manual background operations\n");
3030
3031 return 0;
3032}
3033#endif
"Das U-Boot" Source Tree