[people/ms/u-boot.git] / drivers / mmc / mxsmmc.c

/*
 * Freescale i.MX28 SSP MMC driver
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * Based on code from LTIB:
 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
 * Terry Lv
 *
 * Copyright 2007, Freescale Semiconductor, Inc
 * Andy Fleming
 *
 * Based vaguely on the pxa mmc code:
 * (C) Copyright 2003
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <malloc.h>
#include <mmc.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/dma.h>
#include <bouncebuf.h>

struct mxsmmc_priv {
	int			id;
	struct mxs_ssp_regs	*regs;
	uint32_t		buswidth;
	int			(*mmc_is_wp)(int);
	struct mxs_dma_desc	*desc;
};

#define	MXSMMC_MAX_TIMEOUT	10000
#define MXSMMC_SMALL_TRANSFER	512

static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
{
	struct mxs_ssp_regs *ssp_regs = priv->regs;
	uint32_t *data_ptr;
	int timeout = MXSMMC_MAX_TIMEOUT;
	uint32_t reg;
	uint32_t data_count = data->blocksize * data->blocks;

	if (data->flags & MMC_DATA_READ) {
		data_ptr = (uint32_t *)data->dest;
		while (data_count && --timeout) {
			reg = readl(&ssp_regs->hw_ssp_status);
			if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
				*data_ptr++ = readl(&ssp_regs->hw_ssp_data);
				data_count -= 4;
				timeout = MXSMMC_MAX_TIMEOUT;
			} else
				udelay(1000);
		}
	} else {
		data_ptr = (uint32_t *)data->src;
		timeout *= 100;
		while (data_count && --timeout) {
			reg = readl(&ssp_regs->hw_ssp_status);
			if (!(reg & SSP_STATUS_FIFO_FULL)) {
				writel(*data_ptr++, &ssp_regs->hw_ssp_data);
				data_count -= 4;
				timeout = MXSMMC_MAX_TIMEOUT;
			} else
				udelay(1000);
		}
	}

	return timeout ? 0 : COMM_ERR;
}

static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
{
	uint32_t data_count = data->blocksize * data->blocks;
	int dmach;
	struct mxs_dma_desc *desc = priv->desc;
	void *addr;
	unsigned int flags;
	struct bounce_buffer bbstate;

	memset(desc, 0, sizeof(struct mxs_dma_desc));
	desc->address = (dma_addr_t)desc;

	if (data->flags & MMC_DATA_READ) {
		priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
		addr = data->dest;
		flags = GEN_BB_WRITE;
	} else {
		priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
		addr = (void *)data->src;
		flags = GEN_BB_READ;
	}

	bounce_buffer_start(&bbstate, addr, data_count, flags);

	priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;

	priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
				(data_count << MXS_DMA_DESC_BYTES_OFFSET);

	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
	mxs_dma_desc_append(dmach, priv->desc);
	if (mxs_dma_go(dmach)) {
		bounce_buffer_stop(&bbstate);
		return COMM_ERR;
	}

	bounce_buffer_stop(&bbstate);

	return 0;
}

/*
 * Sends a command out on the bus.  Takes the mmc pointer,
 * a command pointer, and an optional data pointer.
 */
static int
mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
	struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
	struct mxs_ssp_regs *ssp_regs = priv->regs;
	uint32_t reg;
	int timeout;
	uint32_t ctrl0;
	int ret;

	debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);

	/* Check bus busy */
	timeout = MXSMMC_MAX_TIMEOUT;
	while (--timeout) {
		udelay(1000);
		reg = readl(&ssp_regs->hw_ssp_status);
		if (!(reg &
			(SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
			SSP_STATUS_CMD_BUSY))) {
			break;
		}
	}

	if (!timeout) {
		printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
		return TIMEOUT;
	}

	/* See if card is present */
	if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
		printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
		return NO_CARD_ERR;
	}

	/* Start building CTRL0 contents */
	ctrl0 = priv->buswidth;

	/* Set up command */
	if (!(cmd->resp_type & MMC_RSP_CRC))
		ctrl0 |= SSP_CTRL0_IGNORE_CRC;
	if (cmd->resp_type & MMC_RSP_PRESENT)	/* Need to get response */
		ctrl0 |= SSP_CTRL0_GET_RESP;
	if (cmd->resp_type & MMC_RSP_136)	/* It's a 136 bits response */
		ctrl0 |= SSP_CTRL0_LONG_RESP;

	if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
		writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
	else
		writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);

	/* Command index */
	reg = readl(&ssp_regs->hw_ssp_cmd0);
	reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
	reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		reg |= SSP_CMD0_APPEND_8CYC;
	writel(reg, &ssp_regs->hw_ssp_cmd0);

	/* Command argument */
	writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);

	/* Set up data */
	if (data) {
		/* READ or WRITE */
		if (data->flags & MMC_DATA_READ) {
			ctrl0 |= SSP_CTRL0_READ;
		} else if (priv->mmc_is_wp &&
			priv->mmc_is_wp(mmc->block_dev.dev)) {
			printf("MMC%d: Can not write a locked card!\n",
				mmc->block_dev.dev);
			return UNUSABLE_ERR;
		}

		ctrl0 |= SSP_CTRL0_DATA_XFER;
		reg = ((data->blocks - 1) <<
			SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
			((ffs(data->blocksize) - 1) <<
			SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
		writel(reg, &ssp_regs->hw_ssp_block_size);

		reg = data->blocksize * data->blocks;
		writel(reg, &ssp_regs->hw_ssp_xfer_size);
	}

	/* Kick off the command */
	ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
	writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);

	/* Wait for the command to complete */
	timeout = MXSMMC_MAX_TIMEOUT;
	while (--timeout) {
		udelay(1000);
		reg = readl(&ssp_regs->hw_ssp_status);
		if (!(reg & SSP_STATUS_CMD_BUSY))
			break;
	}

	if (!timeout) {
		printf("MMC%d: Command %d busy\n",
			mmc->block_dev.dev, cmd->cmdidx);
		return TIMEOUT;
	}

	/* Check command timeout */
	if (reg & SSP_STATUS_RESP_TIMEOUT) {
		printf("MMC%d: Command %d timeout (status 0x%08x)\n",
			mmc->block_dev.dev, cmd->cmdidx, reg);
		return TIMEOUT;
	}

	/* Check command errors */
	if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
		printf("MMC%d: Command %d error (status 0x%08x)!\n",
			mmc->block_dev.dev, cmd->cmdidx, reg);
		return COMM_ERR;
	}

	/* Copy response to response buffer */
	if (cmd->resp_type & MMC_RSP_136) {
		cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
		cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
		cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
		cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
	} else
		cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);

	/* Return if no data to process */
	if (!data)
		return 0;

	if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
		ret = mxsmmc_send_cmd_pio(priv, data);
		if (ret) {
			printf("MMC%d: Data timeout with command %d "
				"(status 0x%08x)!\n",
				mmc->block_dev.dev, cmd->cmdidx, reg);
			return ret;
		}
	} else {
		ret = mxsmmc_send_cmd_dma(priv, data);
		if (ret) {
			printf("MMC%d: DMA transfer failed\n",
				mmc->block_dev.dev);
			return ret;
		}
	}

	/* Check data errors */
	reg = readl(&ssp_regs->hw_ssp_status);
	if (reg &
		(SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
		SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
		printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
			mmc->block_dev.dev, cmd->cmdidx, reg);
		return COMM_ERR;
	}

	return 0;
}

static void mxsmmc_set_ios(struct mmc *mmc)
{
	struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
	struct mxs_ssp_regs *ssp_regs = priv->regs;

	/* Set the clock speed */
	if (mmc->clock)
		mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);

	switch (mmc->bus_width) {
	case 1:
		priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
		break;
	case 4:
		priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
		break;
	case 8:
		priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
		break;
	}

	/* Set the bus width */
	clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
			SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);

	debug("MMC%d: Set %d bits bus width\n",
		mmc->block_dev.dev, mmc->bus_width);
}

static int mxsmmc_init(struct mmc *mmc)
{
	struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
	struct mxs_ssp_regs *ssp_regs = priv->regs;

	/* Reset SSP */
	mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);

	/* Reconfigure the SSP block for MMC operation */
	writel(SSP_CTRL1_SSP_MODE_SD_MMC |
		SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
		SSP_CTRL1_DMA_ENABLE |
		SSP_CTRL1_POLARITY |
		SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
		SSP_CTRL1_DATA_CRC_IRQ_EN |
		SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
		SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
		SSP_CTRL1_RESP_ERR_IRQ_EN,
		&ssp_regs->hw_ssp_ctrl1_set);

	/* Set initial bit clock 400 KHz */
	mxs_set_ssp_busclock(priv->id, 400);

	/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
	writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
	udelay(200);
	writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);

	return 0;
}

int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
{
	struct mmc *mmc = NULL;
	struct mxsmmc_priv *priv = NULL;
	int ret;
#if defined(CONFIG_MX23)
	const unsigned int mxsmmc_max_id = 2;
	const unsigned int mxsmmc_clk_id = 0;
#elif defined(CONFIG_MX28)
	const unsigned int mxsmmc_max_id = 4;
	const unsigned int mxsmmc_clk_id = id;
#endif

	if (id >= mxsmmc_max_id)
		return -ENODEV;

	mmc = malloc(sizeof(struct mmc));
	if (!mmc)
		return -ENOMEM;

	priv = malloc(sizeof(struct mxsmmc_priv));
	if (!priv) {
		free(mmc);
		return -ENOMEM;
	}

	priv->desc = mxs_dma_desc_alloc();
	if (!priv->desc) {
		free(priv);
		free(mmc);
		return -ENOMEM;
	}

	ret = mxs_dma_init_channel(id);
	if (ret)
		return ret;

	priv->mmc_is_wp = wp;
	priv->id = id;
	priv->regs = mxs_ssp_regs_by_bus(id);

	sprintf(mmc->name, "MXS MMC");
	mmc->send_cmd = mxsmmc_send_cmd;
	mmc->set_ios = mxsmmc_set_ios;
	mmc->init = mxsmmc_init;
	mmc->getcd = NULL;
	mmc->priv = priv;

	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;

	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
			 MMC_MODE_HS_52MHz | MMC_MODE_HS;

	/*
	 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
	 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
	 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
	 * CLOCK_RATE could be any integer from 0 to 255.
	 */
	mmc->f_min = 400000;
	mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
	mmc->b_max = 0x20;

	mmc_register(mmc);
	return 0;
}
Commit	Line	Data
71a758e1 MV	1	/*
	2	* Freescale i.MX28 SSP MMC driver
	3	*
	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
	7	* Based on code from LTIB:
	8	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
	9	* Terry Lv
	10	*
	11	* Copyright 2007, Freescale Semiconductor, Inc
	12	* Andy Fleming
	13	*
	14	* Based vaguely on the pxa mmc code:
	15	* (C) Copyright 2003
	16	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	17	*
	18	* See file CREDITS for list of people who contributed to this
	19	* project.
	20	*
	21	* This program is free software; you can redistribute it and/or
	22	* modify it under the terms of the GNU General Public License as
	23	* published by the Free Software Foundation; either version 2 of
	24	* the License, or (at your option) any later version.
	25	*
	26	* This program is distributed in the hope that it will be useful,
	27	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	28	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	29	* GNU General Public License for more details.
	30	*
	31	* You should have received a copy of the GNU General Public License
	32	* along with this program; if not, write to the Free Software
	33	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	34	* MA 02111-1307 USA
	35	*/
	36	#include <common.h>
	37	#include <malloc.h>
	38	#include <mmc.h>
	39	#include <asm/errno.h>
	40	#include <asm/io.h>
	41	#include <asm/arch/clock.h>
	42	#include <asm/arch/imx-regs.h>
	43	#include <asm/arch/sys_proto.h>
3687c415	44	#include <asm/arch/dma.h>
4e6d81d1	45	#include <bouncebuf.h>
71a758e1 MV	46
	47	struct mxsmmc_priv {
	48	int id;
9c471142	49	struct mxs_ssp_regs *regs;
71a758e1 MV	50	uint32_t buswidth;
71a758e1 MV	51	int (*mmc_is_wp)(int);
3687c415	52	struct mxs_dma_desc *desc;
71a758e1 MV	53	};
	54
	55	#define MXSMMC_MAX_TIMEOUT 10000
20255900	56	#define MXSMMC_SMALL_TRANSFER 512
71a758e1	57
86983328 MV	58	static int mxsmmc_send_cmd_pio(struct mxsmmc_priv priv, struct mmc_data data)
	59	{
	60	struct mxs_ssp_regs *ssp_regs = priv->regs;
	61	uint32_t *data_ptr;
	62	int timeout = MXSMMC_MAX_TIMEOUT;
	63	uint32_t reg;
	64	uint32_t data_count = data->blocksize * data->blocks;
	65
	66	if (data->flags & MMC_DATA_READ) {
	67	data_ptr = (uint32_t *)data->dest;
	68	while (data_count && --timeout) {
	69	reg = readl(&ssp_regs->hw_ssp_status);
	70	if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
	71	*data_ptr++ = readl(&ssp_regs->hw_ssp_data);
	72	data_count -= 4;
	73	timeout = MXSMMC_MAX_TIMEOUT;
	74	} else
	75	udelay(1000);
	76	}
	77	} else {
	78	data_ptr = (uint32_t *)data->src;
	79	timeout *= 100;
	80	while (data_count && --timeout) {
	81	reg = readl(&ssp_regs->hw_ssp_status);
	82	if (!(reg & SSP_STATUS_FIFO_FULL)) {
	83	writel(*data_ptr++, &ssp_regs->hw_ssp_data);
	84	data_count -= 4;
	85	timeout = MXSMMC_MAX_TIMEOUT;
	86	} else
	87	udelay(1000);
	88	}
	89	}
	90
	91	return timeout ? 0 : COMM_ERR;
	92	}
20255900	93
86983328 MV	94	static int mxsmmc_send_cmd_dma(struct mxsmmc_priv priv, struct mmc_data data)
	95	{
	96	uint32_t data_count = data->blocksize * data->blocks;
86983328	97	int dmach;
abb85be7	98	struct mxs_dma_desc *desc = priv->desc;
84d35b28 SW	99	void *addr;
	100	unsigned int flags;
	101	struct bounce_buffer bbstate;
abb85be7 MV	102
	103	memset(desc, 0, sizeof(struct mxs_dma_desc));
	104	desc->address = (dma_addr_t)desc;
86983328	105
86983328 MV	106	if (data->flags & MMC_DATA_READ) {
86983328 MV	107	priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
4e6d81d1 MV	108	addr = data->dest;
4e6d81d1 MV	109	flags = GEN_BB_WRITE;
86983328 MV	110	} else {
86983328 MV	111	priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
4e6d81d1 MV	112	addr = (void *)data->src;
	113	flags = GEN_BB_READ;
	114	}
	115
84d35b28	116	bounce_buffer_start(&bbstate, addr, data_count, flags);
4e6d81d1	117
84d35b28	118	priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
97ed12ce	119
86983328 MV	120	priv->desc->cmd.data \|= MXS_DMA_DESC_IRQ \| MXS_DMA_DESC_DEC_SEM \|
	121	(data_count << MXS_DMA_DESC_BYTES_OFFSET);
	122
86983328 MV	123	dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
86983328 MV	124	mxs_dma_desc_append(dmach, priv->desc);
4e6d81d1	125	if (mxs_dma_go(dmach)) {
84d35b28	126	bounce_buffer_stop(&bbstate);
86983328	127	return COMM_ERR;
4e6d81d1	128	}
86983328	129
84d35b28	130	bounce_buffer_stop(&bbstate);
4e6d81d1	131
86983328 MV	132	return 0;
86983328 MV	133	}
86983328	134
71a758e1 MV	135	/*
	136	* Sends a command out on the bus. Takes the mmc pointer,
	137	* a command pointer, and an optional data pointer.
	138	*/
	139	static int
	140	mxsmmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)
	141	{
	142	struct mxsmmc_priv priv = (struct mxsmmc_priv )mmc->priv;
9c471142	143	struct mxs_ssp_regs *ssp_regs = priv->regs;
71a758e1 MV	144	uint32_t reg;
71a758e1 MV	145	int timeout;
71a758e1	146	uint32_t ctrl0;
86983328	147	int ret;
71a758e1 MV	148
	149	debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
	150
	151	/* Check bus busy */
	152	timeout = MXSMMC_MAX_TIMEOUT;
	153	while (--timeout) {
	154	udelay(1000);
	155	reg = readl(&ssp_regs->hw_ssp_status);
	156	if (!(reg &
	157	(SSP_STATUS_BUSY \| SSP_STATUS_DATA_BUSY \|
	158	SSP_STATUS_CMD_BUSY))) {
	159	break;
	160	}
	161	}
	162
	163	if (!timeout) {
	164	printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
	165	return TIMEOUT;
	166	}
	167
	168	/* See if card is present */
	169	if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
	170	printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
	171	return NO_CARD_ERR;
	172	}
	173
	174	/* Start building CTRL0 contents */
	175	ctrl0 = priv->buswidth;
	176
	177	/* Set up command */
	178	if (!(cmd->resp_type & MMC_RSP_CRC))
	179	ctrl0 \|= SSP_CTRL0_IGNORE_CRC;
	180	if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
	181	ctrl0 \|= SSP_CTRL0_GET_RESP;
	182	if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
	183	ctrl0 \|= SSP_CTRL0_LONG_RESP;
	184
abb85be7 MV	185	if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
	186	writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
	187	else
	188	writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
	189
71a758e1 MV	190	/* Command index */
	191	reg = readl(&ssp_regs->hw_ssp_cmd0);
	192	reg &= ~(SSP_CMD0_CMD_MASK \| SSP_CMD0_APPEND_8CYC);
	193	reg \|= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
	194	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	195	reg \|= SSP_CMD0_APPEND_8CYC;
	196	writel(reg, &ssp_regs->hw_ssp_cmd0);
	197
	198	/* Command argument */
	199	writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
	200
	201	/* Set up data */
	202	if (data) {
	203	/* READ or WRITE */
	204	if (data->flags & MMC_DATA_READ) {
	205	ctrl0 \|= SSP_CTRL0_READ;
c7527b70 MV	206	} else if (priv->mmc_is_wp &&
c7527b70 MV	207	priv->mmc_is_wp(mmc->block_dev.dev)) {
71a758e1 MV	208	printf("MMC%d: Can not write a locked card!\n",
	209	mmc->block_dev.dev);
	210	return UNUSABLE_ERR;
	211	}
	212
	213	ctrl0 \|= SSP_CTRL0_DATA_XFER;
	214	reg = ((data->blocks - 1) <<
	215	SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) \|
	216	((ffs(data->blocksize) - 1) <<
	217	SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
	218	writel(reg, &ssp_regs->hw_ssp_block_size);
	219
	220	reg = data->blocksize * data->blocks;
	221	writel(reg, &ssp_regs->hw_ssp_xfer_size);
	222	}
	223
	224	/* Kick off the command */
	225	ctrl0 \|= SSP_CTRL0_WAIT_FOR_IRQ \| SSP_CTRL0_ENABLE \| SSP_CTRL0_RUN;
	226	writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
	227
	228	/* Wait for the command to complete */
	229	timeout = MXSMMC_MAX_TIMEOUT;
	230	while (--timeout) {
	231	udelay(1000);
	232	reg = readl(&ssp_regs->hw_ssp_status);
	233	if (!(reg & SSP_STATUS_CMD_BUSY))
	234	break;
	235	}
	236
	237	if (!timeout) {
	238	printf("MMC%d: Command %d busy\n",
	239	mmc->block_dev.dev, cmd->cmdidx);
	240	return TIMEOUT;
	241	}
	242
	243	/* Check command timeout */
	244	if (reg & SSP_STATUS_RESP_TIMEOUT) {
	245	printf("MMC%d: Command %d timeout (status 0x%08x)\n",
	246	mmc->block_dev.dev, cmd->cmdidx, reg);
	247	return TIMEOUT;
	248	}
	249
	250	/* Check command errors */
	251	if (reg & (SSP_STATUS_RESP_CRC_ERR \| SSP_STATUS_RESP_ERR)) {
	252	printf("MMC%d: Command %d error (status 0x%08x)!\n",
	253	mmc->block_dev.dev, cmd->cmdidx, reg);
	254	return COMM_ERR;
	255	}
	256
	257	/* Copy response to response buffer */
	258	if (cmd->resp_type & MMC_RSP_136) {
	259	cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
	260	cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
	261	cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
	262	cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
	263	} else
	264	cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
	265
	266	/* Return if no data to process */
	267	if (!data)
	268	return 0;
	269
20255900	270	if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
20255900 MV	271	ret = mxsmmc_send_cmd_pio(priv, data);
	272	if (ret) {
	273	printf("MMC%d: Data timeout with command %d "
	274	"(status 0x%08x)!\n",
	275	mmc->block_dev.dev, cmd->cmdidx, reg);
	276	return ret;
	277	}
abb85be7 MV	278	} else {
	279	ret = mxsmmc_send_cmd_dma(priv, data);
	280	if (ret) {
	281	printf("MMC%d: DMA transfer failed\n",
	282	mmc->block_dev.dev);
	283	return ret;
	284	}
4cc76c60	285	}
3687c415	286
71a758e1 MV	287	/* Check data errors */
	288	reg = readl(&ssp_regs->hw_ssp_status);
	289	if (reg &
	290	(SSP_STATUS_TIMEOUT \| SSP_STATUS_DATA_CRC_ERR \|
	291	SSP_STATUS_FIFO_OVRFLW \| SSP_STATUS_FIFO_UNDRFLW)) {
	292	printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
	293	mmc->block_dev.dev, cmd->cmdidx, reg);
	294	return COMM_ERR;
	295	}
	296
	297	return 0;
	298	}
	299
	300	static void mxsmmc_set_ios(struct mmc *mmc)
	301	{
	302	struct mxsmmc_priv priv = (struct mxsmmc_priv )mmc->priv;
9c471142	303	struct mxs_ssp_regs *ssp_regs = priv->regs;
71a758e1 MV	304
	305	/* Set the clock speed */
	306	if (mmc->clock)
bf48fcb6	307	mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
71a758e1 MV	308
	309	switch (mmc->bus_width) {
	310	case 1:
	311	priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
	312	break;
	313	case 4:
	314	priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
	315	break;
	316	case 8:
	317	priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
	318	break;
	319	}
	320
	321	/* Set the bus width */
	322	clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
	323	SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
	324
	325	debug("MMC%d: Set %d bits bus width\n",
	326	mmc->block_dev.dev, mmc->bus_width);
	327	}
	328
	329	static int mxsmmc_init(struct mmc *mmc)
	330	{
	331	struct mxsmmc_priv priv = (struct mxsmmc_priv )mmc->priv;
9c471142	332	struct mxs_ssp_regs *ssp_regs = priv->regs;
71a758e1 MV	333
71a758e1 MV	334	/* Reset SSP */
fa7a51cb	335	mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
71a758e1	336
8000d8a8 OS	337	/* Reconfigure the SSP block for MMC operation */
	338	writel(SSP_CTRL1_SSP_MODE_SD_MMC \|
	339	SSP_CTRL1_WORD_LENGTH_EIGHT_BITS \|
	340	SSP_CTRL1_DMA_ENABLE \|
	341	SSP_CTRL1_POLARITY \|
	342	SSP_CTRL1_RECV_TIMEOUT_IRQ_EN \|
	343	SSP_CTRL1_DATA_CRC_IRQ_EN \|
	344	SSP_CTRL1_DATA_TIMEOUT_IRQ_EN \|
	345	SSP_CTRL1_RESP_TIMEOUT_IRQ_EN \|
	346	SSP_CTRL1_RESP_ERR_IRQ_EN,
	347	&ssp_regs->hw_ssp_ctrl1_set);
71a758e1 MV	348
71a758e1 MV	349	/* Set initial bit clock 400 KHz */
bf48fcb6	350	mxs_set_ssp_busclock(priv->id, 400);
71a758e1 MV	351
	352	/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
	353	writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
	354	udelay(200);
	355	writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
	356
	357	return 0;
	358	}
	359
	360	int mxsmmc_initialize(bd_t bis, int id, int (wp)(int))
	361	{
71a758e1 MV	362	struct mmc *mmc = NULL;
71a758e1 MV	363	struct mxsmmc_priv *priv = NULL;
96666a39	364	int ret;
1a3c5ffe MV	365	#if defined(CONFIG_MX23)
	366	const unsigned int mxsmmc_max_id = 2;
	367	const unsigned int mxsmmc_clk_id = 0;
	368	#elif defined(CONFIG_MX28)
	369	const unsigned int mxsmmc_max_id = 4;
	370	const unsigned int mxsmmc_clk_id = id;
	371	#endif
	372
	373	if (id >= mxsmmc_max_id)
	374	return -ENODEV;
71a758e1 MV	375
	376	mmc = malloc(sizeof(struct mmc));
	377	if (!mmc)
	378	return -ENOMEM;
	379
	380	priv = malloc(sizeof(struct mxsmmc_priv));
	381	if (!priv) {
	382	free(mmc);
	383	return -ENOMEM;
	384	}
	385
3687c415 MV	386	priv->desc = mxs_dma_desc_alloc();
	387	if (!priv->desc) {
	388	free(priv);
	389	free(mmc);
	390	return -ENOMEM;
	391	}
	392
96666a39 MV	393	ret = mxs_dma_init_channel(id);
	394	if (ret)
	395	return ret;
	396
71a758e1 MV	397	priv->mmc_is_wp = wp;
71a758e1 MV	398	priv->id = id;
14e26bcf	399	priv->regs = mxs_ssp_regs_by_bus(id);
71a758e1 MV	400
	401	sprintf(mmc->name, "MXS MMC");
	402	mmc->send_cmd = mxsmmc_send_cmd;
	403	mmc->set_ios = mxsmmc_set_ios;
	404	mmc->init = mxsmmc_init;
48972d90	405	mmc->getcd = NULL;
71a758e1 MV	406	mmc->priv = priv;
	407
	408	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
	409
	410	mmc->host_caps = MMC_MODE_4BIT \| MMC_MODE_8BIT \|
	411	MMC_MODE_HS_52MHz \| MMC_MODE_HS;
	412
	413	/*
	414	* SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
	415	* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
	416	* CLOCK_DIVIDE has to be an even value from 2 to 254, and
	417	* CLOCK_RATE could be any integer from 0 to 255.
	418	*/
	419	mmc->f_min = 400000;
1a3c5ffe	420	mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
e7205905	421	mmc->b_max = 0x20;
71a758e1 MV	422
	423	mmc_register(mmc);
	424	return 0;
	425	}