]>
Commit | Line | Data |
---|---|---|
de941241 SG |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * Sukumar Ghorai <s-ghorai@ti.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation's version 2 of | |
12 | * the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <config.h> | |
26 | #include <common.h> | |
93bfd616 | 27 | #include <malloc.h> |
f0d53e88 | 28 | #include <memalign.h> |
de941241 SG |
29 | #include <mmc.h> |
30 | #include <part.h> | |
31 | #include <i2c.h> | |
339d5789 | 32 | #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX) |
cb199102 | 33 | #include <palmas.h> |
339d5789 | 34 | #endif |
de941241 SG |
35 | #include <asm/io.h> |
36 | #include <asm/arch/mmc_host_def.h> | |
33c1d77f KVA |
37 | #ifdef CONFIG_OMAP54XX |
38 | #include <asm/arch/mux_dra7xx.h> | |
39 | #include <asm/arch/dra7xx_iodelay.h> | |
40 | #endif | |
3b68939f RQ |
41 | #if !defined(CONFIG_SOC_KEYSTONE) |
42 | #include <asm/gpio.h> | |
96e0e7b3 | 43 | #include <asm/arch/sys_proto.h> |
3b68939f | 44 | #endif |
2a48b3a2 TR |
45 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
46 | #include <asm/arch/mux.h> | |
47 | #endif | |
a9d6a7e2 | 48 | #include <dm.h> |
42182c9b | 49 | #include <power/regulator.h> |
a9d6a7e2 M |
50 | |
51 | DECLARE_GLOBAL_DATA_PTR; | |
de941241 | 52 | |
ab769f22 PA |
53 | /* simplify defines to OMAP_HSMMC_USE_GPIO */ |
54 | #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ | |
55 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) | |
56 | #define OMAP_HSMMC_USE_GPIO | |
57 | #else | |
58 | #undef OMAP_HSMMC_USE_GPIO | |
59 | #endif | |
60 | ||
25c719e2 GI |
61 | /* common definitions for all OMAPs */ |
62 | #define SYSCTL_SRC (1 << 25) | |
63 | #define SYSCTL_SRD (1 << 26) | |
64 | ||
33c1d77f KVA |
65 | #ifdef CONFIG_IODELAY_RECALIBRATION |
66 | struct omap_hsmmc_pinctrl_state { | |
67 | struct pad_conf_entry *padconf; | |
68 | int npads; | |
69 | struct iodelay_cfg_entry *iodelay; | |
70 | int niodelays; | |
71 | }; | |
72 | #endif | |
73 | ||
cc22b0c0 NK |
74 | struct omap_hsmmc_data { |
75 | struct hsmmc *base_addr; | |
c4d660d4 | 76 | #if !CONFIG_IS_ENABLED(DM_MMC) |
93bfd616 | 77 | struct mmc_config cfg; |
3d673ffc | 78 | #endif |
48a2f114 | 79 | uint bus_width; |
5baf543e | 80 | uint clock; |
04f9f8be | 81 | ushort last_cmd; |
ab769f22 | 82 | #ifdef OMAP_HSMMC_USE_GPIO |
c4d660d4 | 83 | #if CONFIG_IS_ENABLED(DM_MMC) |
a9d6a7e2 M |
84 | struct gpio_desc cd_gpio; /* Change Detect GPIO */ |
85 | struct gpio_desc wp_gpio; /* Write Protect GPIO */ | |
a9d6a7e2 | 86 | #else |
e874d5b0 | 87 | int cd_gpio; |
e3913f56 | 88 | int wp_gpio; |
ab769f22 | 89 | #endif |
b5944817 KVA |
90 | #endif |
91 | #if CONFIG_IS_ENABLED(DM_MMC) | |
8fc238bf | 92 | enum bus_mode mode; |
a9d6a7e2 | 93 | #endif |
f0d53e88 | 94 | u8 controller_flags; |
27a4b3bc | 95 | #ifdef CONFIG_MMC_OMAP_HS_ADMA |
f0d53e88 KVA |
96 | struct omap_hsmmc_adma_desc *adma_desc_table; |
97 | uint desc_slot; | |
98 | #endif | |
2d28eeda | 99 | const char *hw_rev; |
04f9f8be JJH |
100 | struct udevice *pbias_supply; |
101 | uint signal_voltage; | |
33c1d77f KVA |
102 | #ifdef CONFIG_IODELAY_RECALIBRATION |
103 | struct omap_hsmmc_pinctrl_state *default_pinctrl_state; | |
104 | struct omap_hsmmc_pinctrl_state *hs_pinctrl_state; | |
105 | struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state; | |
106 | struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state; | |
107 | struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state; | |
108 | struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state; | |
109 | struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state; | |
110 | struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state; | |
111 | struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state; | |
112 | #endif | |
113 | }; | |
114 | ||
115 | struct omap_mmc_of_data { | |
116 | u8 controller_flags; | |
f0d53e88 KVA |
117 | }; |
118 | ||
27a4b3bc | 119 | #ifdef CONFIG_MMC_OMAP_HS_ADMA |
f0d53e88 KVA |
120 | struct omap_hsmmc_adma_desc { |
121 | u8 attr; | |
122 | u8 reserved; | |
123 | u16 len; | |
124 | u32 addr; | |
cc22b0c0 NK |
125 | }; |
126 | ||
f0d53e88 KVA |
127 | #define ADMA_MAX_LEN 63488 |
128 | ||
129 | /* Decriptor table defines */ | |
130 | #define ADMA_DESC_ATTR_VALID BIT(0) | |
131 | #define ADMA_DESC_ATTR_END BIT(1) | |
132 | #define ADMA_DESC_ATTR_INT BIT(2) | |
133 | #define ADMA_DESC_ATTR_ACT1 BIT(4) | |
134 | #define ADMA_DESC_ATTR_ACT2 BIT(5) | |
135 | ||
136 | #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 | |
137 | #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2) | |
138 | #endif | |
139 | ||
eb9a28f6 NM |
140 | /* If we fail after 1 second wait, something is really bad */ |
141 | #define MAX_RETRY_MS 1000 | |
a4efd737 | 142 | #define MMC_TIMEOUT_MS 20 |
eb9a28f6 | 143 | |
f0d53e88 KVA |
144 | /* DMA transfers can take a long time if a lot a data is transferred. |
145 | * The timeout must take in account the amount of data. Let's assume | |
146 | * that the time will never exceed 333 ms per MB (in other word we assume | |
147 | * that the bandwidth is always above 3MB/s). | |
148 | */ | |
149 | #define DMA_TIMEOUT_PER_MB 333 | |
b5944817 KVA |
150 | #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) |
151 | #define OMAP_HSMMC_NO_1_8_V BIT(1) | |
f0d53e88 | 152 | #define OMAP_HSMMC_USE_ADMA BIT(2) |
33c1d77f | 153 | #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3) |
f0d53e88 | 154 | |
933efe64 S |
155 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); |
156 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, | |
157 | unsigned int siz); | |
5baf543e JJH |
158 | static void omap_hsmmc_start_clock(struct hsmmc *mmc_base); |
159 | static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base); | |
14761cae | 160 | static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit); |
14fa2dd0 | 161 | |
ae000e23 JJH |
162 | static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc) |
163 | { | |
c4d660d4 | 164 | #if CONFIG_IS_ENABLED(DM_MMC) |
ae000e23 JJH |
165 | return dev_get_priv(mmc->dev); |
166 | #else | |
167 | return (struct omap_hsmmc_data *)mmc->priv; | |
168 | #endif | |
3d673ffc JJH |
169 | } |
170 | static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc) | |
171 | { | |
c4d660d4 | 172 | #if CONFIG_IS_ENABLED(DM_MMC) |
3d673ffc JJH |
173 | struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev); |
174 | return &plat->cfg; | |
175 | #else | |
176 | return &((struct omap_hsmmc_data *)mmc->priv)->cfg; | |
177 | #endif | |
ae000e23 JJH |
178 | } |
179 | ||
c4d660d4 | 180 | #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC) |
e874d5b0 NK |
181 | static int omap_mmc_setup_gpio_in(int gpio, const char *label) |
182 | { | |
5915a2ad | 183 | int ret; |
e874d5b0 | 184 | |
5915a2ad SG |
185 | #ifndef CONFIG_DM_GPIO |
186 | if (!gpio_is_valid(gpio)) | |
e874d5b0 | 187 | return -1; |
5915a2ad SG |
188 | #endif |
189 | ret = gpio_request(gpio, label); | |
190 | if (ret) | |
191 | return ret; | |
e874d5b0 | 192 | |
5915a2ad SG |
193 | ret = gpio_direction_input(gpio); |
194 | if (ret) | |
195 | return ret; | |
e874d5b0 NK |
196 | |
197 | return gpio; | |
198 | } | |
e874d5b0 NK |
199 | #endif |
200 | ||
750121c3 | 201 | static unsigned char mmc_board_init(struct mmc *mmc) |
de941241 | 202 | { |
de941241 | 203 | #if defined(CONFIG_OMAP34XX) |
3d673ffc | 204 | struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); |
de941241 SG |
205 | t2_t *t2_base = (t2_t *)T2_BASE; |
206 | struct prcm *prcm_base = (struct prcm *)PRCM_BASE; | |
b1e725f2 | 207 | u32 pbias_lite; |
6aca17c9 AF |
208 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
209 | u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL); | |
210 | #endif | |
de941241 | 211 | |
b1e725f2 GI |
212 | pbias_lite = readl(&t2_base->pbias_lite); |
213 | pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); | |
5bfdd1fc AA |
214 | #ifdef CONFIG_TARGET_OMAP3_CAIRO |
215 | /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ | |
216 | pbias_lite &= ~PBIASLITEVMODE0; | |
6aca17c9 | 217 | #endif |
03190a78 AF |
218 | #ifdef CONFIG_TARGET_OMAP3_LOGIC |
219 | /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */ | |
220 | pbias_lite &= ~PBIASLITEVMODE1; | |
221 | #endif | |
6aca17c9 AF |
222 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
223 | if (get_cpu_family() == CPU_OMAP36XX) { | |
224 | /* Disable extended drain IO before changing PBIAS */ | |
225 | wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ; | |
226 | writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL); | |
227 | } | |
5bfdd1fc | 228 | #endif |
b1e725f2 | 229 | writel(pbias_lite, &t2_base->pbias_lite); |
aac5450e | 230 | |
b1e725f2 | 231 | writel(pbias_lite | PBIASLITEPWRDNZ1 | |
de941241 SG |
232 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, |
233 | &t2_base->pbias_lite); | |
234 | ||
6aca17c9 AF |
235 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
236 | if (get_cpu_family() == CPU_OMAP36XX) | |
237 | /* Enable extended drain IO after changing PBIAS */ | |
238 | writel(wkup_ctrl | | |
239 | OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, | |
240 | OMAP34XX_CTRL_WKUP_CTRL); | |
241 | #endif | |
de941241 SG |
242 | writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, |
243 | &t2_base->devconf0); | |
244 | ||
245 | writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, | |
246 | &t2_base->devconf1); | |
247 | ||
bbbc1ae9 | 248 | /* Change from default of 52MHz to 26MHz if necessary */ |
3d673ffc | 249 | if (!(cfg->host_caps & MMC_MODE_HS_52MHz)) |
bbbc1ae9 JS |
250 | writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, |
251 | &t2_base->ctl_prog_io1); | |
252 | ||
de941241 SG |
253 | writel(readl(&prcm_base->fclken1_core) | |
254 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
255 | &prcm_base->fclken1_core); | |
256 | ||
257 | writel(readl(&prcm_base->iclken1_core) | | |
258 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
259 | &prcm_base->iclken1_core); | |
260 | #endif | |
261 | ||
04f9f8be JJH |
262 | #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\ |
263 | !CONFIG_IS_ENABLED(DM_REGULATOR) | |
14fa2dd0 | 264 | /* PBIAS config needed for MMC1 only */ |
dc09127a | 265 | if (mmc_get_blk_desc(mmc)->devnum == 0) |
b4b06006 | 266 | vmmc_pbias_config(LDO_VOLT_3V0); |
dd23e59d | 267 | #endif |
de941241 SG |
268 | |
269 | return 0; | |
270 | } | |
271 | ||
933efe64 | 272 | void mmc_init_stream(struct hsmmc *mmc_base) |
de941241 | 273 | { |
eb9a28f6 | 274 | ulong start; |
de941241 SG |
275 | |
276 | writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); | |
277 | ||
278 | writel(MMC_CMD0, &mmc_base->cmd); | |
eb9a28f6 NM |
279 | start = get_timer(0); |
280 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
281 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
282 | printf("%s: timedout waiting for cc!\n", __func__); | |
283 | return; | |
284 | } | |
285 | } | |
de941241 SG |
286 | writel(CC_MASK, &mmc_base->stat) |
287 | ; | |
288 | writel(MMC_CMD0, &mmc_base->cmd) | |
289 | ; | |
eb9a28f6 NM |
290 | start = get_timer(0); |
291 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
292 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
293 | printf("%s: timedout waiting for cc2!\n", __func__); | |
294 | return; | |
295 | } | |
296 | } | |
de941241 SG |
297 | writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); |
298 | } | |
299 | ||
b5944817 | 300 | #if CONFIG_IS_ENABLED(DM_MMC) |
33c1d77f KVA |
301 | #ifdef CONFIG_IODELAY_RECALIBRATION |
302 | static void omap_hsmmc_io_recalibrate(struct mmc *mmc) | |
303 | { | |
304 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
305 | struct omap_hsmmc_pinctrl_state *pinctrl_state; | |
306 | ||
307 | switch (priv->mode) { | |
308 | case MMC_HS_200: | |
309 | pinctrl_state = priv->hs200_1_8v_pinctrl_state; | |
310 | break; | |
311 | case UHS_SDR104: | |
312 | pinctrl_state = priv->sdr104_pinctrl_state; | |
313 | break; | |
314 | case UHS_SDR50: | |
315 | pinctrl_state = priv->sdr50_pinctrl_state; | |
316 | break; | |
317 | case UHS_DDR50: | |
318 | pinctrl_state = priv->ddr50_pinctrl_state; | |
319 | break; | |
320 | case UHS_SDR25: | |
321 | pinctrl_state = priv->sdr25_pinctrl_state; | |
322 | break; | |
323 | case UHS_SDR12: | |
324 | pinctrl_state = priv->sdr12_pinctrl_state; | |
325 | break; | |
326 | case SD_HS: | |
327 | case MMC_HS: | |
328 | case MMC_HS_52: | |
329 | pinctrl_state = priv->hs_pinctrl_state; | |
330 | break; | |
331 | case MMC_DDR_52: | |
332 | pinctrl_state = priv->ddr_1_8v_pinctrl_state; | |
333 | default: | |
334 | pinctrl_state = priv->default_pinctrl_state; | |
335 | break; | |
336 | } | |
337 | ||
bcc6bd84 JJH |
338 | if (!pinctrl_state) |
339 | pinctrl_state = priv->default_pinctrl_state; | |
340 | ||
33c1d77f KVA |
341 | if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) { |
342 | if (pinctrl_state->iodelay) | |
343 | late_recalibrate_iodelay(pinctrl_state->padconf, | |
344 | pinctrl_state->npads, | |
345 | pinctrl_state->iodelay, | |
346 | pinctrl_state->niodelays); | |
347 | else | |
348 | do_set_mux32((*ctrl)->control_padconf_core_base, | |
349 | pinctrl_state->padconf, | |
350 | pinctrl_state->npads); | |
351 | } | |
352 | } | |
353 | #endif | |
8fc238bf JJH |
354 | static void omap_hsmmc_set_timing(struct mmc *mmc) |
355 | { | |
356 | u32 val; | |
357 | struct hsmmc *mmc_base; | |
358 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
359 | ||
360 | mmc_base = priv->base_addr; | |
361 | ||
33c1d77f | 362 | omap_hsmmc_stop_clock(mmc_base); |
8fc238bf JJH |
363 | val = readl(&mmc_base->ac12); |
364 | val &= ~AC12_UHSMC_MASK; | |
365 | priv->mode = mmc->selected_mode; | |
366 | ||
9b3fc218 KVA |
367 | if (mmc_is_mode_ddr(priv->mode)) |
368 | writel(readl(&mmc_base->con) | DDR, &mmc_base->con); | |
369 | else | |
370 | writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con); | |
371 | ||
8fc238bf JJH |
372 | switch (priv->mode) { |
373 | case MMC_HS_200: | |
374 | case UHS_SDR104: | |
375 | val |= AC12_UHSMC_SDR104; | |
376 | break; | |
377 | case UHS_SDR50: | |
378 | val |= AC12_UHSMC_SDR50; | |
379 | break; | |
380 | case MMC_DDR_52: | |
381 | case UHS_DDR50: | |
382 | val |= AC12_UHSMC_DDR50; | |
383 | break; | |
384 | case SD_HS: | |
385 | case MMC_HS_52: | |
386 | case UHS_SDR25: | |
387 | val |= AC12_UHSMC_SDR25; | |
388 | break; | |
389 | case MMC_LEGACY: | |
390 | case MMC_HS: | |
391 | case SD_LEGACY: | |
392 | case UHS_SDR12: | |
393 | val |= AC12_UHSMC_SDR12; | |
394 | break; | |
395 | default: | |
396 | val |= AC12_UHSMC_RES; | |
397 | break; | |
398 | } | |
399 | writel(val, &mmc_base->ac12); | |
33c1d77f KVA |
400 | |
401 | #ifdef CONFIG_IODELAY_RECALIBRATION | |
402 | omap_hsmmc_io_recalibrate(mmc); | |
403 | #endif | |
404 | omap_hsmmc_start_clock(mmc_base); | |
8fc238bf JJH |
405 | } |
406 | ||
04f9f8be | 407 | static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage) |
b5944817 KVA |
408 | { |
409 | struct hsmmc *mmc_base; | |
410 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
04f9f8be | 411 | u32 hctl, ac12; |
b5944817 KVA |
412 | |
413 | mmc_base = priv->base_addr; | |
414 | ||
04f9f8be JJH |
415 | hctl = readl(&mmc_base->hctl) & ~SDVS_MASK; |
416 | ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN; | |
b5944817 | 417 | |
04f9f8be JJH |
418 | switch (signal_voltage) { |
419 | case MMC_SIGNAL_VOLTAGE_330: | |
420 | hctl |= SDVS_3V0; | |
b5944817 | 421 | break; |
04f9f8be JJH |
422 | case MMC_SIGNAL_VOLTAGE_180: |
423 | hctl |= SDVS_1V8; | |
424 | ac12 |= AC12_V1V8_SIGEN; | |
b5944817 KVA |
425 | break; |
426 | } | |
427 | ||
04f9f8be JJH |
428 | writel(hctl, &mmc_base->hctl); |
429 | writel(ac12, &mmc_base->ac12); | |
b5944817 KVA |
430 | } |
431 | ||
04f9f8be JJH |
432 | #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) |
433 | static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout) | |
434 | { | |
435 | int ret = -ETIMEDOUT; | |
436 | u32 con; | |
437 | bool dat0_high; | |
438 | bool target_dat0_high = !!state; | |
439 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
440 | struct hsmmc *mmc_base = priv->base_addr; | |
441 | ||
442 | con = readl(&mmc_base->con); | |
443 | writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con); | |
444 | ||
445 | timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */ | |
446 | while (timeout--) { | |
447 | dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0); | |
448 | if (dat0_high == target_dat0_high) { | |
449 | ret = 0; | |
450 | break; | |
451 | } | |
452 | udelay(10); | |
453 | } | |
454 | writel(con, &mmc_base->con); | |
455 | ||
456 | return ret; | |
457 | } | |
458 | #endif | |
459 | ||
460 | #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) | |
461 | #if CONFIG_IS_ENABLED(DM_REGULATOR) | |
462 | static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV) | |
463 | { | |
464 | int ret = 0; | |
465 | int uV = mV * 1000; | |
466 | ||
467 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
468 | ||
469 | if (!mmc->vqmmc_supply) | |
470 | return 0; | |
471 | ||
472 | /* Disable PBIAS */ | |
473 | ret = regulator_set_enable(priv->pbias_supply, false); | |
474 | if (ret && ret != -ENOSYS) | |
475 | return ret; | |
476 | ||
477 | /* Turn off IO voltage */ | |
478 | ret = regulator_set_enable(mmc->vqmmc_supply, false); | |
479 | if (ret && ret != -ENOSYS) | |
480 | return ret; | |
481 | /* Program a new IO voltage value */ | |
482 | ret = regulator_set_value(mmc->vqmmc_supply, uV); | |
483 | if (ret) | |
484 | return ret; | |
485 | /* Turn on IO voltage */ | |
486 | ret = regulator_set_enable(mmc->vqmmc_supply, true); | |
487 | if (ret && ret != -ENOSYS) | |
488 | return ret; | |
489 | ||
490 | /* Program PBIAS voltage*/ | |
491 | ret = regulator_set_value(priv->pbias_supply, uV); | |
492 | if (ret && ret != -ENOSYS) | |
493 | return ret; | |
494 | /* Enable PBIAS */ | |
495 | ret = regulator_set_enable(priv->pbias_supply, true); | |
496 | if (ret && ret != -ENOSYS) | |
497 | return ret; | |
498 | ||
499 | return 0; | |
500 | } | |
501 | #endif | |
502 | ||
503 | static int omap_hsmmc_set_signal_voltage(struct mmc *mmc) | |
504 | { | |
505 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
506 | struct hsmmc *mmc_base = priv->base_addr; | |
507 | int mv = mmc_voltage_to_mv(mmc->signal_voltage); | |
508 | u32 capa_mask; | |
509 | __maybe_unused u8 palmas_ldo_volt; | |
510 | u32 val; | |
511 | ||
512 | if (mv < 0) | |
513 | return -EINVAL; | |
514 | ||
515 | if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { | |
516 | /* Use 3.0V rather than 3.3V */ | |
517 | mv = 3000; | |
518 | capa_mask = VS30_3V0SUP; | |
519 | palmas_ldo_volt = LDO_VOLT_3V0; | |
520 | } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { | |
521 | capa_mask = VS18_1V8SUP; | |
522 | palmas_ldo_volt = LDO_VOLT_1V8; | |
523 | } else { | |
524 | return -EOPNOTSUPP; | |
525 | } | |
526 | ||
527 | val = readl(&mmc_base->capa); | |
528 | if (!(val & capa_mask)) | |
529 | return -EOPNOTSUPP; | |
530 | ||
531 | priv->signal_voltage = mmc->signal_voltage; | |
532 | ||
533 | omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage); | |
534 | ||
535 | #if CONFIG_IS_ENABLED(DM_REGULATOR) | |
536 | return omap_hsmmc_set_io_regulator(mmc, mv); | |
537 | #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \ | |
538 | defined(CONFIG_PALMAS_POWER) | |
539 | if (mmc_get_blk_desc(mmc)->devnum == 0) | |
540 | vmmc_pbias_config(palmas_ldo_volt); | |
541 | return 0; | |
542 | #else | |
543 | return 0; | |
544 | #endif | |
545 | } | |
546 | #endif | |
547 | ||
548 | static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc) | |
b5944817 KVA |
549 | { |
550 | struct hsmmc *mmc_base; | |
551 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
552 | u32 val; | |
553 | ||
554 | mmc_base = priv->base_addr; | |
555 | val = readl(&mmc_base->capa); | |
556 | ||
557 | if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { | |
558 | val |= (VS30_3V0SUP | VS18_1V8SUP); | |
b5944817 KVA |
559 | } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) { |
560 | val |= VS30_3V0SUP; | |
561 | val &= ~VS18_1V8SUP; | |
b5944817 KVA |
562 | } else { |
563 | val |= VS18_1V8SUP; | |
564 | val &= ~VS30_3V0SUP; | |
b5944817 KVA |
565 | } |
566 | ||
567 | writel(val, &mmc_base->capa); | |
04f9f8be JJH |
568 | |
569 | return val; | |
b5944817 | 570 | } |
14761cae JJH |
571 | |
572 | #ifdef MMC_SUPPORTS_TUNING | |
573 | static void omap_hsmmc_disable_tuning(struct mmc *mmc) | |
574 | { | |
575 | struct hsmmc *mmc_base; | |
576 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
577 | u32 val; | |
578 | ||
579 | mmc_base = priv->base_addr; | |
580 | val = readl(&mmc_base->ac12); | |
581 | val &= ~(AC12_SCLK_SEL); | |
582 | writel(val, &mmc_base->ac12); | |
583 | ||
584 | val = readl(&mmc_base->dll); | |
585 | val &= ~(DLL_FORCE_VALUE | DLL_SWT); | |
586 | writel(val, &mmc_base->dll); | |
587 | } | |
588 | ||
589 | static void omap_hsmmc_set_dll(struct mmc *mmc, int count) | |
590 | { | |
591 | int i; | |
592 | struct hsmmc *mmc_base; | |
593 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
594 | u32 val; | |
595 | ||
596 | mmc_base = priv->base_addr; | |
597 | val = readl(&mmc_base->dll); | |
598 | val |= DLL_FORCE_VALUE; | |
599 | val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT); | |
600 | val |= (count << DLL_FORCE_SR_C_SHIFT); | |
601 | writel(val, &mmc_base->dll); | |
602 | ||
603 | val |= DLL_CALIB; | |
604 | writel(val, &mmc_base->dll); | |
605 | for (i = 0; i < 1000; i++) { | |
606 | if (readl(&mmc_base->dll) & DLL_CALIB) | |
607 | break; | |
608 | } | |
609 | val &= ~DLL_CALIB; | |
610 | writel(val, &mmc_base->dll); | |
611 | } | |
612 | ||
613 | static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) | |
614 | { | |
615 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
616 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); | |
617 | struct mmc *mmc = upriv->mmc; | |
618 | struct hsmmc *mmc_base; | |
619 | u32 val; | |
620 | u8 cur_match, prev_match = 0; | |
621 | int ret; | |
622 | u32 phase_delay = 0; | |
623 | u32 start_window = 0, max_window = 0; | |
624 | u32 length = 0, max_len = 0; | |
625 | ||
626 | mmc_base = priv->base_addr; | |
627 | val = readl(&mmc_base->capa2); | |
628 | ||
629 | /* clock tuning is not needed for upto 52MHz */ | |
630 | if (!((mmc->selected_mode == MMC_HS_200) || | |
631 | (mmc->selected_mode == UHS_SDR104) || | |
632 | ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50)))) | |
633 | return 0; | |
634 | ||
635 | val = readl(&mmc_base->dll); | |
636 | val |= DLL_SWT; | |
637 | writel(val, &mmc_base->dll); | |
638 | while (phase_delay <= MAX_PHASE_DELAY) { | |
639 | omap_hsmmc_set_dll(mmc, phase_delay); | |
640 | ||
641 | cur_match = !mmc_send_tuning(mmc, opcode, NULL); | |
642 | ||
643 | if (cur_match) { | |
644 | if (prev_match) { | |
645 | length++; | |
646 | } else { | |
647 | start_window = phase_delay; | |
648 | length = 1; | |
649 | } | |
650 | } | |
651 | ||
652 | if (length > max_len) { | |
653 | max_window = start_window; | |
654 | max_len = length; | |
655 | } | |
656 | ||
657 | prev_match = cur_match; | |
658 | phase_delay += 4; | |
659 | } | |
660 | ||
661 | if (!max_len) { | |
662 | ret = -EIO; | |
663 | goto tuning_error; | |
664 | } | |
665 | ||
666 | val = readl(&mmc_base->ac12); | |
667 | if (!(val & AC12_SCLK_SEL)) { | |
668 | ret = -EIO; | |
669 | goto tuning_error; | |
670 | } | |
671 | ||
672 | phase_delay = max_window + 4 * ((3 * max_len) >> 2); | |
673 | omap_hsmmc_set_dll(mmc, phase_delay); | |
674 | ||
675 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
676 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); | |
677 | ||
678 | return 0; | |
679 | ||
680 | tuning_error: | |
681 | ||
682 | omap_hsmmc_disable_tuning(mmc); | |
683 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
684 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); | |
685 | ||
686 | return ret; | |
687 | } | |
688 | #endif | |
42182c9b JJH |
689 | |
690 | static void omap_hsmmc_send_init_stream(struct udevice *dev) | |
691 | { | |
692 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
693 | struct hsmmc *mmc_base = priv->base_addr; | |
694 | ||
695 | mmc_init_stream(mmc_base); | |
696 | } | |
b5944817 KVA |
697 | #endif |
698 | ||
2faa1a30 JJH |
699 | static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd) |
700 | { | |
701 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
702 | struct hsmmc *mmc_base = priv->base_addr; | |
703 | u32 irq_mask = INT_EN_MASK; | |
704 | ||
705 | /* | |
706 | * TODO: Errata i802 indicates only DCRC interrupts can occur during | |
707 | * tuning procedure and DCRC should be disabled. But see occurences | |
708 | * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These | |
709 | * interrupts occur along with BRR, so the data is actually in the | |
710 | * buffer. It has to be debugged why these interrutps occur | |
711 | */ | |
712 | if (cmd && mmc_is_tuning_cmd(cmd->cmdidx)) | |
713 | irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC); | |
714 | ||
715 | writel(irq_mask, &mmc_base->ie); | |
716 | } | |
717 | ||
ab769f22 | 718 | static int omap_hsmmc_init_setup(struct mmc *mmc) |
de941241 | 719 | { |
ae000e23 | 720 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
cc22b0c0 | 721 | struct hsmmc *mmc_base; |
de941241 SG |
722 | unsigned int reg_val; |
723 | unsigned int dsor; | |
eb9a28f6 | 724 | ulong start; |
de941241 | 725 | |
ae000e23 | 726 | mmc_base = priv->base_addr; |
14fa2dd0 | 727 | mmc_board_init(mmc); |
de941241 SG |
728 | |
729 | writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, | |
730 | &mmc_base->sysconfig); | |
eb9a28f6 NM |
731 | start = get_timer(0); |
732 | while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { | |
733 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
734 | printf("%s: timedout waiting for cc2!\n", __func__); | |
915ffa52 | 735 | return -ETIMEDOUT; |
eb9a28f6 NM |
736 | } |
737 | } | |
de941241 | 738 | writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); |
eb9a28f6 NM |
739 | start = get_timer(0); |
740 | while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { | |
741 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
742 | printf("%s: timedout waiting for softresetall!\n", | |
743 | __func__); | |
915ffa52 | 744 | return -ETIMEDOUT; |
eb9a28f6 NM |
745 | } |
746 | } | |
27a4b3bc | 747 | #ifdef CONFIG_MMC_OMAP_HS_ADMA |
f0d53e88 KVA |
748 | reg_val = readl(&mmc_base->hl_hwinfo); |
749 | if (reg_val & MADMA_EN) | |
750 | priv->controller_flags |= OMAP_HSMMC_USE_ADMA; | |
751 | #endif | |
b5944817 KVA |
752 | |
753 | #if CONFIG_IS_ENABLED(DM_MMC) | |
04f9f8be JJH |
754 | reg_val = omap_hsmmc_set_capabilities(mmc); |
755 | omap_hsmmc_conf_bus_power(mmc, (reg_val & VS30_3V0SUP) ? | |
756 | MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180); | |
b5944817 | 757 | #else |
de941241 SG |
758 | writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); |
759 | writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, | |
760 | &mmc_base->capa); | |
b5944817 | 761 | #endif |
de941241 SG |
762 | |
763 | reg_val = readl(&mmc_base->con) & RESERVED_MASK; | |
764 | ||
765 | writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | | |
766 | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | | |
767 | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); | |
768 | ||
769 | dsor = 240; | |
770 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
29171dcf | 771 | (ICE_STOP | DTO_15THDTO)); |
de941241 SG |
772 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, |
773 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
eb9a28f6 NM |
774 | start = get_timer(0); |
775 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
776 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
777 | printf("%s: timedout waiting for ics!\n", __func__); | |
915ffa52 | 778 | return -ETIMEDOUT; |
eb9a28f6 NM |
779 | } |
780 | } | |
de941241 SG |
781 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
782 | ||
783 | writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); | |
784 | ||
2faa1a30 | 785 | mmc_enable_irq(mmc, NULL); |
42182c9b JJH |
786 | |
787 | #if !CONFIG_IS_ENABLED(DM_MMC) | |
de941241 | 788 | mmc_init_stream(mmc_base); |
42182c9b | 789 | #endif |
de941241 SG |
790 | |
791 | return 0; | |
792 | } | |
793 | ||
25c719e2 GI |
794 | /* |
795 | * MMC controller internal finite state machine reset | |
796 | * | |
797 | * Used to reset command or data internal state machines, using respectively | |
798 | * SRC or SRD bit of SYSCTL register | |
799 | */ | |
800 | static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) | |
801 | { | |
802 | ulong start; | |
803 | ||
804 | mmc_reg_out(&mmc_base->sysctl, bit, bit); | |
805 | ||
61a6cc27 OT |
806 | /* |
807 | * CMD(DAT) lines reset procedures are slightly different | |
808 | * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). | |
809 | * According to OMAP3 TRM: | |
810 | * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it | |
811 | * returns to 0x0. | |
812 | * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset | |
813 | * procedure steps must be as follows: | |
814 | * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in | |
815 | * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). | |
816 | * 2. Poll the SRC(SRD) bit until it is set to 0x1. | |
817 | * 3. Wait until the SRC (SRD) bit returns to 0x0 | |
818 | * (reset procedure is completed). | |
819 | */ | |
820 | #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ | |
dce55b93 | 821 | defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) |
61a6cc27 OT |
822 | if (!(readl(&mmc_base->sysctl) & bit)) { |
823 | start = get_timer(0); | |
824 | while (!(readl(&mmc_base->sysctl) & bit)) { | |
a4efd737 | 825 | if (get_timer(0) - start > MMC_TIMEOUT_MS) |
61a6cc27 OT |
826 | return; |
827 | } | |
828 | } | |
829 | #endif | |
25c719e2 GI |
830 | start = get_timer(0); |
831 | while ((readl(&mmc_base->sysctl) & bit) != 0) { | |
832 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
833 | printf("%s: timedout waiting for sysctl %x to clear\n", | |
834 | __func__, bit); | |
835 | return; | |
836 | } | |
837 | } | |
838 | } | |
f0d53e88 | 839 | |
27a4b3bc | 840 | #ifdef CONFIG_MMC_OMAP_HS_ADMA |
f0d53e88 KVA |
841 | static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end) |
842 | { | |
843 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
844 | struct omap_hsmmc_adma_desc *desc; | |
845 | u8 attr; | |
846 | ||
847 | desc = &priv->adma_desc_table[priv->desc_slot]; | |
848 | ||
849 | attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA; | |
850 | if (!end) | |
851 | priv->desc_slot++; | |
852 | else | |
853 | attr |= ADMA_DESC_ATTR_END; | |
854 | ||
855 | desc->len = len; | |
856 | desc->addr = (u32)buf; | |
857 | desc->reserved = 0; | |
858 | desc->attr = attr; | |
859 | } | |
860 | ||
861 | static void omap_hsmmc_prepare_adma_table(struct mmc *mmc, | |
862 | struct mmc_data *data) | |
863 | { | |
864 | uint total_len = data->blocksize * data->blocks; | |
865 | uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN); | |
866 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
867 | int i = desc_count; | |
868 | char *buf; | |
869 | ||
870 | priv->desc_slot = 0; | |
871 | priv->adma_desc_table = (struct omap_hsmmc_adma_desc *) | |
872 | memalign(ARCH_DMA_MINALIGN, desc_count * | |
873 | sizeof(struct omap_hsmmc_adma_desc)); | |
874 | ||
875 | if (data->flags & MMC_DATA_READ) | |
876 | buf = data->dest; | |
877 | else | |
878 | buf = (char *)data->src; | |
879 | ||
880 | while (--i) { | |
881 | omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false); | |
882 | buf += ADMA_MAX_LEN; | |
883 | total_len -= ADMA_MAX_LEN; | |
884 | } | |
885 | ||
886 | omap_hsmmc_adma_desc(mmc, buf, total_len, true); | |
887 | ||
888 | flush_dcache_range((long)priv->adma_desc_table, | |
889 | (long)priv->adma_desc_table + | |
890 | ROUND(desc_count * | |
891 | sizeof(struct omap_hsmmc_adma_desc), | |
892 | ARCH_DMA_MINALIGN)); | |
893 | } | |
894 | ||
895 | static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data) | |
896 | { | |
897 | struct hsmmc *mmc_base; | |
898 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
899 | u32 val; | |
900 | char *buf; | |
901 | ||
902 | mmc_base = priv->base_addr; | |
903 | omap_hsmmc_prepare_adma_table(mmc, data); | |
904 | ||
905 | if (data->flags & MMC_DATA_READ) | |
906 | buf = data->dest; | |
907 | else | |
908 | buf = (char *)data->src; | |
909 | ||
910 | val = readl(&mmc_base->hctl); | |
911 | val |= DMA_SELECT; | |
912 | writel(val, &mmc_base->hctl); | |
913 | ||
914 | val = readl(&mmc_base->con); | |
915 | val |= DMA_MASTER; | |
916 | writel(val, &mmc_base->con); | |
917 | ||
918 | writel((u32)priv->adma_desc_table, &mmc_base->admasal); | |
919 | ||
920 | flush_dcache_range((u32)buf, | |
921 | (u32)buf + | |
922 | ROUND(data->blocksize * data->blocks, | |
923 | ARCH_DMA_MINALIGN)); | |
924 | } | |
925 | ||
926 | static void omap_hsmmc_dma_cleanup(struct mmc *mmc) | |
927 | { | |
928 | struct hsmmc *mmc_base; | |
929 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
930 | u32 val; | |
931 | ||
932 | mmc_base = priv->base_addr; | |
933 | ||
934 | val = readl(&mmc_base->con); | |
935 | val &= ~DMA_MASTER; | |
936 | writel(val, &mmc_base->con); | |
937 | ||
938 | val = readl(&mmc_base->hctl); | |
939 | val &= ~DMA_SELECT; | |
940 | writel(val, &mmc_base->hctl); | |
941 | ||
942 | kfree(priv->adma_desc_table); | |
943 | } | |
944 | #else | |
945 | #define omap_hsmmc_adma_desc | |
946 | #define omap_hsmmc_prepare_adma_table | |
947 | #define omap_hsmmc_prepare_data | |
948 | #define omap_hsmmc_dma_cleanup | |
949 | #endif | |
950 | ||
c4d660d4 | 951 | #if !CONFIG_IS_ENABLED(DM_MMC) |
ab769f22 | 952 | static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
de941241 SG |
953 | struct mmc_data *data) |
954 | { | |
ae000e23 | 955 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
b5511d6c JJH |
956 | #else |
957 | static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, | |
958 | struct mmc_data *data) | |
959 | { | |
960 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
f0d53e88 KVA |
961 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
962 | struct mmc *mmc = upriv->mmc; | |
b5511d6c | 963 | #endif |
cc22b0c0 | 964 | struct hsmmc *mmc_base; |
de941241 | 965 | unsigned int flags, mmc_stat; |
eb9a28f6 | 966 | ulong start; |
04f9f8be | 967 | priv->last_cmd = cmd->cmdidx; |
de941241 | 968 | |
ae000e23 | 969 | mmc_base = priv->base_addr; |
866bb984 KVA |
970 | |
971 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) | |
972 | return 0; | |
973 | ||
eb9a28f6 | 974 | start = get_timer(0); |
a7778f8f | 975 | while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { |
eb9a28f6 | 976 | if (get_timer(0) - start > MAX_RETRY_MS) { |
a7778f8f TR |
977 | printf("%s: timedout waiting on cmd inhibit to clear\n", |
978 | __func__); | |
915ffa52 | 979 | return -ETIMEDOUT; |
eb9a28f6 NM |
980 | } |
981 | } | |
de941241 | 982 | writel(0xFFFFFFFF, &mmc_base->stat); |
eb9a28f6 NM |
983 | start = get_timer(0); |
984 | while (readl(&mmc_base->stat)) { | |
985 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
15ceb1de GI |
986 | printf("%s: timedout waiting for STAT (%x) to clear\n", |
987 | __func__, readl(&mmc_base->stat)); | |
915ffa52 | 988 | return -ETIMEDOUT; |
eb9a28f6 NM |
989 | } |
990 | } | |
de941241 SG |
991 | /* |
992 | * CMDREG | |
993 | * CMDIDX[13:8] : Command index | |
994 | * DATAPRNT[5] : Data Present Select | |
995 | * ENCMDIDX[4] : Command Index Check Enable | |
996 | * ENCMDCRC[3] : Command CRC Check Enable | |
997 | * RSPTYP[1:0] | |
998 | * 00 = No Response | |
999 | * 01 = Length 136 | |
1000 | * 10 = Length 48 | |
1001 | * 11 = Length 48 Check busy after response | |
1002 | */ | |
1003 | /* Delay added before checking the status of frq change | |
1004 | * retry not supported by mmc.c(core file) | |
1005 | */ | |
1006 | if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) | |
1007 | udelay(50000); /* wait 50 ms */ | |
1008 | ||
1009 | if (!(cmd->resp_type & MMC_RSP_PRESENT)) | |
1010 | flags = 0; | |
1011 | else if (cmd->resp_type & MMC_RSP_136) | |
1012 | flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; | |
1013 | else if (cmd->resp_type & MMC_RSP_BUSY) | |
1014 | flags = RSP_TYPE_LGHT48B; | |
1015 | else | |
1016 | flags = RSP_TYPE_LGHT48; | |
1017 | ||
1018 | /* enable default flags */ | |
1019 | flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | | |
29171dcf KVA |
1020 | MSBS_SGLEBLK); |
1021 | flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE); | |
de941241 SG |
1022 | |
1023 | if (cmd->resp_type & MMC_RSP_CRC) | |
1024 | flags |= CCCE_CHECK; | |
1025 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
1026 | flags |= CICE_CHECK; | |
1027 | ||
1028 | if (data) { | |
1029 | if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || | |
1030 | (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { | |
866bb984 | 1031 | flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE); |
de941241 SG |
1032 | data->blocksize = 512; |
1033 | writel(data->blocksize | (data->blocks << 16), | |
1034 | &mmc_base->blk); | |
1035 | } else | |
1036 | writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); | |
1037 | ||
1038 | if (data->flags & MMC_DATA_READ) | |
1039 | flags |= (DP_DATA | DDIR_READ); | |
1040 | else | |
1041 | flags |= (DP_DATA | DDIR_WRITE); | |
f0d53e88 | 1042 | |
27a4b3bc | 1043 | #ifdef CONFIG_MMC_OMAP_HS_ADMA |
f0d53e88 KVA |
1044 | if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && |
1045 | !mmc_is_tuning_cmd(cmd->cmdidx)) { | |
1046 | omap_hsmmc_prepare_data(mmc, data); | |
1047 | flags |= DE_ENABLE; | |
1048 | } | |
1049 | #endif | |
de941241 SG |
1050 | } |
1051 | ||
2faa1a30 JJH |
1052 | mmc_enable_irq(mmc, cmd); |
1053 | ||
de941241 | 1054 | writel(cmd->cmdarg, &mmc_base->arg); |
152ba363 | 1055 | udelay(20); /* To fix "No status update" error on eMMC */ |
de941241 SG |
1056 | writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); |
1057 | ||
eb9a28f6 | 1058 | start = get_timer(0); |
de941241 SG |
1059 | do { |
1060 | mmc_stat = readl(&mmc_base->stat); | |
f0d53e88 | 1061 | if (get_timer(start) > MAX_RETRY_MS) { |
eb9a28f6 | 1062 | printf("%s : timeout: No status update\n", __func__); |
915ffa52 | 1063 | return -ETIMEDOUT; |
eb9a28f6 NM |
1064 | } |
1065 | } while (!mmc_stat); | |
de941241 | 1066 | |
25c719e2 GI |
1067 | if ((mmc_stat & IE_CTO) != 0) { |
1068 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); | |
915ffa52 | 1069 | return -ETIMEDOUT; |
25c719e2 | 1070 | } else if ((mmc_stat & ERRI_MASK) != 0) |
de941241 SG |
1071 | return -1; |
1072 | ||
1073 | if (mmc_stat & CC_MASK) { | |
1074 | writel(CC_MASK, &mmc_base->stat); | |
1075 | if (cmd->resp_type & MMC_RSP_PRESENT) { | |
1076 | if (cmd->resp_type & MMC_RSP_136) { | |
1077 | /* response type 2 */ | |
1078 | cmd->response[3] = readl(&mmc_base->rsp10); | |
1079 | cmd->response[2] = readl(&mmc_base->rsp32); | |
1080 | cmd->response[1] = readl(&mmc_base->rsp54); | |
1081 | cmd->response[0] = readl(&mmc_base->rsp76); | |
1082 | } else | |
1083 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
1084 | cmd->response[0] = readl(&mmc_base->rsp10); | |
1085 | } | |
1086 | } | |
1087 | ||
27a4b3bc | 1088 | #ifdef CONFIG_MMC_OMAP_HS_ADMA |
f0d53e88 KVA |
1089 | if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data && |
1090 | !mmc_is_tuning_cmd(cmd->cmdidx)) { | |
1091 | u32 sz_mb, timeout; | |
1092 | ||
1093 | if (mmc_stat & IE_ADMAE) { | |
1094 | omap_hsmmc_dma_cleanup(mmc); | |
1095 | return -EIO; | |
1096 | } | |
1097 | ||
1098 | sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20); | |
1099 | timeout = sz_mb * DMA_TIMEOUT_PER_MB; | |
1100 | if (timeout < MAX_RETRY_MS) | |
1101 | timeout = MAX_RETRY_MS; | |
1102 | ||
1103 | start = get_timer(0); | |
1104 | do { | |
1105 | mmc_stat = readl(&mmc_base->stat); | |
1106 | if (mmc_stat & TC_MASK) { | |
1107 | writel(readl(&mmc_base->stat) | TC_MASK, | |
1108 | &mmc_base->stat); | |
1109 | break; | |
1110 | } | |
1111 | if (get_timer(start) > timeout) { | |
1112 | printf("%s : DMA timeout: No status update\n", | |
1113 | __func__); | |
1114 | return -ETIMEDOUT; | |
1115 | } | |
1116 | } while (1); | |
1117 | ||
1118 | omap_hsmmc_dma_cleanup(mmc); | |
1119 | return 0; | |
1120 | } | |
1121 | #endif | |
1122 | ||
de941241 SG |
1123 | if (data && (data->flags & MMC_DATA_READ)) { |
1124 | mmc_read_data(mmc_base, data->dest, | |
1125 | data->blocksize * data->blocks); | |
1126 | } else if (data && (data->flags & MMC_DATA_WRITE)) { | |
1127 | mmc_write_data(mmc_base, data->src, | |
1128 | data->blocksize * data->blocks); | |
1129 | } | |
1130 | return 0; | |
1131 | } | |
1132 | ||
933efe64 | 1133 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) |
de941241 SG |
1134 | { |
1135 | unsigned int *output_buf = (unsigned int *)buf; | |
1136 | unsigned int mmc_stat; | |
1137 | unsigned int count; | |
1138 | ||
1139 | /* | |
1140 | * Start Polled Read | |
1141 | */ | |
1142 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
1143 | count /= 4; | |
1144 | ||
1145 | while (size) { | |
eb9a28f6 | 1146 | ulong start = get_timer(0); |
de941241 SG |
1147 | do { |
1148 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
1149 | if (get_timer(0) - start > MAX_RETRY_MS) { |
1150 | printf("%s: timedout waiting for status!\n", | |
1151 | __func__); | |
915ffa52 | 1152 | return -ETIMEDOUT; |
eb9a28f6 | 1153 | } |
de941241 SG |
1154 | } while (mmc_stat == 0); |
1155 | ||
25c719e2 GI |
1156 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
1157 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
1158 | ||
de941241 SG |
1159 | if ((mmc_stat & ERRI_MASK) != 0) |
1160 | return 1; | |
1161 | ||
1162 | if (mmc_stat & BRR_MASK) { | |
1163 | unsigned int k; | |
1164 | ||
1165 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
1166 | &mmc_base->stat); | |
1167 | for (k = 0; k < count; k++) { | |
1168 | *output_buf = readl(&mmc_base->data); | |
1169 | output_buf++; | |
1170 | } | |
1171 | size -= (count*4); | |
1172 | } | |
1173 | ||
1174 | if (mmc_stat & BWR_MASK) | |
1175 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
1176 | &mmc_base->stat); | |
1177 | ||
1178 | if (mmc_stat & TC_MASK) { | |
1179 | writel(readl(&mmc_base->stat) | TC_MASK, | |
1180 | &mmc_base->stat); | |
1181 | break; | |
1182 | } | |
1183 | } | |
1184 | return 0; | |
1185 | } | |
1186 | ||
c7d08d80 | 1187 | #if CONFIG_IS_ENABLED(MMC_WRITE) |
933efe64 | 1188 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, |
c7d08d80 | 1189 | unsigned int size) |
de941241 SG |
1190 | { |
1191 | unsigned int *input_buf = (unsigned int *)buf; | |
1192 | unsigned int mmc_stat; | |
1193 | unsigned int count; | |
1194 | ||
1195 | /* | |
152ba363 | 1196 | * Start Polled Write |
de941241 SG |
1197 | */ |
1198 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
1199 | count /= 4; | |
1200 | ||
1201 | while (size) { | |
eb9a28f6 | 1202 | ulong start = get_timer(0); |
de941241 SG |
1203 | do { |
1204 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
1205 | if (get_timer(0) - start > MAX_RETRY_MS) { |
1206 | printf("%s: timedout waiting for status!\n", | |
1207 | __func__); | |
915ffa52 | 1208 | return -ETIMEDOUT; |
eb9a28f6 | 1209 | } |
de941241 SG |
1210 | } while (mmc_stat == 0); |
1211 | ||
25c719e2 GI |
1212 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
1213 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
1214 | ||
de941241 SG |
1215 | if ((mmc_stat & ERRI_MASK) != 0) |
1216 | return 1; | |
1217 | ||
1218 | if (mmc_stat & BWR_MASK) { | |
1219 | unsigned int k; | |
1220 | ||
1221 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
1222 | &mmc_base->stat); | |
1223 | for (k = 0; k < count; k++) { | |
1224 | writel(*input_buf, &mmc_base->data); | |
1225 | input_buf++; | |
1226 | } | |
1227 | size -= (count*4); | |
1228 | } | |
1229 | ||
1230 | if (mmc_stat & BRR_MASK) | |
1231 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
1232 | &mmc_base->stat); | |
1233 | ||
1234 | if (mmc_stat & TC_MASK) { | |
1235 | writel(readl(&mmc_base->stat) | TC_MASK, | |
1236 | &mmc_base->stat); | |
1237 | break; | |
1238 | } | |
1239 | } | |
1240 | return 0; | |
1241 | } | |
c7d08d80 JJH |
1242 | #else |
1243 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, | |
1244 | unsigned int size) | |
1245 | { | |
1246 | return -ENOTSUPP; | |
1247 | } | |
1248 | #endif | |
5baf543e JJH |
1249 | static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base) |
1250 | { | |
1251 | writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl); | |
1252 | } | |
1253 | ||
1254 | static void omap_hsmmc_start_clock(struct hsmmc *mmc_base) | |
1255 | { | |
1256 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); | |
1257 | } | |
1258 | ||
1259 | static void omap_hsmmc_set_clock(struct mmc *mmc) | |
1260 | { | |
1261 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
1262 | struct hsmmc *mmc_base; | |
1263 | unsigned int dsor = 0; | |
1264 | ulong start; | |
1265 | ||
1266 | mmc_base = priv->base_addr; | |
1267 | omap_hsmmc_stop_clock(mmc_base); | |
1268 | ||
1269 | /* TODO: Is setting DTO required here? */ | |
1270 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK), | |
1271 | (ICE_STOP | DTO_15THDTO)); | |
1272 | ||
1273 | if (mmc->clock != 0) { | |
1274 | dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock); | |
1275 | if (dsor > CLKD_MAX) | |
1276 | dsor = CLKD_MAX; | |
1277 | } else { | |
1278 | dsor = CLKD_MAX; | |
1279 | } | |
1280 | ||
1281 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
1282 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
1283 | ||
1284 | start = get_timer(0); | |
1285 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
1286 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
1287 | printf("%s: timedout waiting for ics!\n", __func__); | |
1288 | return; | |
1289 | } | |
1290 | } | |
1291 | ||
3149c13a JJH |
1292 | priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor; |
1293 | mmc->clock = priv->clock; | |
5baf543e JJH |
1294 | omap_hsmmc_start_clock(mmc_base); |
1295 | } | |
1296 | ||
48a2f114 | 1297 | static void omap_hsmmc_set_bus_width(struct mmc *mmc) |
de941241 | 1298 | { |
ae000e23 | 1299 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
cc22b0c0 | 1300 | struct hsmmc *mmc_base; |
de941241 | 1301 | |
ae000e23 | 1302 | mmc_base = priv->base_addr; |
de941241 SG |
1303 | /* configue bus width */ |
1304 | switch (mmc->bus_width) { | |
1305 | case 8: | |
1306 | writel(readl(&mmc_base->con) | DTW_8_BITMODE, | |
1307 | &mmc_base->con); | |
1308 | break; | |
1309 | ||
1310 | case 4: | |
1311 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
1312 | &mmc_base->con); | |
1313 | writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, | |
1314 | &mmc_base->hctl); | |
1315 | break; | |
1316 | ||
1317 | case 1: | |
1318 | default: | |
1319 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
1320 | &mmc_base->con); | |
1321 | writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, | |
1322 | &mmc_base->hctl); | |
1323 | break; | |
1324 | } | |
1325 | ||
48a2f114 KVA |
1326 | priv->bus_width = mmc->bus_width; |
1327 | } | |
1328 | ||
1329 | #if !CONFIG_IS_ENABLED(DM_MMC) | |
1330 | static int omap_hsmmc_set_ios(struct mmc *mmc) | |
1331 | { | |
1332 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
1333 | #else | |
1334 | static int omap_hsmmc_set_ios(struct udevice *dev) | |
1335 | { | |
1336 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
1337 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); | |
1338 | struct mmc *mmc = upriv->mmc; | |
1339 | #endif | |
90321dce | 1340 | struct hsmmc *mmc_base = priv->base_addr; |
04f9f8be | 1341 | int ret = 0; |
48a2f114 KVA |
1342 | |
1343 | if (priv->bus_width != mmc->bus_width) | |
1344 | omap_hsmmc_set_bus_width(mmc); | |
1345 | ||
5baf543e JJH |
1346 | if (priv->clock != mmc->clock) |
1347 | omap_hsmmc_set_clock(mmc); | |
07b0b9c0 | 1348 | |
90321dce KVA |
1349 | if (mmc->clk_disable) |
1350 | omap_hsmmc_stop_clock(mmc_base); | |
1351 | else | |
1352 | omap_hsmmc_start_clock(mmc_base); | |
1353 | ||
8fc238bf JJH |
1354 | #if CONFIG_IS_ENABLED(DM_MMC) |
1355 | if (priv->mode != mmc->selected_mode) | |
1356 | omap_hsmmc_set_timing(mmc); | |
04f9f8be JJH |
1357 | |
1358 | #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) | |
1359 | if (priv->signal_voltage != mmc->signal_voltage) | |
1360 | ret = omap_hsmmc_set_signal_voltage(mmc); | |
8fc238bf | 1361 | #endif |
04f9f8be JJH |
1362 | #endif |
1363 | return ret; | |
de941241 SG |
1364 | } |
1365 | ||
ab769f22 | 1366 | #ifdef OMAP_HSMMC_USE_GPIO |
c4d660d4 | 1367 | #if CONFIG_IS_ENABLED(DM_MMC) |
b5511d6c | 1368 | static int omap_hsmmc_getcd(struct udevice *dev) |
a9d6a7e2 | 1369 | { |
307a2143 AF |
1370 | int value = -1; |
1371 | #if CONFIG_IS_ENABLED(DM_GPIO) | |
f4df405f | 1372 | struct omap_hsmmc_data *priv = dev_get_priv(dev); |
a9d6a7e2 | 1373 | value = dm_gpio_get_value(&priv->cd_gpio); |
307a2143 | 1374 | #endif |
a9d6a7e2 M |
1375 | /* if no CD return as 1 */ |
1376 | if (value < 0) | |
1377 | return 1; | |
1378 | ||
a9d6a7e2 M |
1379 | return value; |
1380 | } | |
1381 | ||
b5511d6c | 1382 | static int omap_hsmmc_getwp(struct udevice *dev) |
a9d6a7e2 | 1383 | { |
307a2143 AF |
1384 | int value = 0; |
1385 | #if CONFIG_IS_ENABLED(DM_GPIO) | |
b5511d6c | 1386 | struct omap_hsmmc_data *priv = dev_get_priv(dev); |
a9d6a7e2 | 1387 | value = dm_gpio_get_value(&priv->wp_gpio); |
307a2143 | 1388 | #endif |
a9d6a7e2 M |
1389 | /* if no WP return as 0 */ |
1390 | if (value < 0) | |
1391 | return 0; | |
1392 | return value; | |
1393 | } | |
1394 | #else | |
ab769f22 PA |
1395 | static int omap_hsmmc_getcd(struct mmc *mmc) |
1396 | { | |
ae000e23 | 1397 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
ab769f22 PA |
1398 | int cd_gpio; |
1399 | ||
1400 | /* if no CD return as 1 */ | |
ae000e23 | 1401 | cd_gpio = priv->cd_gpio; |
ab769f22 PA |
1402 | if (cd_gpio < 0) |
1403 | return 1; | |
1404 | ||
0b03a931 IG |
1405 | /* NOTE: assumes card detect signal is active-low */ |
1406 | return !gpio_get_value(cd_gpio); | |
ab769f22 PA |
1407 | } |
1408 | ||
1409 | static int omap_hsmmc_getwp(struct mmc *mmc) | |
1410 | { | |
ae000e23 | 1411 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
ab769f22 PA |
1412 | int wp_gpio; |
1413 | ||
1414 | /* if no WP return as 0 */ | |
ae000e23 | 1415 | wp_gpio = priv->wp_gpio; |
ab769f22 PA |
1416 | if (wp_gpio < 0) |
1417 | return 0; | |
1418 | ||
0b03a931 | 1419 | /* NOTE: assumes write protect signal is active-high */ |
ab769f22 PA |
1420 | return gpio_get_value(wp_gpio); |
1421 | } | |
1422 | #endif | |
a9d6a7e2 | 1423 | #endif |
ab769f22 | 1424 | |
c4d660d4 | 1425 | #if CONFIG_IS_ENABLED(DM_MMC) |
b5511d6c JJH |
1426 | static const struct dm_mmc_ops omap_hsmmc_ops = { |
1427 | .send_cmd = omap_hsmmc_send_cmd, | |
1428 | .set_ios = omap_hsmmc_set_ios, | |
1429 | #ifdef OMAP_HSMMC_USE_GPIO | |
1430 | .get_cd = omap_hsmmc_getcd, | |
1431 | .get_wp = omap_hsmmc_getwp, | |
1432 | #endif | |
14761cae JJH |
1433 | #ifdef MMC_SUPPORTS_TUNING |
1434 | .execute_tuning = omap_hsmmc_execute_tuning, | |
1435 | #endif | |
42182c9b | 1436 | .send_init_stream = omap_hsmmc_send_init_stream, |
04f9f8be JJH |
1437 | #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) |
1438 | .wait_dat0 = omap_hsmmc_wait_dat0, | |
1439 | #endif | |
b5511d6c JJH |
1440 | }; |
1441 | #else | |
ab769f22 PA |
1442 | static const struct mmc_ops omap_hsmmc_ops = { |
1443 | .send_cmd = omap_hsmmc_send_cmd, | |
1444 | .set_ios = omap_hsmmc_set_ios, | |
1445 | .init = omap_hsmmc_init_setup, | |
1446 | #ifdef OMAP_HSMMC_USE_GPIO | |
1447 | .getcd = omap_hsmmc_getcd, | |
1448 | .getwp = omap_hsmmc_getwp, | |
1449 | #endif | |
1450 | }; | |
b5511d6c | 1451 | #endif |
ab769f22 | 1452 | |
c4d660d4 | 1453 | #if !CONFIG_IS_ENABLED(DM_MMC) |
e3913f56 NK |
1454 | int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, |
1455 | int wp_gpio) | |
de941241 | 1456 | { |
93bfd616 | 1457 | struct mmc *mmc; |
ae000e23 | 1458 | struct omap_hsmmc_data *priv; |
93bfd616 PA |
1459 | struct mmc_config *cfg; |
1460 | uint host_caps_val; | |
1461 | ||
4a41fec5 | 1462 | priv = calloc(1, sizeof(*priv)); |
ae000e23 | 1463 | if (priv == NULL) |
93bfd616 | 1464 | return -1; |
de941241 | 1465 | |
5a20397b | 1466 | host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; |
de941241 SG |
1467 | |
1468 | switch (dev_index) { | |
1469 | case 0: | |
ae000e23 | 1470 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 | 1471 | break; |
1037d585 | 1472 | #ifdef OMAP_HSMMC2_BASE |
de941241 | 1473 | case 1: |
ae000e23 | 1474 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; |
152ba363 | 1475 | #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ |
3891a54f | 1476 | defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ |
3b68939f RQ |
1477 | defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ |
1478 | defined(CONFIG_HSMMC2_8BIT) | |
152ba363 LP |
1479 | /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ |
1480 | host_caps_val |= MMC_MODE_8BIT; | |
1481 | #endif | |
de941241 | 1482 | break; |
1037d585 TR |
1483 | #endif |
1484 | #ifdef OMAP_HSMMC3_BASE | |
de941241 | 1485 | case 2: |
ae000e23 | 1486 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; |
3891a54f | 1487 | #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) |
152ba363 LP |
1488 | /* Enable 8-bit interface for eMMC on DRA7XX */ |
1489 | host_caps_val |= MMC_MODE_8BIT; | |
1490 | #endif | |
de941241 | 1491 | break; |
1037d585 | 1492 | #endif |
de941241 | 1493 | default: |
ae000e23 | 1494 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 SG |
1495 | return 1; |
1496 | } | |
ab769f22 PA |
1497 | #ifdef OMAP_HSMMC_USE_GPIO |
1498 | /* on error gpio values are set to -1, which is what we want */ | |
ae000e23 JJH |
1499 | priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); |
1500 | priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); | |
ab769f22 | 1501 | #endif |
173ddc5b | 1502 | |
ae000e23 | 1503 | cfg = &priv->cfg; |
de941241 | 1504 | |
93bfd616 PA |
1505 | cfg->name = "OMAP SD/MMC"; |
1506 | cfg->ops = &omap_hsmmc_ops; | |
1507 | ||
1508 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
1509 | cfg->host_caps = host_caps_val & ~host_caps_mask; | |
1510 | ||
1511 | cfg->f_min = 400000; | |
bbbc1ae9 JS |
1512 | |
1513 | if (f_max != 0) | |
93bfd616 | 1514 | cfg->f_max = f_max; |
bbbc1ae9 | 1515 | else { |
93bfd616 PA |
1516 | if (cfg->host_caps & MMC_MODE_HS) { |
1517 | if (cfg->host_caps & MMC_MODE_HS_52MHz) | |
1518 | cfg->f_max = 52000000; | |
bbbc1ae9 | 1519 | else |
93bfd616 | 1520 | cfg->f_max = 26000000; |
bbbc1ae9 | 1521 | } else |
93bfd616 | 1522 | cfg->f_max = 20000000; |
bbbc1ae9 | 1523 | } |
de941241 | 1524 | |
93bfd616 | 1525 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
8feafcc4 | 1526 | |
4ca9244d JR |
1527 | #if defined(CONFIG_OMAP34XX) |
1528 | /* | |
1529 | * Silicon revs 2.1 and older do not support multiblock transfers. | |
1530 | */ | |
1531 | if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) | |
93bfd616 | 1532 | cfg->b_max = 1; |
4ca9244d | 1533 | #endif |
2d28eeda | 1534 | |
ae000e23 | 1535 | mmc = mmc_create(cfg, priv); |
93bfd616 PA |
1536 | if (mmc == NULL) |
1537 | return -1; | |
de941241 SG |
1538 | |
1539 | return 0; | |
1540 | } | |
a9d6a7e2 | 1541 | #else |
33c1d77f KVA |
1542 | |
1543 | #ifdef CONFIG_IODELAY_RECALIBRATION | |
1544 | static struct pad_conf_entry * | |
1545 | omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count) | |
1546 | { | |
1547 | int index = 0; | |
1548 | struct pad_conf_entry *padconf; | |
1549 | ||
1550 | padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count); | |
1551 | if (!padconf) { | |
1552 | debug("failed to allocate memory\n"); | |
1553 | return 0; | |
1554 | } | |
1555 | ||
1556 | while (index < count) { | |
1557 | padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]); | |
1558 | padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]); | |
1559 | index++; | |
1560 | } | |
1561 | ||
1562 | return padconf; | |
1563 | } | |
1564 | ||
1565 | static struct iodelay_cfg_entry * | |
1566 | omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count) | |
1567 | { | |
1568 | int index = 0; | |
1569 | struct iodelay_cfg_entry *iodelay; | |
1570 | ||
1571 | iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count); | |
1572 | if (!iodelay) { | |
1573 | debug("failed to allocate memory\n"); | |
1574 | return 0; | |
1575 | } | |
1576 | ||
1577 | while (index < count) { | |
1578 | iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]); | |
1579 | iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]); | |
1580 | iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]); | |
1581 | index++; | |
1582 | } | |
1583 | ||
1584 | return iodelay; | |
1585 | } | |
1586 | ||
1587 | static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle, | |
1588 | const char *name, int *len) | |
1589 | { | |
1590 | const void *fdt = gd->fdt_blob; | |
1591 | int offset; | |
1592 | const fdt32_t *pinctrl; | |
1593 | ||
1594 | offset = fdt_node_offset_by_phandle(fdt, phandle); | |
1595 | if (offset < 0) { | |
1596 | debug("failed to get pinctrl node %s.\n", | |
1597 | fdt_strerror(offset)); | |
1598 | return 0; | |
1599 | } | |
1600 | ||
1601 | pinctrl = fdt_getprop(fdt, offset, name, len); | |
1602 | if (!pinctrl) { | |
1603 | debug("failed to get property %s\n", name); | |
1604 | return 0; | |
1605 | } | |
1606 | ||
1607 | return pinctrl; | |
1608 | } | |
1609 | ||
1610 | static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc, | |
1611 | char *prop_name) | |
1612 | { | |
1613 | const void *fdt = gd->fdt_blob; | |
1614 | const __be32 *phandle; | |
1615 | int node = dev_of_offset(mmc->dev); | |
1616 | ||
1617 | phandle = fdt_getprop(fdt, node, prop_name, NULL); | |
1618 | if (!phandle) { | |
1619 | debug("failed to get property %s\n", prop_name); | |
1620 | return 0; | |
1621 | } | |
1622 | ||
1623 | return fdt32_to_cpu(*phandle); | |
1624 | } | |
1625 | ||
1626 | static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc, | |
1627 | char *prop_name) | |
1628 | { | |
1629 | const void *fdt = gd->fdt_blob; | |
1630 | const __be32 *phandle; | |
1631 | int len; | |
1632 | int count; | |
1633 | int node = dev_of_offset(mmc->dev); | |
1634 | ||
1635 | phandle = fdt_getprop(fdt, node, prop_name, &len); | |
1636 | if (!phandle) { | |
1637 | debug("failed to get property %s\n", prop_name); | |
1638 | return 0; | |
1639 | } | |
1640 | ||
1641 | /* No manual mode iodelay values if count < 2 */ | |
1642 | count = len / sizeof(*phandle); | |
1643 | if (count < 2) | |
1644 | return 0; | |
1645 | ||
1646 | return fdt32_to_cpu(*(phandle + 1)); | |
1647 | } | |
1648 | ||
1649 | static struct pad_conf_entry * | |
1650 | omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads) | |
1651 | { | |
1652 | int len; | |
1653 | int count; | |
1654 | struct pad_conf_entry *padconf; | |
1655 | u32 phandle; | |
1656 | const fdt32_t *pinctrl; | |
1657 | ||
1658 | phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name); | |
1659 | if (!phandle) | |
1660 | return ERR_PTR(-EINVAL); | |
1661 | ||
1662 | pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins", | |
1663 | &len); | |
1664 | if (!pinctrl) | |
1665 | return ERR_PTR(-EINVAL); | |
1666 | ||
1667 | count = (len / sizeof(*pinctrl)) / 2; | |
1668 | padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count); | |
1669 | if (!padconf) | |
1670 | return ERR_PTR(-EINVAL); | |
1671 | ||
1672 | *npads = count; | |
1673 | ||
1674 | return padconf; | |
1675 | } | |
1676 | ||
1677 | static struct iodelay_cfg_entry * | |
1678 | omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay) | |
1679 | { | |
1680 | int len; | |
1681 | int count; | |
1682 | struct iodelay_cfg_entry *iodelay; | |
1683 | u32 phandle; | |
1684 | const fdt32_t *pinctrl; | |
1685 | ||
1686 | phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name); | |
1687 | /* Not all modes have manual mode iodelay values. So its not fatal */ | |
1688 | if (!phandle) | |
1689 | return 0; | |
1690 | ||
1691 | pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array", | |
1692 | &len); | |
1693 | if (!pinctrl) | |
1694 | return ERR_PTR(-EINVAL); | |
1695 | ||
1696 | count = (len / sizeof(*pinctrl)) / 3; | |
1697 | iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count); | |
1698 | if (!iodelay) | |
1699 | return ERR_PTR(-EINVAL); | |
1700 | ||
1701 | *niodelay = count; | |
1702 | ||
1703 | return iodelay; | |
1704 | } | |
1705 | ||
1706 | static struct omap_hsmmc_pinctrl_state * | |
1707 | omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode) | |
1708 | { | |
1709 | int index; | |
1710 | int npads = 0; | |
1711 | int niodelays = 0; | |
1712 | const void *fdt = gd->fdt_blob; | |
1713 | int node = dev_of_offset(mmc->dev); | |
1714 | char prop_name[11]; | |
1715 | struct omap_hsmmc_pinctrl_state *pinctrl_state; | |
1716 | ||
1717 | pinctrl_state = (struct omap_hsmmc_pinctrl_state *) | |
1718 | malloc(sizeof(*pinctrl_state)); | |
1719 | if (!pinctrl_state) { | |
1720 | debug("failed to allocate memory\n"); | |
1721 | return 0; | |
1722 | } | |
1723 | ||
1724 | index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode); | |
1725 | if (index < 0) { | |
1726 | debug("fail to find %s mode %s\n", mode, fdt_strerror(index)); | |
1727 | goto err_pinctrl_state; | |
1728 | } | |
1729 | ||
1730 | sprintf(prop_name, "pinctrl-%d", index); | |
1731 | ||
1732 | pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name, | |
1733 | &npads); | |
1734 | if (IS_ERR(pinctrl_state->padconf)) | |
1735 | goto err_pinctrl_state; | |
1736 | pinctrl_state->npads = npads; | |
1737 | ||
1738 | pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name, | |
1739 | &niodelays); | |
1740 | if (IS_ERR(pinctrl_state->iodelay)) | |
1741 | goto err_padconf; | |
1742 | pinctrl_state->niodelays = niodelays; | |
1743 | ||
1744 | return pinctrl_state; | |
1745 | ||
1746 | err_padconf: | |
1747 | kfree(pinctrl_state->padconf); | |
1748 | ||
1749 | err_pinctrl_state: | |
1750 | kfree(pinctrl_state); | |
1751 | return 0; | |
1752 | } | |
1753 | ||
bcc6bd84 | 1754 | #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \ |
2d28eeda KVA |
1755 | do { \ |
1756 | struct omap_hsmmc_pinctrl_state *s = NULL; \ | |
1757 | char str[20]; \ | |
1758 | if (!(cfg->host_caps & capmask)) \ | |
1759 | break; \ | |
1760 | \ | |
1761 | if (priv->hw_rev) { \ | |
1762 | sprintf(str, "%s-%s", #mode, priv->hw_rev); \ | |
1763 | s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \ | |
1764 | } \ | |
1765 | \ | |
1766 | if (!s) \ | |
1767 | s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \ | |
1768 | \ | |
bcc6bd84 | 1769 | if (!s && !optional) { \ |
2d28eeda KVA |
1770 | debug("%s: no pinctrl for %s\n", \ |
1771 | mmc->dev->name, #mode); \ | |
1772 | cfg->host_caps &= ~(capmask); \ | |
1773 | } else { \ | |
1774 | priv->mode##_pinctrl_state = s; \ | |
1775 | } \ | |
33c1d77f KVA |
1776 | } while (0) |
1777 | ||
1778 | static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc) | |
1779 | { | |
1780 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); | |
1781 | struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); | |
1782 | struct omap_hsmmc_pinctrl_state *default_pinctrl; | |
1783 | ||
1784 | if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) | |
1785 | return 0; | |
1786 | ||
1787 | default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default"); | |
1788 | if (!default_pinctrl) { | |
1789 | printf("no pinctrl state for default mode\n"); | |
1790 | return -EINVAL; | |
1791 | } | |
1792 | ||
1793 | priv->default_pinctrl_state = default_pinctrl; | |
1794 | ||
bcc6bd84 JJH |
1795 | OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false); |
1796 | OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false); | |
1797 | OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false); | |
1798 | OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false); | |
1799 | OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false); | |
33c1d77f | 1800 | |
bcc6bd84 JJH |
1801 | OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false); |
1802 | OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false); | |
1803 | OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true); | |
33c1d77f KVA |
1804 | |
1805 | return 0; | |
1806 | } | |
1807 | #endif | |
1808 | ||
2558c049 | 1809 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
2d28eeda KVA |
1810 | #ifdef CONFIG_OMAP54XX |
1811 | __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) | |
1812 | { | |
1813 | return NULL; | |
1814 | } | |
1815 | #endif | |
1816 | ||
a9d6a7e2 M |
1817 | static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) |
1818 | { | |
3d673ffc | 1819 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); |
33c1d77f KVA |
1820 | struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev); |
1821 | ||
3d673ffc | 1822 | struct mmc_config *cfg = &plat->cfg; |
2d28eeda KVA |
1823 | #ifdef CONFIG_OMAP54XX |
1824 | const struct mmc_platform_fixups *fixups; | |
1825 | #endif | |
a9d6a7e2 | 1826 | const void *fdt = gd->fdt_blob; |
e160f7d4 | 1827 | int node = dev_of_offset(dev); |
2d7482cf | 1828 | int ret; |
a9d6a7e2 | 1829 | |
a821c4af SG |
1830 | plat->base_addr = map_physmem(devfdt_get_addr(dev), |
1831 | sizeof(struct hsmmc *), | |
741726ae | 1832 | MAP_NOCACHE); |
a9d6a7e2 | 1833 | |
2d7482cf KVA |
1834 | ret = mmc_of_parse(dev, cfg); |
1835 | if (ret < 0) | |
1836 | return ret; | |
a9d6a7e2 | 1837 | |
beac7d33 JJH |
1838 | if (!cfg->f_max) |
1839 | cfg->f_max = 52000000; | |
2d7482cf | 1840 | cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
a9d6a7e2 | 1841 | cfg->f_min = 400000; |
a9d6a7e2 M |
1842 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; |
1843 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; | |
b5944817 KVA |
1844 | if (fdtdec_get_bool(fdt, node, "ti,dual-volt")) |
1845 | plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; | |
1846 | if (fdtdec_get_bool(fdt, node, "no-1-8-v")) | |
1847 | plat->controller_flags |= OMAP_HSMMC_NO_1_8_V; | |
33c1d77f KVA |
1848 | if (of_data) |
1849 | plat->controller_flags |= of_data->controller_flags; | |
a9d6a7e2 | 1850 | |
2d28eeda KVA |
1851 | #ifdef CONFIG_OMAP54XX |
1852 | fixups = platform_fixups_mmc(devfdt_get_addr(dev)); | |
1853 | if (fixups) { | |
1854 | plat->hw_rev = fixups->hw_rev; | |
1855 | cfg->host_caps &= ~fixups->unsupported_caps; | |
1856 | cfg->f_max = fixups->max_freq; | |
1857 | } | |
1858 | #endif | |
1859 | ||
a9d6a7e2 M |
1860 | return 0; |
1861 | } | |
2558c049 | 1862 | #endif |
a9d6a7e2 | 1863 | |
17c9a1c1 JJH |
1864 | #ifdef CONFIG_BLK |
1865 | ||
1866 | static int omap_hsmmc_bind(struct udevice *dev) | |
1867 | { | |
1868 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); | |
45530e39 JJH |
1869 | plat->mmc = calloc(1, sizeof(struct mmc)); |
1870 | return mmc_bind(dev, plat->mmc, &plat->cfg); | |
17c9a1c1 JJH |
1871 | } |
1872 | #endif | |
a9d6a7e2 M |
1873 | static int omap_hsmmc_probe(struct udevice *dev) |
1874 | { | |
3d673ffc | 1875 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); |
a9d6a7e2 M |
1876 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
1877 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
3d673ffc | 1878 | struct mmc_config *cfg = &plat->cfg; |
a9d6a7e2 | 1879 | struct mmc *mmc; |
33c1d77f KVA |
1880 | #ifdef CONFIG_IODELAY_RECALIBRATION |
1881 | int ret; | |
1882 | #endif | |
a9d6a7e2 | 1883 | |
a9d6a7e2 | 1884 | cfg->name = "OMAP SD/MMC"; |
2558c049 | 1885 | priv->base_addr = plat->base_addr; |
33c1d77f | 1886 | priv->controller_flags = plat->controller_flags; |
2d28eeda | 1887 | priv->hw_rev = plat->hw_rev; |
a9d6a7e2 | 1888 | |
17c9a1c1 | 1889 | #ifdef CONFIG_BLK |
45530e39 | 1890 | mmc = plat->mmc; |
17c9a1c1 | 1891 | #else |
a9d6a7e2 M |
1892 | mmc = mmc_create(cfg, priv); |
1893 | if (mmc == NULL) | |
1894 | return -1; | |
17c9a1c1 | 1895 | #endif |
04f9f8be JJH |
1896 | #if CONFIG_IS_ENABLED(DM_REGULATOR) |
1897 | device_get_supply_regulator(dev, "pbias-supply", | |
1898 | &priv->pbias_supply); | |
1899 | #endif | |
307a2143 AF |
1900 | #if defined(OMAP_HSMMC_USE_GPIO) |
1901 | #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO) | |
5cc6a245 M |
1902 | gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); |
1903 | gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); | |
307a2143 | 1904 | #endif |
5cc6a245 M |
1905 | #endif |
1906 | ||
cffe5d86 | 1907 | mmc->dev = dev; |
a9d6a7e2 M |
1908 | upriv->mmc = mmc; |
1909 | ||
33c1d77f KVA |
1910 | #ifdef CONFIG_IODELAY_RECALIBRATION |
1911 | ret = omap_hsmmc_get_pinctrl_state(mmc); | |
1912 | /* | |
1913 | * disable high speed modes for the platforms that require IO delay | |
1914 | * and for which we don't have this information | |
1915 | */ | |
1916 | if ((ret < 0) && | |
1917 | (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) { | |
1918 | priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY; | |
1919 | cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) | | |
1920 | UHS_CAPS); | |
1921 | } | |
1922 | #endif | |
1923 | ||
b5511d6c | 1924 | return omap_hsmmc_init_setup(mmc); |
a9d6a7e2 M |
1925 | } |
1926 | ||
2558c049 | 1927 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
33c1d77f KVA |
1928 | |
1929 | static const struct omap_mmc_of_data dra7_mmc_of_data = { | |
1930 | .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY, | |
1931 | }; | |
1932 | ||
a9d6a7e2 | 1933 | static const struct udevice_id omap_hsmmc_ids[] = { |
741726ae JJH |
1934 | { .compatible = "ti,omap3-hsmmc" }, |
1935 | { .compatible = "ti,omap4-hsmmc" }, | |
1936 | { .compatible = "ti,am33xx-hsmmc" }, | |
33c1d77f | 1937 | { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data }, |
a9d6a7e2 M |
1938 | { } |
1939 | }; | |
2558c049 | 1940 | #endif |
a9d6a7e2 M |
1941 | |
1942 | U_BOOT_DRIVER(omap_hsmmc) = { | |
1943 | .name = "omap_hsmmc", | |
1944 | .id = UCLASS_MMC, | |
2558c049 | 1945 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
a9d6a7e2 M |
1946 | .of_match = omap_hsmmc_ids, |
1947 | .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata, | |
2558c049 LV |
1948 | .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat), |
1949 | #endif | |
17c9a1c1 JJH |
1950 | #ifdef CONFIG_BLK |
1951 | .bind = omap_hsmmc_bind, | |
1952 | #endif | |
b5511d6c | 1953 | .ops = &omap_hsmmc_ops, |
a9d6a7e2 M |
1954 | .probe = omap_hsmmc_probe, |
1955 | .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data), | |
cbcb1701 | 1956 | .flags = DM_FLAG_PRE_RELOC, |
a9d6a7e2 M |
1957 | }; |
1958 | #endif |