[people/ms/u-boot.git] / drivers / mmc / sdhci-cadence.c

/*
 * Copyright (C) 2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/sizes.h>
#include <libfdt.h>
#include <mmc.h>
#include <sdhci.h>

/* HRS - Host Register Set (specific to Cadence) */
#define SDHCI_CDNS_HRS04		0x10		/* PHY access port */
#define   SDHCI_CDNS_HRS04_ACK			BIT(26)
#define   SDHCI_CDNS_HRS04_RD			BIT(25)
#define   SDHCI_CDNS_HRS04_WR			BIT(24)
#define   SDHCI_CDNS_HRS04_RDATA_SHIFT		16
#define   SDHCI_CDNS_HRS04_WDATA_SHIFT		8
#define   SDHCI_CDNS_HRS04_ADDR_SHIFT		0

/* SRS - Slot Register Set (SDHCI-compatible) */
#define SDHCI_CDNS_SRS_BASE		0x200

/* PHY */
#define SDHCI_CDNS_PHY_DLY_SD_HS	0x00
#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT	0x01
#define SDHCI_CDNS_PHY_DLY_UHS_SDR12	0x02
#define SDHCI_CDNS_PHY_DLY_UHS_SDR25	0x03
#define SDHCI_CDNS_PHY_DLY_UHS_SDR50	0x04
#define SDHCI_CDNS_PHY_DLY_UHS_DDR50	0x05
#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY	0x06
#define SDHCI_CDNS_PHY_DLY_EMMC_SDR	0x07
#define SDHCI_CDNS_PHY_DLY_EMMC_DDR	0x08
#define SDHCI_CDNS_PHY_DLY_SDCLK	0x0b
#define SDHCI_CDNS_PHY_DLY_HSMMC	0x0c
#define SDHCI_CDNS_PHY_DLY_STROBE	0x0d

struct sdhci_cdns_plat {
	struct mmc_config cfg;
	struct mmc mmc;
	void __iomem *hrs_addr;
};

struct sdhci_cdns_phy_cfg {
	const char *property;
	u8 addr;
};

static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
	{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
	{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
	{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
	{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
	{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
	{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
	{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
	{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
	{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
	{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
	{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
};

static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
				    u8 addr, u8 data)
{
	void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
	u32 tmp;
	int ret;

	tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
	      (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
	writel(tmp, reg);

	tmp |= SDHCI_CDNS_HRS04_WR;
	writel(tmp, reg);

	ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
	if (ret)
		return ret;

	tmp &= ~SDHCI_CDNS_HRS04_WR;
	writel(tmp, reg);

	return 0;
}

static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
				const void *fdt, int nodeoffset)
{
	const u32 *prop;
	int ret, i;

	for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
		prop = fdt_getprop(fdt, nodeoffset,
				   sdhci_cdns_phy_cfgs[i].property, NULL);
		if (!prop)
			continue;

		ret = sdhci_cdns_write_phy_reg(plat,
					       sdhci_cdns_phy_cfgs[i].addr,
					       fdt32_to_cpu(*prop));
		if (ret)
			return ret;
	}

	return 0;
}

static int sdhci_cdns_bind(struct udevice *dev)
{
	struct sdhci_cdns_plat *plat = dev_get_platdata(dev);

	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}

static int sdhci_cdns_probe(struct udevice *dev)
{
	DECLARE_GLOBAL_DATA_PTR;
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
	struct sdhci_host *host = dev_get_priv(dev);
	fdt_addr_t base;
	int ret;

	base = devfdt_get_addr(dev);
	if (base == FDT_ADDR_T_NONE)
		return -EINVAL;

	plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
	if (!plat->hrs_addr)
		return -ENOMEM;

	host->name = dev->name;
	host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
	host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;

	ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
	if (ret)
		return ret;

	ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
	if (ret)
		return ret;

	upriv->mmc = &plat->mmc;
	host->mmc = &plat->mmc;
	host->mmc->priv = host;

	return sdhci_probe(dev);
}

static const struct udevice_id sdhci_cdns_match[] = {
	{ .compatible = "socionext,uniphier-sd4hc" },
	{ .compatible = "cdns,sd4hc" },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(sdhci_cdns) = {
	.name = "sdhci-cdns",
	.id = UCLASS_MMC,
	.of_match = sdhci_cdns_match,
	.bind = sdhci_cdns_bind,
	.probe = sdhci_cdns_probe,
	.priv_auto_alloc_size = sizeof(struct sdhci_host),
	.platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
	.ops = &sdhci_ops,
};
Commit	Line	Data
e5e7a7c2 MY	1	/*
	2	* Copyright (C) 2016 Socionext Inc.
	3	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
9d922450	9	#include <dm.h>
e5e7a7c2	10	#include <linux/io.h>
0cacd6b7	11	#include <linux/iopoll.h>
e5e7a7c2	12	#include <linux/sizes.h>
0cacd6b7	13	#include <libfdt.h>
e5e7a7c2 MY	14	#include <mmc.h>
	15	#include <sdhci.h>
	16
	17	/* HRS - Host Register Set (specific to Cadence) */
	18	#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
	19	#define SDHCI_CDNS_HRS04_ACK BIT(26)
	20	#define SDHCI_CDNS_HRS04_RD BIT(25)
	21	#define SDHCI_CDNS_HRS04_WR BIT(24)
0cacd6b7	22	#define SDHCI_CDNS_HRS04_RDATA_SHIFT 16
e5e7a7c2 MY	23	#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
	24	#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0
	25
	26	/* SRS - Slot Register Set (SDHCI-compatible) */
	27	#define SDHCI_CDNS_SRS_BASE 0x200
	28
	29	/* PHY */
	30	#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
	31	#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
	32	#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
	33	#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
	34	#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
	35	#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
	36	#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
	37	#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
	38	#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
0cacd6b7 MY	39	#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
	40	#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
	41	#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
e5e7a7c2 MY	42
	43	struct sdhci_cdns_plat {
	44	struct mmc_config cfg;
	45	struct mmc mmc;
	46	void __iomem *hrs_addr;
	47	};
	48
0cacd6b7 MY	49	struct sdhci_cdns_phy_cfg {
	50	const char *property;
	51	u8 addr;
	52	};
	53
	54	static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
	55	{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
	56	{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
	57	{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
	58	{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
	59	{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
	60	{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
	61	{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
	62	{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
	63	{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
	64	{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
	65	{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
	66	};
	67
	68	static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
	69	u8 addr, u8 data)
e5e7a7c2 MY	70	{
	71	void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
	72	u32 tmp;
0cacd6b7	73	int ret;
e5e7a7c2 MY	74
	75	tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) \|
	76	(addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
	77	writel(tmp, reg);
	78
	79	tmp \|= SDHCI_CDNS_HRS04_WR;
	80	writel(tmp, reg);
	81
0cacd6b7 MY	82	ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
	83	if (ret)
	84	return ret;
	85
e5e7a7c2 MY	86	tmp &= ~SDHCI_CDNS_HRS04_WR;
e5e7a7c2 MY	87	writel(tmp, reg);
0cacd6b7 MY	88
0cacd6b7 MY	89	return 0;
e5e7a7c2 MY	90	}
e5e7a7c2 MY	91
0cacd6b7 MY	92	static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
0cacd6b7 MY	93	const void *fdt, int nodeoffset)
e5e7a7c2	94	{
0cacd6b7 MY	95	const u32 *prop;
	96	int ret, i;
	97
	98	for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
	99	prop = fdt_getprop(fdt, nodeoffset,
	100	sdhci_cdns_phy_cfgs[i].property, NULL);
	101	if (!prop)
	102	continue;
	103
	104	ret = sdhci_cdns_write_phy_reg(plat,
	105	sdhci_cdns_phy_cfgs[i].addr,
	106	fdt32_to_cpu(*prop));
	107	if (ret)
	108	return ret;
	109	}
	110
	111	return 0;
e5e7a7c2 MY	112	}
	113
	114	static int sdhci_cdns_bind(struct udevice *dev)
	115	{
	116	struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
	117
	118	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
	119	}
	120
	121	static int sdhci_cdns_probe(struct udevice *dev)
	122	{
0cacd6b7	123	DECLARE_GLOBAL_DATA_PTR;
e5e7a7c2 MY	124	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	125	struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
	126	struct sdhci_host *host = dev_get_priv(dev);
	127	fdt_addr_t base;
	128	int ret;
	129
a821c4af	130	base = devfdt_get_addr(dev);
e5e7a7c2 MY	131	if (base == FDT_ADDR_T_NONE)
	132	return -EINVAL;
	133
	134	plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
	135	if (!plat->hrs_addr)
	136	return -ENOMEM;
	137
	138	host->name = dev->name;
	139	host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
	140	host->quirks \|= SDHCI_QUIRK_WAIT_SEND_CMD;
	141
da409ccc	142	ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
0cacd6b7 MY	143	if (ret)
0cacd6b7 MY	144	return ret;
e5e7a7c2 MY	145
	146	ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
	147	if (ret)
	148	return ret;
	149
	150	upriv->mmc = &plat->mmc;
	151	host->mmc = &plat->mmc;
	152	host->mmc->priv = host;
	153
	154	return sdhci_probe(dev);
	155	}
	156
	157	static const struct udevice_id sdhci_cdns_match[] = {
	158	{ .compatible = "socionext,uniphier-sd4hc" },
	159	{ .compatible = "cdns,sd4hc" },
	160	{ /* sentinel */ }
	161	};
	162
	163	U_BOOT_DRIVER(sdhci_cdns) = {
	164	.name = "sdhci-cdns",
	165	.id = UCLASS_MMC,
	166	.of_match = sdhci_cdns_match,
	167	.bind = sdhci_cdns_bind,
	168	.probe = sdhci_cdns_probe,
	169	.priv_auto_alloc_size = sizeof(struct sdhci_host),
	170	.platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
	171	.ops = &sdhci_ops,
	172	};