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af62a557 LW |
1 | /* |
2 | * Copyright 2011, Marvell Semiconductor Inc. | |
3 | * Lei Wen <leiwen@marvell.com> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | * Back ported to the 8xx platform (from the 8260 platform) by | |
24 | * Murray.Jensen@cmst.csiro.au, 27-Jan-01. | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <malloc.h> | |
29 | #include <mmc.h> | |
30 | #include <sdhci.h> | |
31 | ||
32 | void *aligned_buffer; | |
33 | ||
34 | static void sdhci_reset(struct sdhci_host *host, u8 mask) | |
35 | { | |
36 | unsigned long timeout; | |
37 | ||
38 | /* Wait max 100 ms */ | |
39 | timeout = 100; | |
40 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); | |
41 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { | |
42 | if (timeout == 0) { | |
43 | printf("Reset 0x%x never completed.\n", (int)mask); | |
44 | return; | |
45 | } | |
46 | timeout--; | |
47 | udelay(1000); | |
48 | } | |
49 | } | |
50 | ||
51 | static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) | |
52 | { | |
53 | int i; | |
54 | if (cmd->resp_type & MMC_RSP_136) { | |
55 | /* CRC is stripped so we need to do some shifting. */ | |
56 | for (i = 0; i < 4; i++) { | |
57 | cmd->response[i] = sdhci_readl(host, | |
58 | SDHCI_RESPONSE + (3-i)*4) << 8; | |
59 | if (i != 3) | |
60 | cmd->response[i] |= sdhci_readb(host, | |
61 | SDHCI_RESPONSE + (3-i)*4-1); | |
62 | } | |
63 | } else { | |
64 | cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); | |
65 | } | |
66 | } | |
67 | ||
68 | static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) | |
69 | { | |
70 | int i; | |
71 | char *offs; | |
72 | for (i = 0; i < data->blocksize; i += 4) { | |
73 | offs = data->dest + i; | |
74 | if (data->flags == MMC_DATA_READ) | |
75 | *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); | |
76 | else | |
77 | sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); | |
78 | } | |
79 | } | |
80 | ||
81 | static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, | |
82 | unsigned int start_addr) | |
83 | { | |
a004abde | 84 | unsigned int stat, rdy, mask, timeout, block = 0; |
af62a557 | 85 | |
a004abde | 86 | timeout = 10000; |
af62a557 LW |
87 | rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; |
88 | mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; | |
89 | do { | |
90 | stat = sdhci_readl(host, SDHCI_INT_STATUS); | |
91 | if (stat & SDHCI_INT_ERROR) { | |
92 | printf("Error detected in status(0x%X)!\n", stat); | |
93 | return -1; | |
94 | } | |
95 | if (stat & rdy) { | |
96 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) | |
97 | continue; | |
98 | sdhci_writel(host, rdy, SDHCI_INT_STATUS); | |
99 | sdhci_transfer_pio(host, data); | |
100 | data->dest += data->blocksize; | |
101 | if (++block >= data->blocks) | |
102 | break; | |
103 | } | |
104 | #ifdef CONFIG_MMC_SDMA | |
105 | if (stat & SDHCI_INT_DMA_END) { | |
106 | sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); | |
3e81c772 | 107 | start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); |
af62a557 LW |
108 | start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; |
109 | sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); | |
110 | } | |
111 | #endif | |
a004abde LW |
112 | if (timeout-- > 0) |
113 | udelay(10); | |
114 | else { | |
115 | printf("Transfer data timeout\n"); | |
116 | return -1; | |
117 | } | |
af62a557 LW |
118 | } while (!(stat & SDHCI_INT_DATA_END)); |
119 | return 0; | |
120 | } | |
121 | ||
122 | int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, | |
123 | struct mmc_data *data) | |
124 | { | |
125 | struct sdhci_host *host = (struct sdhci_host *)mmc->priv; | |
126 | unsigned int stat = 0; | |
127 | int ret = 0; | |
128 | int trans_bytes = 0, is_aligned = 1; | |
129 | u32 mask, flags, mode; | |
130 | unsigned int timeout, start_addr = 0; | |
131 | ||
132 | /* Wait max 10 ms */ | |
133 | timeout = 10; | |
134 | ||
135 | sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); | |
136 | mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; | |
137 | ||
138 | /* We shouldn't wait for data inihibit for stop commands, even | |
139 | though they might use busy signaling */ | |
140 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) | |
141 | mask &= ~SDHCI_DATA_INHIBIT; | |
142 | ||
143 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { | |
144 | if (timeout == 0) { | |
145 | printf("Controller never released inhibit bit(s).\n"); | |
146 | return COMM_ERR; | |
147 | } | |
148 | timeout--; | |
149 | udelay(1000); | |
150 | } | |
151 | ||
152 | mask = SDHCI_INT_RESPONSE; | |
153 | if (!(cmd->resp_type & MMC_RSP_PRESENT)) | |
154 | flags = SDHCI_CMD_RESP_NONE; | |
155 | else if (cmd->resp_type & MMC_RSP_136) | |
156 | flags = SDHCI_CMD_RESP_LONG; | |
157 | else if (cmd->resp_type & MMC_RSP_BUSY) { | |
158 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
159 | mask |= SDHCI_INT_DATA_END; | |
160 | } else | |
161 | flags = SDHCI_CMD_RESP_SHORT; | |
162 | ||
163 | if (cmd->resp_type & MMC_RSP_CRC) | |
164 | flags |= SDHCI_CMD_CRC; | |
165 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
166 | flags |= SDHCI_CMD_INDEX; | |
167 | if (data) | |
168 | flags |= SDHCI_CMD_DATA; | |
169 | ||
170 | /*Set Transfer mode regarding to data flag*/ | |
171 | if (data != 0) { | |
172 | sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); | |
173 | mode = SDHCI_TRNS_BLK_CNT_EN; | |
174 | trans_bytes = data->blocks * data->blocksize; | |
175 | if (data->blocks > 1) | |
176 | mode |= SDHCI_TRNS_MULTI; | |
177 | ||
178 | if (data->flags == MMC_DATA_READ) | |
179 | mode |= SDHCI_TRNS_READ; | |
180 | ||
181 | #ifdef CONFIG_MMC_SDMA | |
182 | if (data->flags == MMC_DATA_READ) | |
183 | start_addr = (unsigned int)data->dest; | |
184 | else | |
185 | start_addr = (unsigned int)data->src; | |
186 | if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && | |
187 | (start_addr & 0x7) != 0x0) { | |
188 | is_aligned = 0; | |
189 | start_addr = (unsigned int)aligned_buffer; | |
190 | if (data->flags != MMC_DATA_READ) | |
191 | memcpy(aligned_buffer, data->src, trans_bytes); | |
192 | } | |
193 | ||
194 | sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); | |
195 | mode |= SDHCI_TRNS_DMA; | |
196 | #endif | |
197 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, | |
198 | data->blocksize), | |
199 | SDHCI_BLOCK_SIZE); | |
200 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); | |
201 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); | |
202 | } | |
203 | ||
204 | sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); | |
205 | #ifdef CONFIG_MMC_SDMA | |
2c2ec4c9 | 206 | flush_cache(start_addr, trans_bytes); |
af62a557 LW |
207 | #endif |
208 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); | |
209 | do { | |
210 | stat = sdhci_readl(host, SDHCI_INT_STATUS); | |
211 | if (stat & SDHCI_INT_ERROR) | |
212 | break; | |
213 | } while ((stat & mask) != mask); | |
214 | ||
215 | if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { | |
216 | sdhci_cmd_done(host, cmd); | |
217 | sdhci_writel(host, mask, SDHCI_INT_STATUS); | |
218 | } else | |
219 | ret = -1; | |
220 | ||
221 | if (!ret && data) | |
222 | ret = sdhci_transfer_data(host, data, start_addr); | |
223 | ||
224 | stat = sdhci_readl(host, SDHCI_INT_STATUS); | |
225 | sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); | |
226 | if (!ret) { | |
227 | if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && | |
228 | !is_aligned && (data->flags == MMC_DATA_READ)) | |
229 | memcpy(data->dest, aligned_buffer, trans_bytes); | |
230 | return 0; | |
231 | } | |
232 | ||
233 | sdhci_reset(host, SDHCI_RESET_CMD); | |
234 | sdhci_reset(host, SDHCI_RESET_DATA); | |
235 | if (stat & SDHCI_INT_TIMEOUT) | |
236 | return TIMEOUT; | |
237 | else | |
238 | return COMM_ERR; | |
239 | } | |
240 | ||
241 | static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) | |
242 | { | |
243 | struct sdhci_host *host = (struct sdhci_host *)mmc->priv; | |
244 | unsigned int div, clk, timeout; | |
245 | ||
246 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | |
247 | ||
248 | if (clock == 0) | |
249 | return 0; | |
250 | ||
251 | if (host->version >= SDHCI_SPEC_300) { | |
252 | /* Version 3.00 divisors must be a multiple of 2. */ | |
253 | if (mmc->f_max <= clock) | |
254 | div = 1; | |
255 | else { | |
256 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { | |
257 | if ((mmc->f_max / div) <= clock) | |
258 | break; | |
259 | } | |
260 | } | |
261 | } else { | |
262 | /* Version 2.00 divisors must be a power of 2. */ | |
263 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { | |
264 | if ((mmc->f_max / div) <= clock) | |
265 | break; | |
266 | } | |
267 | } | |
268 | div >>= 1; | |
269 | ||
270 | clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; | |
271 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) | |
272 | << SDHCI_DIVIDER_HI_SHIFT; | |
273 | clk |= SDHCI_CLOCK_INT_EN; | |
274 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
275 | ||
276 | /* Wait max 20 ms */ | |
277 | timeout = 20; | |
278 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) | |
279 | & SDHCI_CLOCK_INT_STABLE)) { | |
280 | if (timeout == 0) { | |
281 | printf("Internal clock never stabilised.\n"); | |
282 | return -1; | |
283 | } | |
284 | timeout--; | |
285 | udelay(1000); | |
286 | } | |
287 | ||
288 | clk |= SDHCI_CLOCK_CARD_EN; | |
289 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
290 | return 0; | |
291 | } | |
292 | ||
293 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) | |
294 | { | |
295 | u8 pwr = 0; | |
296 | ||
297 | if (power != (unsigned short)-1) { | |
298 | switch (1 << power) { | |
299 | case MMC_VDD_165_195: | |
300 | pwr = SDHCI_POWER_180; | |
301 | break; | |
302 | case MMC_VDD_29_30: | |
303 | case MMC_VDD_30_31: | |
304 | pwr = SDHCI_POWER_300; | |
305 | break; | |
306 | case MMC_VDD_32_33: | |
307 | case MMC_VDD_33_34: | |
308 | pwr = SDHCI_POWER_330; | |
309 | break; | |
310 | } | |
311 | } | |
312 | ||
313 | if (pwr == 0) { | |
314 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); | |
315 | return; | |
316 | } | |
317 | ||
318 | pwr |= SDHCI_POWER_ON; | |
319 | ||
320 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); | |
321 | } | |
322 | ||
323 | void sdhci_set_ios(struct mmc *mmc) | |
324 | { | |
325 | u32 ctrl; | |
326 | struct sdhci_host *host = (struct sdhci_host *)mmc->priv; | |
327 | ||
328 | if (mmc->clock != host->clock) | |
329 | sdhci_set_clock(mmc, mmc->clock); | |
330 | ||
331 | /* Set bus width */ | |
332 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
333 | if (mmc->bus_width == 8) { | |
334 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
335 | if (host->version >= SDHCI_SPEC_300) | |
336 | ctrl |= SDHCI_CTRL_8BITBUS; | |
337 | } else { | |
338 | if (host->version >= SDHCI_SPEC_300) | |
339 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
340 | if (mmc->bus_width == 4) | |
341 | ctrl |= SDHCI_CTRL_4BITBUS; | |
342 | else | |
343 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
344 | } | |
345 | ||
346 | if (mmc->clock > 26000000) | |
347 | ctrl |= SDHCI_CTRL_HISPD; | |
348 | else | |
349 | ctrl &= ~SDHCI_CTRL_HISPD; | |
350 | ||
351 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
352 | } | |
353 | ||
354 | int sdhci_init(struct mmc *mmc) | |
355 | { | |
356 | struct sdhci_host *host = (struct sdhci_host *)mmc->priv; | |
357 | ||
358 | if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { | |
359 | aligned_buffer = memalign(8, 512*1024); | |
360 | if (!aligned_buffer) { | |
361 | printf("Aligned buffer alloc failed!!!"); | |
362 | return -1; | |
363 | } | |
364 | } | |
365 | ||
366 | /* Eable all state */ | |
367 | sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE); | |
368 | sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE); | |
369 | ||
370 | sdhci_set_power(host, fls(mmc->voltages) - 1); | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
375 | int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) | |
376 | { | |
377 | struct mmc *mmc; | |
378 | unsigned int caps; | |
379 | ||
380 | mmc = malloc(sizeof(struct mmc)); | |
381 | if (!mmc) { | |
382 | printf("mmc malloc fail!\n"); | |
383 | return -1; | |
384 | } | |
385 | ||
386 | mmc->priv = host; | |
6cf1b17c | 387 | host->mmc = mmc; |
af62a557 LW |
388 | |
389 | sprintf(mmc->name, "%s", host->name); | |
390 | mmc->send_cmd = sdhci_send_command; | |
391 | mmc->set_ios = sdhci_set_ios; | |
392 | mmc->init = sdhci_init; | |
48972d90 | 393 | mmc->getcd = NULL; |
af62a557 LW |
394 | |
395 | caps = sdhci_readl(host, SDHCI_CAPABILITIES); | |
396 | #ifdef CONFIG_MMC_SDMA | |
397 | if (!(caps & SDHCI_CAN_DO_SDMA)) { | |
398 | printf("Your controller don't support sdma!!\n"); | |
399 | return -1; | |
400 | } | |
401 | #endif | |
402 | ||
403 | if (max_clk) | |
404 | mmc->f_max = max_clk; | |
405 | else { | |
406 | if (host->version >= SDHCI_SPEC_300) | |
407 | mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) | |
408 | >> SDHCI_CLOCK_BASE_SHIFT; | |
409 | else | |
410 | mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK) | |
411 | >> SDHCI_CLOCK_BASE_SHIFT; | |
412 | mmc->f_max *= 1000000; | |
413 | } | |
414 | if (mmc->f_max == 0) { | |
415 | printf("Hardware doesn't specify base clock frequency\n"); | |
416 | return -1; | |
417 | } | |
418 | if (min_clk) | |
419 | mmc->f_min = min_clk; | |
420 | else { | |
421 | if (host->version >= SDHCI_SPEC_300) | |
422 | mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300; | |
423 | else | |
424 | mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200; | |
425 | } | |
426 | ||
427 | mmc->voltages = 0; | |
428 | if (caps & SDHCI_CAN_VDD_330) | |
429 | mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; | |
430 | if (caps & SDHCI_CAN_VDD_300) | |
431 | mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; | |
432 | if (caps & SDHCI_CAN_VDD_180) | |
433 | mmc->voltages |= MMC_VDD_165_195; | |
434 | mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; | |
435 | if (caps & SDHCI_CAN_DO_8BIT) | |
436 | mmc->host_caps |= MMC_MODE_8BIT; | |
437 | ||
438 | sdhci_reset(host, SDHCI_RESET_ALL); | |
439 | mmc_register(mmc); | |
440 | ||
441 | return 0; | |
442 | } |